251 lines
8.3 KiB
C
251 lines
8.3 KiB
C
// This file is part of noxos and licensed under the MIT open source license
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#ifndef NOXOS_AHCI_H
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#define NOXOS_AHCI_H
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#include "utils/stdtypes.h"
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#include "drivers/pci.h"
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#include "drivers/drive_manager.h"
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#define SATA_SIG_ATA 0x00000101
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#define SATA_SIG_ATAPI 0xEB140101
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#define SATA_SIG_SEMB 0xC33C0101
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#define SATA_SIG_PORT_MULTIPLIER 0x96690101
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#define ATA_DEVICE_BUSY 0x80
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#define ATA_DEVICE_DRQ 0x08
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#define ATA_CMD_READ_DMA_EX 0x25
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#define ATA_CMD_WRITE_DMA_EX 0x35
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#define HBA_PX_IS_TFES (1 << 30)
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#define HBA_PX_COMMAND_CMD_LIST_RUNNING 0x8000
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#define HBA_PX_COMMAND_START 0x0001
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#define HBA_PX_COMMAND_FIS_RECV_ENABLE 0x0010
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#define HBA_PX_COMMAND_FIS_RECV_RUNNING 0x4000
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#define HBA_PORT_DEVICE_PRESENT 0x03
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#define HBA_PORT_IPM_ACTIVE 0x01
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typedef enum {
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AHCI_DEVICE_NONE,
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AHCI_DEVICE_SATA,
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AHCI_DEVICE_SEMB,
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AHCI_DEVICE_PORT_MULTIPLIER,
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AHCI_DEVICE_SATAPI,
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AHCI_DEVICE_TYPE_END_OF_ENUM
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} ahci_device_type_E;
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typedef enum {
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AHCI_FIS_REGISTER_HOST_TO_DEVICE = 0x27, // host --> device
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AHCI_FIS_REGISTER_DEVICE_TO_HOST = 0x34, // host <-- device
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AHCI_FIS_DMA_ACTIVATE = 0x39, // host <-- device
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AHCI_FIS_DMA_SETUP = 0x41, // host <--> device
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AHCI_FIS_DATA = 0x46, // host <--> device
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AHCI_FIS_BIST = 0x58, // host <--> device
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AHCI_FIS_PIO_SETUP = 0x5F, // host <-- device
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AHCI_FIS_DEVICE_BITS = 0xA1 // host <-- device
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} ahci_fis_type_E;
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typedef struct {
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uint8_t type;
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uint8_t port_multiplier:4;
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uint8_t reserved_0:3;
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uint8_t command_control_select:1;
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uint8_t command;
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uint8_t feature_0;
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uint8_t lba_0;
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uint8_t lba_1;
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uint8_t lba_2;
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uint8_t device;
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uint8_t lba_3;
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uint8_t lba_4;
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uint8_t lba_5;
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uint8_t feature_1;
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uint8_t count_low;
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uint8_t count_high;
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uint8_t icc;
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uint8_t control;
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uint32_t reserved_1;
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} ahci_fis_register_host_to_device_T;
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typedef struct {
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uint8_t type;
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uint8_t port_multiplier:4;
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uint8_t reserved_0:2;
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uint8_t interrupt:1;
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uint8_t reserved_1:1;
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uint8_t status;
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uint8_t error;
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uint8_t lba_0;
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uint8_t lba_1;
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uint8_t lba_2;
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uint8_t device;
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uint8_t lba_3;
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uint8_t lba_4;
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uint8_t lba_5;
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uint8_t reserved_2;
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uint16_t count;
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uint16_t reserved_3;
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uint32_t reserved_4;
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} ahci_fis_register_device_to_host_T;
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typedef struct {
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uint8_t type;
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uint8_t port_multiplier:4;
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uint8_t reserved_0:4;
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uint16_t reserved_1;
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uint32_t data; // this can be followed by more data
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} ahci_fis_data_T;
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typedef struct {
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uint8_t type;
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uint8_t port_multiplier:4;
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uint8_t reserved_0:1;
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uint8_t transfer_direction:1;
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uint8_t interrupt:1;
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uint8_t reserved_1:1;
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uint8_t status;
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uint8_t error;
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uint8_t lba_0;
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uint8_t lba_1;
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uint8_t lba_2;
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uint8_t device;
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uint8_t lba_3;
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uint8_t lba_4;
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uint8_t lba_5;
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uint8_t reserved_2;
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uint16_t count;
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uint8_t reserved_3;
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uint8_t new_status;
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uint16_t transfer_count;
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uint16_t reserved_4;
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} ahci_fis_pio_setup_T;
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typedef struct {
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uint8_t type;
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uint8_t port_multiplier:4;
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uint8_t reserved_0:1;
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uint8_t transfer_direction:1;
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uint8_t interrupt:1;
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uint8_t auto_activate:1;
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uint16_t reserved_1;
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uint64_t dma_buffer_id;
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uint32_t reserved_2;
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uint32_t dma_buffer_offset;
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uint32_t transfer_count;
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uint32_t reserved_3;
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} ahci_fis_dma_setup_T;
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typedef struct {
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uint32_t command_list_base;
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uint32_t command_list_base_upper;
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uint32_t fis_base_address;
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uint32_t fis_base_address_upper;
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uint32_t interrupt_status;
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uint32_t interrupt_enable;
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uint32_t command_status;
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uint32_t reserved_0;
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uint32_t task_file_data;
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uint32_t signature;
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uint32_t sata_status;
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uint32_t sata_control;
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uint32_t sata_error;
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uint32_t sata_active;
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uint32_t command_issue;
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uint32_t sata_notification;
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uint32_t fis_switch_control;
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uint32_t reserved_1 [11];
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uint32_t vendor [4];
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} ahci_hba_port_T;
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typedef struct {
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uint32_t host_capability;
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uint32_t global_host_control;
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uint32_t interrupt_status;
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uint32_t ports_implemented;
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uint32_t version;
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uint32_t ccc_control;
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uint32_t ccc_ports;
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uint32_t enclosure_management_location;
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uint32_t enclosure_management_control;
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uint32_t host_capabilities_extended;
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uint32_t bios_handoff_control_status;
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uint8_t reserved_0 [0x74];
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uint8_t vendor [0x60];
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ahci_hba_port_T ports [1];
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} ahci_hba_memory_T;
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typedef struct {
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uint8_t command_fis_length:5;
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uint8_t atapi:1;
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uint8_t write:1;
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uint8_t prefetchable:1;
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uint8_t reset:1;
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uint8_t bist:1;
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uint8_t clear_busy:1;
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uint8_t reserved_0:1;
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uint8_t port_multiplier:4;
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uint16_t prdt_length;
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uint32_t prdb_count;
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uint32_t command_table_base_address;
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uint32_t command_table_base_address_upper;
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uint32_t reserved_1 [4];
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} ahci_hba_command_T;
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typedef struct {
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uint32_t data_base_address;
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uint32_t data_base_address_upper;
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uint32_t reserved_0;
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uint32_t byte_count:22;
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uint32_t reserved_1:9;
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uint32_t interrupt_on_completion:1;
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} ahci_hba_prdt_entry_T;
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typedef struct{
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uint8_t command_fis [64];
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uint8_t atapi_command [16];
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uint8_t reserved [48];
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ahci_hba_prdt_entry_T prdt_entry [];
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} ahci_hba_command_table_T;
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typedef struct ahci_controller_T ahci_controller_T;
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typedef struct {
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ahci_hba_port_T* hba_port;
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ahci_device_type_E type;
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ahci_controller_T* controller;
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uint8_t id;
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drive_T* drive;
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void* cmd_list_base;
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void* fis_base;
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void* command_tables [32];
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} ahci_port_T;
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struct ahci_controller_T {
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ahci_port_T ports [32];
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int num_ports;
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pci_device_T* pci_device;
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ahci_hba_memory_T* abar;
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};
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ahci_controller_T* ahci_controller_alloc (pci_device_T* pci_device);
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void ahci_controller_destruct (ahci_controller_T* controller);
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void ahci_port_init (ahci_port_T* port);
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void ahci_port_init_partitions_mbr (ahci_port_T* port);
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void ahci_port_init_partitions_gpt (ahci_port_T* port);
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void ahci_port_destruct (ahci_port_T* port);
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ahci_device_type_E ahci_port_get_type (ahci_hba_port_T* port);
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void ahci_port_command_stop (ahci_port_T* port);
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void ahci_port_command_start (ahci_port_T* port);
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bool ahci_port_read (ahci_port_T* port, uint64_t sector, uint32_t num_sectors, void* buffer_out);
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bool ahci_port_write (ahci_port_T* port, uint64_t sector, uint32_t num_sectors, void* buffer_in);
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extern string_t g_ahci_device_type_strings[AHCI_DEVICE_TYPE_END_OF_ENUM];
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#endif //NOXOS_AHCI_H
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