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This commit is contained in:
Eric-Paul Ickhorn 2023-04-22 11:10:58 +02:00
parent b1f71e0230
commit a904ffaaad
4 changed files with 8 additions and 336 deletions
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213
inc/drivers/pci.h
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@ -1,216 +1,7 @@
#ifndef NOXOS_pci_H #ifndef NOXOS_PCI_H
#define NOXOS_pci_H #define NOXOS_PCI_H
#include <drivers/acpi/acpi.h>
typedef enum {
PCI_CLASS_UNCLASSIFIED = 0x00,
PCI_CLASS_MASS_STORAGE_CONTROLLER = 0x01,
PCI_CLASS_NETWORK_CONTROLLER = 0x02,
PCI_CLASS_DISPLAY_CONTROLLER = 0x03,
PCI_CLASS_MULTIMEDIA_CONTROLLER = 0x04,
PCI_CLASS_MEMORY_CONTROLLER = 0x05,
PCI_CLASS_BRIDGE = 0x06,
PCI_CLASS_SIMPLE_COMMUNICATION_CONTROLLER = 0x07,
PCI_CLASS_BASE_SYSTEM_PERIPHERAL = 0x08,
PCI_CLASS_INPUT_DEVICE_CONTROLLER = 0x09,
PCI_CLASS_DOCKING_STATION = 0x0a,
PCI_CLASS_PROCESSOR = 0x0b,
PCI_CLASS_SERIAL_BUS_CONTROLLER = 0x0c,
PCI_CLASS_WIRELESS_CONTROLLER = 0x0d,
PCI_CLASS_INTELLIGENT_CONTROLLER = 0x0e,
PCI_CLASS_SATELLITE_COMMUNICATION_CONTROLLER = 0x0f,
PCI_CLASS_ENCRYPTION_CONTROLLER = 0x10,
PCI_CLASS_SIGNAL_PROCESSING_CONTROLLER = 0x11,
PCI_CLASS_PROCESSING_ACCELERATOR = 0x12,
PCI_CLASS_NON_ESSENTIAL_INSTRUMENTATION = 0x13,
PCI_CLASS_COPROCESSOR = 0x40
} pci_class_T;
typedef enum {
PCI_SUBCLASS_NON_VGA_COMPATIBLE_UNCLASSIFIED_DEVICE = 0x00,
PCI_SUBCLASS_VGA_COMPATIBLE_UNCLASSIFIED_DEVICE = 0x01
} pci_unclassified_sublasses_T;
typedef enum {
PCI_SUBCLASS_SCSI_BUS_CONTROLLER = 0x00,
PCI_SUBCLASS_IDE_CONTROLLER = 0x01,
PCI_SUBCLASS_FLOPPY_DISK_CONTROLLER = 0x02,
PCI_SUBCLASS_IPI_BUS_CONTROLLER = 0x03,
PCI_SUBCLASS_RAID_CONTROLLER = 0x04,
PCI_SUBCLASS_ATA_CONTROLLER = 0x05,
PCI_SUBCLASS_SERIAL_ATA_CONTROLLER = 0x06,
PCI_SUBCLASS_SERIAL_ATTACHED_SCSI_CONTROLLER = 0x07,
PCI_SUBCLASS_NON_VOLATILE_MEMORY_CONTROLLER = 0x08,
PCI_SUBCLASS_OTHER_MASS_STORAGE_CONTROLLER = 0x80
} pci_mass_storage_controller_subclasses_T;
typedef enum {
PCI_SUBCLASS_ETHERNET_CONTROLLER = 0x00,
PCI_SUBCLASS_TOKEN_RING_CONTROLLER = 0x01,
PCI_SUBCLASS_FDDI_CONTROLLER = 0x02,
PCI_SUBCLASS_ATM_CONTROLLER = 0x03,
PCI_SUBCLASS_ISDN_CONTROLLER = 0x04,
PCI_SUBCLASS_WORLDFIP_CONTROLLER = 0x05,
PCI_SUBCLASS_PICMG_2_14_MULTI_COMPUTING_CONTROLLER = 0x06,
PCI_SUBCLASS_INFINIBAND_NETWORKCONTROLLER = 0x07,
PCI_SUBCLASS_FABRIC_CONTROLLER = 0x08,
PCI_SUBCLASS_OTHER_NETWORK_CONTROLLER = 0x80
} pci_network_controller_subclasses_T;
typedef enum {
PCI_SUBCLASS_VGA_COMPATIBLE_CONTROLLER = 0x00,
PCI_SUBCLASS_XGA_COMPATIBLE_CONTROLLER = 0x01,
PCI_SUBCLASS_3D_CONTROLLER_NOT_VGA_COMPATIBLE = 0x02,
PCI_SUBCLASS_OTHER_DISPLAY_CONTROLLER = 0x80
} pci_display_controller_subclasses_T;
typedef enum {
PCI_SUBCLASS_MULTIMEDIA_VIDEO_CONTROLLER = 0x00,
PCI_SUBCLASS_MULTIMEDIA_AUDIO_CONTROLLER = 0x01,
PCI_SUBCLASS_COMPUTER_TELEPHONY_DEVICE = 0x02,
PCI_SUBCLASS_AUDIO_DEVICE = 0x03,
PCI_SUBCLASS_OTHER_MULTIMEDIA_CONTROLLER = 0x80
} pci_multimedia_controller_subclasses_T;
typedef enum {
PCI_SUBCLASS_RAM_CONTROLLER = 0x00,
PCI_SUBCLASS_FLASH_CONTROLLER = 0x01,
PCI_SUBCLASS_OTHER_MEMORY_CONTROLLER = 0x80
} pci_memory_controller_subclasses_T;
typedef enum {
PCI_SUBCLASS_HOST_BRIDGE = 0x00,
PCI_SUBCLASS_ISA_BRIDGE = 0x01,
PCI_SUBCLASS_EISA_BRIDGE = 0x02,
PCI_SUBCLASS_MCA_BRIDGE = 0x03,
PCI_SUBCLASS_PCI_TO_PCI_BRIDGE = 0x04,
PCI_SUBCLASS_PCMCIA_BRIDGE = 0x05,
PCI_SUBCLASS_NUBUS_BRIDGE = 0x06,
PCI_SUBCLASS_CARDBUS_BRIDGE = 0x07,
PCI_SUBCLASS_RACEWAY_BRIDGE = 0x08,
PCI_SUBCLASS_PCI_TO_PCI_BRIDGE_2 = 0x09,
PCI_SUBCLASS_INFINIBAND_TO_PCI_HOST_BRIDGE = 0x0a,
PCI_SUBCLASS_OTHER_BRIDGE = 0x80
} pci_bridge_subclasses_T;
typedef enum {
PCI_SUBCLASS_SERIAL_SIMPLE_COMMUNICATION_CONTROLLER = 0x00,
PCI_SUBCLASS_PARALLEL_SIMPLE_COMMUNICATION_CONTROLLER = 0x01,
PCI_SUBCLASS_MULTIPORT_SERIAL_CONTROLLER = 0x02,
PCI_SUBCLASS_MODEM = 0x03,
PCI_SUBCLASS_IEEE_488_1_2_GPIB_CONTROLLER = 0x04,
PCI_SUBCLASS_SMART_CARD_CONTROLLER = 0x05,
PCI_SUBCLASS_OTHER_SIMPLE_COMMUNICATION_CONTROLLER = 0x80
} pci_simple_communication_controller_subclasses_T;
typedef enum {
PCI_SUBCLASS_PIC = 0x00,
PCI_SUBCLASS_DMA_CONTROLLER = 0x01,
PCI_SUBCLASS_TIMER = 0x02,
PCI_SUBCLASS_RTC_CONTROLLER = 0x03,
PCI_SUBCLASS_PCI_HOT_PLUG_CONTROLLER = 0x04,
PCI_SUBCLASS_SD_HOST_CONTROLLER = 0x05,
PCI_SUBCLASS_IOMMU = 0x06,
PCI_SUBCLASS_OTHER_BASE_SYSTEM_PERIPHERAL = 0x80
} pci_base_system_peripheral_subclasses_T;
typedef enum {
PCI_SUBCLASS_KEKYBOARD_CONTROLLER = 0x00,
PCI_SUBCLASS_DIGITIZER_PEN = 0x01,
PCI_SUBCLASS_MOUSE_CONTROLLER = 0x02,
PCI_SUBCLASS_SCANNER_CONTROLLER = 0x03,
PCI_SUBCLASS_GAMEPORT_CONTROLLER = 0x04,
PCI_SUBCLASS_OTHER_INPUT_DEVICE_CONTROLLER = 0x80
} pci_input_device_controller_subclasses_T;
typedef enum {
PCI_SUBCLASS_GENERIC_DOCKING_STATION = 0x00,
PCI_SUBCLASS_OTHER_DOCKING_STATION = 0x80
} pci_docking_station_subclasses_T;
typedef enum {
PCI_SUBCLASS_386_PROCESSOR = 0x00,
PCI_SUBCLASS_486_PROCESSOR = 0x01,
PCI_SUBCLASS_PENTIUM_PROCESSOR = 0x02,
PCI_SUBCLASS_PENTIUM_PRO_PROCESSOR = 0x03,
PCI_SUBCLASS_ALPHA_PROCESSOR = 0x10,
PCI_SUBCLASS_POWERPC_PROCESSOR = 0x20,
PCI_SUBCLASS_MIPS_PROCESSOR = 0x30,
PCI_SUBCLASS_COPROCESSOR = 0x40,
PCI_SUBCLASS_OTHER_PROCESSOR = 0x80
} pci_processor_subclasses_T;
typedef enum {
PCI_SUBCLASS_FIREWIRE_CONTROLLER = 0x00,
PCI_SUBCLASS_ACCESS_BUS_CONTROLLER = 0x01,
PCI_SUBCLASS_SSA = 0x02,
PCI_SUBCLASS_USB_CONTROLLER = 0x03,
PCI_SUBCLASS_FIBRE_CHANNEL = 0x04,
PCI_SUBCLASS_SMBUS_CONTROLLER = 0x05,
PCI_SUBCLASS_INFINIBAND_SERIAL_BUS_CONTROLLER = 0x06,
PCI_SUBCLASS_IPMI_INTERFACE = 0x07,
PCI_SUBCLASS_SERCOS_INTERFACE = 0x08,
PCI_SUBCLASS_CANBUS_CONTROOLLER = 0x09,
PCI_SUBCLASS_OTHER_SERIAL_BUS_CONTROLLER = 0x80
} pci_serial_bus_controller_subclasses_T;
typedef enum {
PCI_SUBCLASS_IRDA_COMPATIBLE_CONTROLLER = 0x00,
PCI_SUBCLASS_CONSUMER_IR_CONTROLLER = 0x01,
PCI_SUBCLASS_RF_CONTROLLER = 0x10,
PCI_SUBCLASS_BLUETOOTH_CONTROLLER = 0x11,
PCI_SUBCLASS_BROADBAND_CONTROLLER = 0x12,
PCI_SUBCLASS_ETHERNET_CONTROLLER_802_1A = 0x20,
PCI_SUBCLASS_ETHERNET_CONTROLLER_802_1B = 0x21,
PCI_SUBCLASS_OTHER_WIRELESS_CONTROLLER = 0x80
} pci_wireless_controller_subclasses_T;
typedef enum {
PCI_SUBCLASS_I20_INTELLIGENT_CONTROLLER = 0x00
} pci_intelligent_controller_subclasses_T;
typedef enum {
PCI_SUBCLASS_SATELLITE_TV_CONTROLLER = 0x01,
PCI_SUBCLASS_SATELLITE_AUDIO_CONTROLLER = 0x02,
PCI_SUBCLASS_SATELLITE_VOICE_CONTROLLER = 0x03,
PCI_SUBCLASS_SATELLITE_DATA_CONTROLLER = 0x04
} pci_satellite_communication_controller_subclasses_T;
typedef enum {
PCI_SUBCLASS_NETWORK_AND_COMPUTING_ENCRYPTION_DECRYPTION = 0x00,
PCI_SUBCLASS_ENTERTAINMENT_ENCRYPTION_DECRYPTION = 0x10,
PCI_SUBCLASS_OTHER_ENCRYPTION_CONTROLLER = 0x80
} pci_encryption_controller_subclasses_T;
typedef enum {
PCI_SUBCLASS_DPIO_MODULES = 0x00,
PCI_SUBCLASS_PERFORMANCE_COUTNERS = 0x01,
PCI_SUBCLASS_COMMUNICATION_SYNCHRONIZER = 0x10,
PCI_SUBCLASS_SIGNAL_PROCESSING_MANAGEMENT = 0x20,
PCI_SUBCLASS_OTHER_SIGNAL_PROCESSING_CONTROLLER = 0x80
} pci_signal_processing_controller_subclasses_T;
/*
typedef enum {
} pci_processing_accelerator_subclasses_T;
typedef enum {
} pci_non_essential_instrumentation_subclasses_T;
*/
typedef struct {
pci_class_T pci_class;
uint16_t pci_subclass;
} pci_device_T;
extern pci_device_T *g_pci_devices;
void pci_init(boot_info_T* boot_info);
#endif #endif

9
run.sh
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@ -1,8 +1,11 @@
#!/bin/bash #!/bin/bash
# This file is part of noxos and licensed under the MIT open source license # This file is part of noxos and licensed under the MIT open source license
EMUFLAGS="-no-reboot -m 256M -cdrom build/noxos.iso -chardev stdio,id=log,logfile=noxos.log -serial chardev:log" EMUFLAGS="-no-reboot -m 256M -cdrom build/noxos.iso -chardev stdio,id=log,logfile=noxos.log -serial chardev:log -drive id=disk,file=test_disk.img,if=none \
-device ahci,id=disk \
-device ide-hd,drive=disk
"
emulate_bios() { emulate_bios() {
echo "<=====| Emulating |=====>" echo "<=====| Emulating |=====>"
@ -30,4 +33,4 @@ case $1 in
*) *)
emulate_uefi emulate_uefi
;; ;;
esac esac

2
src/boot/kmain.c
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@ -42,8 +42,6 @@ void kernel_init(boot_info_T* boot_info) {
vfs_init(boot_info); vfs_init(boot_info);
acpi_init(boot_info); acpi_init(boot_info);
pci_init(boot_info);
// ps2_keyboard_init(); // ps2_keyboard_init();

120
src/drivers/pci.c
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@ -1,123 +1,3 @@
#include <drivers/pci.h> #include <drivers/pci.h>
#include <utils/logger.h>
#define PCI_CONFIG_ADDRESS 0xCF8
#define PCI_CONFIG_DATA 0xCFC
typedef struct {
uint16_t device_id;
uint16_t vendor_id;
uint16_t status_reg;
uint16_t command_reg;
uint8_t main_class;
uint8_t subclass;
uint8_t progif; // Programming Interface Byte
uint8_t revision_id;
uint8_t bist; // Built-in Self-Test
uint8_t header_type;
uint8_t latency_timer;
uint8_t cache_line_size;
} __attribute__((packed)) pci_internal_device_T;
typedef struct {
uint16_t device_id;
uint16_t vendor_id;
uint16_t status_reg;
uint16_t command_reg;
uint8_t main_class;
uint8_t subclass;
uint8_t progif; // Programming Interface Byte
uint8_t revision_id;
uint8_t bist; // Built-in Self-Test
uint8_t header_type;
uint8_t latency_timer;
uint8_t cache_line_size;
uint32_t bar0;
uint32_t bar1;
uint32_t bar2;
uint32_t bar3;
uint32_t bar4;
uint32_t bar5;
uint32_t cardbus_cis_pointer;
uint16_t subsystem_id;
uint16_t subsystem_vendor_id;
uint32_t expansion_rom_base_address;
uint8_t reserved1[3];
uint8_t capabilities;
uint8_t reserved2[4];
uint8_t max_latency;
uint8_t min_grant;
uint8_t interrupt_pin;
uint8_t interrupt_line;
} __attribute__((packed)) pci_internal_default_header_t;
pci_device_T *g_pci_devices = NULL;
uint32_t pci_read_config_word(uint8_t bus, uint8_t slot, uint8_t function, uint8_t offset) {
uint32_t bus32 = bus;
uint32_t slot32 = slot;
uint32_t function32 = function;
uint32_t offset32 = offset;
uint32_t address = 0x80000000 | bus32 << 16 | slot32 << 11 | function32 << 8 | offset32;
io_out_word(PCI_CONFIG_ADDRESS, address);
//uint32_t raw = io_in_word(PCI_CONFIG_DATA);
uint32_t raw = 0;
raw |= ((uint32_t) io_in_byte(PCI_CONFIG_DATA)) << 24;
raw |= ((uint32_t) io_in_byte(PCI_CONFIG_DATA)) << 16;
raw |= ((uint32_t) io_in_byte(PCI_CONFIG_DATA)) << 8;
raw |= ((uint32_t) io_in_byte(PCI_CONFIG_DATA));
uint32_t processed = (raw >> 24) | ((raw >> 8) & 0x00ff0000) | (raw << 8 & 0x0000ff00) | (raw << 24);
//return processed;
return raw;
}
pci_internal_default_header_t pci_read_internal_default_header(uint8_t bus, uint8_t slot, uint8_t function) {
pci_internal_default_header_t header;
uint32_t *header32 = (void *) &header;
uint32_t word_index = 0;
while(word_index < 16) {
header32[word_index] = pci_read_config_word(bus, slot, function, sizeof(pci_internal_device_T) + word_index*4);
++word_index;
}
return header;
}
void pci_init(boot_info_T* boot_info) {
// g_pci_devices = memory_allocate(sizeof(pci_device_T) * 256);
uint16_t bus_index = 0;
while(bus_index < 256) {
uint16_t slot_index = 0;
while(slot_index < 256) {
uint32_t first_config_word = pci_read_config_word(bus_index, slot_index, 0, 0);
if(first_config_word == 0xffffffff) {
break;
}
log(LOG_DEBUG, "Header Byte: %d", (pci_read_config_word(bus_index, slot_index, 0, 4) & 0x00ff0000) >> 16);
pci_internal_default_header_t header = pci_read_internal_default_header(bus_index, slot_index, 0);
uint32_t *header32 = &header;
// log(LOG_DEBUG, "%d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d",
log(LOG_DEBUG, "%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x",
header32[0], header32[1], header32[2], header32[3],
header32[4], header32[5], header32[6], header32[7],
header32[8], header32[9], header32[10], header32[11],
header32[12], header32[13], header32[14], header32[15]
);
log(LOG_DEBUG, "This is the real data:\nmain_class: %d\nsubclass: %d\n", header.main_class, header.subclass);
log(LOG_DEBUG, "First header part 16-bits: %x %x", (header32[2] >> 24) & 0xff, (header32[2] >> 16) & 0xff);
/*
if(header.main_class == PCI_CLASS_MASS_STORAGE_CONTROLLER) {
log(LOG_DEBUG, "Mass Storage Controller found!");
if(header.subclass == PCI_SUBCLASS_SERIAL_ATA_CONTROLLER) log(LOG_DEBUG, "Found the SATA controller!");
}
*/
++slot_index;
}
++bus_index;
}
}