feature (pci): Added PCI subclass enums
This commit is contained in:
Eric-Paul Ickhorn
parent
cae02e598d
commit
457bf6aa60
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@ -26,6 +26,8 @@ typedef struct {
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uint64_t address;
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} __attribute__((packed)) acpi_gas_T;
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extern acpi_sdt_header_T *g_mcfg_table;
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void acpi_init (boot_info_T* boot_info);
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acpi_sdt_header_T* acpi_find_table (acpi_sdt_header_T* xsdt, string_t table_id);
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@ -0,0 +1,215 @@
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#ifndef NOXOS_pci_H
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#define NOXOS_pci_H
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#include <drivers/acpi/acpi.h>
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typedef enum {
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PCI_CLASS_UNCLASSIFIED = 0x00,
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PCI_CLASS_MASS_STORAGE_CONTROLLER = 0x01,
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PCI_CLASS_NETWORK_CONTROLLER = 0x02,
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PCI_CLASS_DISPLAY_CONTROLLER = 0x03,
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PCI_CLASS_MULTIMEDIA_CONTROLLER = 0x04,
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PCI_CLASS_MEMORY_CONTROLLER = 0x05,
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PCI_CLASS_BRIDGE = 0x06,
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PCI_CLASS_SIMPLE_COMMUNICATION_CONTROLLER = 0x07,
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PCI_CLASS_BASE_SYSTEM_PERIPHERAL = 0x08,
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PCI_CLASS_INPUT_DEVICE_CONTROLLER = 0x09,
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PCI_CLASS_DOCKING_STATION = 0x0a,
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PCI_CLASS_PROCESSOR = 0x0b,
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PCI_CLASS_SERIAL_BUS_CONTROLLER = 0x0c,
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PCI_CLASS_WIRELESS_CONTROLLER = 0x0d,
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PCI_CLASS_INTELLIGENT_CONTROLLER = 0x0e,
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PCI_CLASS_SATELLITE_COMMUNICATION_CONTROLLER = 0x0f,
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PCI_CLASS_ENCRYPTION_CONTROLLER = 0x10,
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PCI_CLASS_SIGNAL_PROCESSING_CONTROLLER = 0x11,
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PCI_CLASS_PROCESSING_ACCELERATOR = 0x12,
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PCI_CLASS_NON_ESSENTIAL_INSTRUMENTATION = 0x13,
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PCI_CLASS_COPROCESSOR = 0x40
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} pci_class_T;
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typedef enum {
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PCI_SUBCLASS_NON_VGA_COMPATIBLE_UNCLASSIFIED_DEVICE = 0x00,
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PCI_SUBCLASS_VGA_COMPATIBLE_UNCLASSIFIED_DEVICE = 0x01
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} pci_unclassified_sublasses_T;
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typedef enum {
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PCI_SUBCLASS_SCSI_BUS_CONTROLLER = 0x00,
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PCI_SUBCLASS_IDE_CONTROLLER = 0x01,
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PCI_SUBCLASS_FLOPPY_DISK_CONTROLLER = 0x02,
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PCI_SUBCLASS_IPI_BUS_CONTROLLER = 0x03,
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PCI_SUBCLASS_RAID_CONTROLLER = 0x04,
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PCI_SUBCLASS_ATA_CONTROLLER = 0x05,
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PCI_SUBCLASS_SERIAL_ATA_CONTROLLER = 0x06,
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PCI_SUBCLASS_SERIAL_ATTACHED_SCSI_CONTROLLER = 0x07,
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PCI_SUBCLASS_NON_VOLATILE_MEMORY_CONTROLLER = 0x08,
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PCI_SUBCLASS_OTHER_MASS_STORAGE_CONTROLLER = 0x80
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} pci_mass_storage_controller_subclasses_T;
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typedef enum {
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PCI_SUBCLASS_ETHERNET_CONTROLLER = 0x00,
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PCI_SUBCLASS_TOKEN_RING_CONTROLLER = 0x01,
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PCI_SUBCLASS_FDDI_CONTROLLER = 0x02,
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PCI_SUBCLASS_ATM_CONTROLLER = 0x03,
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PCI_SUBCLASS_ISDN_CONTROLLER = 0x04,
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PCI_SUBCLASS_WORLDFIP_CONTROLLER = 0x05,
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PCI_SUBCLASS_PICMG_2_14_MULTI_COMPUTING_CONTROLLER = 0x06,
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PCI_SUBCLASS_INFINIBAND_CONTROLLER = 0x07,
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PCI_SUBCLASS_FABRIC_CONTROLLER = 0x08,
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PCI_SUBCLASS_OTHER_NETWORK_CONTROLLER = 0x80
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} pci_network_controller_subclasses_T;
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typedef enum {
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PCI_SUBCLASS_VGA_COMPATIBLE_CONTROLLER = 0x00,
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PCI_SUBCLASS_XGA_COMPATIBLE_CONTROLLER = 0x01,
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PCI_SUBCLASS_3D_CONTROLLER_NOT_VGA_COMPATIBLE = 0x02,
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PCI_SUBCLASS_OTHER_DISPLAY_CONTROLLER = 0x80
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} pci_display_controller_subclasses_T;
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typedef enum {
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PCI_SUBCLASS_MULTIMEDIA_VIDEO_CONTROLLER = 0x00,
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PCI_SUBCLASS_MULTIMEDIA_AUDIO_CONTROLLER = 0x01,
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PCI_SUBCLASS_COMPUTER_TELEPHONY_DEVICE = 0x02,
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PCI_SUBCLASS_AUDIO_DEVICE = 0x03,
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PCI_SUBCLASS_OTHER_MULTIMEDIA_CONTROLLER = 0x80
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} pci_multimedia_controller_subclasses_T;
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typedef enum {
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PCI_SUBCLASS_RAM_CONTROLLER = 0x00,
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PCI_SUBCLASS_FLASH_CONTROLLER = 0x01,
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PCI_SUBCLASS_OTHER_MEMORY_CONTROLLER = 0x80
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} pci_memory_controller_subclasses_T;
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typedef enum {
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PCI_SUBCLASS_HOST_BRIDGE = 0x00,
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PCI_SUBCLASS_ISA_BRIDGE = 0x01,
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PCI_SUBCLASS_EISA_BRIDGE = 0x02,
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PCI_SUBCLASS_MCA_BRIDGE = 0x03,
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PCI_SUBCLASS_PCI_TO_PCI_BRIDGE = 0x04,
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PCI_SUBCLASS_PCMCIA_BRIDGE = 0x05,
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PCI_SUBCLASS_NUBUS_BRIDGE = 0x06,
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PCI_SUBCLASS_CARDBUS_BRIDGE = 0x07,
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PCI_SUBCLASS_RACEWAY_BRIDGE = 0x08,
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PCI_SUBCLASS_PCI_TO_PCI_BRIDGE_2 = 0x09,
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PCI_SUBCLASS_INFINIBAND_TO_PCI_HOST_BRIDGE = 0x0a,
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PCI_SUBCLASS_OTHER_BRIDGE = 0x80
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} pci_bridge_subclasses_T;
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typedef enum {
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PCI_SUBCLASS_SERIAL_SIMPLE_COMMUNICATION_CONTROLLER = 0x00,
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PCI_SUBCLASS_PARALLEL_SIMPLE_COMMUNICATION_CONTROLLER = 0x01,
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PCI_SUBCLASS_MULTIPORT_SERIAL_CONTROLLER = 0x02,
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PCI_SUBCLASS_MODEM = 0x03,
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PCI_SUBCLASS_IEEE_488_1_2_GPIB_CONTROLLER = 0x04,
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PCI_SUBCLASS_SMART_CARD_CONTROLLER = 0x05,
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PCI_SUBCLASS_OTHER_SIMPLE_COMMUNICATION_CONTROLLER = 0x80
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} pci_simple_communication_controller_subclasses_T;
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typedef enum {
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PCI_SUBCLASS_PIC = 0x00,
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PCI_SUBCLASS_DMA_CONTROLLER = 0x01,
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PCI_SUBCLASS_TIMER = 0x02,
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PCI_SUBCLASS_RTC_CONTROLLER = 0x03,
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PCI_SUBCLASS_PCI_HOT_PLUG_CONTROLLER = 0x04,
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PCI_SUBCLASS_SD_HOST_CONTROLLER = 0x05,
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PCI_SUBCLASS_IOMMU = 0x06,
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PCI_SUBCLASS_OTHER_BASE_SYSTEM_PERIPHERAL = 0x80
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} pci_base_system_peripheral_subclasses_T;
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typedef enum {
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PCI_SUBCLASS_KEKYBOARD_CONTROLLER = 0x00,
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PCI_SUBCLASS_DIGITIZER_PEN = 0x01,
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PCI_SUBCLASS_MOUSE_CONTROLLER = 0x02,
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PCI_SUBCLASS_SCANNER_CONTROLLER = 0x03,
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PCI_SUBCLASS_GAMEPORT_CONTROLLER = 0x04,
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PCI_SUBCLASS_OTHER_INPUT_DEVICE_CONTROLLER = 0x80
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} pci_input_device_controller_subclasses_T;
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typedef enum {
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PCI_SUBCLASS_GENERIC_DOCKING_STATION = 0x00,
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PCI_SUBCLASS_OTHER_DOCKING_STATION = 0x80
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} pci_docking_station_subclasses_T;
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typedef enum {
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PCI_SUBCLASS_386_PROCESSOR = 0x00,
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PCI_SUBCLASS_486_PROCESSOR = 0x01,
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PCI_SUBCLASS_PENTIUM_PROCESSOR = 0x02,
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PCI_SUBCLASS_PENTIUM_PRO_PROCESSOR = 0x03,
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PCI_SUBCLASS_ALPHA_PROCESSOR = 0x10,
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PCI_SUBCLASS_POWERPC_PROCESSOR = 0x20,
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PCI_SUBCLASS_MIPS_PROCESSOR = 0x30,
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PCI_SUBCLASS_COPROCESSOR = 0x40,
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PCI_SUBCLASS_OTHER_PROCESSOR = 0x80
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} pci_processor_subclasses_T;
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typedef enum {
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PCI_SUBCLASS_FIREWIRE_CONTROLLER = 0x00,
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PCI_SUBCLASS_ACCESS_BUS_CONTROLLER = 0x01,
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PCI_SUBCLASS_SSA = 0x02,
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PCI_SUBCLASS_USB_CONTROLLER = 0x03,
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PCI_SUBCLASS_FIBRE_CHANNEL = 0x04,
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PCI_SUBCLASS_SMBUS_CONTROLLER = 0x05,
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PCI_SUBCLASS_INFINIBAND_CONTROLLER = 0x06,
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PCI_SUBCLASS_IPMI_INTERFACE = 0x07,
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PCI_SUBCLASS_SERCOS_INTERFACE = 0x08,
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PCI_SUBCLASS_CANBUS_CONTROOLLER = 0x09,
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PCI_SUBCLASS_OTHER_SERIAL_BUS_CONTROLLER = 0x80
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} pci_serial_bus_controller_subclasses_T;
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typedef enum {
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PCI_SUBCLASS_IRDA_COMPATIBLE_CONTROLLER = 0x00,
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PCI_SUBCLASS_CONSUMER_IR_CONTROLLER = 0x01,
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PCI_SUBCLASS_RF_CONTROLLER = 0x10,
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PCI_SUBCLASS_BLUETOOTH_CONTROLLER = 0x11,
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PCI_SUBCLASS_BROADBAND_CONTROLLER = 0x12,
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PCI_SUBCLASS_ETHERNET_CONTROLLER_802_1A = 0x20,
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PCI_SUBCLASS_ETHERNET_CONTROLLER_802_1B = 0x21,
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PCI_SUBCLASS_OTHER_WIRELESS_CONTROLLER = 0x80
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} pci_wireless_controller_subclasses_T;
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typedef enum {
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PCI_SUBCLASS_I20_INTELLIGENT_CONTROLLER = 0x00
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} pci_intelligent_controller_subclasses_T;
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typedef enum {
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PCI_SUBCLASS_SATELLITE_TV_CONTROLLER = 0x01,
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PCI_SUBCLASS_SATELLITE_AUDIO_CONTROLLER = 0x02,
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PCI_SUBCLASS_SATELLITE_VOICE_CONTROLLER = 0x03,
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PCI_SUBCLASS_SATELLITE_DATA_CONTROLLER = 0x04
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} pci_satellite_communication_controller_subclasses_T;
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typedef enum {
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PCI_SUBCLASS_NETWORK_AND_COMPUTING_ENCRYPTION_DECRYPTION = 0x00,
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PCI_SUBCLASS_ENTERTAINMENT_ENCRYPTION_DECRYPTION = 0x10,
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PCI_SUBCLASS_OTHER_ENCRYPTION_CONTROLLER = 0x80
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} pci_encryption_controller_subclasses_T;
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typedef enum {
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PCI_SUBCLASS_DPIO_MODULES = 0x00,
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PCI_SUBCLASS_PERFORMANCE_COUTNERS = 0x01,
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PCI_SUBCLASS_COMMUNICATION_SYNCHRONIZER = 0x10,
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PCI_SUBCLASS_SIGNAL_PROCESSING_MANAGEMENT = 0x20,
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PCI_SUBCLASS_OTHER_SIGNAL_PROCESSING_CONTROLLER = 0x80
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} pci_signal_processing_controller_subclasses_T;
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typedef enum {
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} pci_processing_accelerator_subclasses_T;
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typedef enum {
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} pci_non_essential_instrumentation_subclasses_T;
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typedef struct {
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} pci_device_T;
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void pci_init(acpi_sdt_header_T *xsdt);
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#endif
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@ -7,7 +7,8 @@
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#include "utils/memory.h"
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#include "utils/panic.h"
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acpi_fadt_T* g_acpi_table_fadt;
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acpi_sdt_header_T *g_mcfg_table;
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acpi_fadt_T *g_acpi_table_fadt;
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void acpi_init(boot_info_T* boot_info) {
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log(LOG_INFO, "Initializing ACPI - RSDP: 0x%x", boot_info->rsdp);
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@ -39,6 +40,8 @@ void acpi_init(boot_info_T* boot_info) {
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break;
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}
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}
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g_mcfg_table = acpi_find_table("MCFG");
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}
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acpi_sdt_header_T* acpi_find_table(acpi_sdt_header_T* xsdt, string_t table_id) {
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@ -0,0 +1,46 @@
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#include <drivers/pci.h>
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typedef struct {
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uint64_t config_base_address;
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uint16_t segment_group_number;
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uint8_t min_pci_bus_number;
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uint8_t max_pci_bus_number;
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uint32_t reserved;
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} __attribute__((packed)) pci_mcfg_table_entry_T;
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typedef struct{
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uint16_t device_index;
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uint16_t vendor_id;
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uint16_t status;
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uint16_t command;
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uint8_t class_code;
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uint8_t subclass;
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uint8_t prog_info_struct;
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uint8_t revision_id;
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uint8_t bist;
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uint8_t header_type;
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uint8_t latency_timer;
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uint8_t cache_line_size;
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} __attribute__((packed)) pci_config_space;
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pci_device_T *g_pci_devices;
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pci_device_T pci_decode_device(void *config_space) {
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}
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void pci_init(acpi_sdt_header_T *xsdt) {
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uint32_t num_devices = (g_mcfg_table->length - 44); // Table data length in bytes
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if(num_devices == 0) return;
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num_devices /= 16; // Each entry is 16 bytes long; get the number of entries from the number of bytes.
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pci_mcfg_table_entry_T *entries = g_mcfg_table + 44;
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g_pci_devices = memory_allocate(sizeof(pci_mcfg_table_entry_T) * num_devices);
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uint32_t device_index = 0;
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while(device_index < num_devices) {
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pci_decode_device(entries[device_index]);
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++device_index;
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}
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}
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