2023-04-25 15:13:09 +00:00
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// This file is part of noxos and licensed under the MIT open source license
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2023-04-22 01:28:42 +00:00
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2023-04-22 09:10:58 +00:00
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#ifndef NOXOS_PCI_H
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#define NOXOS_PCI_H
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2023-04-22 01:28:42 +00:00
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2023-04-25 15:13:09 +00:00
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#include "utils/stdtypes.h"
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#include "utils/string.h"
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2023-04-22 01:28:42 +00:00
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2023-04-26 19:57:18 +00:00
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typedef enum {
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PCI_CLASS_UNCLASSIFIED = 0x00,
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PCI_CLASS_MASS_STORAGE_CONTROLLER = 0x01,
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PCI_CLASS_NETWORK_CONTROLLER = 0x02,
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PCI_CLASS_DISPLAY_CONTROLLER = 0x03,
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PCI_CLASS_MULTIMEDIA_CONTROLLER = 0x04,
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PCI_CLASS_MEMORY_CONTROLLER = 0x05,
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PCI_CLASS_BRIDGE = 0x06,
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PCI_CLASS_SIMPLE_COMMUNICATION_CONTROLLER = 0x07,
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PCI_CLASS_BASE_SYSTEM_PERIPHERAL = 0x08,
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PCI_CLASS_INPUT_DEVICE_CONTROLLER = 0x09,
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PCI_CLASS_DOCKING_STATION = 0x0a,
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PCI_CLASS_PROCESSOR = 0x0b,
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PCI_CLASS_SERIAL_BUS_CONTROLLER = 0x0c,
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PCI_CLASS_WIRELESS_CONTROLLER = 0x0d,
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PCI_CLASS_INTELLIGENT_CONTROLLER = 0x0e,
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PCI_CLASS_SATELLITE_COMMUNICATION_CONTROLLER = 0x0f,
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PCI_CLASS_ENCRYPTION_CONTROLLER = 0x10,
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PCI_CLASS_SIGNAL_PROCESSING_CONTROLLER = 0x11,
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PCI_CLASS_PROCESSING_ACCELERATOR = 0x12,
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PCI_CLASS_NON_ESSENTIAL_INSTRUMENTATION = 0x13,
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PCI_CLASS_COPROCESSOR = 0x40
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} pci_class_E;
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typedef enum {
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PCI_SUBCLASS_NON_VGA_COMPATIBLE_UNCLASSIFIED_DEVICE = 0x00,
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PCI_SUBCLASS_VGA_COMPATIBLE_UNCLASSIFIED_DEVICE = 0x01
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} pci_unclassified_sublasses_E;
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typedef enum {
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PCI_SUBCLASS_SCSI_BUS_CONTROLLER = 0x00,
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PCI_SUBCLASS_IDE_CONTROLLER = 0x01,
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PCI_SUBCLASS_FLOPPY_DISK_CONTROLLER = 0x02,
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PCI_SUBCLASS_IPI_BUS_CONTROLLER = 0x03,
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PCI_SUBCLASS_RAID_CONTROLLER = 0x04,
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PCI_SUBCLASS_ATA_CONTROLLER = 0x05,
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PCI_SUBCLASS_SERIAL_ATA_CONTROLLER = 0x06,
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PCI_SUBCLASS_SERIAL_ATTACHED_SCSI_CONTROLLER = 0x07,
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PCI_SUBCLASS_NON_VOLATILE_MEMORY_CONTROLLER = 0x08,
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PCI_SUBCLASS_OTHER_MASS_STORAGE_CONTROLLER = 0x80
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} pci_mass_storage_controller_subclasses_E;
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typedef enum {
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PCI_SUBCLASS_ETHERNET_CONTROLLER = 0x00,
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PCI_SUBCLASS_TOKEN_RING_CONTROLLER = 0x01,
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PCI_SUBCLASS_FDDI_CONTROLLER = 0x02,
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PCI_SUBCLASS_ATM_CONTROLLER = 0x03,
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PCI_SUBCLASS_ISDN_CONTROLLER = 0x04,
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PCI_SUBCLASS_WORLDFIP_CONTROLLER = 0x05,
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PCI_SUBCLASS_PICMG_2_14_MULTI_COMPUTING_CONTROLLER = 0x06,
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PCI_SUBCLASS_INFINIBAND_NETWORKCONTROLLER = 0x07,
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PCI_SUBCLASS_FABRIC_CONTROLLER = 0x08,
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PCI_SUBCLASS_OTHER_NETWORK_CONTROLLER = 0x80
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} pci_network_controller_subclasses_E;
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typedef enum {
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PCI_SUBCLASS_VGA_COMPATIBLE_CONTROLLER = 0x00,
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PCI_SUBCLASS_XGA_COMPATIBLE_CONTROLLER = 0x01,
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PCI_SUBCLASS_3D_CONTROLLER_NOT_VGA_COMPATIBLE = 0x02,
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PCI_SUBCLASS_OTHER_DISPLAY_CONTROLLER = 0x80
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} pci_display_controller_subclasses_E;
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typedef enum {
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PCI_SUBCLASS_MULTIMEDIA_VIDEO_CONTROLLER = 0x00,
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PCI_SUBCLASS_MULTIMEDIA_AUDIO_CONTROLLER = 0x01,
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PCI_SUBCLASS_COMPUTER_TELEPHONY_DEVICE = 0x02,
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PCI_SUBCLASS_AUDIO_DEVICE = 0x03,
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PCI_SUBCLASS_OTHER_MULTIMEDIA_CONTROLLER = 0x80
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} pci_multimedia_controller_subclasses_E;
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typedef enum {
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PCI_SUBCLASS_RAM_CONTROLLER = 0x00,
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PCI_SUBCLASS_FLASH_CONTROLLER = 0x01,
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PCI_SUBCLASS_OTHER_MEMORY_CONTROLLER = 0x80
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} pci_memory_controller_subclasses_E;
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typedef enum {
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PCI_SUBCLASS_HOST_BRIDGE = 0x00,
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PCI_SUBCLASS_ISA_BRIDGE = 0x01,
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PCI_SUBCLASS_EISA_BRIDGE = 0x02,
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PCI_SUBCLASS_MCA_BRIDGE = 0x03,
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PCI_SUBCLASS_PCI_TO_PCI_BRIDGE = 0x04,
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PCI_SUBCLASS_PCMCIA_BRIDGE = 0x05,
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PCI_SUBCLASS_NUBUS_BRIDGE = 0x06,
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PCI_SUBCLASS_CARDBUS_BRIDGE = 0x07,
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PCI_SUBCLASS_RACEWAY_BRIDGE = 0x08,
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PCI_SUBCLASS_PCI_TO_PCI_BRIDGE_2 = 0x09,
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PCI_SUBCLASS_INFINIBAND_TO_PCI_HOST_BRIDGE = 0x0a,
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PCI_SUBCLASS_OTHER_BRIDGE = 0x80
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} pci_bridge_subclasses_E;
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typedef enum {
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PCI_SUBCLASS_SERIAL_SIMPLE_COMMUNICATION_CONTROLLER = 0x00,
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PCI_SUBCLASS_PARALLEL_SIMPLE_COMMUNICATION_CONTROLLER = 0x01,
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PCI_SUBCLASS_MULTIPORT_SERIAL_CONTROLLER = 0x02,
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PCI_SUBCLASS_MODEM = 0x03,
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PCI_SUBCLASS_IEEE_488_1_2_GPIB_CONTROLLER = 0x04,
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PCI_SUBCLASS_SMART_CARD_CONTROLLER = 0x05,
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PCI_SUBCLASS_OTHER_SIMPLE_COMMUNICATION_CONTROLLER = 0x80
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} pci_simple_communication_controller_subclasses_E;
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typedef enum {
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PCI_SUBCLASS_PIC = 0x00,
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PCI_SUBCLASS_DMA_CONTROLLER = 0x01,
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PCI_SUBCLASS_TIMER = 0x02,
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PCI_SUBCLASS_RTC_CONTROLLER = 0x03,
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PCI_SUBCLASS_PCI_HOT_PLUG_CONTROLLER = 0x04,
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PCI_SUBCLASS_SD_HOST_CONTROLLER = 0x05,
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PCI_SUBCLASS_IOMMU = 0x06,
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PCI_SUBCLASS_OTHER_BASE_SYSTEM_PERIPHERAL = 0x80
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} pci_base_system_peripheral_subclasses_E;
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typedef enum {
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PCI_SUBCLASS_KEYBOARD_CONTROLLER = 0x00,
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PCI_SUBCLASS_DIGITIZER_PEN = 0x01,
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PCI_SUBCLASS_MOUSE_CONTROLLER = 0x02,
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PCI_SUBCLASS_SCANNER_CONTROLLER = 0x03,
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PCI_SUBCLASS_GAMEPORT_CONTROLLER = 0x04,
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PCI_SUBCLASS_OTHER_INPUT_DEVICE_CONTROLLER = 0x80
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} pci_input_device_controller_subclasses_E;
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typedef enum {
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PCI_SUBCLASS_GENERIC_DOCKING_STATION = 0x00,
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PCI_SUBCLASS_OTHER_DOCKING_STATION = 0x80
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} pci_docking_station_subclasses_E;
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typedef enum {
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PCI_SUBCLASS_386_PROCESSOR = 0x00,
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PCI_SUBCLASS_486_PROCESSOR = 0x01,
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PCI_SUBCLASS_PENTIUM_PROCESSOR = 0x02,
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PCI_SUBCLASS_PENTIUM_PRO_PROCESSOR = 0x03,
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PCI_SUBCLASS_ALPHA_PROCESSOR = 0x10,
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PCI_SUBCLASS_POWERPC_PROCESSOR = 0x20,
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PCI_SUBCLASS_MIPS_PROCESSOR = 0x30,
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PCI_SUBCLASS_COPROCESSOR = 0x40,
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PCI_SUBCLASS_OTHER_PROCESSOR = 0x80
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} pci_processor_subclasses_E;
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typedef enum {
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PCI_SUBCLASS_FIREWIRE_CONTROLLER = 0x00,
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PCI_SUBCLASS_ACCESS_BUS_CONTROLLER = 0x01,
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PCI_SUBCLASS_SSA = 0x02,
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PCI_SUBCLASS_USB_CONTROLLER = 0x03,
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PCI_SUBCLASS_FIBRE_CHANNEL = 0x04,
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PCI_SUBCLASS_SMBUS_CONTROLLER = 0x05,
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PCI_SUBCLASS_INFINIBAND_SERIAL_BUS_CONTROLLER = 0x06,
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PCI_SUBCLASS_IPMI_INTERFACE = 0x07,
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PCI_SUBCLASS_SERCOS_INTERFACE = 0x08,
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2023-04-25 20:28:10 +00:00
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PCI_SUBCLASS_CANBUS_CONTROLLER = 0x09,
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2023-04-26 19:57:18 +00:00
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PCI_SUBCLASS_OTHER_SERIAL_BUS_CONTROLLER = 0x80
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} pci_serial_bus_controller_subclasses_E;
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typedef enum {
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PCI_SUBCLASS_IRDA_COMPATIBLE_CONTROLLER = 0x00,
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PCI_SUBCLASS_CONSUMER_IR_CONTROLLER = 0x01,
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PCI_SUBCLASS_RF_CONTROLLER = 0x10,
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PCI_SUBCLASS_BLUETOOTH_CONTROLLER = 0x11,
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PCI_SUBCLASS_BROADBAND_CONTROLLER = 0x12,
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PCI_SUBCLASS_ETHERNET_CONTROLLER_802_1A = 0x20,
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PCI_SUBCLASS_ETHERNET_CONTROLLER_802_1B = 0x21,
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PCI_SUBCLASS_OTHER_WIRELESS_CONTROLLER = 0x80
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} pci_wireless_controller_subclasses_E;
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typedef enum {
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PCI_SUBCLASS_I20_INTELLIGENT_CONTROLLER = 0x00
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} pci_intelligent_controller_subclasses_E;
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typedef enum {
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PCI_SUBCLASS_SATELLITE_TV_CONTROLLER = 0x01,
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PCI_SUBCLASS_SATELLITE_AUDIO_CONTROLLER = 0x02,
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PCI_SUBCLASS_SATELLITE_VOICE_CONTROLLER = 0x03,
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PCI_SUBCLASS_SATELLITE_DATA_CONTROLLER = 0x04
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} pci_satellite_communication_controller_subclasses_E;
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typedef enum {
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PCI_SUBCLASS_NETWORK_AND_COMPUTING_ENCRYPTION_DECRYPTION = 0x00,
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PCI_SUBCLASS_ENTERTAINMENT_ENCRYPTION_DECRYPTION = 0x10,
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PCI_SUBCLASS_OTHER_ENCRYPTION_CONTROLLER = 0x80
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} pci_encryption_controller_subclasses_E;
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typedef enum {
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PCI_SUBCLASS_DPIO_MODULES = 0x00,
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2023-04-25 20:28:10 +00:00
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PCI_SUBCLASS_PERFORMANCE_COUNTERS = 0x01,
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2023-04-26 19:57:18 +00:00
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PCI_SUBCLASS_COMMUNICATION_SYNCHRONIZER = 0x10,
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PCI_SUBCLASS_SIGNAL_PROCESSING_MANAGEMENT = 0x20,
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PCI_SUBCLASS_OTHER_SIGNAL_PROCESSING_CONTROLLER = 0x80
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} pci_signal_processing_controller_subclasses_E;
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2023-04-25 15:13:09 +00:00
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typedef struct {
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uint16_t vendor_id;
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uint16_t device_id;
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uint16_t command_reg;
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uint16_t status_reg;
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uint8_t revision_id;
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uint8_t progif; // Programming Interface Byte
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uint8_t subclass;
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uint8_t main_class;
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uint8_t cache_line_size;
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uint8_t latency_timer;
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uint8_t header_type;
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uint8_t bist; // Built-in Self-Test
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} __attribute__((packed)) pci_device_header_T;
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2023-04-22 01:28:42 +00:00
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2023-04-25 15:13:09 +00:00
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typedef struct {
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pci_device_header_T header;
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uint32_t bar0;
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uint32_t bar1;
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uint32_t bar2;
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uint32_t bar3;
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uint32_t bar4;
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uint32_t bar5;
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uint32_t cardbus_cis_pointer;
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uint16_t subsystem_vendor_id;
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uint16_t subsystem_id;
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uint32_t expansion_rom_base_address;
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uint8_t capabilities;
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uint8_t reserved[7];
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uint8_t interrupt_line;
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uint8_t interrupt_pin;
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uint8_t min_grant;
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uint8_t max_latency;
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} __attribute__((packed)) pci_header_0_T;
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2023-04-25 21:03:03 +00:00
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typedef struct pci_device_T pci_device_T;
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struct pci_device_T {
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pci_device_header_T* header;
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2023-05-04 11:28:55 +00:00
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void* specific;
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2023-04-25 21:03:03 +00:00
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pci_device_T* prev;
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pci_device_T* next;
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};
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typedef struct {
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pci_device_T* devices;
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} pci_manager_T;
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void pci_init ();
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void pci_manager_add_device (pci_device_header_T* header);
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void pci_manager_remove_device (pci_device_T* device);
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pci_device_T* pci_manager_find_device (pci_class_E class, uint8_t subclass, uint8_t progif);
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void pci_manager_dump_devices ();
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string_t pci_get_subclass_string (pci_class_E class, uint8_t subclass);
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string_t pci_get_vendor_string (uint16_t vendor_id);
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2023-04-25 15:13:09 +00:00
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#endif // NOXOS_PCI_H
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