noxos (docs): documented logger DEBUG macro and PCI
This commit is contained in:
parent
5a4c42635c
commit
82228306c8
|
@ -0,0 +1,80 @@
|
||||||
|
---
|
||||||
|
title: pci.h
|
||||||
|
summary: PCI bus stuff
|
||||||
|
---
|
||||||
|
|
||||||
|
# Class and subclasses enums
|
||||||
|
All these enums are not documented in here, because they are basically just the definitions matching the PCI device main and sub classes.
|
||||||
|
A [list of these (sub)classes](https://wiki.osdev.org/PCI#Class_Codes) can be found in the osdev wiki.
|
||||||
|
|
||||||
|
# `pci_device_header_T` - struct
|
||||||
|
| Name | Type | Description |
|
||||||
|
|-----------------|----------|------------------------------------------------------------------------------------------------------------------------------|
|
||||||
|
| vendor_id | uint16_t | The Device manufacturers ID number |
|
||||||
|
| device_id | uint16_t | The devices ID number |
|
||||||
|
| command_reg | uint16_t | Provides control over a device's ability to generate and respond to PCI cycles. |
|
||||||
|
| status | uint16_t | The status register PCI bus related events |
|
||||||
|
| revision_id | uint8_t | The devices revision ID number |
|
||||||
|
| progif | uint8_t | Programming Interface Byte. This can specify special programming interfaces. |
|
||||||
|
| subclass | uint8_t | The special function that the device performs. |
|
||||||
|
| main_class | uint8_t | The general function class, which the device operates in. |
|
||||||
|
| cache_line_size | uint8_t | Specifies the system cache line size in 32-bit units. |
|
||||||
|
| latency_timer | uint8_t | Specifies the latency timer in units of PCI bus clocks. |
|
||||||
|
| header_type | uint8_t | Specifies whether the device is a general device or a bridge. This affects the data representation that follows this header. |
|
||||||
|
| bist | uint8_t | Built-In-Self-Test status and control. |
|
||||||
|
|
||||||
|
# `pci_header_0_T` - struct
|
||||||
|
| Name | Type | Description |
|
||||||
|
|----------------------------|---------------------|-------------------------------------------------------------------------------------------------|
|
||||||
|
| header | pci_device_header_T | The devices base header |
|
||||||
|
| bar0 | uint32_t | Base address 0 |
|
||||||
|
| bar1 | uint32_t | Base address 1 |
|
||||||
|
| bar2 | uint32_t | Base address 2 |
|
||||||
|
| bar3 | uint32_t | Base address 3 |
|
||||||
|
| bar4 | uint32_t | Base address 4 |
|
||||||
|
| bar5 | uint32_t | Base address 5 |
|
||||||
|
| cardbus_cis_pointer | uint32_t | Used by devices that share silicon between CardBus and PCI. |
|
||||||
|
| subsystem_vendor_id | uint16_t | idk, but probably not that important |
|
||||||
|
| subsystem_id | uint16_t | idk, but probably not that important |
|
||||||
|
| expansion_rom_base_address | uint32_t | An optional max 16MB ROM BAR. |
|
||||||
|
| capabilities | uint8_t | An offset in the devices config space that points to a linked list of implemented capabilities. |
|
||||||
|
| reserved | uint8_t[7] | Reserved. |
|
||||||
|
| interrupt_line | uint8_t | The devices interrupt IRQ. |
|
||||||
|
| interrupt_pin | uint8_t | The devices interrupt pin. |
|
||||||
|
| min_grant | uint8_t | Specifies the burst period length, in 1/4 microsecond units, that the device needs. |
|
||||||
|
| max_latency | uint8_t | Specifies how often the device needs access to the PCI bus (in 1/4 microsecond units). |
|
||||||
|
|
||||||
|
# `pci_device_T` - struct
|
||||||
|
| Name | Type | Description |
|
||||||
|
|--------|----------------------|-------------------------|
|
||||||
|
| header | pci_device_header_T* | The devices base header |
|
||||||
|
| prev | pci_device_T* | The previous device. |
|
||||||
|
| next | pci_device_T* | The next device. |
|
||||||
|
|
||||||
|
# `pci_manager_T` - struct
|
||||||
|
| Name | Type | Description |
|
||||||
|
|---------|---------------|-----------------------------------------------|
|
||||||
|
| devices | pci_device_T* | The linked list of devices connected via PCI. |
|
||||||
|
|
||||||
|
# `pci_init()` - function (void)
|
||||||
|
Initializes the global PCI manager and enumerates the PCI bus.
|
||||||
|
This needs to be called after `acpi_init`, because it uses the _MCFG_ table.
|
||||||
|
|
||||||
|
# `pci_manager_add_device(header*)` - function (void)
|
||||||
|
Adds a device to the global PCI manager.
|
||||||
|
This should only be called by the PCI enumerator.
|
||||||
|
|
||||||
|
# `pci_manager_remove_device(device*)` - function (void)
|
||||||
|
Removes a device from the global PCI manager, and frees it resources in the manager.
|
||||||
|
|
||||||
|
# `pci_manager_find_device(class, subclass, progif)` - function (pci_device_T*)
|
||||||
|
Returns the first device with **_class_**, **_subclass_** and **_progif_** that is defined in the global PCI manager.
|
||||||
|
|
||||||
|
# `pci_manager_dump_devices()` - function (void)
|
||||||
|
Logs a list of all registered PCI devices.
|
||||||
|
|
||||||
|
# `pci_get_subclass_string(class, subclass)` - function (string_t)
|
||||||
|
Returns the Name of **_class_** + **_subclass_**.
|
||||||
|
|
||||||
|
# `pci_get_vendor_string(vendor_id)` - function (string_t)
|
||||||
|
Returns the name of the vendor.
|
|
@ -3,6 +3,10 @@ title: "logger.h"
|
||||||
summary: "functionalities to write logs to QEMU's serial port."
|
summary: "functionalities to write logs to QEMU's serial port."
|
||||||
---
|
---
|
||||||
|
|
||||||
|
# `DEBUG(string, ...)` - macro
|
||||||
|
calls `log` with log_level _Debug_.
|
||||||
|
Puts filename and line number in front of the format text.
|
||||||
|
|
||||||
# `log_level_E` - enum
|
# `log_level_E` - enum
|
||||||
- **None** - Logs just the message without a prefix
|
- **None** - Logs just the message without a prefix
|
||||||
- **Info** - General information, that could be useful
|
- **Info** - General information, that could be useful
|
||||||
|
|
Reference in New Issue