444 lines
12 KiB
C
Executable File
444 lines
12 KiB
C
Executable File
/*
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* s2mu004_charger.h - Header of S2MU004 Charger Driver
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*
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* Copyright (C) 2016 Samsung Electronics Co.Ltd
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef S2MU004_CHARGER_H
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#define S2MU004_CHARGER_H
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#include <linux/mfd/samsung/s2mu004.h>
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#include <linux/mfd/samsung/s2mu004-private.h>
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#if defined(CONFIG_MUIC_NOTIFIER)
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#include <linux/muic/muic.h>
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#include <linux/muic/muic_notifier.h>
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#endif /* CONFIG_MUIC_NOTIFIER */
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//#include <linux/muic/s2mu004-muic.h>
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#include <linux/power/s2mu00x_battery.h>
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#define MASK(width, shift) (((0x1 << (width)) - 1) << shift)
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#define S2MU004_CHG_STATUS0 0x0A
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#define S2MU004_CHG_STATUS1 0x0B
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#define S2MU004_CHG_STATUS2 0x0C
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#define S2MU004_CHG_STATUS3 0x0D
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#define S2MU004_CHG_STATUS4 0x0E
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#define S2MU004_CHG_STATUS5 0x0F
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#define S2MU004_CHG_CTRL0 0x10
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#define S2MU004_CHG_CTRL1 0x11
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#define S2MU004_CHG_CTRL2 0x12
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#define S2MU004_CHG_CTRL3 0x13
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#define S2MU004_CHG_CTRL4 0x14
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#define S2MU004_CHG_CTRL5 0x15
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#define S2MU004_CHG_CTRL6 0x16
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#define S2MU004_CHG_CTRL7 0x17
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#define S2MU004_CHG_CTRL8 0x18
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#define S2MU004_CHG_CTRL9 0x19
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#define S2MU004_CHG_CTRL10 0x1A
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#define S2MU004_CHG_CTRL11 0x1B
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#define S2MU004_CHG_CTRL12 0x1C
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#define S2MU004_CHG_CTRL13 0x1D
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#define S2MU004_CHG_CTRL14 0x1E
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#define S2MU004_CHG_CTRL15 0x1F
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#define S2MU004_CHG_CTRL16 0x20
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#define S2MU004_CHG_CTRL17 0x21
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#define S2MU004_CHG_CTRL18 0x22
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#define S2MU004_CHG_CTRL19 0x23
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#define S2MU004_CHG_CTRL20 0x24
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#define S2MU004_PWRSEL_CTRL0 0x72
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#define PWRSEL_CTRL0_SHIFT 7
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#define PWRSEL_CTRL0_WIDTH 1
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#define PWRSEL_CTRL0_MASK MASK(PWRSEL_CTRL0_WIDTH, PWRSEL_CTRL0_SHIFT)
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#define EN_JIG_REG_AP_SHIFT 7
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#define EN_JIG_REG_AP_WIDTH 1
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#define EN_JIG_REG_AP_MASK MASK(EN_JIG_REG_AP_WIDTH, EN_JIG_REG_AP_SHIFT)
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/* S2MU004_SC_INT_MASK */
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#define Poor_CHG_INT_SHIFT 1
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#define Poor_CHG_INT_MASK BIT(Poor_CHG_INT_SHIFT)
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/* S2MU004_CHG_STATUS0 */
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#define FG_SOC_STATUS_SHIFT 0
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#define FG_SOC_STATUS_WIDTH 2
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#define FG_SOC_STATUS_MASK MASK(FG_SOC_STATUS_WIDTH, FG_SOC_STATUS_SHIFT)
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#define WCIN_STATUS_SHIFT 2
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#define WCIN_STATUS_WIDTH 3
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#define WCIN_STATUS_MASK MASK(WCIN_STATUS_WIDTH, WCIN_STATUS_SHIFT)
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#define WCIN_M_SHIFT 6
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#define WCIN_M_MASK BIT(WCIN_M_SHIFT)
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#define CHGIN_STATUS_SHIFT 5
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#define CHGIN_STATUS_WIDTH 3
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#define CHGIN_STATUS_MASK MASK(CHGIN_STATUS_WIDTH, CHGIN_STATUS_SHIFT)
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#define VBUS_OVP_MASK 0xE0
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#define VBUS_OVP_SHIFT 5
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/* S2MU004_CHG_STATUS1 */
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#define SELF_DISCHG_STATUS_SHIFT 7
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#define SELF_DISCHG_STATUS_MASK BIT(SELF_DISCHG_STATUS_SHIFT)
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#define CHG_FAULT_STATUS_SHIFT 3
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#define CHG_FAULT_STATUS_WIDTH 4
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#define CHG_FAULT_STATUS_MASK MASK(CHG_FAULT_STATUS_WIDTH,\
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CHG_FAULT_STATUS_SHIFT)
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#define CHG_STATUS_PRE_CHARGE 1
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#define CHG_STATUS_FAST_CHARGE 2
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#define CHG_STATUS_WD_SUSPEND 3
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#define CHG_STATUS_WD_RST 4
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#define CHG_STATUS_TSD 5
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#define CHG_STATUS_TFB 6
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#define CHG_Restart_STATUS_SHIFT 2
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#define CHG_Restart_STATUS_MASK BIT(CHG_Restart_STATUS_SHIFT)
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#define TOP_OFF_STATUS_SHIFT 1
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#define TOP_OFF_STATUS_MASK BIT(TOP_OFF_STATUS_SHIFT)
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#define DONE_STATUS_SHIFT 0
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#define DONE_STATUS_MASK BIT(DONE_STATUS_SHIFT)
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/* S2MU004_CHG_STATUS2 */
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#define OTG_STATUS_SHIFT 5
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#define OTG_STATUS_WIDTH 3
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#define OTG_STATUS_MASK MASK(OTG_STATUS_WIDTH, OTG_STATUS_SHIFT)
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#define TX_STATUS_SHIFT 2
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#define TX_STATUS_WIDTH 3
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#define TX_STATUS_MASK MASK(TX_STATUS_WIDTH, TX_STATUS_SHIFT)
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#define SYS_STATUS_SHIFT 2
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#define SYS_STATUS_WIDTH 3
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#define SYS_STATUS_MASK MASK(SYS_STATUS_WIDTH, SYS_STATUS_SHIFT)
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/* S2MU004_CHG_STATUS3 */
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#define DET_BAT_STATUS_SHIFT 0
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#define DET_BAT_STATUS_MASK BIT(DET_BAT_STATUS_SHIFT)
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#define BAT_STATUS_SHIFT 1
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#define BAT_STATUS_WIDTH 2
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#define BAT_STATUS_MASK MASK(BAT_STATUS_WIDTH, BAT_STATUS_SHIFT)
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#define AICL_STATUS_SHIFT 4
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#define AICL_STATUS_WIDTH 2
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#define AICL_STATUS_MASK MASK(AICL_STATUS_WIDTH, AICL_STATUS_SHIFT)
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#define ICR_STATUS_SHIFT 6
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#define ICR_STATUS_MASK BIT(ICR_STATUS_SHIFT)
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#define IVR_STATUS_SHIFT 7
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#define IVR_STATUS_MASK BIT(IVR_STATUS_SHIFT)
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/* S2MU004_CHG_CTRL0 */
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#define EN_CHG_SHIFT 7
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#define EN_CHG_MASK BIT(EN_CHG_SHIFT)
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#define REG_MODE_SHIFT 0
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#define REG_MODE_WIDTH 4
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#define REG_MODE_MASK MASK(REG_MODE_WIDTH, REG_MODE_SHIFT)
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#define CHARGER_OFF_MODE 0
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#define CHG_MODE 3
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#define BUCK_MODE 1
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#define OTG_BST_MODE 6
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/* S2MU004_CHG_CTRL1 */
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/* S2MU004_CHG_CTRL2 */
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#define INPUT_CURRENT_LIMIT_SHIFT 0
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#define INPUT_CURRENT_LIMIT_WIDTH 7
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#define INPUT_CURRENT_LIMIT_MASK MASK(INPUT_CURRENT_LIMIT_WIDTH,\
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INPUT_CURRENT_LIMIT_SHIFT)
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/* S2MU004_CHG_CTRL4 */
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#define OTG_OCP_SW_ON_SHIFT 5
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#define OTG_OCP_SW_ON_MASK BIT(OTG_OCP_SW_ON_SHIFT)
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#define OTG_OCP_SW_OFF_SHIFT 4
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#define OTG_OCP_SW_OFF_MASK BIT(OTG_OCP_SW_OFF_SHIFT)
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#define SET_OTG_OCP_SHIFT 2
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#define SET_OTG_OCP_WIDTH 2
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#define SET_OTG_OCP_MASK MASK(SET_OTG_OCP_WIDTH, SET_OTG_OCP_SHIFT)
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/* S2MU004_CHG_CTRL5 */
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#define SET_CHG_2L_DROP_SHIFT 4
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#define SET_CHG_2L_DROP_WIDTH 2
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#define SET_CHG_2L_DROP_MASK MASK(SET_CHG_2L_DROP_WIDTH,\
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SET_CHG_2L_DROP_SHIFT)
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#define SET_CHG_3L_DROP_SHIFT 6
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#define SET_CHG_3L_DROP_WIDTH 2
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#define SET_CHG_3L_DROP_MASK MASK(SET_CHG_3L_DROP_WIDTH,\
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SET_CHG_3L_DROP_SHIFT)
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/* S2MU004_CHG_CTRL6 */
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#define SET_VF_VBAT_SHIFT 0
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#define SET_VF_VBAT_WIDTH 6
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#define SET_VF_VBAT_MASK MASK(SET_VF_VBAT_WIDTH, SET_VF_VBAT_SHIFT)
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/* S2MU004_CHG_CTRL7 */
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#define SET_VF_VBYP_SHIFT 5
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#define SET_VF_VBYP_WIDTH 2
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#define SET_VF_VBYP_MASK MASK(SET_VF_VBYP_WIDTH, SET_VF_VBYP_SHIFT)
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#define SET_VSYS_SHIFT 0
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#define SET_VSYS_WIDTH 3
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#define SET_VSYS_MASK MASK(SET_VSYS_WIDTH, SET_VSYS_SHIFT)
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/* S2MU004_CHG_CTRL8 */
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#define COOL_CHARGING_CURRENT_SHIFT 0
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#define COOL_CHARGING_CURRENT_WIDTH 7
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#define COOL_CHARGING_CURRENT_MASK MASK(COOL_CHARGING_CURRENT_WIDTH,\
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COOL_CHARGING_CURRENT_SHIFT)
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/* S2MU004_CHG_CTRL9 */
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#define FAST_CHARGING_CURRENT_SHIFT 0
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#define FAST_CHARGING_CURRENT_WIDTH 7
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#define FAST_CHARGING_CURRENT_MASK MASK(FAST_CHARGING_CURRENT_WIDTH,\
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FAST_CHARGING_CURRENT_SHIFT)
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/* S2MU004_CHG_CTRL11 */
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#define FIRST_TOPOFF_CURRENT_SHIFT 0
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#define FIRST_TOPOFF_CURRENT_WIDTH 4
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#define FIRST_TOPOFF_CURRENT_MASK MASK(FIRST_TOPOFF_CURRENT_WIDTH,\
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FIRST_TOPOFF_CURRENT_SHIFT)
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#define SECOND_TOPOFF_CURRENT_SHIFT 4
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#define SECOND_TOPOFF_CURRENT_WIDTH 4
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#define SECOND_TOPOFF_CURRENT_MASK MASK(SECOND_TOPOFF_CURRENT_WIDTH,\
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SECOND_TOPOFF_CURRENT_SHIFT)
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/* S2MU004_CHG_CTRL12 */
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#define SET_OSC_BUCK_SHIFT 0
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#define SET_OSC_BUCK_WIDTH 3
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#define SET_OSC_BUCK_MASK MASK(SET_OSC_BUCK_WIDTH,\
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SET_OSC_BUCK_SHIFT)
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#define SET_OSC_BUCK_3L_SHIFT 3
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#define SET_OSC_BUCK_3L_WIDTH 3
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#define SET_OSC_BUCK_3L_MASK MASK(SET_OSC_BUCK_3L_WIDTH,\
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SET_OSC_BUCK_3L_SHIFT)
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enum {
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S2MU004_OSC_BUCK_FRQ_500kHz = 0x0,
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S2MU004_OSC_BUCK_FRQ_750kHz = 0x1,
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S2MU004_OSC_BUCK_FRQ_1MHz = 0x2,
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S2MU004_OSC_BUCK_FRQ_1P25MHz = 0x3,
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S2MU004_OSC_BUCK_FRQ_1P5MHz = 0x4,
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S2MU004_OSC_BUCK_FRQ_1P75MHz = 0x5,
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S2MU004_OSC_BUCK_FRQ_2MHz = 0x6,
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S2MU004_OSC_BUCK_FRQ_2P25MHz = 0x7,
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};
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/* S2MU004_CHG_CTRL13 */
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#define SET_IVR_Recovery_SHIFT 5
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#define SET_IVR_Recovery_MASK BIT(SET_IVR_Recovery_SHIFT)
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#define SET_EN_WDT_SHIFT 1
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#define SET_EN_WDT_MASK BIT(SET_EN_WDT_SHIFT)
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#define SET_EN_WDT_AP_RESET_SHIFT 0
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#define SET_EN_WDT_AP_RESET_MASK BIT(SET_EN_WDT_AP_RESET_SHIFT)
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/* S2MU004_CHG_CTRL14 */
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#define WDT_CLR_SHIFT 0
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#define WDT_CLR_MASK BIT(WDT_CLR_SHIFT)
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/* S2MU004_CHG_CTRL15 */
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#define SET_OSC_BST_SHIFT 5
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#define SET_OSC_BST_WIDTH 3
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#define SET_OSC_BST_MASK MASK(SET_OSC_BST_WIDTH, SET_OSC_BST_SHIFT)
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/* S2MU004_CHG_CTRL16 */
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#define SET_TIME_CHG_SHIFT 3
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#define SET_TIME_CHG_WIDTH 3
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#define SET_TIME_CHG_MASK MASK(SET_TIME_CHG_WIDTH, SET_TIME_CHG_SHIFT)
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/* S2MU004_CHG_CTRL17 */
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#define TOP_OFF_TIME_SHIFT 3
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#define TOP_OFF_TIME_WIDTH 3
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#define TOP_OFF_TIME_MASK MASK(TOP_OFF_TIME_WIDTH, TOP_OFF_TIME_SHIFT)
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#define WDT_TIME_SHIFT 0
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#define WDT_TIME_WIDTH 3
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#define WDT_TIME_MASK MASK(WDT_TIME_WIDTH, WDT_TIME_SHIFT)
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/* S2MU004_CHG_CTRL18 */
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#define CHGIN_ON_SHIFT 2
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#define CHGIN_ON_WIDTH 2
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#define CHGIN_ON_MASK MASK(CHGIN_ON_WIDTH, CHGIN_ON_SHIFT)
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/* S2MU005_REG_SELFDIS_CFG1 */
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#define FC_SELF_DISCHG_SHIFT 3
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#define FC_SELF_DISCHG_MASK BIT(FC_SELF_DISCHG_SHIFT)
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/* S2MU004_REG_SELFDIS_CFG3 */
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#define SELF_DISCHG_MODE_SHIFT 7
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#define SELF_DISCHG_MODE_MASK BIT(SELF_DISCHG_MODE_SHIFT)
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#define FAKE_BAT_LEVEL 50
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enum {
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CHIP_ID = 0,
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};
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ssize_t s2mu004_chg_show_attrs(struct device *dev,
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struct device_attribute *attr, char *buf);
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ssize_t s2mu004_chg_store_attrs(struct device *dev,
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struct device_attribute *attr, const char *buf, size_t count);
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#define S2MU004_CHARGER_ATTR(_name) \
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{ \
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.attr = {.name = #_name, .mode = 0664}, \
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.show = s2mu004_chg_show_attrs, \
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.store = s2mu004_chg_store_attrs, \
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}
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enum {
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CHG_REG = 0,
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CHG_DATA,
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CHG_REGS,
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};
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enum {
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S2MU004_TOPOFF_TIMER_500us = 0x0,
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S2MU004_TOPOFF_TIMER_5m = 0x1,
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S2MU004_TOPOFF_TIMER_10m = 0x2,
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S2MU004_TOPOFF_TIMER_30m = 0x3,
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S2MU004_TOPOFF_TIMER_50m = 0x4,
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S2MU004_TOPOFF_TIMER_70m = 0x5,
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S2MU004_TOPOFF_TIMER_90m = 0x6,
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S2MU004_TOPOFF_TIMER_DIS = 0x7,
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};
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enum {
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S2MU004_WDT_TIMER_40s = 0x1,
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S2MU004_WDT_TIMER_50s = 0x2,
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S2MU004_WDT_TIMER_60s = 0x3,
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S2MU004_WDT_TIMER_70s = 0x4,
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S2MU004_WDT_TIMER_80s = 0x5,
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S2MU004_WDT_TIMER_90s = 0x6,
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S2MU004_WDT_TIMER_100s = 0x7,
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};
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enum {
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S2MU004_FC_CHG_TIMER_4hr = 0x1,
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S2MU004_FC_CHG_TIMER_6hr = 0x2,
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S2MU004_FC_CHG_TIMER_8hr = 0x3,
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S2MU004_FC_CHG_TIMER_10hr = 0x4,
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S2MU004_FC_CHG_TIMER_12hr = 0x5,
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S2MU004_FC_CHG_TIMER_14hr = 0x6,
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S2MU004_FC_CHG_TIMER_16hr = 0x7,
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};
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enum {
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S2MU004_SET_OTG_OCP_500mA = 0x0,
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S2MU004_SET_OTG_OCP_900mA = 0x1,
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S2MU004_SET_OTG_OCP_1200mA = 0x2,
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S2MU004_SET_OTG_OCP_1500mA = 0x3,
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};
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typedef struct s2mu004_charger_platform_data {
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s2mu00x_charging_current_t *charging_current_table;
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s2mu00x_charging_current_t *charging_current;
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int chg_float_voltage;
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char *charger_name;
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char *fuelgauge_name;
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bool chg_eoc_dualpath;
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int recharge_vcell;
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uint32_t is_1MHz_switching:1;
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int chg_switching_freq;
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} s2mu004_charger_platform_data_t;
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struct s2mu004_charger_data {
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struct i2c_client *i2c;
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struct device *dev;
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struct s2mu004_platform_data *s2mu004_pdata;
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struct delayed_work charger_work;
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struct delayed_work otg_vbus_work;
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struct workqueue_struct *charger_wqueue;
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struct power_supply *psy_chg;
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struct power_supply_desc psy_chg_desc;
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struct power_supply *psy_otg;
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struct power_supply_desc psy_otg_desc;
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s2mu004_charger_platform_data_t *pdata;
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int dev_id;
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int input_current;
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int charging_current;
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int topoff_current;
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int siop_level;
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int cable_type;
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int battery_cable_type;
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bool is_charging;
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struct mutex charger_mutex;
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bool noti_check;
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/* register programming */
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int reg_addr;
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int reg_data;
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bool full_charged;
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bool ovp;
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bool otg_on;
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int unhealth_cnt;
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bool battery_valid;
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int status;
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int health;
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struct delayed_work get_capacity;
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struct delayed_work afc_current_down;
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struct delayed_work polling_work;
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/* s2mu004 */
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int irq_det_bat;
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int irq_chg;
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int irq_chgin;
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int irq_chg_fault;
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int irq_vbus;
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int irq_rst;
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int irq_done;
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int irq_sys;
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int irq_event;
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int charge_mode;
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#if defined(CONFIG_FUELGAUGE_S2MU004)
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int voltage_now;
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int voltage_avg;
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int voltage_ocv;
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unsigned int capacity;
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#endif
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#if defined(CONFIG_MUIC_NOTIFIER)
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struct notifier_block cable_check;
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#endif
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};
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#endif /*S2MU004_CHARGER_H*/
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