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lineage_kernel_xcoverpro/drivers/soc/samsung/cal-if/exynos9810_evt0/cmucal-node.h

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#ifndef __CMUCAL_NODE_H__
#define __CMUCAL_NODE_H__
#include "../cmucal.h"
/*=================CMUCAL version: S5E9810================================*/
enum clk_id {
OSCCLK_RCO_APM = FIXED_RATE_TYPE,
PAD_CLK_APM_BUS,
CLK_DLL_DCO,
OSCCLK_AUD,
CLKIO_AUD_UAIF0,
CLKIO_AUD_UAIF1,
CLKIO_AUD_UAIF2,
CLKIO_AUD_UAIF3,
OSCCLK_BUS1,
PAD_CLK_BUS1_BUS,
OSCCLK_BUSC,
OSCCLK_RCO_CHUB,
RTCCLK_CHUB,
OSCCLK_RCO_CMGP,
OSCCLK_CMGP,
OSCCLK_CMU,
OSCCLK_CORE,
OSCCLK_CPUCL0,
PAD_CLK_CPUCL0_DBG_ATCLK,
PAD_CLK_CPUCL0_DBG_PCLKDBG,
OSCCLK_EMBEDDED_CPUCL0,
SCLK_OUT,
ACLK_OUT,
ACLKP_OUT,
OSCCLK_CPUCL1,
CLK_CLUSTER1_DIV_ACLK,
CLK_CLUSTER1_DIV_ATCLK,
OSCCLK_EMBEDDED_CPUCL1,
OSCCLK_DCF,
OSCCLK_DCPOST,
PAD_CLK_DCPOST_BUSD,
OSCCLK_DCRD,
OSCCLK_DPU,
CLK_DEBUG_DECON0,
CLK_DEBUG_DECON1,
CLK_DEBUG_DECON2,
OSCCLK_DSPM,
PAD_CLK_DSPM_BUSD,
PAD_CLK_DSPM_BUSP,
OSCCLK_DSPS,
OSCCLK_FSYS0,
PAD_CLK_FSYS0_UFS_EMBD,
USBDPPHY_TXCLK_CH0,
USBDPPHY_RXCLK_CH0,
USBDPPHY_DP_TXCLK,
USB20PHY_PHY_CLOCK,
USBDPPHY_VCOCLK_DIV40_MON,
OSCCLK_FSYS1,
PAD_CLK_FSYS1_BUS,
PAD_CLK_FSYS1_MMC_CARD,
PAD_CLK_FSYS1_UFS_CARD,
OSCCLK_G2D,
OSCCLK_G3D,
OSCCLK_EMBEDDED_G3D,
CLK_G3D_GPU_FEEDBACK,
OSCCLK_ISPHQ,
OSCCLK_ISPLP,
OSCCLK_ISPPRE,
OSCCLK_IVA,
OSCCLK_MFC,
OSCCLK_MIF,
OSCCLK_PERIC0,
OSCCLK_PERIC1,
OSCCLK_PERIS,
OSCCLK_S2D,
OSCCLK_RCO_VTS,
RTCCLK_VTS,
CLK_RCO_VTS,
end_of_fixed_rate,
num_of_fixed_rate = end_of_fixed_rate - FIXED_RATE_TYPE,
CLKCMU_FSYS1_PCIE = FIXED_FACTOR_TYPE,
CLKCMU_OTP,
CLKCMU_FSYS0_USBDP_DEBUG,
CLK_MIF_BUSD,
CLK_MIF_BUSD_S2D,
end_of_fixed_factor,
num_of_fixed_factor = end_of_fixed_factor - FIXED_FACTOR_TYPE,
PLL_AUD = PLL_TYPE,
PLL_SHARED1,
PLL_SHARED4,
PLL_SHARED3,
PLL_SHARED2,
PLL_SHARED0,
PLL_MMC,
PLL_CPUCL0,
PLL_CPUCL1,
PLL_G3D,
PLL_MIF,
PLL_MIF_S2D,
end_of_pll,
num_of_pll = end_of_pll - PLL_TYPE,
MUX_CLK_APM_BUS = MUX_TYPE,
MUX_CLK_AUD_UAIF3,
MUX_CLK_AUD_UAIF2,
MUX_CLK_AUD_UAIF1,
MUX_CLK_AUD_UAIF0,
MUX_CLK_AUD_CPU,
MUX_CLK_CHUB_BUS,
MUX_CLK_CHUB_I2C,
MUX_CLK_CHUB_USI00,
MUX_CLK_CHUB_USI01,
CLK_CHUB_TIMER_FCLK,
MUX_CLK_I2C_CMGP,
MUX_CLK_USI_CMGP00,
MUX_CLK_USI_CMGP01,
MUX_CLK_USI_CMGP02,
MUX_CLK_USI_CMGP03,
MUX_CLK_CMGP_BUS,
CLK_CMGP_ADC,
MUX_CLKCMU_BUS1_BUS,
MUX_CLKCMU_MFC_BUS,
MUX_CLKCMU_FSYS0_USB30DRD,
MUX_CLKCMU_FSYS0_UFS_EMBD,
MUX_CLKCMU_CMGP_BUS,
MUX_CLKCMU_BUSC_BUS,
MUX_CLKCMU_G2D_G2D,
MUX_CLKCMU_FSYS1_MMC_CARD,
MUX_CLKCMU_DSPM_BUS,
MUX_CLKCMU_CPUCL0_SWITCH,
MUX_CLKCMU_CORE_BUS,
MUX_CLKCMU_MIF_SWITCH,
MUX_CLKCMU_ISPPRE_BUS,
MUX_CLKCMU_ISPLP_BUS,
MUX_CLKCMU_ISPHQ_BUS,
MUX_CLKCMU_AUD_CPU,
MUX_CLKCMU_G2D_MSCL,
MUX_CLKCMU_HPM,
MUX_CLKCMU_CPUCL0_DBG_BUS,
MUX_CLKCMU_FSYS0_BUS,
MUX_CLKCMU_CIS_CLK0,
MUX_CLKCMU_CIS_CLK1,
MUX_CLKCMU_CIS_CLK2,
MUX_CLKCMU_CIS_CLK3,
MUX_CLKCMU_IVA_BUS,
MUX_CLKCMU_FSYS1_UFS_CARD,
MUX_CMU_CMUREF,
MUX_CLKCMU_PERIC0_BUS,
MUX_CLKCMU_PERIC1_BUS,
MUX_CLKCMU_PERIS_BUS,
MUX_CLKCMU_DCRD_BUS,
MUX_CLKCMU_FSYS0_DPGTC,
MUX_CLKCMU_FSYS1_PCIE,
MUX_CLKCMU_CHUB_BUS,
MUX_CLKCMU_DCF_BUS,
MUX_CLKCMU_APM_BUS,
MUX_CLKCMU_FSYS1_BUS,
MUX_CLK_CMU_CMUREF,
MUX_CLKCMU_CPUCL1_SWITCH,
MUX_CLKCMU_VTS_BUS,
MUX_CLKCMU_ISPLP_VRA,
MUX_CLKCMU_MFC_WFD,
MUX_CLKCMU_MIF_BUSP,
MUX_CLKCMU_PERIC0_IP,
MUX_CLKCMU_PERIC1_IP,
MUX_CLKCMU_DCPOST_BUS,
MUX_CLKCMU_FSYS0_USBDP_DEBUG,
MUX_CLKCMU_ISPLP_GDC,
MUX_CLKCMU_DSPS_AUD,
MUX_CLKCMU_DPU_BUS,
MUX_CLK_CPUCL0_PLL,
MUX_CLK_CLUSTER0_SCLK,
MUX_CLK_CLUSTER0_ACLK,
MUX_CLK_CLUSTER0_ACLKP,
MUX_CLK_CPUCL1_PLL,
MUX_CLK_DSPS_BUS,
MUX_CLK_G3D_BUSD,
CLKMUX_MIF_DDRPHY2X,
MUX_MIF_CMUREF,
CLKCMU_MIF_DDRPHY2X_S2D,
MUX_CLK_S2D_CORE,
MUX_CLK_VTS_BUS,
APM_CMU_APM_CLKOUT0,
APM_CMU_APM_CLKOUT1,
AUD_CMU_AUD_CLKOUT0,
AUD_CMU_AUD_CLKOUT1,
BUS1_CMU_BUS1_CLKOUT0,
BUS1_CMU_BUS1_CLKOUT1,
BUSC_CMU_BUSC_CLKOUT0,
BUSC_CMU_BUSC_CLKOUT1,
CHUB_CMU_CHUB_CLKOUT0,
CHUB_CMU_CHUB_CLKOUT1,
CMGP_CMU_CMGP_CLKOUT0,
CMGP_CMU_CMGP_CLKOUT1,
CMU_CMU_CMU_CLKOUT0,
CMU_CMU_CMU_CLKOUT1,
CORE_CMU_CORE_CLKOUT0,
CORE_CMU_CORE_CLKOUT1,
CPUCL0_CMU_CPUCL0_CLKOUT0,
CPUCL0_CMU_CPUCL0_CLKOUT1,
CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT0,
CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT1,
CPUCL1_CMU_CPUCL1_CLKOUT0,
CPUCL1_CMU_CPUCL1_CLKOUT1,
CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT0,
CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT1,
DCF_CMU_DCF_CLKOUT0,
DCF_CMU_DCF_CLKOUT1,
DCPOST_CMU_DCPOST_CLKOUT0,
DCPOST_CMU_DCPOST_CLKOUT1,
DCRD_CMU_DCRD_CLKOUT0,
DCRD_CMU_DCRD_CLKOUT1,
DPU_CMU_DPU_CLKOUT0,
DPU_CMU_DPU_CLKOUT1,
DSPM_CMU_DSPM_CLKOUT0,
DSPM_CMU_DSPM_CLKOUT1,
DSPS_CMU_DSPS_CLKOUT0,
DSPS_CMU_DSPS_CLKOUT1,
FSYS0_CMU_FSYS0_CLKOUT0,
FSYS0_CMU_FSYS0_CLKOUT1,
FSYS1_CMU_FSYS1_CLKOUT0,
FSYS1_CMU_FSYS1_CLKOUT1,
G2D_CMU_G2D_CLKOUT0,
G2D_CMU_G2D_CLKOUT1,
G3D_CMU_G3D_CLKOUT0,
G3D_CMU_G3D_CLKOUT1,
G3D_EMBEDDED_CMU_G3D_CLKOUT0,
G3D_EMBEDDED_CMU_G3D_CLKOUT1,
ISPHQ_CMU_ISPHQ_CLKOUT0,
ISPHQ_CMU_ISPHQ_CLKOUT1,
ISPLP_CMU_ISPLP_CLKOUT0,
ISPLP_CMU_ISPLP_CLKOUT1,
ISPPRE_CMU_ISPPRE_CLKOUT0,
ISPPRE_CMU_ISPPRE_CLKOUT1,
IVA_CMU_IVA_CLKOUT0,
IVA_CMU_IVA_CLKOUT1,
MFC_CMU_MFC_CLKOUT0,
MFC_CMU_MFC_CLKOUT1,
MIF_CMU_MIF_CLKOUT0,
MIF_CMU_MIF_CLKOUT1,
PERIC0_CMU_PERIC0_CLKOUT0,
PERIC0_CMU_PERIC0_CLKOUT1,
PERIC1_CMU_PERIC1_CLKOUT0,
PERIC1_CMU_PERIC1_CLKOUT1,
PERIS_CMU_PERIS_CLKOUT0,
PERIS_CMU_PERIS_CLKOUT1,
VTS_CMU_VTS_CLKOUT0,
VTS_CMU_VTS_CLKOUT1,
MUX_HCHGEN_CLK_AUD_CPU = ((MASK_OF_ID & VTS_CMU_VTS_CLKOUT1) | CONST_MUX_TYPE) + 1,
MUX_CLK_PERIS_GIC,
MUX_CLKCMU_APM_BUS_USER = ((MASK_OF_ID & MUX_CLK_PERIS_GIC) | USER_MUX_TYPE) + 1,
MUX_DLL_USER,
MUX_CLKCMU_AUD_CPU_USER,
MUX_CLKCMU_BUS1_BUS_USER,
MUX_CLKCMU_BUSC_BUS_USER,
MUX_CLKCMU_CHUB_BUS_USER,
MUX_CLKCMU_CHUB_DLL_BUS_USER,
MUX_CLKCMU_CMGP_BUS_USER,
MUX_CLKCMU_CMGP_DLL_USER,
MUX_CLKCMU_CORE_BUS_USER,
MUX_CLKCMU_CPUCL0_SWITCH_USER,
MUX_CLKCMU_CPUCL0_DBG_BUS_USER,
MUX_CLKCMU_CPUCL1_SWITCH_USER,
MUX_CLKCMU_DCF_BUS_USER,
MUX_CLKCMU_DCPOST_BUS_USER,
MUX_CLKCMU_DCRD_BUS_USER,
MUX_CLKCMU_DPU_BUS_USER,
MUX_CLKCMU_DSPM_BUS_USER,
MUX_CLKCMU_DSPS_BUS_USER,
MUX_CLKCMU_DSPS_AUD_USER,
MUX_CLKCMU_FSYS0_UFS_EMBD_USER,
MUX_CLKCMU_FSYS0_BUS_USER,
MUX_CLKCMU_FSYS0_USB30DRD_USER,
MUX_CLKCMU_FSYS0_DPGTC_USER,
MUX_CLKCMU_FSYS0_USBDP_DEBUG_USER,
MUX_CLKCMU_FSYS1_BUS_USER,
MUX_CLKCMU_FSYS1_MMC_CARD_USER,
MUX_CLKCMU_FSYS1_PCIE_USER,
MUX_CLKCMU_FSYS1_UFS_CARD_USER,
MUX_CLKCMU_G2D_G2D_USER,
MUX_CLKCMU_G2D_MSCL_USER,
MUX_CLKCMU_G3D_SWITCH_USER,
MUX_CLKCMU_EMBEDDED_G3D_USER,
MUX_CLKCMU_ISPHQ_BUS_USER,
MUX_CLKCMU_ISPLP_BUS_USER,
MUX_CLKCMU_ISPLP_VRA_USER,
MUX_CLKCMU_ISPLP_GDC_USER,
MUX_CLKCMU_ISPPRE_BUS_USER,
MUX_CLKCMU_IVA_BUS_USER,
MUX_CLKCMU_MFC_BUS_USER,
MUX_CLKCMU_MFC_WFD_USER,
MUX_CLKCMU_MIF_BUSP_USER,
MUX_CLKCMU_PERIC0_BUS_USER,
MUX_CLKCMU_PERIC0_IP_USER,
MUX_CLKCMU_PERIC1_BUS_USER,
MUX_CLKCMU_PERIC1_IP_USER,
MUX_CLKCMU_PERIS_BUS_USER,
MUX_CLKCMU_VTS_BUS_USER,
MUX_CLKCMU_VTS_DLL_USER,
end_of_mux,
num_of_mux = (end_of_mux - MUX_TYPE) & MASK_OF_ID,
CLKCMU_APM_DLL_CMGP = DIV_TYPE,
CLKCMU_APM_DLL_VTS,
DIV_CLK_APM_BUS,
DIV_CLK_AUD_PLL,
DIV_CLK_AUD_AUDIF,
DIV_CLK_AUD_CPU_ATCLK,
DIV_CLK_AUD_CPU_PCLKDBG,
DIV_CLK_AUD_DSIF,
DIV_CLK_AUD_UAIF0,
DIV_CLK_AUD_UAIF1,
DIV_CLK_AUD_UAIF2,
DIV_CLK_AUD_UAIF3,
DIV_CLK_AUD_CPU_ACLK,
DIV_CLK_AUD_BUS,
DIV_CLK_AUD_BUSP,
DIV_CLK_AUD_DMIC,
DIV_CLK_BUSC_BUSP,
DIV_CLK_CHUB_USI01,
DIV_CLK_CHUB_I2C,
DIV_CLK_CHUB_USI00,
DIV_CLK_CHUB_BUS,
DIV_CLK_I2C_CMGP,
DIV_CLK_USI_CMGP01,
DIV_CLK_USI_CMGP00,
DIV_CLK_USI_CMGP02,
DIV_CLK_USI_CMGP03,
DIV_CLK_CMGP_ADC,
CLKCMU_APM_BUS,
DIV_PLL_SHARED0_DIV2,
CLKCMU_G3D_SWITCH,
CLKCMU_PERIC0_BUS,
CLKCMU_PERIS_BUS,
CLKCMU_FSYS0_BUS,
CLKCMU_DPU_BUS,
DIV_PLL_SHARED1_DIV2,
CLKCMU_BUS1_BUS,
DIV_PLL_SHARED2_DIV2,
DIV_PLL_SHARED3_DIV2,
DIV_PLL_SHARED4_DIV2,
DIV_PLL_SHARED0_DIV4,
CLKCMU_MFC_BUS,
CLKCMU_G2D_G2D,
CLKCMU_FSYS0_USB30DRD,
CLKCMU_FSYS0_UFS_EMBD,
CLKCMU_FSYS1_MMC_CARD,
CLKCMU_FSYS1_BUS,
CLKCMU_CMGP_BUS,
CLKCMU_DSPM_BUS,
CLKCMU_PERIC1_BUS,
CLKCMU_BUSC_BUS,
CLKCMU_CPUCL1_SWITCH,
CLKCMU_CPUCL0_SWITCH,
CLKCMU_CORE_BUS,
CLKCMU_ISPPRE_BUS,
CLKCMU_ISPLP_BUS,
CLKCMU_ISPHQ_BUS,
CLKCMU_AUD_CPU,
CLKCMU_G2D_MSCL,
CLKCMU_HPM,
CLKCMU_CPUCL0_DBG_BUS,
CLKCMU_CIS_CLK0,
CLKCMU_CIS_CLK1,
CLKCMU_CIS_CLK2,
CLKCMU_CIS_CLK3,
CLKCMU_IVA_BUS,
CLKCMU_FSYS1_UFS_CARD,
DIV_PLL_SHARED1_DIV4,
CLKCMU_FSYS0_DPGTC,
CLKCMU_MODEM_SHARED0,
CLKCMU_MODEM_SHARED1,
CLKCMU_DCRD_BUS,
DIV_CLK_CMU_CMUREF,
CLKCMU_CHUB_BUS,
CLKCMU_DCF_BUS,
CLKCMU_VTS_BUS,
CLKCMU_ISPLP_VRA,
CLKCMU_MFC_WFD,
CLKCMU_MIF_BUSP,
CLKCMU_PERIC0_IP,
CLKCMU_PERIC1_IP,
CLKCMU_DCPOST_BUS,
CLKCMU_ISPLP_GDC,
CLKCMU_DSPS_AUD,
DIV_PLL_SHARED1_DIV3,
DIV_PLL_SHARED0_DIV3,
DIV_CLK_CORE_BUSP,
DIV_CLK_CPUCL0_CMUREF,
DIV_CLK_CLUSTER0_ACLK,
DIV_CLK_CLUSTER0_ATCLK,
DIV_CLK_CLUSTER0_PCLKDBG,
DIV_CLK_CLUSTER0_PERIPHCLK,
DIV_CLK_CPUCL0_DBG_PCLKDBG,
DIV_CLK_CPUCL0_PCLK,
DIV_CLK_CLUSTER0_ACLKP,
DIV_CLK_CPUCL1_CMUREF,
DIV_CLK_CPUCL1_PCLK,
DIV_CLK_CLUSTER1_ACLK,
DIV_CLK_CLUSTER1_ATCLK,
DIV_CLK_CPUCL1_PCLKDBG,
DIV_CLK_DCF_BUSP,
DIV_CLK_DCPOST_BUSP,
DIV_CLK_DCRD_BUSP,
DIV_CLK_DCRD_BUSD_HALF,
DIV_CLK_DPU_BUSP,
DIV_CLK_DSPM_BUSP,
DIV_CLK_DSPS_BUSP,
DIV_CLK_G2D_BUSP,
DIV_CLK_G3D_BUSP,
DIV_CLK_ISPHQ_BUSP,
DIV_CLK_ISPLP_BUSP,
DIV_CLK_ISPPRE_BUSP,
DIV_CLK_IVA_BUSP,
DIV_CLK_IVA_DEBUG,
DIV_CLK_MFC_BUSP,
DIV_CLK_MIF_PRE,
DIV_CLK_PERIC0_USI00_USI,
DIV_CLK_PERIC0_USI01_USI,
DIV_CLK_PERIC0_USI02_USI,
DIV_CLK_PERIC0_USI03_USI,
DIV_CLK_PERIC0_USI04_USI,
DIV_CLK_PERIC0_USI05_USI,
DIV_CLK_PERIC0_USI_I2C,
DIV_CLK_PERIC0_UART_DBG,
DIV_CLK_PERIC0_USI12_USI,
DIV_CLK_PERIC0_USI13_USI,
DIV_CLK_PERIC0_USI14_USI,
DIV_CLK_PERIC1_UART_BT,
DIV_CLK_PERIC1_USI_I2C,
DIV_CLK_PERIC1_USI06_USI,
DIV_CLK_PERIC1_USI07_USI,
DIV_CLK_PERIC1_USI08_USI,
DIV_CLK_PERIC1_I2C_CAM0,
DIV_CLK_PERIC1_I2C_CAM1,
DIV_CLK_PERIC1_I2C_CAM2,
DIV_CLK_PERIC1_I2C_CAM3,
DIV_CLK_PERIC1_SPI_CAM0,
DIV_CLK_PERIC1_USI09_USI,
DIV_CLK_PERIC1_USI10_USI,
DIV_CLK_PERIC1_USI11_USI,
DIV_CLK_VTS_DMIC_IF,
DIV_CLK_VTS_DMIC,
DIV_CLK_VTS_DMIC_DIV2,
DIV_CLK_VTS_BUS,
DIV_CLK_CPUCL0_CPU = (DIV_CLK_VTS_BUS | CONST_DIV_TYPE) + 1,
DIV_CLK_CPUCL1_CPU,
DIV_CLK_G3D_BUSD,
end_of_div,
num_of_div = (end_of_div - DIV_TYPE) & MASK_OF_ID,
GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK = GATE_TYPE,
GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK,
GOUT_BLK_APM_UID_RSTnSYNC_CLK_APM_BUS_IPCLKPORT_CLK,
GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK,
GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK,
GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK,
GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK,
CLKCMU_APM_DLL_CHUB,
GATE_CLKCMU_APM_DLL_VTS,
GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK,
GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK,
GOUT_BLK_APM_UID_LHM_AXI_P_APM_CHUB_IPCLKPORT_I_CLK,
GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK,
GOUT_BLK_APM_UID_LHM_AXI_P_APM_CP_IPCLKPORT_I_CLK,
GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
GOUT_BLK_APM_UID_MAILBOX_APM2CHUB_IPCLKPORT_PCLK,
GOUT_BLK_APM_UID_MAILBOX_CHUB2CP_IPCLKPORT_PCLK,
GOUT_BLK_APM_UID_MAILBOX_GNSS2CHUB_IPCLKPORT_PCLK,
GOUT_BLK_APM_UID_MAILBOX_GNSS2CP_IPCLKPORT_PCLK,
GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK,
GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK,
GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK,
CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK,
GOUT_BLK_APM_UID_LHS_AXI_P_APM2CMGP_IPCLKPORT_I_CLK,
GATE_CLKCMU_APM_DLL_CMGP,
GOUT_BLK_APM_UID_PGEN_APM_IPCLKPORT_CLK,
GOUT_BLK_APM_UID_LHS_AXI_LP_CHUB_IPCLKPORT_I_CLK,
GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK,
GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK,
GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK,
GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK,
GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK,
GOUT_BLK_APM_UID_MAILBOX_AP2CHUB_IPCLKPORT_PCLK,
GOUT_BLK_APM_UID_MAILBOX_AP2VTS_IPCLKPORT_PCLK,
GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK,
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0,
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1,
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3,
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF,
GOUT_BLK_AUD_UID_LHS_ATB_AUD_IPCLKPORT_I_CLK,
GOUT_BLK_AUD_UID_RSTnSYNC_CLK_AUD_CPU_ATCLK_IPCLKPORT_CLK,
GOUT_BLK_AUD_UID_RSTnSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK,
GOUT_BLK_AUD_UID_RSTnSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK,
GOUT_BLK_AUD_UID_RSTnSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK,
GOUT_BLK_AUD_UID_RSTnSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK,
GOUT_BLK_AUD_UID_RSTnSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK,
GOUT_BLK_AUD_UID_RSTnSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK,
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2,
GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK,
GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS,
GOUT_BLK_AUD_UID_RSTnSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK,
CLK_BLK_AUD_UID_DMIC_IPCLKPORT_CLK,
GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ATB,
GOUT_BLK_AUD_UID_ABOX_DAP_IPCLKPORT_dapclk,
CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK,
GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK,
GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK,
GOUT_BLK_BUS1_UID_RSTnSYNC_CLK_BUS1_BUS_IPCLKPORT_CLK,
GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK,
GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK,
GOUT_BLK_BUS1_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK,
GOUT_BLK_BUS1_UID_LHM_AXI_D_CHUB_IPCLKPORT_I_CLK,
GOUT_BLK_BUS1_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK,
GOUT_BLK_BUS1_UID_LHS_AXI_D_BUS1_IPCLKPORT_I_CLK,
GOUT_BLK_BUS1_UID_LHS_AXI_P_CHUB_IPCLKPORT_I_CLK,
GOUT_BLK_BUS1_UID_LHS_AXI_P_CSSYS_IPCLKPORT_I_CLK,
GOUT_BLK_BUS1_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK,
GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK,
GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_pclk,
CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK,
GOUT_BLK_BUS1_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK,
GOUT_BLK_BUS1_UID_BAAW_P_CHUB_IPCLKPORT_I_PCLK,
GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1,
GOUT_BLK_BUS1_UID_XIU_D_BUS1_IPCLKPORT_ACLK,
GOUT_BLK_CHUB_UID_I2C_CHUB00_IPCLKPORT_IPCLK,
GOUT_BLK_CHUB_UID_I2C_CHUB01_IPCLKPORT_IPCLK,
GOUT_BLK_CHUB_UID_USI_CHUB00_IPCLKPORT_IPCLK,
GOUT_BLK_CHUB_UID_USI_CHUB01_IPCLKPORT_IPCLK,
GOUT_BLK_CHUB_UID_RSTnSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK,
GOUT_BLK_CHUB_UID_RSTnSYNC_CLK_CHUB_USI00_IPCLKPORT_CLK,
GOUT_BLK_CHUB_UID_RSTnSYNC_CLK_CHUB_USI01_IPCLKPORT_CLK,
GATE_CLK_CHUB_I2C,
GATE_CLK_CHUB_USI00,
GATE_CLK_CHUB_USI01,
CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK,
GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0,
GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1,
GOUT_BLK_CMGP_UID_AXI2APB_CMGP0_IPCLKPORT_ACLK,
GOUT_BLK_CMGP_UID_AXI2APB_CMGP1_IPCLKPORT_ACLK,
GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK,
GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK,
GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK,
GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK,
GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK,
GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK,
GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK,
GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK,
GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK,
GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK,
GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_I2C_CMGP00_IPCLKPORT_CLK,
GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK,
GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_USI_CMGP00_IPCLKPORT_CLK,
GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_USI_CMGP01_IPCLKPORT_CLK,
GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_USI_CMGP02_IPCLKPORT_CLK,
GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_USI_CMGP03_IPCLKPORT_CLK,
GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK,
GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK,
GOUT_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK,
GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_I2C_CMGP01_IPCLKPORT_CLK,
GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_I2C_CMGP02_IPCLKPORT_CLK,
GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_I2C_CMGP03_IPCLKPORT_CLK,
GOUT_BLK_CMGP_UID_XIU_P_CMGP_IPCLKPORT_ACLK,
GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK,
GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK,
GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK,
GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK,
GOUT_BLK_CMGP_UID_LHM_AXI_P_APM2CMGP_IPCLKPORT_I_CLK,
GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK,
GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK,
GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK,
GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK,
GATE_CLK_I2C_CMGP,
GATE_CLK_USI_CMGP00,
GATE_CLK_USI_CMGP01,
GATE_CLK_USI_CMGP02,
GATE_CLK_USI_CMGP03,
GATE_CLKCMU_APM_BUS,
GATE_CLKCMU_FSYS0_BUS,
CLKCMU_MIF_SWITCH,
GATE_CLKCMU_MFC_BUS,
GATE_CLKCMU_G2D_G2D,
GATE_CLKCMU_FSYS0_USB30DRD,
GATE_CLKCMU_FSYS0_UFS_EMBD,
GATE_CLKCMU_FSYS1_BUS,
GATE_CLKCMU_FSYS1_MMC_CARD,
GATE_CLKCMU_DPU_BUS,
GATE_CLKCMU_G3D_SWITCH,
GATE_CLKCMU_PERIS_BUS,
GATE_CLKCMU_CMGP_BUS,
GATE_CLKCMU_DSPM_BUS,
GATE_CLKCMU_PERIC0_BUS,
GATE_CLKCMU_PERIC1_BUS,
GATE_CLKCMU_BUSC_BUS,
GATE_CLKCMU_BUS1_BUS,
GATE_CLKCMU_CPUCL1_SWITCH,
GATE_CLKCMU_CPUCL0_SWITCH,
GATE_CLKCMU_CORE_BUS,
GATE_CLKCMU_ISPPRE_BUS,
GATE_CLKCMU_ISPLP_BUS,
GATE_CLKCMU_ISPHQ_BUS,
GATE_CLKCMU_AUD_CPU,
GATE_CLKCMU_G2D_MSCL,
GATE_CLKCMU_HPM,
GATE_CLKCMU_FSYS1_PCIE,
GATE_CLKCMU_CPUCL0_DBG_BUS,
GATE_CLKCMU_CIS_CLK0,
GATE_CLKCMU_CIS_CLK1,
GATE_CLKCMU_CIS_CLK3,
GATE_CLKCMU_CIS_CLK2,
GATE_CLKCMU_IVA_BUS,
GATE_CLKCMU_FSYS1_UFS_CARD,
GATE_CLKCMU_FSYS0_DPGTC,
GATE_CLKCMU_MODEM_SHARED0,
GATE_CLKCMU_MODEM_SHARED1,
GATE_CLKCMU_DCRD_BUS,
GATE_CLKCMU_CHUB_BUS,
GATE_CLKCMU_DCF_BUS,
GATE_CLKCMU_VTS_BUS,
GATE_CLKCMU_ISPLP_VRA,
GATE_CLKCMU_MFC_WFD,
GATE_CLKCMU_MIF_BUSP,
GATE_CLKCMU_PERIC0_IP,
GATE_CLKCMU_PERIC1_IP,
GATE_CLKCMU_DCPOST_BUS,
GATE_CLKCMU_FSYS0_USBDP_DEBUG,
GATE_CLKCMU_ISPLP_GDC,
GATE_CLKCMU_DSPS_AUD,
CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK,
GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK,
GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK,
GOUT_BLK_CORE_UID_PPMUPPC_CCI_IPCLKPORT_PCLK,
GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_pclk,
GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK,
GOUT_BLK_CORE_UID_PPMU_CPUCL0_IPCLKPORT_PCLK,
GOUT_BLK_CORE_UID_PPMU_CPUCL1_IPCLKPORT_PCLK,
GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK,
GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM,
GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK,
GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_pclk,
GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK,
GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK,
GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK,
GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK,
GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK,
GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK,
GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK,
GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK,
GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_pclk,
CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_hpm_targetclk_c,
GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK,
GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK,
GOUT_BLK_CORE_UID_LHS_AXI_P_CP_IPCLKPORT_I_CLK,
GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_G3D_IPCLKPORT_PCLKS,
GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_IO_IPCLKPORT_PCLKS,
GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK,
GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_DP_IPCLKPORT_PCLKS,
GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE,
GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE,
GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK,
GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK,
CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_hpm_targetclk_c,
GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK,
GATE_CLK_CPUCL0_CPU,
GOUT_BLK_CPUCL0_UID_RSTnSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK,
GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG,
GOUT_BLK_CPUCL0_UID_ADS_APB_G_BDU_IPCLKPORT_PCLKS,
GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER0_IPCLKPORT_I_PCLK,
GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER1_IPCLKPORT_I_PCLK,
GOUT_BLK_CPUCL0_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK,
GOUT_BLK_CPUCL0_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK,
GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK,
GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK,
GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER0_IPCLKPORT_PCLKS,
GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER1_IPCLKPORT_PCLKS,
GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK,
GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK,
GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK,
GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK,
GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK,
GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK,
GOUT_BLK_CPUCL0_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK,
GOUT_BLK_CPUCL0_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK,
GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_i_clk,
GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLKS,
GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK,
CLK_BLK_CPUCL0_UID_RSTnSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK,
CLK_BLK_CPUCL0_UID_RSTnSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK,
GOUT_BLK_CPUCL0_UID_ADS_APB_G_DSPM_IPCLKPORT_PCLKS,
GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CSSYS_IPCLKPORT_I_CLK,
GOUT_BLK_CPUCL0_UID_AXI2APB_P_CSSYS_IPCLKPORT_ACLK,
GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CLUSTER0_IPCLKPORT_I_CLK,
GOUT_BLK_CPUCL0_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK,
GOUT_BLK_CPUCL0_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK,
GOUT_BLK_CPUCL0_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK,
GOUT_BLK_CPUCL0_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK,
GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM,
GOUT_BLK_CPUCL0_UID_AXI_DS_64to32_G_CSSYS_IPCLKPORT_aclk,
GOUT_BLK_CPUCL0_UID_RSTnSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK,
GOUT_BLK_CPUCL0_UID_RSTnSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK,
GOUT_BLK_CPUCL0_UID_RSTnSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK,
CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK,
GOUT_BLK_CPUCL0_UID_LHS_AXI_P_CLUSTER0_IPCLKPORT_I_CLK,
GOUT_BLK_CPUCL0_UID_RSTnSYNC_CLK_CLUSTER0_ACLKP_IPCLKPORT_CLK,
CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK,
CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK,
CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK,
GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK,
CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_SCLK,
GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKM,
GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKS,
GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKM,
GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKS,
CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK,
GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK,
GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK,
CLK_BLK_CPUCL1_UID_HPM_CPUCL1_0_IPCLKPORT_hpm_targetclk_c,
GATE_CLK_CPUCL1_CPU,
GOUT_BLK_CPUCL1_UID_RSTnSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK,
CLK_BLK_CPUCL1_UID_CLUSTER1_IPCLKPORT_PCLKDBG,
GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK,
GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK,
CLK_BLK_CPUCL1_UID_HPM_CPUCL1_1_IPCLKPORT_hpm_targetclk_c,
CLK_BLK_CPUCL1_UID_HPM_CPUCL1_2_IPCLKPORT_hpm_targetclk_c,
GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCF_IPCLKPORT_I_CLK,
GOUT_BLK_DCPOST_UID_LHS_AXI_D_DCPOSTDCF_IPCLKPORT_I_CLK,
GOUT_BLK_DCPOST_UID_LHM_ATB_DCRDDCPOST_IPCLKPORT_I_CLK,
GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_SYSREG_DCPOST_PCLK,
GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_CIP2_PCLKM,
GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_CIP2_PCLKS,
GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_ACLK,
GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_PCLK,
GOUT_BLK_DCPOST_UID_LHM_AXI_P_DCFDCPOST_IPCLKPORT_I_CLK,
GOUT_BLK_DCPOST_UID_RSTnSYNC_CLK_DCPOST_BUSD_IPCLKPORT_CLK,
GOUT_BLK_DCPOST_UID_RSTnSYNC_CLK_DCPOST_BUSP_IPCLKPORT_CLK,
CLK_BLK_DCPOST_UID_DCPOST_CMU_DCPOST_IPCLKPORT_PCLK,
GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_C2SYNC_1SLV_PCLKM,
GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_C2SYNC_1SLV_PCLKS,
GOUT_BLK_DCPOST_UID_LHM_ATB_DCFDCPOST_IPCLKPORT_I_CLK,
GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCRD_IPCLKPORT_I_CLK,
GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_CIP2_ACLK,
GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_C2SYNC_1SLV_ACLK,
GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AXI2APB_DCPOST_ACLK,
CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK,
GOUT_BLK_DPU_UID_BTM_DPUD0_IPCLKPORT_I_PCLK,
GOUT_BLK_DPU_UID_BTM_DPUD1_IPCLKPORT_I_PCLK,
GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK,
GOUT_BLK_DPU_UID_AXI2APB_DPUP1_IPCLKPORT_ACLK,
GOUT_BLK_DPU_UID_AXI2APB_DPUP0_IPCLKPORT_ACLK,
GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK,
GOUT_BLK_DPU_UID_XIU_P_DPU_IPCLKPORT_ACLK,
GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKS,
GOUT_BLK_DPU_UID_AD_APB_DECON1_IPCLKPORT_PCLKS,
GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS,
GOUT_BLK_DPU_UID_AD_APB_DPP_IPCLKPORT_PCLKS,
GOUT_BLK_DPU_UID_BTM_DPUD2_IPCLKPORT_I_PCLK,
GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS,
GOUT_BLK_DPU_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS,
GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK,
GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK,
GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK,
GOUT_BLK_DPU_UID_RSTnSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK,
GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS,
GOUT_BLK_DPU_UID_AD_APB_DECON2_IPCLKPORT_PCLKS,
GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_IPCLKPORT_PCLKS,
GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_S_IPCLKPORT_PCLKS,
GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_IPCLKPORT_PCLKS,
GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_S_IPCLKPORT_PCLKS,
GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_IPCLKPORT_PCLKS,
GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_S_IPCLKPORT_PCLKS,
GOUT_BLK_DPU_UID_wrapper_for_s5i6211_hsi_dcphy_combo_top_IPCLKPORT_PCLK,
GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_PGEN_IPCLKPORT_PCLKS,
CLK_BLK_DSPM_UID_DSPM_CMU_DSPM_IPCLKPORT_PCLK,
GOUT_BLK_DSPM_UID_SYSREG_DSPM_IPCLKPORT_PCLK,
GOUT_BLK_DSPM_UID_AXI2APB_DSPM_IPCLKPORT_ACLK,
GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_ACLK,
GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_PCLK,
GOUT_BLK_DSPM_UID_SYSMMU_DSPM0_IPCLKPORT_CLK,
GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_ACLK,
GOUT_BLK_DSPM_UID_LHM_AXI_P_DSPM_IPCLKPORT_I_CLK,
GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_PCLK,
GOUT_BLK_DSPM_UID_LHS_ACEL_D0_DSPM_IPCLKPORT_I_CLK,
GOUT_BLK_DSPM_UID_RSTnSYNC_CLK_DSPM_BUSD_IPCLKPORT_CLK,
GOUT_BLK_DSPM_UID_RSTnSYNC_CLK_DSPM_BUSP_IPCLKPORT_CLK,
GOUT_BLK_DSPM_UID_LHM_AXI_P_IVADSPM_IPCLKPORT_I_CLK,
GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMIVA_IPCLKPORT_I_CLK,
GOUT_BLK_DSPM_UID_WRAP2_CONV_DSPM_IPCLKPORT_I_CLK,
GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKM,
GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKS,
GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKM,
GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKS,
GOUT_BLK_DSPM_UID_AD_APB_DSPM2_IPCLKPORT_PCLKM,
GOUT_BLK_DSPM_UID_AD_APB_DSPM2_IPCLKPORT_PCLKS,
GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKS,
GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKM,
GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKS,
GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKM,
GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_ACLK,
GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_PCLK,
GOUT_BLK_DSPM_UID_LHS_ACEL_D1_DSPM_IPCLKPORT_I_CLK,
GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK,
GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_ACLK,
GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_PCLK,
GOUT_BLK_DSPM_UID_SYSMMU_DSPM1_IPCLKPORT_CLK,
CLKCMU_DSPS_BUS,
GOUT_BLK_DSPM_UID_ADM_APB_DSPM_IPCLKPORT_PCLKM,
GOUT_BLK_DSPM_UID_LHM_AXI_D0_DSPSDSPM_IPCLKPORT_I_CLK,
GOUT_BLK_DSPM_UID_LHM_AXI_D1_DSPSDSPM_IPCLKPORT_I_CLK,
GOUT_BLK_DSPM_UID_XIU_P_DSPM_IPCLKPORT_ACLK,
GOUT_BLK_DSPM_UID_PGEN_lite_DSPM_IPCLKPORT_CLK,
GOUT_BLK_DSPM_UID_PPMU_DSPM2_IPCLKPORT_ACLK,
GOUT_BLK_DSPM_UID_PPMU_DSPM2_IPCLKPORT_PCLK,
GOUT_BLK_DSPM_UID_SYSMMU_DSPM2_IPCLKPORT_CLK,
GOUT_BLK_DSPM_UID_BTM_DSPM2_IPCLKPORT_I_PCLK,
GOUT_BLK_DSPM_UID_LHS_ACEL_D2_DSPM_IPCLKPORT_I_CLK,
GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKM,
GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKS,
GOUT_BLK_DSPM_UID_AD_APB_DSPM5_IPCLKPORT_PCLKM,
GOUT_BLK_DSPM_UID_AD_APB_DSPM5_IPCLKPORT_PCLKS,
GOUT_BLK_DSPM_UID_AXI2AHB_DSPM_IPCLKPORT_CLK,
GOUT_BLK_DSPM_UID_CNN_IPCLKPORT_ASYNCDAPM_DAPCLK,
GOUT_BLK_DSPM_UID_BAAW_DSPM_IPCLKPORT_I_PCLK,
GOUT_BLK_DSPM_UID_CNN_IPCLKPORT_HCLK,
GOUT_BLK_DSPM_UID_BTM_DSPM2_IPCLKPORT_I_ACLK,
GOUT_BLK_DSPM_UID_CNN_IPCLKPORT_Clk,
GOUT_BLK_DSPM_UID_SCORE_MASTER_IPCLKPORT_i_CLK,
GOUT_BLK_DSPM_UID_AD_AXI_DSPM1_IPCLKPORT_ACLKS,
GOUT_BLK_DSPM_UID_AD_AXI_DSPM1_IPCLKPORT_ACLKM,
GOUT_BLK_DSPM_UID_AD_AXI_DSPM2_IPCLKPORT_ACLKM,
GOUT_BLK_DSPM_UID_AD_AXI_DSPM2_IPCLKPORT_ACLKS,
CLK_BLK_DSPS_UID_DSPS_CMU_DSPS_IPCLKPORT_PCLK,
GOUT_BLK_DSPS_UID_AXI2APB_DSPS_IPCLKPORT_ACLK,
GOUT_BLK_DSPS_UID_LHM_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK,
GOUT_BLK_DSPS_UID_SYSREG_DSPS_IPCLKPORT_PCLK,
GOUT_BLK_DSPS_UID_RSTnSYNC_CLK_DSPS_BUSP_IPCLKPORT_CLK,
GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
GOUT_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USB30DRD_ref_clk,
CLK_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL,
GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK,
GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK,
GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_ieee1500_wrapper_for_pcieg2_phy_x1_inst_0_i_scl_apb_pclk,
GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_i_PCLK,
GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_i_PCLK,
GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK,
GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK,
GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK,
GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK,
GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK,
GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK,
GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_ACLK,
GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_PCLK,
GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_aclk,
GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK,
GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK,
GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK,
GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK,
GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK,
CLK_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_phy_refclk_in,
GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_slv_aclk,
GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_dbi_aclk,
GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_pcie_sub_ctrl_inst_0_i_driver_apb_clk,
GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_pipe2_digital_x1_wrap_inst_0_i_apb_pclk_scl,
GOUT_BLK_FSYS1_UID_RSTnSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK,
GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO,
GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM,
GOUT_BLK_FSYS1_UID_PCIE_IA_GEN2_IPCLKPORT_i_CLK,
GOUT_BLK_FSYS1_UID_PCIE_IA_GEN3_IPCLKPORT_i_CLK,
GOUT_BLK_FSYS1_UID_SYSMMU_FSYS1_IPCLKPORT_CLK,
GOUT_BLK_FSYS1_UID_PGEN_LITE_FSYS1_IPCLKPORT_CLK,
GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_dbi_aclk,
GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_ieee1500_wrapper_for_qchannel_wrapper_for_pcieg3_phy_x1_top_inst_0_i_apb_pclk,
GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_LT_PCIE3_pcie_sub_ctrl_inst_0_i_driver_apb_clk,
GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_phy_refclk_in,
GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_pipe42_pcie_pcs_x1_wrap_inst_0_i_apb_pclk,
GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_slv_aclk,
GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_DBI_IPCLKPORT_ACLK,
GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_SLV_IPCLKPORT_ACLK,
GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_SLV_IPCLKPORT_ACLK,
GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_DBI_IPCLKPORT_ACLK,
GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_mstr_aclk,
GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK,
GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_mstr_aclk,
GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_i_ACLK,
GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_i_ACLK,
GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK,
GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK,
GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK,
GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK,
GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK,
CLK_BLK_G3D_UID_HPM_G3D0_IPCLKPORT_hpm_targetclk_c,
GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK,
GOUT_BLK_G3D_UID_RSTnSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK,
CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK,
GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK,
GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK,
CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK,
GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK,
GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK,
GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK,
CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK,
GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK,
GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK,
GOUT_BLK_IVA_UID_PPMU_IVA_IPCLKPORT_PCLK,
GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK,
GOUT_BLK_IVA_UID_AD_APB_IVA0_IPCLKPORT_PCLKS,
GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK,
GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK,
GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK,
GOUT_BLK_IVA_UID_RSTnSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK,
GOUT_BLK_IVA_UID_ADM_DAP_IVA_IPCLKPORT_dapclkm,
GOUT_BLK_IVA_UID_RSTnSYNC_CLK_IVA_DEBUG_IPCLKPORT_CLK,
GOUT_BLK_IVA_UID_AD_APB_IVA1_IPCLKPORT_PCLKS,
GOUT_BLK_IVA_UID_AD_APB_IVA2_IPCLKPORT_PCLKS,
GOUT_BLK_IVA_UID_IVA_IPCLKPORT_dap_clk,
GOUT_BLK_IVA_UID_PGEN_lite_IVA_IPCLKPORT_CLK,
GOUT_BLK_IVA_UID_TREX_RB_IVA_IPCLKPORT_pclk,
CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_hpm_targetclk_c,
GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_i_PCLK_S0,
GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_PCLK,
GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_PCLK,
GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_PCLK,
GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_PCLK,
GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P0_IPCLKPORT_ACLK,
CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK,
GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK,
GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P1_IPCLKPORT_ACLK,
GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_PCLK,
GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_PCLK,
GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_PCLK,
GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_PCLK,
GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_PCLK,
GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK,
GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_PCLK,
GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK,
GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI00_I2C_IPCLKPORT_CLK,
GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK,
GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK,
GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK,
GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK,
GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK,
GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK,
GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK,
GOUT_BLK_PERIC0_UID_XIU_P_PERIC0_IPCLKPORT_ACLK,
GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI01_I2C_IPCLKPORT_CLK,
GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI02_I2C_IPCLKPORT_CLK,
GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI03_I2C_IPCLKPORT_CLK,
GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI04_I2C_IPCLKPORT_CLK,
GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI05_I2C_IPCLKPORT_CLK,
GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK,
GATE_CLK_PERIC0_USI00_USI,
GATE_CLK_PERIC0_USI01_USI,
GATE_CLK_PERIC0_USI02_USI,
GATE_CLK_PERIC0_USI03_USI,
GATE_CLK_PERIC0_USI04_USI,
GATE_CLK_PERIC0_USI05_USI,
GATE_CLK_PERIC0_USI_I2C,
GATE_CLK_PERIC0_UART_DBG,
GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_IPCLK,
GATE_CLK_PERIC0_USI12_USI,
GATE_CLK_PERIC0_USI13_USI,
GATE_CLK_PERIC0_USI14_USI,
GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI12_USI_IPCLKPORT_CLK,
GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK,
GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK,
GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_PCLK,
GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_PCLK,
GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI12_I2C_IPCLKPORT_CLK,
GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI13_I2C_IPCLKPORT_CLK,
GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI14_I2C_IPCLKPORT_CLK,
GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_PCLK,
GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_PCLK,
GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK,
GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_PCLK,
GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK,
GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK,
GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_PCLK,
GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_PCLK,
GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_PCLK,
GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_PCLK,
GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK,
GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK,
GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_PCLK,
GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK,
GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK,
CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK,
GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK,
GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_PCLK,
GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,
GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK,
GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_PCLK,
GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_PCLK,
GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK,
GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK,
GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK,
GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK,
GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK,
GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK,
GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK,
GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_USI06_I2C_IPCLKPORT_CLK,
CLK_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK,
CLK_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_SPI_CAM0_IPCLKPORT_CLK,
CLK_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_I2C_CAM0_IPCLKPORT_CLK,
CLK_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_I2C_CAM1_IPCLKPORT_CLK,
CLK_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_I2C_CAM2_IPCLKPORT_CLK,
CLK_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_I2C_CAM3_IPCLKPORT_CLK,
GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_USI07_I2C_IPCLKPORT_CLK,
GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_USI08_I2C_IPCLKPORT_CLK,
GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_USI09_I2C_IPCLKPORT_CLK,
GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_USI10_I2C_IPCLKPORT_CLK,
GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,
GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK,
GATE_CLK_PERIC1_UART_BT,
GATE_CLK_PERIC1_USI_I2C,
GATE_CLK_PERIC1_USI06_USI,
GATE_CLK_PERIC1_USI07_USI,
GATE_CLK_PERIC1_USI08_USI,
GATE_CLK_PERIC1_I2C_CAM0,
GATE_CLK_PERIC1_I2C_CAM1,
GATE_CLK_PERIC1_I2C_CAM2,
GATE_CLK_PERIC1_I2C_CAM3,
GATE_CLK_PERIC1_SPI_CAM0,
GATE_CLK_PERIC1_USI09_USI,
GATE_CLK_PERIC1_USI10_USI,
GATE_CLK_PERIC1_USI11_USI,
GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK,
GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_PCLK,
GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_IPCLK,
GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK,
GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_USI11_I2C_IPCLKPORT_CLK,
GOUT_BLK_PERIS_UID_AXI2APB_PERISP_IPCLKPORT_ACLK,
GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK,
GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK,
GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK,
GOUT_BLK_PERIS_UID_RSTnSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK,
GOUT_BLK_PERIS_UID_RSTnSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK,
GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS,
GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM,
GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK,
GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK,
GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK,
CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK,
GOUT_BLK_S2D_UID_RSTnSYNC_CLK_S2D_CORE_IPCLKPORT_CLK,
GOUT_BLK_VTS_UID_RSTnSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK,
GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_CLK,
CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_DIV2_CLK,
GOUT_BLK_VTS_UID_RSTnSYNC_CLK_VTS_DMIC_IPCLKPORT_CLK,
CLK_BLK_VTS_UID_u_DMIC_CLK_MUX_IPCLKPORT_D0,
end_of_gate,
num_of_gate = end_of_gate - GATE_TYPE,
};
#endif
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