1817 lines
281 KiB
C
Executable File
1817 lines
281 KiB
C
Executable File
#include "../cmucal.h"
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#include "cmucal-node.h"
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#include "cmucal-sfr.h"
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/*=================CMUCAL version: S5E9810================================*/
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/*====================The section of PLL rate tables===================*/
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struct cmucal_pll_table pll_aud_rate_table[] = {
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PLL_RATE_MPSK(1179648000, 45, 1, 0, 24319),
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PLL_RATE_MPSK(1083801600, 42, 1, 0, -20665),
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};
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struct cmucal_pll_table pll_shared1_rate_table[] = {
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PLL_RATE_MPS(1865500000, 287, 4, 0),
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};
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struct cmucal_pll_table pll_shared4_rate_table[] = {
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PLL_RATE_MPS(672000000, 336, 13, 0),
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};
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struct cmucal_pll_table pll_shared3_rate_table[] = {
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PLL_RATE_MPS(640000000, 320, 13, 0),
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};
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struct cmucal_pll_table pll_shared2_rate_table[] = {
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PLL_RATE_MPS(800000000, 400, 13, 0),
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};
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struct cmucal_pll_table pll_shared0_rate_table[] = {
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PLL_RATE_MPS(2132000000, 328, 4, 0),
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};
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struct cmucal_pll_table pll_mmc_rate_table[] = {
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PLL_RATE_MPSK(825999878, 31, 1, 0, 50412),
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PLL_RATE_MPSK(26000000, 0, 0, 0, 0),
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};
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struct cmucal_pll_table pll_cpucl0_rate_table[] = {
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PLL_RATE_MPS(1150500000, 354, 4, 1),
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PLL_RATE_MPS(1499333374, 173, 3, 0),
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PLL_RATE_MPS(1850333252, 427, 6, 0),
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PLL_RATE_MPS(349916656, 323, 6, 2),
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PLL_RATE_MPS(650000000, 200, 4, 1),
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};
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struct cmucal_pll_table pll_cpucl1_rate_table[] = {
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PLL_RATE_MPS(1478750000, 455, 4, 1),
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PLL_RATE_MPS(1893666748, 437, 6, 0),
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PLL_RATE_MPS(2327000000, 358, 4, 0),
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PLL_RATE_MPS(400000000, 200, 13, 0),
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PLL_RATE_MPS(928200012, 357, 5, 1),
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};
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struct cmucal_pll_table pll_g3d_rate_table[] = {
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PLL_RATE_MPS(860000000, 430, 13, 0),
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PLL_RATE_MPS(320000000, 320, 13, 1),
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PLL_RATE_MPS(650000000, 175, 7, 0),
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};
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struct cmucal_pll_table pll_mif_rate_table[] = {
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PLL_RATE_MPS(3731000000, 574, 4, 0),
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PLL_RATE_MPS(4264000000, 492, 3, 0),
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PLL_RATE_MPS(1418000000, 709, 13, 0),
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PLL_RATE_MPS(2576599854, 991, 5, 1),
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};
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struct cmucal_pll_table pll_mif1_rate_table[] = {
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PLL_RATE_MPS(26000000, 0, 0, 0),
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};
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struct cmucal_pll_table pll_mif2_rate_table[] = {
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PLL_RATE_MPS(26000000, 0, 0, 0),
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};
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struct cmucal_pll_table pll_mif3_rate_table[] = {
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PLL_RATE_MPS(26000000, 0, 0, 0),
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};
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struct cmucal_pll_table pll_mif_s2d_rate_table[] = {
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PLL_RATE_MPS(1664000000, 400, 13, 1),
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PLL_RATE_MPS(1664000000, 13, 400, 1),
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};
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/*====================The section of PLLs===================*/
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unsigned int cmucal_pll_size = 12;
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struct cmucal_pll cmucal_pll_list[] = {
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CLK_PLL(PLL_1031X, PLL_AUD, OSCCLK_AUD, PLL_LOCKTIME_PLL_AUD_PLL_LOCK_TIME, PLL_CON0_PLL_AUD_ENABLE, PLL_CON0_PLL_AUD_STABLE, PLL_CON0_PLL_AUD_DIV_P, PLL_CON0_PLL_AUD_DIV_M, PLL_CON0_PLL_AUD_DIV_S, PLL_CON3_PLL_AUD_DIV_K, pll_aud_rate_table, 0, 0),
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CLK_PLL(PLL_1017X, PLL_SHARED1, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED1_PLL_LOCK_TIME, PLL_CON0_PLL_SHARED1_ENABLE, PLL_CON0_PLL_SHARED1_STABLE, PLL_CON0_PLL_SHARED1_DIV_P, PLL_CON0_PLL_SHARED1_DIV_M, PLL_CON0_PLL_SHARED1_DIV_S, EMPTY_CAL_ID, pll_shared1_rate_table, 0, 0),
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CLK_PLL(PLL_1018X, PLL_SHARED4, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED4_PLL_LOCK_TIME, PLL_CON0_PLL_SHARED4_ENABLE, PLL_CON0_PLL_SHARED4_STABLE, PLL_CON0_PLL_SHARED4_DIV_P, PLL_CON0_PLL_SHARED4_DIV_M, PLL_CON0_PLL_SHARED4_DIV_S, EMPTY_CAL_ID, pll_shared4_rate_table, 0, 0),
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CLK_PLL(PLL_1018X, PLL_SHARED3, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED3_PLL_LOCK_TIME, PLL_CON0_PLL_SHARED3_ENABLE, PLL_CON0_PLL_SHARED3_STABLE, PLL_CON0_PLL_SHARED3_DIV_P, PLL_CON0_PLL_SHARED3_DIV_M, PLL_CON0_PLL_SHARED3_DIV_S, EMPTY_CAL_ID, pll_shared3_rate_table, 0, 0),
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CLK_PLL(PLL_1018X, PLL_SHARED2, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED2_PLL_LOCK_TIME, PLL_CON0_PLL_SHARED2_ENABLE, PLL_CON0_PLL_SHARED2_STABLE, PLL_CON0_PLL_SHARED2_DIV_P, PLL_CON0_PLL_SHARED2_DIV_M, PLL_CON0_PLL_SHARED2_DIV_S, EMPTY_CAL_ID, pll_shared2_rate_table, 0, 0),
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CLK_PLL(PLL_1017X, PLL_SHARED0, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED0_PLL_LOCK_TIME, PLL_CON0_PLL_SHARED0_ENABLE, PLL_CON0_PLL_SHARED0_STABLE, PLL_CON0_PLL_SHARED0_DIV_P, PLL_CON0_PLL_SHARED0_DIV_M, PLL_CON0_PLL_SHARED0_DIV_S, EMPTY_CAL_ID, pll_shared0_rate_table, 0, 0),
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CLK_PLL(PLL_1031X, PLL_MMC, OSCCLK_CMU, PLL_LOCKTIME_PLL_MMC_PLL_LOCK_TIME, PLL_CON0_PLL_MMC_ENABLE, PLL_CON0_PLL_MMC_STABLE, PLL_CON0_PLL_MMC_DIV_P, PLL_CON0_PLL_MMC_DIV_M, PLL_CON0_PLL_MMC_DIV_S, PLL_CON3_PLL_MMC_DIV_K, pll_mmc_rate_table, 0, 0),
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CLK_PLL(PLL_1050X, PLL_CPUCL0, OSCCLK_CPUCL0, PLL_LOCKTIME_PLL_CPUCL0_PLL_LOCK_TIME, PLL_CON0_PLL_CPUCL0_ENABLE, PLL_CON0_PLL_CPUCL0_STABLE, PLL_CON0_PLL_CPUCL0_DIV_P, PLL_CON0_PLL_CPUCL0_DIV_M, PLL_CON0_PLL_CPUCL0_DIV_S, EMPTY_CAL_ID, pll_cpucl0_rate_table, 150, 0),
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CLK_PLL(PLL_1019X, PLL_CPUCL1, OSCCLK_CPUCL1, PLL_LOCKTIME_PLL_CPUCL1_PLL_LOCK_TIME, PLL_CON0_PLL_CPUCL1_ENABLE, PLL_CON0_PLL_CPUCL1_STABLE, PLL_CON0_PLL_CPUCL1_DIV_P, PLL_CON0_PLL_CPUCL1_DIV_M, PLL_CON0_PLL_CPUCL1_DIV_S, EMPTY_CAL_ID, pll_cpucl1_rate_table, 0, 0),
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CLK_PLL(PLL_1018X, PLL_G3D, OSCCLK_G3D, PLL_LOCKTIME_PLL_G3D_PLL_LOCK_TIME, PLL_CON0_PLL_G3D_ENABLE, PLL_CON0_PLL_G3D_STABLE, PLL_CON0_PLL_G3D_DIV_P, PLL_CON0_PLL_G3D_DIV_M, PLL_CON0_PLL_G3D_DIV_S, EMPTY_CAL_ID, pll_g3d_rate_table, 0, 0),
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CLK_PLL(PLL_1050X, PLL_MIF, OSCCLK_MIF, PLL_LOCKTIME_PLL_MIF_PLL_LOCK_TIME, PLL_CON0_PLL_MIF_ENABLE, PLL_CON0_PLL_MIF_STABLE, PLL_CON0_PLL_MIF_DIV_P, PLL_CON0_PLL_MIF_DIV_M, PLL_CON0_PLL_MIF_DIV_S, EMPTY_CAL_ID, pll_mif_rate_table, 150, 0),
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CLK_PLL(PLL_1016X, PLL_MIF_S2D, OSCCLK_S2D, PLL_LOCKTIME_PLL_MIF_S2D_PLL_LOCK_TIME, PLL_CON0_PLL_MIF_S2D_ENABLE, PLL_CON0_PLL_MIF_S2D_STABLE, PLL_CON0_PLL_MIF_S2D_DIV_P, PLL_CON0_PLL_MIF_S2D_DIV_M, PLL_CON0_PLL_MIF_S2D_DIV_S, EMPTY_CAL_ID, pll_mif_s2d_rate_table, 0, 0),
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};
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/*====================The section of MUXs' parents===================*/
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enum clk_id cmucal_mux_clk_apm_bus_parents[] = {
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MUX_CLKCMU_APM_BUS_USER,
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MUX_DLL_USER,
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};
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enum clk_id cmucal_mux_clk_aud_uaif3_parents[] = {
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DIV_CLK_AUD_UAIF3,
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CLKIO_AUD_UAIF3,
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};
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enum clk_id cmucal_mux_clk_aud_uaif2_parents[] = {
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DIV_CLK_AUD_UAIF2,
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CLKIO_AUD_UAIF2,
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};
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enum clk_id cmucal_mux_clk_aud_uaif1_parents[] = {
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DIV_CLK_AUD_UAIF1,
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CLKIO_AUD_UAIF1,
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};
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enum clk_id cmucal_mux_clk_aud_uaif0_parents[] = {
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DIV_CLK_AUD_UAIF0,
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CLKIO_AUD_UAIF0,
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};
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enum clk_id cmucal_mux_clk_aud_cpu_parents[] = {
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DIV_CLK_AUD_PLL,
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MUX_CLKCMU_AUD_CPU_USER,
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};
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enum clk_id cmucal_mux_hchgen_clk_aud_cpu_parents[] = {
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MUX_CLK_AUD_CPU,
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OSCCLK_AUD,
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};
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enum clk_id cmucal_mux_clk_chub_bus_parents[] = {
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MUX_CLKCMU_CHUB_BUS_USER,
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MUX_CLKCMU_CHUB_DLL_BUS_USER,
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};
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enum clk_id cmucal_mux_clk_chub_i2c_parents[] = {
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OSCCLK_RCO_CHUB,
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MUX_CLK_CHUB_BUS,
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};
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enum clk_id cmucal_mux_clk_chub_usi00_parents[] = {
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OSCCLK_RCO_CHUB,
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MUX_CLK_CHUB_BUS,
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};
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enum clk_id cmucal_mux_clk_chub_usi01_parents[] = {
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OSCCLK_RCO_CHUB,
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MUX_CLK_CHUB_BUS,
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};
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enum clk_id cmucal_clk_chub_timer_fclk_parents[] = {
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OSCCLK_RCO_CHUB,
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RTCCLK_CHUB,
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};
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enum clk_id cmucal_mux_clk_i2c_cmgp_parents[] = {
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OSCCLK_RCO_CMGP,
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MUX_CLK_CMGP_BUS,
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};
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enum clk_id cmucal_mux_clk_usi_cmgp00_parents[] = {
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OSCCLK_RCO_CMGP,
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MUX_CLK_CMGP_BUS,
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};
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enum clk_id cmucal_mux_clk_usi_cmgp01_parents[] = {
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OSCCLK_RCO_CMGP,
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MUX_CLK_CMGP_BUS,
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};
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enum clk_id cmucal_mux_clk_usi_cmgp02_parents[] = {
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OSCCLK_RCO_CMGP,
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MUX_CLK_CMGP_BUS,
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};
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enum clk_id cmucal_mux_clk_usi_cmgp03_parents[] = {
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OSCCLK_RCO_CMGP,
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MUX_CLK_CMGP_BUS,
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};
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enum clk_id cmucal_mux_clk_cmgp_bus_parents[] = {
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MUX_CLKCMU_CMGP_BUS_USER,
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MUX_CLKCMU_CMGP_DLL_USER,
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};
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enum clk_id cmucal_clk_cmgp_adc_parents[] = {
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OSCCLK_CMGP,
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DIV_CLK_CMGP_ADC,
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};
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enum clk_id cmucal_mux_clkcmu_bus1_bus_parents[] = {
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DIV_PLL_SHARED0_DIV4,
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DIV_PLL_SHARED1_DIV4,
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DIV_PLL_SHARED2_DIV2,
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DIV_PLL_SHARED4_DIV2,
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};
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enum clk_id cmucal_mux_clkcmu_mfc_bus_parents[] = {
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DIV_PLL_SHARED0_DIV2,
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PLL_SHARED4,
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DIV_PLL_SHARED0_DIV4,
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DIV_PLL_SHARED1_DIV4,
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DIV_PLL_SHARED2_DIV2,
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OSCCLK_CMU,
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OSCCLK_CMU,
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OSCCLK_CMU,
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};
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enum clk_id cmucal_mux_clkcmu_fsys0_usb30drd_parents[] = {
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OSCCLK_CMU,
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DIV_PLL_SHARED0_DIV4,
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DIV_PLL_SHARED2_DIV2,
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DIV_PLL_SHARED4_DIV2,
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};
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enum clk_id cmucal_mux_clkcmu_fsys0_ufs_embd_parents[] = {
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OSCCLK_CMU,
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DIV_PLL_SHARED0_DIV4,
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DIV_PLL_SHARED2_DIV2,
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DIV_PLL_SHARED4_DIV2,
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};
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enum clk_id cmucal_mux_clkcmu_cmgp_bus_parents[] = {
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DIV_PLL_SHARED0_DIV4,
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DIV_PLL_SHARED2_DIV2,
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};
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enum clk_id cmucal_mux_clkcmu_busc_bus_parents[] = {
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DIV_PLL_SHARED0_DIV4,
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DIV_PLL_SHARED1_DIV4,
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DIV_PLL_SHARED2_DIV2,
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DIV_PLL_SHARED4_DIV2,
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};
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enum clk_id cmucal_mux_clkcmu_g2d_g2d_parents[] = {
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DIV_PLL_SHARED0_DIV2,
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DIV_PLL_SHARED0_DIV3,
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PLL_SHARED4,
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DIV_PLL_SHARED0_DIV4,
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DIV_PLL_SHARED1_DIV4,
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DIV_PLL_SHARED2_DIV2,
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OSCCLK_CMU,
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OSCCLK_CMU,
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};
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enum clk_id cmucal_mux_clkcmu_fsys1_mmc_card_parents[] = {
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OSCCLK_CMU,
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PLL_SHARED2,
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PLL_SHARED4,
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DIV_PLL_SHARED0_DIV4,
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PLL_MMC,
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OSCCLK_CMU,
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OSCCLK_CMU,
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OSCCLK_CMU,
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};
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enum clk_id cmucal_mux_clkcmu_dspm_bus_parents[] = {
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DIV_PLL_SHARED0_DIV4,
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DIV_PLL_SHARED1_DIV4,
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DIV_PLL_SHARED2_DIV2,
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DIV_PLL_SHARED4_DIV2,
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};
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enum clk_id cmucal_mux_clkcmu_cpucl0_switch_parents[] = {
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DIV_PLL_SHARED0_DIV2,
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DIV_PLL_SHARED1_DIV2,
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PLL_SHARED2,
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PLL_SHARED4,
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};
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enum clk_id cmucal_mux_clkcmu_core_bus_parents[] = {
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DIV_PLL_SHARED0_DIV2,
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DIV_PLL_SHARED1_DIV2,
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PLL_SHARED2,
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DIV_PLL_SHARED0_DIV3,
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PLL_SHARED4,
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DIV_PLL_SHARED0_DIV4,
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PLL_SHARED3,
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PLL_MMC,
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};
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enum clk_id cmucal_mux_clkcmu_mif_switch_parents[] = {
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PLL_SHARED0,
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PLL_SHARED1,
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DIV_PLL_SHARED0_DIV2,
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DIV_PLL_SHARED1_DIV2,
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PLL_SHARED2,
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DIV_PLL_SHARED0_DIV4,
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DIV_PLL_SHARED2_DIV2,
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OSCCLK_CMU,
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};
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enum clk_id cmucal_mux_clkcmu_isppre_bus_parents[] = {
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DIV_PLL_SHARED0_DIV4,
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DIV_PLL_SHARED1_DIV4,
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DIV_PLL_SHARED2_DIV2,
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DIV_PLL_SHARED4_DIV2,
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};
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enum clk_id cmucal_mux_clkcmu_isplp_bus_parents[] = {
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DIV_PLL_SHARED0_DIV4,
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DIV_PLL_SHARED1_DIV4,
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DIV_PLL_SHARED2_DIV2,
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DIV_PLL_SHARED4_DIV2,
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};
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enum clk_id cmucal_mux_clkcmu_isphq_bus_parents[] = {
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DIV_PLL_SHARED0_DIV4,
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DIV_PLL_SHARED1_DIV4,
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DIV_PLL_SHARED2_DIV2,
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DIV_PLL_SHARED4_DIV2,
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};
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enum clk_id cmucal_mux_clkcmu_aud_cpu_parents[] = {
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DIV_PLL_SHARED0_DIV2,
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DIV_PLL_SHARED1_DIV2,
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PLL_SHARED2,
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PLL_SHARED4,
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};
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enum clk_id cmucal_mux_clkcmu_g2d_mscl_parents[] = {
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DIV_PLL_SHARED0_DIV4,
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DIV_PLL_SHARED1_DIV4,
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DIV_PLL_SHARED2_DIV2,
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DIV_PLL_SHARED4_DIV2,
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};
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enum clk_id cmucal_mux_clkcmu_hpm_parents[] = {
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OSCCLK_CMU,
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PLL_SHARED2,
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DIV_PLL_SHARED0_DIV4,
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DIV_PLL_SHARED1_DIV4,
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};
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enum clk_id cmucal_mux_clkcmu_cpucl0_dbg_bus_parents[] = {
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PLL_SHARED2,
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PLL_SHARED4,
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DIV_PLL_SHARED0_DIV4,
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DIV_PLL_SHARED1_DIV4,
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};
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enum clk_id cmucal_mux_clkcmu_fsys0_bus_parents[] = {
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DIV_PLL_SHARED1_DIV2,
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PLL_SHARED2,
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PLL_SHARED4,
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DIV_PLL_SHARED0_DIV4,
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};
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enum clk_id cmucal_mux_clkcmu_cis_clk0_parents[] = {
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OSCCLK_CMU,
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DIV_PLL_SHARED2_DIV2,
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};
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enum clk_id cmucal_mux_clkcmu_cis_clk1_parents[] = {
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OSCCLK_CMU,
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DIV_PLL_SHARED2_DIV2,
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};
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enum clk_id cmucal_mux_clkcmu_cis_clk2_parents[] = {
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OSCCLK_CMU,
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DIV_PLL_SHARED2_DIV2,
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};
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enum clk_id cmucal_mux_clkcmu_cis_clk3_parents[] = {
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OSCCLK_CMU,
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DIV_PLL_SHARED2_DIV2,
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};
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enum clk_id cmucal_mux_clkcmu_iva_bus_parents[] = {
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DIV_PLL_SHARED0_DIV4,
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DIV_PLL_SHARED1_DIV4,
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DIV_PLL_SHARED2_DIV2,
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DIV_PLL_SHARED4_DIV2,
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};
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enum clk_id cmucal_mux_clkcmu_fsys1_ufs_card_parents[] = {
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OSCCLK_CMU,
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DIV_PLL_SHARED0_DIV4,
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DIV_PLL_SHARED2_DIV2,
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DIV_PLL_SHARED4_DIV2,
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};
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enum clk_id cmucal_mux_cmu_cmuref_parents[] = {
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OSCCLK_CMU,
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DIV_CLK_CMU_CMUREF,
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};
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enum clk_id cmucal_mux_clkcmu_peric0_bus_parents[] = {
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DIV_PLL_SHARED0_DIV4,
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DIV_PLL_SHARED2_DIV2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric1_bus_parents[] = {
|
|
DIV_PLL_SHARED0_DIV4,
|
|
DIV_PLL_SHARED2_DIV2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peris_bus_parents[] = {
|
|
DIV_PLL_SHARED0_DIV4,
|
|
DIV_PLL_SHARED2_DIV2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dcrd_bus_parents[] = {
|
|
PLL_SHARED4,
|
|
DIV_PLL_SHARED0_DIV4,
|
|
DIV_PLL_SHARED1_DIV4,
|
|
DIV_PLL_SHARED2_DIV2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_fsys0_dpgtc_parents[] = {
|
|
OSCCLK_CMU,
|
|
DIV_PLL_SHARED0_DIV4,
|
|
DIV_PLL_SHARED2_DIV2,
|
|
DIV_PLL_SHARED4_DIV2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_fsys1_pcie_parents[] = {
|
|
OSCCLK_CMU,
|
|
PLL_SHARED2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_chub_bus_parents[] = {
|
|
DIV_PLL_SHARED0_DIV3,
|
|
DIV_PLL_SHARED2_DIV2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dcf_bus_parents[] = {
|
|
DIV_PLL_SHARED0_DIV4,
|
|
DIV_PLL_SHARED1_DIV4,
|
|
DIV_PLL_SHARED2_DIV2,
|
|
DIV_PLL_SHARED4_DIV2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_apm_bus_parents[] = {
|
|
DIV_PLL_SHARED0_DIV3,
|
|
DIV_PLL_SHARED2_DIV2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_fsys1_bus_parents[] = {
|
|
DIV_PLL_SHARED1_DIV2,
|
|
PLL_SHARED2,
|
|
PLL_SHARED4,
|
|
DIV_PLL_SHARED0_DIV4,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cmu_cmuref_parents[] = {
|
|
DIV_PLL_SHARED0_DIV4,
|
|
DIV_PLL_SHARED2_DIV2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cpucl1_switch_parents[] = {
|
|
DIV_PLL_SHARED0_DIV2,
|
|
DIV_PLL_SHARED1_DIV2,
|
|
PLL_SHARED2,
|
|
PLL_SHARED4,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_vts_bus_parents[] = {
|
|
DIV_PLL_SHARED0_DIV4,
|
|
DIV_PLL_SHARED2_DIV2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_isplp_vra_parents[] = {
|
|
DIV_PLL_SHARED0_DIV4,
|
|
DIV_PLL_SHARED1_DIV4,
|
|
DIV_PLL_SHARED2_DIV2,
|
|
DIV_PLL_SHARED4_DIV2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mfc_wfd_parents[] = {
|
|
PLL_SHARED4,
|
|
DIV_PLL_SHARED0_DIV4,
|
|
DIV_PLL_SHARED1_DIV4,
|
|
DIV_PLL_SHARED2_DIV2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mif_busp_parents[] = {
|
|
DIV_PLL_SHARED0_DIV4,
|
|
DIV_PLL_SHARED1_DIV4,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric0_ip_parents[] = {
|
|
DIV_PLL_SHARED0_DIV4,
|
|
DIV_PLL_SHARED2_DIV2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric1_ip_parents[] = {
|
|
DIV_PLL_SHARED0_DIV4,
|
|
DIV_PLL_SHARED2_DIV2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dcpost_bus_parents[] = {
|
|
DIV_PLL_SHARED0_DIV4,
|
|
DIV_PLL_SHARED1_DIV4,
|
|
DIV_PLL_SHARED2_DIV2,
|
|
DIV_PLL_SHARED4_DIV2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_fsys0_usbdp_debug_parents[] = {
|
|
OSCCLK_CMU,
|
|
PLL_SHARED2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_isplp_gdc_parents[] = {
|
|
DIV_PLL_SHARED0_DIV4,
|
|
DIV_PLL_SHARED1_DIV4,
|
|
DIV_PLL_SHARED2_DIV2,
|
|
DIV_PLL_SHARED4_DIV2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dsps_aud_parents[] = {
|
|
DIV_PLL_SHARED0_DIV4,
|
|
DIV_PLL_SHARED1_DIV4,
|
|
DIV_PLL_SHARED2_DIV2,
|
|
DIV_PLL_SHARED4_DIV2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dpu_bus_parents[] = {
|
|
DIV_PLL_SHARED0_DIV2,
|
|
PLL_SHARED3,
|
|
PLL_SHARED4,
|
|
DIV_PLL_SHARED0_DIV4,
|
|
DIV_PLL_SHARED1_DIV4,
|
|
DIV_PLL_SHARED2_DIV2,
|
|
OSCCLK_CMU,
|
|
OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl0_pll_parents[] = {
|
|
PLL_CPUCL0,
|
|
MUX_CLKCMU_CPUCL0_SWITCH_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cluster0_sclk_parents[] = {
|
|
GATE_CLK_CPUCL0_CPU,
|
|
SCLK_OUT,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cluster0_aclk_parents[] = {
|
|
DIV_CLK_CLUSTER0_ACLK,
|
|
ACLK_OUT,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cluster0_aclkp_parents[] = {
|
|
DIV_CLK_CLUSTER0_ACLKP,
|
|
ACLKP_OUT,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl1_pll_parents[] = {
|
|
PLL_CPUCL1,
|
|
MUX_CLKCMU_CPUCL1_SWITCH_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_dsps_bus_parents[] = {
|
|
MUX_CLKCMU_DSPS_BUS_USER,
|
|
MUX_CLKCMU_DSPS_AUD_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_g3d_busd_parents[] = {
|
|
PLL_G3D,
|
|
MUX_CLKCMU_G3D_SWITCH_USER,
|
|
};
|
|
enum clk_id cmucal_clkmux_mif_ddrphy2x_parents[] = {
|
|
PLL_MIF,
|
|
CLKCMU_MIF_SWITCH,
|
|
};
|
|
enum clk_id cmucal_mux_mif_cmuref_parents[] = {
|
|
OSCCLK_MIF,
|
|
MUX_CLKCMU_MIF_BUSP_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peris_gic_parents[] = {
|
|
MUX_CLKCMU_PERIS_BUS_USER,
|
|
OSCCLK_PERIS,
|
|
};
|
|
enum clk_id cmucal_clkcmu_mif_ddrphy2x_s2d_parents[] = {
|
|
PLL_MIF_S2D,
|
|
OSCCLK_S2D,
|
|
};
|
|
enum clk_id cmucal_mux_clk_s2d_core_parents[] = {
|
|
OSCCLK_S2D,
|
|
CLK_MIF_BUSD_S2D,
|
|
};
|
|
enum clk_id cmucal_mux_clk_vts_bus_parents[] = {
|
|
CLK_RCO_VTS,
|
|
MUX_CLKCMU_VTS_BUS_USER,
|
|
MUX_CLKCMU_VTS_DLL_USER,
|
|
MUX_CLKCMU_VTS_DLL_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_apm_bus_user_parents[] = {
|
|
OSCCLK_RCO_APM,
|
|
CLKCMU_APM_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_dll_user_parents[] = {
|
|
OSCCLK_RCO_APM,
|
|
CLK_DLL_DCO,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_aud_cpu_user_parents[] = {
|
|
OSCCLK_AUD,
|
|
CLKCMU_AUD_CPU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_bus1_bus_user_parents[] = {
|
|
OSCCLK_BUS1,
|
|
CLKCMU_BUS1_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_busc_bus_user_parents[] = {
|
|
OSCCLK_BUSC,
|
|
CLKCMU_BUSC_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_chub_bus_user_parents[] = {
|
|
OSCCLK_RCO_CHUB,
|
|
CLKCMU_CHUB_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_chub_dll_bus_user_parents[] = {
|
|
OSCCLK_RCO_CHUB,
|
|
CLKCMU_APM_DLL_CHUB,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cmgp_bus_user_parents[] = {
|
|
OSCCLK_RCO_CMGP,
|
|
CLKCMU_CMGP_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cmgp_dll_user_parents[] = {
|
|
OSCCLK_RCO_CMGP,
|
|
CLKCMU_APM_DLL_CMGP,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_core_bus_user_parents[] = {
|
|
OSCCLK_CORE,
|
|
CLKCMU_CORE_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cpucl0_switch_user_parents[] = {
|
|
OSCCLK_CPUCL0,
|
|
CLKCMU_CPUCL0_SWITCH,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cpucl0_dbg_bus_user_parents[] = {
|
|
OSCCLK_CPUCL0,
|
|
CLKCMU_CPUCL0_DBG_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cpucl1_switch_user_parents[] = {
|
|
OSCCLK_CPUCL1,
|
|
CLKCMU_CPUCL1_SWITCH,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dcf_bus_user_parents[] = {
|
|
OSCCLK_DCF,
|
|
CLKCMU_DCF_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dcpost_bus_user_parents[] = {
|
|
OSCCLK_DCPOST,
|
|
CLKCMU_DCPOST_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dcrd_bus_user_parents[] = {
|
|
OSCCLK_DCRD,
|
|
CLKCMU_DCRD_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dpu_bus_user_parents[] = {
|
|
OSCCLK_DPU,
|
|
CLKCMU_DPU_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dspm_bus_user_parents[] = {
|
|
OSCCLK_DSPM,
|
|
CLKCMU_DSPM_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dsps_bus_user_parents[] = {
|
|
OSCCLK_DSPS,
|
|
CLKCMU_DSPS_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dsps_aud_user_parents[] = {
|
|
OSCCLK_DSPS,
|
|
CLKCMU_DSPS_AUD,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_fsys0_ufs_embd_user_parents[] = {
|
|
OSCCLK_FSYS0,
|
|
CLKCMU_FSYS0_UFS_EMBD,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_fsys0_bus_user_parents[] = {
|
|
OSCCLK_FSYS0,
|
|
CLKCMU_FSYS0_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_fsys0_usb30drd_user_parents[] = {
|
|
OSCCLK_FSYS0,
|
|
CLKCMU_FSYS0_USB30DRD,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_fsys0_dpgtc_user_parents[] = {
|
|
OSCCLK_FSYS0,
|
|
CLKCMU_FSYS0_DPGTC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_fsys0_usbdp_debug_user_parents[] = {
|
|
OSCCLK_FSYS0,
|
|
CLKCMU_FSYS0_USBDP_DEBUG,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_fsys1_bus_user_parents[] = {
|
|
OSCCLK_FSYS1,
|
|
CLKCMU_FSYS1_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_fsys1_mmc_card_user_parents[] = {
|
|
OSCCLK_FSYS1,
|
|
CLKCMU_FSYS1_MMC_CARD,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_fsys1_pcie_user_parents[] = {
|
|
OSCCLK_FSYS1,
|
|
CLKCMU_FSYS1_PCIE,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_fsys1_ufs_card_user_parents[] = {
|
|
OSCCLK_FSYS1,
|
|
CLKCMU_FSYS1_UFS_CARD,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_g2d_g2d_user_parents[] = {
|
|
OSCCLK_G2D,
|
|
CLKCMU_G2D_G2D,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_g2d_mscl_user_parents[] = {
|
|
OSCCLK_G2D,
|
|
CLKCMU_G2D_MSCL,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_g3d_switch_user_parents[] = {
|
|
OSCCLK_G3D,
|
|
CLKCMU_G3D_SWITCH,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_embedded_g3d_user_parents[] = {
|
|
OSCCLK_EMBEDDED_G3D,
|
|
DIV_CLK_G3D_BUSD,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_isphq_bus_user_parents[] = {
|
|
OSCCLK_ISPHQ,
|
|
CLKCMU_ISPHQ_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_isplp_bus_user_parents[] = {
|
|
OSCCLK_ISPLP,
|
|
CLKCMU_ISPLP_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_isplp_vra_user_parents[] = {
|
|
OSCCLK_ISPLP,
|
|
CLKCMU_ISPLP_VRA,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_isplp_gdc_user_parents[] = {
|
|
OSCCLK_ISPLP,
|
|
CLKCMU_ISPLP_GDC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_isppre_bus_user_parents[] = {
|
|
OSCCLK_ISPPRE,
|
|
CLKCMU_ISPPRE_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_iva_bus_user_parents[] = {
|
|
OSCCLK_IVA,
|
|
CLKCMU_IVA_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mfc_bus_user_parents[] = {
|
|
OSCCLK_MFC,
|
|
CLKCMU_MFC_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mfc_wfd_user_parents[] = {
|
|
OSCCLK_MFC,
|
|
CLKCMU_MFC_WFD,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mif_busp_user_parents[] = {
|
|
OSCCLK_MIF,
|
|
CLKCMU_MIF_BUSP,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric0_bus_user_parents[] = {
|
|
OSCCLK_PERIC0,
|
|
CLKCMU_PERIC0_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric0_ip_user_parents[] = {
|
|
OSCCLK_PERIC0,
|
|
CLKCMU_PERIC0_IP,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric1_bus_user_parents[] = {
|
|
OSCCLK_PERIC1,
|
|
CLKCMU_PERIC1_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric1_ip_user_parents[] = {
|
|
OSCCLK_PERIC1,
|
|
CLKCMU_PERIC1_IP,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peris_bus_user_parents[] = {
|
|
OSCCLK_PERIS,
|
|
CLKCMU_PERIS_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_vts_bus_user_parents[] = {
|
|
OSCCLK_RCO_VTS,
|
|
CLKCMU_VTS_BUS,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_vts_dll_user_parents[] = {
|
|
OSCCLK_RCO_VTS,
|
|
CLKCMU_APM_DLL_VTS,
|
|
};
|
|
|
|
|
|
/*====================The section of MUXs===================*/
|
|
unsigned int cmucal_mux_size = 197;
|
|
|
|
|
|
struct cmucal_mux cmucal_mux_list[] = {
|
|
CLK_MUX(MUX_CLK_APM_BUS, cmucal_mux_clk_apm_bus_parents, CLK_CON_MUX_MUX_CLK_APM_BUS_SELECT, CLK_CON_MUX_MUX_CLK_APM_BUS_BUSY, CLK_CON_MUX_MUX_CLK_APM_BUS_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_AUD_UAIF3, cmucal_mux_clk_aud_uaif3_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF3_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF3_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_AUD_UAIF2, cmucal_mux_clk_aud_uaif2_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_AUD_UAIF1, cmucal_mux_clk_aud_uaif1_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_AUD_UAIF0, cmucal_mux_clk_aud_uaif0_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_AUD_CPU, cmucal_mux_clk_aud_cpu_parents, CLK_CON_MUX_MUX_CLK_AUD_CPU_SELECT, CLK_CON_MUX_MUX_CLK_AUD_CPU_BUSY, CLK_CON_MUX_MUX_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_HCHGEN_CLK_AUD_CPU, cmucal_mux_hchgen_clk_aud_cpu_parents, CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_SELECT, CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_BUSY, CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_CHUB_BUS, cmucal_mux_clk_chub_bus_parents, CLK_CON_MUX_MUX_CLK_CHUB_BUS_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_BUS_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_CHUB_I2C, cmucal_mux_clk_chub_i2c_parents, CLK_CON_MUX_MUX_CLK_CHUB_I2C_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_I2C_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CHUB_USI00, cmucal_mux_clk_chub_usi00_parents, CLK_CON_MUX_MUX_CLK_CHUB_USI00_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_USI00_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_USI00_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CHUB_USI01, cmucal_mux_clk_chub_usi01_parents, CLK_CON_MUX_MUX_CLK_CHUB_USI01_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_USI01_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_USI01_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLK_CHUB_TIMER_FCLK, cmucal_clk_chub_timer_fclk_parents, CLK_CON_MUX_CLK_CHUB_TIMER_FCLK_SELECT, CLK_CON_MUX_CLK_CHUB_TIMER_FCLK_BUSY, CLK_CON_MUX_CLK_CHUB_TIMER_FCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_I2C_CMGP, cmucal_mux_clk_i2c_cmgp_parents, CLK_CON_MUX_MUX_CLK_I2C_CMGP_SELECT, CLK_CON_MUX_MUX_CLK_I2C_CMGP_BUSY, CLK_CON_MUX_MUX_CLK_I2C_CMGP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_USI_CMGP00, cmucal_mux_clk_usi_cmgp00_parents, CLK_CON_MUX_MUX_CLK_USI_CMGP00_SELECT, CLK_CON_MUX_MUX_CLK_USI_CMGP00_BUSY, CLK_CON_MUX_MUX_CLK_USI_CMGP00_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_USI_CMGP01, cmucal_mux_clk_usi_cmgp01_parents, CLK_CON_MUX_MUX_CLK_USI_CMGP01_SELECT, CLK_CON_MUX_MUX_CLK_USI_CMGP01_BUSY, CLK_CON_MUX_MUX_CLK_USI_CMGP01_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_USI_CMGP02, cmucal_mux_clk_usi_cmgp02_parents, CLK_CON_MUX_MUX_CLK_USI_CMGP02_SELECT, CLK_CON_MUX_MUX_CLK_USI_CMGP02_BUSY, CLK_CON_MUX_MUX_CLK_USI_CMGP02_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_USI_CMGP03, cmucal_mux_clk_usi_cmgp03_parents, CLK_CON_MUX_MUX_CLK_USI_CMGP03_SELECT, CLK_CON_MUX_MUX_CLK_USI_CMGP03_BUSY, CLK_CON_MUX_MUX_CLK_USI_CMGP03_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CMGP_BUS, cmucal_mux_clk_cmgp_bus_parents, CLK_CON_MUX_MUX_CLK_CMGP_BUS_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_BUS_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLK_CMGP_ADC, cmucal_clk_cmgp_adc_parents, CLK_CON_MUX_CLK_CMGP_ADC_SELECT, CLK_CON_MUX_CLK_CMGP_ADC_BUSY, CLK_CON_MUX_CLK_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_BUS1_BUS, cmucal_mux_clkcmu_bus1_bus_parents, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MFC_BUS, cmucal_mux_clkcmu_mfc_bus_parents, CLK_CON_MUX_MUX_CLKCMU_MFC_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_MFC_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_MFC_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_FSYS0_USB30DRD, cmucal_mux_clkcmu_fsys0_usb30drd_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS0_USB30DRD_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS0_USB30DRD_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS0_USB30DRD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_FSYS0_UFS_EMBD, cmucal_mux_clkcmu_fsys0_ufs_embd_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CMGP_BUS, cmucal_mux_clkcmu_cmgp_bus_parents, CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_BUSC_BUS, cmucal_mux_clkcmu_busc_bus_parents, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_G2D_G2D, cmucal_mux_clkcmu_g2d_g2d_parents, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_SELECT, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_BUSY, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_FSYS1_MMC_CARD, cmucal_mux_clkcmu_fsys1_mmc_card_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DSPM_BUS, cmucal_mux_clkcmu_dspm_bus_parents, CLK_CON_MUX_MUX_CLKCMU_DSPM_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_DSPM_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_DSPM_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CPUCL0_SWITCH, cmucal_mux_clkcmu_cpucl0_switch_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CORE_BUS, cmucal_mux_clkcmu_core_bus_parents, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MIF_SWITCH, cmucal_mux_clkcmu_mif_switch_parents, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_ISPPRE_BUS, cmucal_mux_clkcmu_isppre_bus_parents, CLK_CON_MUX_MUX_CLKCMU_ISPPRE_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_ISPPRE_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_ISPPRE_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_ISPLP_BUS, cmucal_mux_clkcmu_isplp_bus_parents, CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_ISPHQ_BUS, cmucal_mux_clkcmu_isphq_bus_parents, CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_AUD_CPU, cmucal_mux_clkcmu_aud_cpu_parents, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_SELECT, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_BUSY, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_G2D_MSCL, cmucal_mux_clkcmu_g2d_mscl_parents, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_SELECT, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_BUSY, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HPM, cmucal_mux_clkcmu_hpm_parents, CLK_CON_MUX_MUX_CLKCMU_HPM_SELECT, CLK_CON_MUX_MUX_CLKCMU_HPM_BUSY, CLK_CON_MUX_MUX_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CPUCL0_DBG_BUS, cmucal_mux_clkcmu_cpucl0_dbg_bus_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_FSYS0_BUS, cmucal_mux_clkcmu_fsys0_bus_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CIS_CLK0, cmucal_mux_clkcmu_cis_clk0_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CIS_CLK1, cmucal_mux_clkcmu_cis_clk1_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CIS_CLK2, cmucal_mux_clkcmu_cis_clk2_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CIS_CLK3, cmucal_mux_clkcmu_cis_clk3_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_IVA_BUS, cmucal_mux_clkcmu_iva_bus_parents, CLK_CON_MUX_MUX_CLKCMU_IVA_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_IVA_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_IVA_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_FSYS1_UFS_CARD, cmucal_mux_clkcmu_fsys1_ufs_card_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CMU_CMUREF, cmucal_mux_cmu_cmuref_parents, CLK_CON_MUX_MUX_CMU_CMUREF_SELECT, CLK_CON_MUX_MUX_CMU_CMUREF_BUSY, CLK_CON_MUX_MUX_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC0_BUS, cmucal_mux_clkcmu_peric0_bus_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC1_BUS, cmucal_mux_clkcmu_peric1_bus_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIS_BUS, cmucal_mux_clkcmu_peris_bus_parents, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DCRD_BUS, cmucal_mux_clkcmu_dcrd_bus_parents, CLK_CON_MUX_MUX_CLKCMU_DCRD_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_DCRD_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_DCRD_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_FSYS0_DPGTC, cmucal_mux_clkcmu_fsys0_dpgtc_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_FSYS1_PCIE, cmucal_mux_clkcmu_fsys1_pcie_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CHUB_BUS, cmucal_mux_clkcmu_chub_bus_parents, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DCF_BUS, cmucal_mux_clkcmu_dcf_bus_parents, CLK_CON_MUX_MUX_CLKCMU_DCF_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_DCF_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_DCF_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_APM_BUS, cmucal_mux_clkcmu_apm_bus_parents, CLK_CON_MUX_MUX_CLKCMU_APM_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_APM_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_FSYS1_BUS, cmucal_mux_clkcmu_fsys1_bus_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CMU_CMUREF, cmucal_mux_clk_cmu_cmuref_parents, CLK_CON_MUX_MUX_CLK_CMU_CMUREF_SELECT, CLK_CON_MUX_MUX_CLK_CMU_CMUREF_BUSY, CLK_CON_MUX_MUX_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CPUCL1_SWITCH, cmucal_mux_clkcmu_cpucl1_switch_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_VTS_BUS, cmucal_mux_clkcmu_vts_bus_parents, CLK_CON_MUX_MUX_CLKCMU_VTS_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_VTS_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_ISPLP_VRA, cmucal_mux_clkcmu_isplp_vra_parents, CLK_CON_MUX_MUX_CLKCMU_ISPLP_VRA_SELECT, CLK_CON_MUX_MUX_CLKCMU_ISPLP_VRA_BUSY, CLK_CON_MUX_MUX_CLKCMU_ISPLP_VRA_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MFC_WFD, cmucal_mux_clkcmu_mfc_wfd_parents, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD_SELECT, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD_BUSY, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MIF_BUSP, cmucal_mux_clkcmu_mif_busp_parents, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_SELECT, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_BUSY, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC0_IP, cmucal_mux_clkcmu_peric0_ip_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC1_IP, cmucal_mux_clkcmu_peric1_ip_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DCPOST_BUS, cmucal_mux_clkcmu_dcpost_bus_parents, CLK_CON_MUX_MUX_CLKCMU_DCPOST_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_DCPOST_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_DCPOST_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_FSYS0_USBDP_DEBUG, cmucal_mux_clkcmu_fsys0_usbdp_debug_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDP_DEBUG_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDP_DEBUG_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDP_DEBUG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_ISPLP_GDC, cmucal_mux_clkcmu_isplp_gdc_parents, CLK_CON_MUX_MUX_CLKCMU_ISPLP_GDC_SELECT, CLK_CON_MUX_MUX_CLKCMU_ISPLP_GDC_BUSY, CLK_CON_MUX_MUX_CLKCMU_ISPLP_GDC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DSPS_AUD, cmucal_mux_clkcmu_dsps_aud_parents, CLK_CON_MUX_MUX_CLKCMU_DSPS_AUD_SELECT, CLK_CON_MUX_MUX_CLKCMU_DSPS_AUD_BUSY, CLK_CON_MUX_MUX_CLKCMU_DSPS_AUD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DPU_BUS, cmucal_mux_clkcmu_dpu_bus_parents, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL0_PLL, cmucal_mux_clk_cpucl0_pll_parents, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CLUSTER0_SCLK, cmucal_mux_clk_cluster0_sclk_parents, CLK_CON_MUX_MUX_CLK_CLUSTER0_SCLK_SELECT, CLK_CON_MUX_MUX_CLK_CLUSTER0_SCLK_BUSY, CLK_CON_MUX_MUX_CLK_CLUSTER0_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CLUSTER0_ACLK, cmucal_mux_clk_cluster0_aclk_parents, CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLK_SELECT, CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLK_BUSY, CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CLUSTER0_ACLKP, cmucal_mux_clk_cluster0_aclkp_parents, CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLKP_SELECT, CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLKP_BUSY, CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLKP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL1_PLL, cmucal_mux_clk_cpucl1_pll_parents, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_DSPS_BUS, cmucal_mux_clk_dsps_bus_parents, CLK_CON_MUX_MUX_CLK_DSPS_BUS_SELECT, CLK_CON_MUX_MUX_CLK_DSPS_BUS_BUSY, CLK_CON_MUX_MUX_CLK_DSPS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_G3D_BUSD, cmucal_mux_clk_g3d_busd_parents, CLK_CON_MUX_MUX_CLK_G3D_BUSD_SELECT, CLK_CON_MUX_MUX_CLK_G3D_BUSD_BUSY, CLK_CON_MUX_MUX_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKMUX_MIF_DDRPHY2X, cmucal_clkmux_mif_ddrphy2x_parents, CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X_SELECT, CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X_BUSY, CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_MIF_CMUREF, cmucal_mux_mif_cmuref_parents, CLK_CON_MUX_MUX_MIF_CMUREF_SELECT, CLK_CON_MUX_MUX_MIF_CMUREF_BUSY, CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIS_GIC, cmucal_mux_clk_peris_gic_parents, CLK_CON_MUX_MUX_CLK_PERIS_GIC_SELECT, CLK_CON_MUX_MUX_CLK_PERIS_GIC_BUSY, CLK_CON_MUX_MUX_CLK_PERIS_GIC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_MIF_DDRPHY2X_S2D, cmucal_clkcmu_mif_ddrphy2x_s2d_parents, CLK_CON_MUX_CLKCMU_MIF_DDRPHY2X_S2D_SELECT, CLK_CON_MUX_CLKCMU_MIF_DDRPHY2X_S2D_BUSY, CLK_CON_MUX_CLKCMU_MIF_DDRPHY2X_S2D_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_S2D_CORE, cmucal_mux_clk_s2d_core_parents, CLK_CON_MUX_MUX_CLK_S2D_CORE_SELECT, CLK_CON_MUX_MUX_CLK_S2D_CORE_BUSY, CLK_CON_MUX_MUX_CLK_S2D_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_VTS_BUS, cmucal_mux_clk_vts_bus_parents, CLK_CON_MUX_MUX_CLK_VTS_BUS_SELECT, CLK_CON_MUX_MUX_CLK_VTS_BUS_BUSY, CLK_CON_MUX_MUX_CLK_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(APM_CMU_APM_CLKOUT0, NULL, CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0_SELECT, CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0_BUSY, CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(APM_CMU_APM_CLKOUT1, NULL, CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT1_SELECT, CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT1_BUSY, CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(AUD_CMU_AUD_CLKOUT0, NULL, CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT0_SELECT, CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT0_BUSY, CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(AUD_CMU_AUD_CLKOUT1, NULL, CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT1_SELECT, CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT1_BUSY, CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(BUS1_CMU_BUS1_CLKOUT0, NULL, CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT0_SELECT, CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT0_BUSY, CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(BUS1_CMU_BUS1_CLKOUT1, NULL, CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT1_SELECT, CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT1_BUSY, CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(BUSC_CMU_BUSC_CLKOUT0, NULL, CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT0_SELECT, CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT0_BUSY, CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(BUSC_CMU_BUSC_CLKOUT1, NULL, CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT1_SELECT, CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT1_BUSY, CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CHUB_CMU_CHUB_CLKOUT0, NULL, CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT0_SELECT, CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT0_BUSY, CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CHUB_CMU_CHUB_CLKOUT1, NULL, CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT1_SELECT, CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT1_BUSY, CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CMGP_CMU_CMGP_CLKOUT0, NULL, CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT0_SELECT, CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT0_BUSY, CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CMGP_CMU_CMGP_CLKOUT1, NULL, CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT1_SELECT, CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT1_BUSY, CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CMU_CMU_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CMU_CMU_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CORE_CMU_CORE_CLKOUT0, NULL, CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT0_SELECT, CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT0_BUSY, CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CORE_CMU_CORE_CLKOUT1, NULL, CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT1_SELECT, CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT1_BUSY, CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CPUCL0_CMU_CPUCL0_CLKOUT0, NULL, CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT0_SELECT, CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT0_BUSY, CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CPUCL0_CMU_CPUCL0_CLKOUT1, NULL, CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT1_SELECT, CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT1_BUSY, CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT0, NULL, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT0_SELECT, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT0_BUSY, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT1, NULL, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT1_SELECT, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT1_BUSY, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CPUCL1_CMU_CPUCL1_CLKOUT0, NULL, CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT0_SELECT, CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT0_BUSY, CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CPUCL1_CMU_CPUCL1_CLKOUT1, NULL, CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT1_SELECT, CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT1_BUSY, CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT0, NULL, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT0_SELECT, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT0_BUSY, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT1, NULL, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT1_SELECT, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT1_BUSY, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(DCF_CMU_DCF_CLKOUT0, NULL, CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT0_SELECT, CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT0_BUSY, CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(DCF_CMU_DCF_CLKOUT1, NULL, CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT1_SELECT, CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT1_BUSY, CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(DCPOST_CMU_DCPOST_CLKOUT0, NULL, CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT0_SELECT, CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT0_BUSY, CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(DCPOST_CMU_DCPOST_CLKOUT1, NULL, CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT1_SELECT, CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT1_BUSY, CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(DCRD_CMU_DCRD_CLKOUT0, NULL, CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT0_SELECT, CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT0_BUSY, CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(DCRD_CMU_DCRD_CLKOUT1, NULL, CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT1_SELECT, CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT1_BUSY, CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(DPU_CMU_DPU_CLKOUT0, NULL, CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT0_SELECT, CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT0_BUSY, CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(DPU_CMU_DPU_CLKOUT1, NULL, CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT1_SELECT, CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT1_BUSY, CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(DSPM_CMU_DSPM_CLKOUT0, NULL, CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT0_SELECT, CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT0_BUSY, CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(DSPM_CMU_DSPM_CLKOUT1, NULL, CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT1_SELECT, CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT1_BUSY, CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(DSPS_CMU_DSPS_CLKOUT0, NULL, CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT0_SELECT, CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT0_BUSY, CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(DSPS_CMU_DSPS_CLKOUT1, NULL, CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT1_SELECT, CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT1_BUSY, CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(FSYS0_CMU_FSYS0_CLKOUT0, NULL, CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT0_SELECT, CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT0_BUSY, CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(FSYS0_CMU_FSYS0_CLKOUT1, NULL, CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT1_SELECT, CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT1_BUSY, CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(FSYS1_CMU_FSYS1_CLKOUT0, NULL, CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT0_SELECT, CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT0_BUSY, CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(FSYS1_CMU_FSYS1_CLKOUT1, NULL, CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT1_SELECT, CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT1_BUSY, CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(G2D_CMU_G2D_CLKOUT0, NULL, CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT0_SELECT, CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT0_BUSY, CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(G2D_CMU_G2D_CLKOUT1, NULL, CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT1_SELECT, CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT1_BUSY, CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(G3D_CMU_G3D_CLKOUT0, NULL, CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT0_SELECT, CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT0_BUSY, CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(G3D_CMU_G3D_CLKOUT1, NULL, CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT1_SELECT, CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT1_BUSY, CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(G3D_EMBEDDED_CMU_G3D_CLKOUT0, NULL, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT0_SELECT, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT0_BUSY, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(G3D_EMBEDDED_CMU_G3D_CLKOUT1, NULL, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT1_SELECT, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT1_BUSY, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(ISPHQ_CMU_ISPHQ_CLKOUT0, NULL, CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT0_SELECT, CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT0_BUSY, CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(ISPHQ_CMU_ISPHQ_CLKOUT1, NULL, CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT1_SELECT, CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT1_BUSY, CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(ISPLP_CMU_ISPLP_CLKOUT0, NULL, CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT0_SELECT, CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT0_BUSY, CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(ISPLP_CMU_ISPLP_CLKOUT1, NULL, CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT1_SELECT, CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT1_BUSY, CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(ISPPRE_CMU_ISPPRE_CLKOUT0, NULL, CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT0_SELECT, CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT0_BUSY, CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(ISPPRE_CMU_ISPPRE_CLKOUT1, NULL, CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT1_SELECT, CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT1_BUSY, CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(IVA_CMU_IVA_CLKOUT0, NULL, CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT0_SELECT, CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT0_BUSY, CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(IVA_CMU_IVA_CLKOUT1, NULL, CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT1_SELECT, CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT1_BUSY, CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MFC_CMU_MFC_CLKOUT0, NULL, CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT0_SELECT, CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT0_BUSY, CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MFC_CMU_MFC_CLKOUT1, NULL, CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT1_SELECT, CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT1_BUSY, CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MIF_CMU_MIF_CLKOUT0, NULL, CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT0_SELECT, CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT0_BUSY, CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MIF_CMU_MIF_CLKOUT1, NULL, CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT1_SELECT, CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT1_BUSY, CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(PERIC0_CMU_PERIC0_CLKOUT0, NULL, CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0_SELECT, CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0_BUSY, CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(PERIC0_CMU_PERIC0_CLKOUT1, NULL, CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT1_SELECT, CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT1_BUSY, CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(PERIC1_CMU_PERIC1_CLKOUT0, NULL, CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0_SELECT, CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0_BUSY, CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(PERIC1_CMU_PERIC1_CLKOUT1, NULL, CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT1_SELECT, CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT1_BUSY, CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(PERIS_CMU_PERIS_CLKOUT0, NULL, CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT0_SELECT, CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT0_BUSY, CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(PERIS_CMU_PERIS_CLKOUT1, NULL, CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT1_SELECT, CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT1_BUSY, CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(VTS_CMU_VTS_CLKOUT0, NULL, CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT0_SELECT, CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT0_BUSY, CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(VTS_CMU_VTS_CLKOUT1, NULL, CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT1_SELECT, CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT1_BUSY, CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_APM_BUS_USER, cmucal_mux_clkcmu_apm_bus_user_parents, PLL_CON0_MUX_CLKCMU_APM_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_APM_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_APM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_DLL_USER, cmucal_mux_dll_user_parents, PLL_CON0_MUX_DLL_USER_MUX_SEL, PLL_CON0_MUX_DLL_USER_BUSY, PLL_CON2_MUX_DLL_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_AUD_CPU_USER, cmucal_mux_clkcmu_aud_cpu_user_parents, PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_BUSY, PLL_CON2_MUX_CLKCMU_AUD_CPU_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_BUS1_BUS_USER, cmucal_mux_clkcmu_bus1_bus_user_parents, PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_BUS1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_BUSC_BUS_USER, cmucal_mux_clkcmu_busc_bus_user_parents, PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_BUSC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CHUB_BUS_USER, cmucal_mux_clkcmu_chub_bus_user_parents, PLL_CON0_MUX_CLKCMU_CHUB_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CHUB_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_CHUB_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CHUB_DLL_BUS_USER, cmucal_mux_clkcmu_chub_dll_bus_user_parents, PLL_CON0_MUX_CLKCMU_CHUB_DLL_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CHUB_DLL_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_CHUB_DLL_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CMGP_BUS_USER, cmucal_mux_clkcmu_cmgp_bus_user_parents, PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_CMGP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CMGP_DLL_USER, cmucal_mux_clkcmu_cmgp_dll_user_parents, PLL_CON0_MUX_CLKCMU_CMGP_DLL_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CMGP_DLL_USER_BUSY, PLL_CON2_MUX_CLKCMU_CMGP_DLL_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CORE_BUS_USER, cmucal_mux_clkcmu_core_bus_user_parents, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_CORE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CPUCL0_SWITCH_USER, cmucal_mux_clkcmu_cpucl0_switch_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_BUSY, PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CPUCL0_DBG_BUS_USER, cmucal_mux_clkcmu_cpucl0_dbg_bus_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CPUCL1_SWITCH_USER, cmucal_mux_clkcmu_cpucl1_switch_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_BUSY, PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DCF_BUS_USER, cmucal_mux_clkcmu_dcf_bus_user_parents, PLL_CON0_MUX_CLKCMU_DCF_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DCF_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_DCF_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DCPOST_BUS_USER, cmucal_mux_clkcmu_dcpost_bus_user_parents, PLL_CON0_MUX_CLKCMU_DCPOST_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DCPOST_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_DCPOST_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DCRD_BUS_USER, cmucal_mux_clkcmu_dcrd_bus_user_parents, PLL_CON0_MUX_CLKCMU_DCRD_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DCRD_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_DCRD_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DPU_BUS_USER, cmucal_mux_clkcmu_dpu_bus_user_parents, PLL_CON0_MUX_CLKCMU_DPU_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DPU_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_DPU_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DSPM_BUS_USER, cmucal_mux_clkcmu_dspm_bus_user_parents, PLL_CON0_MUX_CLKCMU_DSPM_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DSPM_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_DSPM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DSPS_BUS_USER, cmucal_mux_clkcmu_dsps_bus_user_parents, PLL_CON0_MUX_CLKCMU_DSPS_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DSPS_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_DSPS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DSPS_AUD_USER, cmucal_mux_clkcmu_dsps_aud_user_parents, PLL_CON0_MUX_CLKCMU_DSPS_AUD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DSPS_AUD_USER_BUSY, PLL_CON2_MUX_CLKCMU_DSPS_AUD_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_FSYS0_UFS_EMBD_USER, cmucal_mux_clkcmu_fsys0_ufs_embd_user_parents, PLL_CON0_MUX_CLKCMU_FSYS0_UFS_EMBD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS0_UFS_EMBD_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS0_UFS_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_FSYS0_BUS_USER, cmucal_mux_clkcmu_fsys0_bus_user_parents, PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_FSYS0_USB30DRD_USER, cmucal_mux_clkcmu_fsys0_usb30drd_user_parents, PLL_CON0_MUX_CLKCMU_FSYS0_USB30DRD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS0_USB30DRD_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS0_USB30DRD_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_FSYS0_DPGTC_USER, cmucal_mux_clkcmu_fsys0_dpgtc_user_parents, PLL_CON0_MUX_CLKCMU_FSYS0_DPGTC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS0_DPGTC_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS0_DPGTC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_FSYS0_USBDP_DEBUG_USER, cmucal_mux_clkcmu_fsys0_usbdp_debug_user_parents, PLL_CON0_MUX_CLKCMU_FSYS0_USBDP_DEBUG_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS0_USBDP_DEBUG_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS0_USBDP_DEBUG_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_FSYS1_BUS_USER, cmucal_mux_clkcmu_fsys1_bus_user_parents, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_FSYS1_MMC_CARD_USER, cmucal_mux_clkcmu_fsys1_mmc_card_user_parents, PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS1_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_FSYS1_PCIE_USER, cmucal_mux_clkcmu_fsys1_pcie_user_parents, PLL_CON0_MUX_CLKCMU_FSYS1_PCIE_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS1_PCIE_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS1_PCIE_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_FSYS1_UFS_CARD_USER, cmucal_mux_clkcmu_fsys1_ufs_card_user_parents, PLL_CON0_MUX_CLKCMU_FSYS1_UFS_CARD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS1_UFS_CARD_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS1_UFS_CARD_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_G2D_G2D_USER, cmucal_mux_clkcmu_g2d_g2d_user_parents, PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_BUSY, PLL_CON2_MUX_CLKCMU_G2D_G2D_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_G2D_MSCL_USER, cmucal_mux_clkcmu_g2d_mscl_user_parents, PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER_BUSY, PLL_CON2_MUX_CLKCMU_G2D_MSCL_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_G3D_SWITCH_USER, cmucal_mux_clkcmu_g3d_switch_user_parents, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_BUSY, PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_EMBEDDED_G3D_USER, cmucal_mux_clkcmu_embedded_g3d_user_parents, PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_USER_BUSY, PLL_CON2_MUX_CLKCMU_EMBEDDED_G3D_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_ISPHQ_BUS_USER, cmucal_mux_clkcmu_isphq_bus_user_parents, PLL_CON0_MUX_CLKCMU_ISPHQ_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_ISPHQ_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_ISPHQ_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_ISPLP_BUS_USER, cmucal_mux_clkcmu_isplp_bus_user_parents, PLL_CON0_MUX_CLKCMU_ISPLP_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_ISPLP_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_ISPLP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_ISPLP_VRA_USER, cmucal_mux_clkcmu_isplp_vra_user_parents, PLL_CON0_MUX_CLKCMU_ISPLP_VRA_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_ISPLP_VRA_USER_BUSY, PLL_CON2_MUX_CLKCMU_ISPLP_VRA_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_ISPLP_GDC_USER, cmucal_mux_clkcmu_isplp_gdc_user_parents, PLL_CON0_MUX_CLKCMU_ISPLP_GDC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_ISPLP_GDC_USER_BUSY, PLL_CON2_MUX_CLKCMU_ISPLP_GDC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_ISPPRE_BUS_USER, cmucal_mux_clkcmu_isppre_bus_user_parents, PLL_CON0_MUX_CLKCMU_ISPPRE_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_ISPPRE_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_ISPPRE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_IVA_BUS_USER, cmucal_mux_clkcmu_iva_bus_user_parents, PLL_CON0_MUX_CLKCMU_IVA_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_IVA_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_IVA_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MFC_BUS_USER, cmucal_mux_clkcmu_mfc_bus_user_parents, PLL_CON0_MUX_CLKCMU_MFC_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MFC_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_MFC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MFC_WFD_USER, cmucal_mux_clkcmu_mfc_wfd_user_parents, PLL_CON0_MUX_CLKCMU_MFC_WFD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MFC_WFD_USER_BUSY, PLL_CON2_MUX_CLKCMU_MFC_WFD_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MIF_BUSP_USER, cmucal_mux_clkcmu_mif_busp_user_parents, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_BUSY, PLL_CON2_MUX_CLKCMU_MIF_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC0_BUS_USER, cmucal_mux_clkcmu_peric0_bus_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC0_IP_USER, cmucal_mux_clkcmu_peric0_ip_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC0_IP_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC1_BUS_USER, cmucal_mux_clkcmu_peric1_bus_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC1_IP_USER, cmucal_mux_clkcmu_peric1_ip_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC1_IP_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIS_BUS_USER, cmucal_mux_clkcmu_peris_bus_user_parents, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_VTS_BUS_USER, cmucal_mux_clkcmu_vts_bus_user_parents, PLL_CON0_MUX_CLKCMU_VTS_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_VTS_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_VTS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_VTS_DLL_USER, cmucal_mux_clkcmu_vts_dll_user_parents, PLL_CON0_MUX_CLKCMU_VTS_DLL_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_VTS_DLL_USER_BUSY, PLL_CON2_MUX_CLKCMU_VTS_DLL_USER_ENABLE_AUTOMATIC_CLKGATING),
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};
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/*====================The section of DIVs===================*/
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unsigned int cmucal_div_size = 146;
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struct cmucal_div cmucal_div_list[] = {
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CLK_DIV(CLKCMU_APM_DLL_CMGP, GATE_CLKCMU_APM_DLL_CMGP, CLK_CON_DIV_CLKCMU_APM_DLL_CMGP_DIVRATIO, CLK_CON_DIV_CLKCMU_APM_DLL_CMGP_BUSY, CLK_CON_DIV_CLKCMU_APM_DLL_CMGP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_APM_DLL_VTS, GATE_CLKCMU_APM_DLL_VTS, CLK_CON_DIV_CLKCMU_APM_DLL_VTS_DIVRATIO, CLK_CON_DIV_CLKCMU_APM_DLL_VTS_BUSY, CLK_CON_DIV_CLKCMU_APM_DLL_VTS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_APM_BUS, MUX_CLK_APM_BUS, CLK_CON_DIV_DIV_CLK_APM_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_APM_BUS_BUSY, CLK_CON_DIV_DIV_CLK_APM_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_PLL, PLL_AUD, CLK_CON_DIV_DIV_CLK_AUD_PLL_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_PLL_BUSY, CLK_CON_DIV_DIV_CLK_AUD_PLL_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_AUDIF, PLL_AUD, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_BUSY, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_CPU_ATCLK, MUX_HCHGEN_CLK_AUD_CPU, CLK_CON_DIV_DIV_CLK_AUD_CPU_ATCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_ATCLK_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_ATCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_CPU_PCLKDBG, MUX_HCHGEN_CLK_AUD_CPU, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_DSIF, DIV_CLK_AUD_AUDIF, CLK_CON_DIV_DIV_CLK_AUD_DSIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_DSIF_BUSY, CLK_CON_DIV_DIV_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_UAIF0, DIV_CLK_AUD_AUDIF, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_UAIF1, DIV_CLK_AUD_AUDIF, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_UAIF2, DIV_CLK_AUD_AUDIF, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_UAIF3, DIV_CLK_AUD_AUDIF, CLK_CON_DIV_DIV_CLK_AUD_UAIF3_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF3_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_CPU_ACLK, MUX_HCHGEN_CLK_AUD_CPU, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_BUS, PLL_AUD, CLK_CON_DIV_DIV_CLK_AUD_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_BUS_BUSY, CLK_CON_DIV_DIV_CLK_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_BUSP, DIV_CLK_AUD_BUS, CLK_CON_DIV_DIV_CLK_AUD_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_AUD_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_DMIC, DIV_CLK_AUD_DSIF, CLK_CON_DIV_DIV_CLK_AUD_DMIC_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_DMIC_BUSY, CLK_CON_DIV_DIV_CLK_AUD_DMIC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_BUSC_BUSP, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_DIV_DIV_CLK_BUSC_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_BUSC_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_BUSC_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CHUB_USI01, GATE_CLK_CHUB_USI01, CLK_CON_DIV_DIV_CLK_CHUB_USI01_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_USI01_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_USI01_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CHUB_I2C, GATE_CLK_CHUB_I2C, CLK_CON_DIV_DIV_CLK_CHUB_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_I2C_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CHUB_USI00, GATE_CLK_CHUB_USI00, CLK_CON_DIV_DIV_CLK_CHUB_USI00_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_USI00_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_USI00_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CHUB_BUS, MUX_CLK_CHUB_BUS, CLK_CON_DIV_DIV_CLK_CHUB_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_BUS_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_I2C_CMGP, GATE_CLK_I2C_CMGP, CLK_CON_DIV_DIV_CLK_I2C_CMGP_DIVRATIO, CLK_CON_DIV_DIV_CLK_I2C_CMGP_BUSY, CLK_CON_DIV_DIV_CLK_I2C_CMGP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_USI_CMGP01, GATE_CLK_USI_CMGP01, CLK_CON_DIV_DIV_CLK_USI_CMGP01_DIVRATIO, CLK_CON_DIV_DIV_CLK_USI_CMGP01_BUSY, CLK_CON_DIV_DIV_CLK_USI_CMGP01_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_USI_CMGP00, GATE_CLK_USI_CMGP00, CLK_CON_DIV_DIV_CLK_USI_CMGP00_DIVRATIO, CLK_CON_DIV_DIV_CLK_USI_CMGP00_BUSY, CLK_CON_DIV_DIV_CLK_USI_CMGP00_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_USI_CMGP02, GATE_CLK_USI_CMGP02, CLK_CON_DIV_DIV_CLK_USI_CMGP02_DIVRATIO, CLK_CON_DIV_DIV_CLK_USI_CMGP02_BUSY, CLK_CON_DIV_DIV_CLK_USI_CMGP02_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_USI_CMGP03, GATE_CLK_USI_CMGP03, CLK_CON_DIV_DIV_CLK_USI_CMGP03_DIVRATIO, CLK_CON_DIV_DIV_CLK_USI_CMGP03_BUSY, CLK_CON_DIV_DIV_CLK_USI_CMGP03_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CMGP_ADC, MUX_CLK_CMGP_BUS, CLK_CON_DIV_DIV_CLK_CMGP_ADC_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_ADC_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_APM_BUS, GATE_CLKCMU_APM_BUS, CLK_CON_DIV_CLKCMU_APM_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_APM_BUS_BUSY, CLK_CON_DIV_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_PLL_SHARED0_DIV2, PLL_SHARED0, CLK_CON_DIV_DIV_PLL_SHARED0_DIV2_DIVRATIO, CLK_CON_DIV_DIV_PLL_SHARED0_DIV2_BUSY, CLK_CON_DIV_DIV_PLL_SHARED0_DIV2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_G3D_SWITCH, GATE_CLKCMU_G3D_SWITCH, CLK_CON_DIV_CLKCMU_G3D_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_G3D_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIC0_BUS, GATE_CLKCMU_PERIC0_BUS, CLK_CON_DIV_CLKCMU_PERIC0_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC0_BUS_BUSY, CLK_CON_DIV_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIS_BUS, GATE_CLKCMU_PERIS_BUS, CLK_CON_DIV_CLKCMU_PERIS_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIS_BUS_BUSY, CLK_CON_DIV_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_FSYS0_BUS, GATE_CLKCMU_FSYS0_BUS, CLK_CON_DIV_CLKCMU_FSYS0_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS0_BUS_BUSY, CLK_CON_DIV_CLKCMU_FSYS0_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_DPU_BUS, GATE_CLKCMU_DPU_BUS, CLK_CON_DIV_CLKCMU_DPU_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_DPU_BUS_BUSY, CLK_CON_DIV_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_PLL_SHARED1_DIV2, PLL_SHARED1, CLK_CON_DIV_DIV_PLL_SHARED1_DIV2_DIVRATIO, CLK_CON_DIV_DIV_PLL_SHARED1_DIV2_BUSY, CLK_CON_DIV_DIV_PLL_SHARED1_DIV2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_BUS1_BUS, GATE_CLKCMU_BUS1_BUS, CLK_CON_DIV_CLKCMU_BUS1_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_BUS1_BUS_BUSY, CLK_CON_DIV_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_PLL_SHARED2_DIV2, PLL_SHARED2, CLK_CON_DIV_DIV_PLL_SHARED2_DIV2_DIVRATIO, CLK_CON_DIV_DIV_PLL_SHARED2_DIV2_BUSY, CLK_CON_DIV_DIV_PLL_SHARED2_DIV2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_PLL_SHARED3_DIV2, PLL_SHARED3, CLK_CON_DIV_DIV_PLL_SHARED3_DIV2_DIVRATIO, CLK_CON_DIV_DIV_PLL_SHARED3_DIV2_BUSY, CLK_CON_DIV_DIV_PLL_SHARED3_DIV2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_PLL_SHARED4_DIV2, PLL_SHARED4, CLK_CON_DIV_DIV_PLL_SHARED4_DIV2_DIVRATIO, CLK_CON_DIV_DIV_PLL_SHARED4_DIV2_BUSY, CLK_CON_DIV_DIV_PLL_SHARED4_DIV2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_PLL_SHARED0_DIV4, DIV_PLL_SHARED0_DIV2, CLK_CON_DIV_DIV_PLL_SHARED0_DIV4_DIVRATIO, CLK_CON_DIV_DIV_PLL_SHARED0_DIV4_BUSY, CLK_CON_DIV_DIV_PLL_SHARED0_DIV4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_MFC_BUS, GATE_CLKCMU_MFC_BUS, CLK_CON_DIV_CLKCMU_MFC_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_MFC_BUS_BUSY, CLK_CON_DIV_CLKCMU_MFC_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_G2D_G2D, GATE_CLKCMU_G2D_G2D, CLK_CON_DIV_CLKCMU_G2D_G2D_DIVRATIO, CLK_CON_DIV_CLKCMU_G2D_G2D_BUSY, CLK_CON_DIV_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_FSYS0_USB30DRD, GATE_CLKCMU_FSYS0_USB30DRD, CLK_CON_DIV_CLKCMU_FSYS0_USB30DRD_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS0_USB30DRD_BUSY, CLK_CON_DIV_CLKCMU_FSYS0_USB30DRD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_FSYS0_UFS_EMBD, GATE_CLKCMU_FSYS0_UFS_EMBD, CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD_BUSY, CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_FSYS1_MMC_CARD, GATE_CLKCMU_FSYS1_MMC_CARD, CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD_BUSY, CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_FSYS1_BUS, GATE_CLKCMU_FSYS1_BUS, CLK_CON_DIV_CLKCMU_FSYS1_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS1_BUS_BUSY, CLK_CON_DIV_CLKCMU_FSYS1_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CMGP_BUS, GATE_CLKCMU_CMGP_BUS, CLK_CON_DIV_CLKCMU_CMGP_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_CMGP_BUS_BUSY, CLK_CON_DIV_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_DSPM_BUS, GATE_CLKCMU_DSPM_BUS, CLK_CON_DIV_CLKCMU_DSPM_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_DSPM_BUS_BUSY, CLK_CON_DIV_CLKCMU_DSPM_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIC1_BUS, GATE_CLKCMU_PERIC1_BUS, CLK_CON_DIV_CLKCMU_PERIC1_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_BUS_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_BUSC_BUS, GATE_CLKCMU_BUSC_BUS, CLK_CON_DIV_CLKCMU_BUSC_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_BUSC_BUS_BUSY, CLK_CON_DIV_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CPUCL1_SWITCH, GATE_CLKCMU_CPUCL1_SWITCH, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CPUCL0_SWITCH, GATE_CLKCMU_CPUCL0_SWITCH, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CORE_BUS, GATE_CLKCMU_CORE_BUS, CLK_CON_DIV_CLKCMU_CORE_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_CORE_BUS_BUSY, CLK_CON_DIV_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_ISPPRE_BUS, GATE_CLKCMU_ISPPRE_BUS, CLK_CON_DIV_CLKCMU_ISPPRE_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_ISPPRE_BUS_BUSY, CLK_CON_DIV_CLKCMU_ISPPRE_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_ISPLP_BUS, GATE_CLKCMU_ISPLP_BUS, CLK_CON_DIV_CLKCMU_ISPLP_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_ISPLP_BUS_BUSY, CLK_CON_DIV_CLKCMU_ISPLP_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_ISPHQ_BUS, GATE_CLKCMU_ISPHQ_BUS, CLK_CON_DIV_CLKCMU_ISPHQ_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_ISPHQ_BUS_BUSY, CLK_CON_DIV_CLKCMU_ISPHQ_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_AUD_CPU, GATE_CLKCMU_AUD_CPU, CLK_CON_DIV_CLKCMU_AUD_CPU_DIVRATIO, CLK_CON_DIV_CLKCMU_AUD_CPU_BUSY, CLK_CON_DIV_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_G2D_MSCL, GATE_CLKCMU_G2D_MSCL, CLK_CON_DIV_CLKCMU_G2D_MSCL_DIVRATIO, CLK_CON_DIV_CLKCMU_G2D_MSCL_BUSY, CLK_CON_DIV_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_HPM, GATE_CLKCMU_HPM, CLK_CON_DIV_CLKCMU_HPM_DIVRATIO, CLK_CON_DIV_CLKCMU_HPM_BUSY, CLK_CON_DIV_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CPUCL0_DBG_BUS, GATE_CLKCMU_CPUCL0_DBG_BUS, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_BUSY, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CIS_CLK0, GATE_CLKCMU_CIS_CLK0, CLK_CON_DIV_CLKCMU_CIS_CLK0_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK0_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CIS_CLK1, GATE_CLKCMU_CIS_CLK1, CLK_CON_DIV_CLKCMU_CIS_CLK1_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK1_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CIS_CLK2, GATE_CLKCMU_CIS_CLK2, CLK_CON_DIV_CLKCMU_CIS_CLK2_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK2_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CIS_CLK3, GATE_CLKCMU_CIS_CLK3, CLK_CON_DIV_CLKCMU_CIS_CLK3_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK3_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_IVA_BUS, GATE_CLKCMU_IVA_BUS, CLK_CON_DIV_CLKCMU_IVA_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_IVA_BUS_BUSY, CLK_CON_DIV_CLKCMU_IVA_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_FSYS1_UFS_CARD, GATE_CLKCMU_FSYS1_UFS_CARD, CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD_BUSY, CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_PLL_SHARED1_DIV4, DIV_PLL_SHARED1_DIV2, CLK_CON_DIV_DIV_PLL_SHARED1_DIV4_DIVRATIO, CLK_CON_DIV_DIV_PLL_SHARED1_DIV4_BUSY, CLK_CON_DIV_DIV_PLL_SHARED1_DIV4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_FSYS0_DPGTC, GATE_CLKCMU_FSYS0_DPGTC, CLK_CON_DIV_CLKCMU_FSYS0_DPGTC_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS0_DPGTC_BUSY, CLK_CON_DIV_CLKCMU_FSYS0_DPGTC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_MODEM_SHARED0, GATE_CLKCMU_MODEM_SHARED0, CLK_CON_DIV_CLKCMU_MODEM_SHARED0_DIVRATIO, CLK_CON_DIV_CLKCMU_MODEM_SHARED0_BUSY, CLK_CON_DIV_CLKCMU_MODEM_SHARED0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_MODEM_SHARED1, GATE_CLKCMU_MODEM_SHARED1, CLK_CON_DIV_CLKCMU_MODEM_SHARED1_DIVRATIO, CLK_CON_DIV_CLKCMU_MODEM_SHARED1_BUSY, CLK_CON_DIV_CLKCMU_MODEM_SHARED1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_DCRD_BUS, GATE_CLKCMU_DCRD_BUS, CLK_CON_DIV_CLKCMU_DCRD_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_DCRD_BUS_BUSY, CLK_CON_DIV_CLKCMU_DCRD_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CMU_CMUREF, MUX_CLK_CMU_CMUREF, CLK_CON_DIV_DIV_CLK_CMU_CMUREF_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMU_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CHUB_BUS, GATE_CLKCMU_CHUB_BUS, CLK_CON_DIV_CLKCMU_CHUB_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_CHUB_BUS_BUSY, CLK_CON_DIV_CLKCMU_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_DCF_BUS, GATE_CLKCMU_DCF_BUS, CLK_CON_DIV_CLKCMU_DCF_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_DCF_BUS_BUSY, CLK_CON_DIV_CLKCMU_DCF_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_VTS_BUS, GATE_CLKCMU_VTS_BUS, CLK_CON_DIV_CLKCMU_VTS_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_VTS_BUS_BUSY, CLK_CON_DIV_CLKCMU_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_ISPLP_VRA, GATE_CLKCMU_ISPLP_VRA, CLK_CON_DIV_CLKCMU_ISPLP_VRA_DIVRATIO, CLK_CON_DIV_CLKCMU_ISPLP_VRA_BUSY, CLK_CON_DIV_CLKCMU_ISPLP_VRA_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_MFC_WFD, GATE_CLKCMU_MFC_WFD, CLK_CON_DIV_CLKCMU_MFC_WFD_DIVRATIO, CLK_CON_DIV_CLKCMU_MFC_WFD_BUSY, CLK_CON_DIV_CLKCMU_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_MIF_BUSP, GATE_CLKCMU_MIF_BUSP, CLK_CON_DIV_CLKCMU_MIF_BUSP_DIVRATIO, CLK_CON_DIV_CLKCMU_MIF_BUSP_BUSY, CLK_CON_DIV_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIC0_IP, GATE_CLKCMU_PERIC0_IP, CLK_CON_DIV_CLKCMU_PERIC0_IP_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC0_IP_BUSY, CLK_CON_DIV_CLKCMU_PERIC0_IP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIC1_IP, GATE_CLKCMU_PERIC1_IP, CLK_CON_DIV_CLKCMU_PERIC1_IP_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_IP_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_IP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_DCPOST_BUS, GATE_CLKCMU_DCPOST_BUS, CLK_CON_DIV_CLKCMU_DCPOST_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_DCPOST_BUS_BUSY, CLK_CON_DIV_CLKCMU_DCPOST_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_ISPLP_GDC, GATE_CLKCMU_ISPLP_GDC, CLK_CON_DIV_CLKCMU_ISPLP_GDC_DIVRATIO, CLK_CON_DIV_CLKCMU_ISPLP_GDC_BUSY, CLK_CON_DIV_CLKCMU_ISPLP_GDC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_DSPS_AUD, GATE_CLKCMU_DSPS_AUD, CLK_CON_DIV_CLKCMU_DSPS_AUD_DIVRATIO, CLK_CON_DIV_CLKCMU_DSPS_AUD_BUSY, CLK_CON_DIV_CLKCMU_DSPS_AUD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_PLL_SHARED1_DIV3, PLL_SHARED1, CLK_CON_DIV_DIV_PLL_SHARED1_DIV3_DIVRATIO, CLK_CON_DIV_DIV_PLL_SHARED1_DIV3_BUSY, CLK_CON_DIV_DIV_PLL_SHARED1_DIV3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_PLL_SHARED0_DIV3, PLL_SHARED0, CLK_CON_DIV_DIV_PLL_SHARED0_DIV3_DIVRATIO, CLK_CON_DIV_DIV_PLL_SHARED0_DIV3_BUSY, CLK_CON_DIV_DIV_PLL_SHARED0_DIV3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CORE_BUSP, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_DIV_DIV_CLK_CORE_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_CORE_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_CORE_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL0_CMUREF, DIV_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CLUSTER0_ACLK, GATE_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CLUSTER0_ATCLK, GATE_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CLUSTER0_PCLKDBG, GATE_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL0_CPU, MUX_CLK_CPUCL0_PLL, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CLUSTER0_PERIPHCLK, GATE_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL0_DBG_PCLKDBG, MUX_CLKCMU_CPUCL0_DBG_BUS_USER, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL0_PCLK, DIV_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CLUSTER0_ACLKP, GATE_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLKP_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLKP_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLKP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL1_CMUREF, DIV_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL1_PCLK, DIV_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CLUSTER1_ACLK, GATE_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CLUSTER1_ATCLK, GATE_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL1_CPU, MUX_CLK_CPUCL1_PLL, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL1_PCLKDBG, DIV_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_DCF_BUSP, MUX_CLKCMU_DCF_BUS_USER, CLK_CON_DIV_DIV_CLK_DCF_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DCF_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_DCF_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_DCPOST_BUSP, MUX_CLKCMU_DCPOST_BUS_USER, CLK_CON_DIV_DIV_CLK_DCPOST_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DCPOST_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_DCPOST_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_DCRD_BUSP, MUX_CLKCMU_DCRD_BUS_USER, CLK_CON_DIV_DIV_CLK_DCRD_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DCRD_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_DCRD_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_DCRD_BUSD_HALF, MUX_CLKCMU_DCRD_BUS_USER, CLK_CON_DIV_DIV_CLK_DCRD_BUSD_HALF_DIVRATIO, CLK_CON_DIV_DIV_CLK_DCRD_BUSD_HALF_BUSY, CLK_CON_DIV_DIV_CLK_DCRD_BUSD_HALF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_DPU_BUSP, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_DIV_DIV_CLK_DPU_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DPU_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_DPU_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_DSPM_BUSP, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_DIV_DIV_CLK_DSPM_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DSPM_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_DSPM_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_DSPS_BUSP, MUX_CLK_DSPS_BUS, CLK_CON_DIV_DIV_CLK_DSPS_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DSPS_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_DSPS_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_G2D_BUSP, MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_DIV_DIV_CLK_G2D_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_G2D_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_G2D_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_G3D_BUSP, MUX_CLK_G3D_BUSD, CLK_CON_DIV_DIV_CLK_G3D_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_G3D_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_G3D_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_G3D_BUSD, MUX_CLK_G3D_BUSD, CLK_CON_DIV_DIV_CLK_G3D_BUSD_DIVRATIO, CLK_CON_DIV_DIV_CLK_G3D_BUSD_BUSY, CLK_CON_DIV_DIV_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_ISPHQ_BUSP, MUX_CLKCMU_ISPHQ_BUS_USER, CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_ISPLP_BUSP, MUX_CLKCMU_ISPLP_BUS_USER, CLK_CON_DIV_DIV_CLK_ISPLP_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_ISPLP_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_ISPLP_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_ISPPRE_BUSP, MUX_CLKCMU_ISPPRE_BUS_USER, CLK_CON_DIV_DIV_CLK_ISPPRE_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_ISPPRE_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_ISPPRE_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_IVA_BUSP, MUX_CLKCMU_IVA_BUS_USER, CLK_CON_DIV_DIV_CLK_IVA_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_IVA_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_IVA_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_IVA_DEBUG, MUX_CLKCMU_IVA_BUS_USER, CLK_CON_DIV_DIV_CLK_IVA_DEBUG_DIVRATIO, CLK_CON_DIV_DIV_CLK_IVA_DEBUG_BUSY, CLK_CON_DIV_DIV_CLK_IVA_DEBUG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_MFC_BUSP, MUX_CLKCMU_MFC_BUS_USER, CLK_CON_DIV_DIV_CLK_MFC_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MFC_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MFC_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_MIF_PRE, CLKCMU_MIF_SWITCH, CLK_CON_DIV_DIV_CLK_MIF_PRE_DIVRATIO, CLK_CON_DIV_DIV_CLK_MIF_PRE_BUSY, CLK_CON_DIV_DIV_CLK_MIF_PRE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC0_USI00_USI, GATE_CLK_PERIC0_USI00_USI, CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC0_USI01_USI, GATE_CLK_PERIC0_USI01_USI, CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC0_USI02_USI, GATE_CLK_PERIC0_USI02_USI, CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC0_USI03_USI, GATE_CLK_PERIC0_USI03_USI, CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC0_USI04_USI, GATE_CLK_PERIC0_USI04_USI, CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC0_USI05_USI, GATE_CLK_PERIC0_USI05_USI, CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC0_USI_I2C, GATE_CLK_PERIC0_USI_I2C, CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC0_UART_DBG, GATE_CLK_PERIC0_UART_DBG, CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC0_USI12_USI, GATE_CLK_PERIC0_USI12_USI, CLK_CON_DIV_DIV_CLK_PERIC0_USI12_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI12_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI12_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC0_USI13_USI, GATE_CLK_PERIC0_USI13_USI, CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC0_USI14_USI, GATE_CLK_PERIC0_USI14_USI, CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_UART_BT, GATE_CLK_PERIC1_UART_BT, CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_USI_I2C, GATE_CLK_PERIC1_USI_I2C, CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_USI06_USI, GATE_CLK_PERIC1_USI06_USI, CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_USI07_USI, GATE_CLK_PERIC1_USI07_USI, CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_USI08_USI, GATE_CLK_PERIC1_USI08_USI, CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_I2C_CAM0, GATE_CLK_PERIC1_I2C_CAM0, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM0_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM0_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_I2C_CAM1, GATE_CLK_PERIC1_I2C_CAM1, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM1_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM1_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_I2C_CAM2, GATE_CLK_PERIC1_I2C_CAM2, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM2_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM2_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_I2C_CAM3, GATE_CLK_PERIC1_I2C_CAM3, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM3_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM3_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_SPI_CAM0, GATE_CLK_PERIC1_SPI_CAM0, CLK_CON_DIV_DIV_CLK_PERIC1_SPI_CAM0_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_SPI_CAM0_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_SPI_CAM0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_USI09_USI, GATE_CLK_PERIC1_USI09_USI, CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_USI10_USI, GATE_CLK_PERIC1_USI10_USI, CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_USI11_USI, GATE_CLK_PERIC1_USI11_USI, CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_VTS_DMIC_IF, CLK_RCO_VTS, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_BUSY, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_VTS_DMIC, DIV_CLK_VTS_DMIC_IF, CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_DMIC_BUSY, CLK_CON_DIV_DIV_CLK_VTS_DMIC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_VTS_DMIC_DIV2, DIV_CLK_VTS_DMIC_IF, CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2_BUSY, CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_VTS_BUS, MUX_CLK_VTS_BUS, CLK_CON_DIV_DIV_CLK_VTS_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_BUS_BUSY, CLK_CON_DIV_DIV_CLK_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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};
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/*====================The section of GATEs===================*/
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unsigned int cmucal_gate_size = 647;
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struct cmucal_gate cmucal_gate_list[] = {
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CLK_GATE(GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_RSTnSYNC_CLK_APM_BUS_IPCLKPORT_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLKCMU_APM_DLL_CHUB, MUX_DLL_USER, CLK_CON_GAT_CLKCMU_APM_DLL_CHUB_CG_VAL, CLK_CON_GAT_CLKCMU_APM_DLL_CHUB_MANUAL, CLK_CON_GAT_CLKCMU_APM_DLL_CHUB_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_APM_DLL_VTS, MUX_DLL_USER, CLK_CON_GAT_GATE_CLKCMU_APM_DLL_VTS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_APM_DLL_VTS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_APM_DLL_VTS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_LHM_AXI_P_APM_CHUB_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_LHM_AXI_P_APM_CP_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM2CHUB_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_CHUB2CP_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CHUB2CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CHUB2CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CHUB2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_GNSS2CHUB_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_GNSS2CP_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_LHS_AXI_P_APM2CMGP_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_P_APM2CMGP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_P_APM2CMGP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_P_APM2CMGP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_APM_DLL_CMGP, MUX_DLL_USER, CLK_CON_GAT_GATE_CLKCMU_APM_DLL_CMGP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_APM_DLL_CMGP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_APM_DLL_CMGP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_PGEN_APM_IPCLKPORT_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_APM_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_APM_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_APM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_LHS_AXI_LP_CHUB_IPCLKPORT_I_CLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_CHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_CHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_AP2CHUB_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_AP2VTS_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK, DIV_CLK_APM_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0, MUX_CLK_AUD_UAIF0, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1, MUX_CLK_AUD_UAIF1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3, MUX_CLK_AUD_UAIF3, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF, DIV_CLK_AUD_DSIF, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_LHS_ATB_AUD_IPCLKPORT_I_CLK, DIV_CLK_AUD_CPU_ATCLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_ATB_AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_ATB_AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_ATB_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTnSYNC_CLK_AUD_CPU_ATCLK_IPCLKPORT_CLK, DIV_CLK_AUD_CPU_ATCLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ATCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ATCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTnSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK, DIV_CLK_AUD_CPU_PCLKDBG, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTnSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK, DIV_CLK_AUD_DSIF, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTnSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK, MUX_CLK_AUD_UAIF0, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTnSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK, MUX_CLK_AUD_UAIF1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTnSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK, MUX_CLK_AUD_UAIF2, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTnSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK, MUX_CLK_AUD_UAIF3, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2, MUX_CLK_AUD_UAIF2, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK, DIV_CLK_AUD_BUSP, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS, DIV_CLK_AUD_BUSP, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_RSTnSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK, DIV_CLK_AUD_BUSP, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_DMIC_IPCLKPORT_CLK, DIV_CLK_AUD_DMIC, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ATB, DIV_CLK_AUD_CPU_ATCLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ATB_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ATB_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ATB_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_AUD_UID_ABOX_DAP_IPCLKPORT_dapclk, DIV_CLK_AUD_CPU_PCLKDBG, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_DAP_IPCLKPORT_DAPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_DAP_IPCLKPORT_DAPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_DAP_IPCLKPORT_DAPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK, DIV_CLK_AUD_AUDIF, CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_RSTnSYNC_CLK_BUS1_BUS_IPCLKPORT_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_LHM_AXI_D_CHUB_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_CHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_CHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_LHS_AXI_D_BUS1_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_BUS1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_BUS1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_BUS1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_LHS_AXI_P_CHUB_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_LHS_AXI_P_CSSYS_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_pclk, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_BAAW_P_CHUB_IPCLKPORT_I_PCLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_CHUB_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_CHUB_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_CHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_BUS1_UID_XIU_D_BUS1_IPCLKPORT_ACLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D_BUS1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D_BUS1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D_BUS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CHUB_UID_I2C_CHUB00_IPCLKPORT_IPCLK, DIV_CLK_CHUB_I2C, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB00_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB00_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CHUB_UID_I2C_CHUB01_IPCLKPORT_IPCLK, DIV_CLK_CHUB_I2C, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB01_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB01_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB01_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CHUB_UID_USI_CHUB00_IPCLKPORT_IPCLK, DIV_CLK_CHUB_USI00, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB00_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB00_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CHUB_UID_USI_CHUB01_IPCLKPORT_IPCLK, DIV_CLK_CHUB_USI01, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB01_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB01_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB01_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CHUB_UID_RSTnSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK, DIV_CLK_CHUB_I2C, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CHUB_UID_RSTnSYNC_CLK_CHUB_USI00_IPCLKPORT_CLK, DIV_CLK_CHUB_USI00, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI00_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI00_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI00_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CHUB_UID_RSTnSYNC_CLK_CHUB_USI01_IPCLKPORT_CLK, DIV_CLK_CHUB_USI01, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI01_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI01_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI01_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_CHUB_I2C, MUX_CLK_CHUB_I2C, CLK_CON_GAT_GATE_CLK_CHUB_I2C_CG_VAL, CLK_CON_GAT_GATE_CLK_CHUB_I2C_MANUAL, CLK_CON_GAT_GATE_CLK_CHUB_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_CHUB_USI00, MUX_CLK_CHUB_USI00, CLK_CON_GAT_GATE_CLK_CHUB_USI00_CG_VAL, CLK_CON_GAT_GATE_CLK_CHUB_USI00_MANUAL, CLK_CON_GAT_GATE_CLK_CHUB_USI00_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_CHUB_USI01, MUX_CLK_CHUB_USI01, CLK_CON_GAT_GATE_CLK_CHUB_USI01_CG_VAL, CLK_CON_GAT_GATE_CLK_CHUB_USI01_MANUAL, CLK_CON_GAT_GATE_CLK_CHUB_USI01_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_AXI2APB_CMGP0_IPCLKPORT_ACLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_AXI2APB_CMGP1_IPCLKPORT_ACLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_I2C_CMGP00_IPCLKPORT_CLK, DIV_CLK_I2C_CMGP, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP00_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP00_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP00_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_USI_CMGP00_IPCLKPORT_CLK, DIV_CLK_USI_CMGP00, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP00_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP00_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP00_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_USI_CMGP01_IPCLKPORT_CLK, DIV_CLK_USI_CMGP01, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP01_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP01_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP01_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_USI_CMGP02_IPCLKPORT_CLK, DIV_CLK_USI_CMGP02, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP02_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP02_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP02_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_USI_CMGP03_IPCLKPORT_CLK, DIV_CLK_USI_CMGP03, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP03_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP03_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP03_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_I2C_CMGP01_IPCLKPORT_CLK, DIV_CLK_I2C_CMGP, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP01_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP01_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP01_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_I2C_CMGP02_IPCLKPORT_CLK, DIV_CLK_I2C_CMGP, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP02_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP02_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP02_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_RSTnSYNC_CLK_CMGP_I2C_CMGP03_IPCLKPORT_CLK, DIV_CLK_I2C_CMGP, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP03_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP03_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP03_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_XIU_P_CMGP_IPCLKPORT_ACLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_XIU_P_CMGP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_XIU_P_CMGP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_XIU_P_CMGP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK, DIV_CLK_I2C_CMGP, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK, DIV_CLK_I2C_CMGP, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK, DIV_CLK_I2C_CMGP, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK, DIV_CLK_I2C_CMGP, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_LHM_AXI_P_APM2CMGP_IPCLKPORT_I_CLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_P_APM2CMGP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_P_APM2CMGP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_P_APM2CMGP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK, DIV_CLK_USI_CMGP00, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK, DIV_CLK_USI_CMGP02, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK, DIV_CLK_USI_CMGP03, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK, DIV_CLK_USI_CMGP01, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_I2C_CMGP, MUX_CLK_I2C_CMGP, CLK_CON_GAT_GATE_CLK_I2C_CMGP_CG_VAL, CLK_CON_GAT_GATE_CLK_I2C_CMGP_MANUAL, CLK_CON_GAT_GATE_CLK_I2C_CMGP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_USI_CMGP00, MUX_CLK_USI_CMGP00, CLK_CON_GAT_GATE_CLK_USI_CMGP00_CG_VAL, CLK_CON_GAT_GATE_CLK_USI_CMGP00_MANUAL, CLK_CON_GAT_GATE_CLK_USI_CMGP00_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_USI_CMGP01, MUX_CLK_USI_CMGP01, CLK_CON_GAT_GATE_CLK_USI_CMGP01_CG_VAL, CLK_CON_GAT_GATE_CLK_USI_CMGP01_MANUAL, CLK_CON_GAT_GATE_CLK_USI_CMGP01_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_USI_CMGP02, MUX_CLK_USI_CMGP02, CLK_CON_GAT_GATE_CLK_USI_CMGP02_CG_VAL, CLK_CON_GAT_GATE_CLK_USI_CMGP02_MANUAL, CLK_CON_GAT_GATE_CLK_USI_CMGP02_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_USI_CMGP03, MUX_CLK_USI_CMGP03, CLK_CON_GAT_GATE_CLK_USI_CMGP03_CG_VAL, CLK_CON_GAT_GATE_CLK_USI_CMGP03_MANUAL, CLK_CON_GAT_GATE_CLK_USI_CMGP03_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_APM_BUS, MUX_CLKCMU_APM_BUS, CLK_CON_GAT_GATE_CLKCMU_APM_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_APM_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_FSYS0_BUS, MUX_CLKCMU_FSYS0_BUS, CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLKCMU_MIF_SWITCH, MUX_CLKCMU_MIF_SWITCH, CLK_CON_GAT_CLKCMU_MIF_SWITCH_CG_VAL, CLK_CON_GAT_CLKCMU_MIF_SWITCH_MANUAL, CLK_CON_GAT_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_MFC_BUS, MUX_CLKCMU_MFC_BUS, CLK_CON_GAT_GATE_CLKCMU_MFC_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MFC_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MFC_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_G2D_G2D, MUX_CLKCMU_G2D_G2D, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_FSYS0_USB30DRD, MUX_CLKCMU_FSYS0_USB30DRD, CLK_CON_GAT_GATE_CLKCMU_FSYS0_USB30DRD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_USB30DRD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_USB30DRD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_FSYS0_UFS_EMBD, MUX_CLKCMU_FSYS0_UFS_EMBD, CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_FSYS1_BUS, MUX_CLKCMU_FSYS1_BUS, CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_FSYS1_MMC_CARD, MUX_CLKCMU_FSYS1_MMC_CARD, CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DPU_BUS, MUX_CLKCMU_DPU_BUS, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_G3D_SWITCH, PLL_SHARED2, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIS_BUS, MUX_CLKCMU_PERIS_BUS, CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CMGP_BUS, MUX_CLKCMU_CMGP_BUS, CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DSPM_BUS, MUX_CLKCMU_DSPM_BUS, CLK_CON_GAT_GATE_CLKCMU_DSPM_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DSPM_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DSPM_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIC0_BUS, MUX_CLKCMU_PERIC0_BUS, CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIC1_BUS, MUX_CLKCMU_PERIC1_BUS, CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_BUSC_BUS, MUX_CLKCMU_BUSC_BUS, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_BUS1_BUS, MUX_CLKCMU_BUS1_BUS, CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CPUCL1_SWITCH, MUX_CLKCMU_CPUCL1_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CPUCL0_SWITCH, MUX_CLKCMU_CPUCL0_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CORE_BUS, MUX_CLKCMU_CORE_BUS, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_ISPPRE_BUS, MUX_CLKCMU_ISPPRE_BUS, CLK_CON_GAT_GATE_CLKCMU_ISPPRE_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ISPPRE_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ISPPRE_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_ISPLP_BUS, MUX_CLKCMU_ISPLP_BUS, CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_ISPHQ_BUS, MUX_CLKCMU_ISPHQ_BUS, CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_AUD_CPU, MUX_CLKCMU_AUD_CPU, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_MANUAL, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_G2D_MSCL, MUX_CLKCMU_G2D_MSCL, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_HPM, MUX_CLKCMU_HPM, CLK_CON_GAT_GATE_CLKCMU_HPM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HPM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_FSYS1_PCIE, MUX_CLKCMU_FSYS1_PCIE, CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CPUCL0_DBG_BUS, MUX_CLKCMU_CPUCL0_DBG_BUS, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CIS_CLK0, MUX_CLKCMU_CIS_CLK0, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CIS_CLK1, MUX_CLKCMU_CIS_CLK1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CIS_CLK3, MUX_CLKCMU_CIS_CLK3, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CIS_CLK2, MUX_CLKCMU_CIS_CLK2, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_IVA_BUS, MUX_CLKCMU_IVA_BUS, CLK_CON_GAT_GATE_CLKCMU_IVA_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_IVA_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_IVA_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_FSYS1_UFS_CARD, MUX_CLKCMU_FSYS1_UFS_CARD, CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_FSYS0_DPGTC, MUX_CLKCMU_FSYS0_DPGTC, CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_MODEM_SHARED0, DIV_PLL_SHARED0_DIV2, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_MODEM_SHARED1, PLL_SHARED2, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DCRD_BUS, MUX_CLKCMU_DCRD_BUS, CLK_CON_GAT_GATE_CLKCMU_DCRD_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DCRD_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DCRD_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CHUB_BUS, MUX_CLKCMU_CHUB_BUS, CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DCF_BUS, MUX_CLKCMU_DCF_BUS, CLK_CON_GAT_GATE_CLKCMU_DCF_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DCF_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DCF_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_VTS_BUS, MUX_CLKCMU_VTS_BUS, CLK_CON_GAT_GATE_CLKCMU_VTS_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_VTS_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_ISPLP_VRA, MUX_CLKCMU_ISPLP_VRA, CLK_CON_GAT_GATE_CLKCMU_ISPLP_VRA_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ISPLP_VRA_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ISPLP_VRA_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_MFC_WFD, MUX_CLKCMU_MFC_WFD, CLK_CON_GAT_GATE_CLKCMU_MFC_WFD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MFC_WFD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_MIF_BUSP, MUX_CLKCMU_MIF_BUSP, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIC0_IP, MUX_CLKCMU_PERIC0_IP, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIC1_IP, MUX_CLKCMU_PERIC1_IP, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DCPOST_BUS, MUX_CLKCMU_DCPOST_BUS, CLK_CON_GAT_GATE_CLKCMU_DCPOST_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DCPOST_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DCPOST_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_FSYS0_USBDP_DEBUG, MUX_CLKCMU_FSYS0_USBDP_DEBUG, CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDP_DEBUG_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDP_DEBUG_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDP_DEBUG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_ISPLP_GDC, MUX_CLKCMU_ISPLP_GDC, CLK_CON_GAT_GATE_CLKCMU_ISPLP_GDC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ISPLP_GDC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ISPLP_GDC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DSPS_AUD, MUX_CLKCMU_DSPS_AUD, CLK_CON_GAT_GATE_CLKCMU_DSPS_AUD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DSPS_AUD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DSPS_AUD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPMUPPC_CCI_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMUPPC_CCI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMUPPC_CCI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMUPPC_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_pclk, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPMU_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPMU_CPUCL1_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_pclk, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_pclk, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_CP_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_G3D_IPCLKPORT_PCLKS, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_G3D_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_G3D_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_G3D_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_IO_IPCLKPORT_PCLKS, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_IO_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_IO_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_IO_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_DP_IPCLKPORT_PCLKS, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_DP_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_DP_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_DP_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_CPUCL0_CPU, DIV_CLK_CPUCL0_CPU, CLK_CON_GAT_GATE_CLK_CPUCL0_CPU_CG_VAL, CLK_CON_GAT_GATE_CLK_CPUCL0_CPU_MANUAL, CLK_CON_GAT_GATE_CLK_CPUCL0_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_RSTnSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_ADS_APB_G_BDU_IPCLKPORT_PCLKS, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_BDU_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_BDU_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_BDU_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER0_IPCLKPORT_I_PCLK, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER1_IPCLKPORT_I_PCLK, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK, PAD_CLK_CPUCL0_DBG_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK, PAD_CLK_CPUCL0_DBG_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK, PAD_CLK_CPUCL0_DBG_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK, PAD_CLK_CPUCL0_DBG_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER0_IPCLKPORT_PCLKS, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER0_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER0_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER1_IPCLKPORT_PCLKS, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER1_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER1_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK, PAD_CLK_CPUCL0_DBG_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK, PAD_CLK_CPUCL0_DBG_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK, PAD_CLK_CPUCL0_DBG_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK, PAD_CLK_CPUCL0_DBG_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK, PAD_CLK_CPUCL0_DBG_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK, PAD_CLK_CPUCL0_DBG_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK, PAD_CLK_CPUCL0_DBG_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_i_clk, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLKS, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_RSTnSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_RSTnSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK, PAD_CLK_CPUCL0_DBG_ATCLK, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_ADS_APB_G_DSPM_IPCLKPORT_PCLKS, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_DSPM_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_DSPM_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_DSPM_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CSSYS_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_AXI2APB_P_CSSYS_IPCLKPORT_ACLK, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_P_CSSYS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_P_CSSYS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_P_CSSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLK_CLUSTER0_ACLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER0_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER0_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER0_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER0_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM, DIV_CLK_CLUSTER0_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_AXI_DS_64to32_G_CSSYS_IPCLKPORT_aclk, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI_DS_64TO32_G_CSSYS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI_DS_64TO32_G_CSSYS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI_DS_64TO32_G_CSSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_RSTnSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK, MUX_CLK_CLUSTER0_ACLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_RSTnSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER0_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_RSTnSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK, DIV_CLK_CLUSTER0_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_LHS_AXI_P_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLK_CLUSTER0_ACLKP, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_P_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_P_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_P_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_RSTnSYNC_CLK_CLUSTER0_ACLKP_IPCLKPORT_CLK, MUX_CLK_CLUSTER0_ACLKP, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLKP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLKP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLKP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK, DIV_CLK_CLUSTER0_ATCLK, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK, DIV_CLK_CLUSTER0_PCLKDBG, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK, DIV_CLK_CLUSTER0_PERIPHCLK, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK, PAD_CLK_CPUCL0_DBG_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_SCLK, GATE_CLK_CPUCL0_CPU, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKM, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKS, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKM, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKS, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_HPM_CPUCL1_0_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_0_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_0_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_0_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_CPUCL1_CPU, DIV_CLK_CPUCL1_CPU, CLK_CON_GAT_GATE_CLK_CPUCL1_CPU_CG_VAL, CLK_CON_GAT_GATE_CLK_CPUCL1_CPU_MANUAL, CLK_CON_GAT_GATE_CLK_CPUCL1_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL1_UID_RSTnSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_CLUSTER1_IPCLKPORT_PCLKDBG, DIV_CLK_CPUCL1_PCLKDBG, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CLUSTER1_IPCLKPORT_PCLKDBG_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CLUSTER1_IPCLKPORT_PCLKDBG_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CLUSTER1_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_HPM_CPUCL1_1_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_1_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_1_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_1_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_HPM_CPUCL1_2_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_2_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_2_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_2_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCF_IPCLKPORT_I_CLK, MUX_CLKCMU_DCPOST_BUS_USER, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DCPOST_UID_LHS_AXI_D_DCPOSTDCF_IPCLKPORT_I_CLK, MUX_CLKCMU_DCPOST_BUS_USER, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_AXI_D_DCPOSTDCF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_AXI_D_DCPOSTDCF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_AXI_D_DCPOSTDCF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DCPOST_UID_LHM_ATB_DCRDDCPOST_IPCLKPORT_I_CLK, MUX_CLKCMU_DCPOST_BUS_USER, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCRDDCPOST_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCRDDCPOST_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCRDDCPOST_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_SYSREG_DCPOST_PCLK, DIV_CLK_DCPOST_BUSP, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_SYSREG_DCPOST_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_SYSREG_DCPOST_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_SYSREG_DCPOST_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_CIP2_PCLKM, MUX_CLKCMU_DCPOST_BUS_USER, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_CIP2_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_CIP2_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_CIP2_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_CIP2_PCLKS, DIV_CLK_DCPOST_BUSP, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_CIP2_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_CIP2_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_CIP2_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_ACLK, MUX_CLKCMU_DCPOST_BUS_USER, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_PCLK, DIV_CLK_DCPOST_BUSP, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DCPOST_UID_LHM_AXI_P_DCFDCPOST_IPCLKPORT_I_CLK, DIV_CLK_DCPOST_BUSP, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_AXI_P_DCFDCPOST_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_AXI_P_DCFDCPOST_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_AXI_P_DCFDCPOST_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DCPOST_UID_RSTnSYNC_CLK_DCPOST_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_DCPOST_BUS_USER, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DCPOST_UID_RSTnSYNC_CLK_DCPOST_BUSP_IPCLKPORT_CLK, DIV_CLK_DCPOST_BUSP, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DCPOST_UID_DCPOST_CMU_DCPOST_IPCLKPORT_PCLK, DIV_CLK_DCPOST_BUSP, CLK_CON_GAT_CLK_BLK_DCPOST_UID_DCPOST_CMU_DCPOST_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DCPOST_UID_DCPOST_CMU_DCPOST_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DCPOST_UID_DCPOST_CMU_DCPOST_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_C2SYNC_1SLV_PCLKM, MUX_CLKCMU_DCPOST_BUS_USER, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_C2SYNC_1SLV_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_C2SYNC_1SLV_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_C2SYNC_1SLV_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_C2SYNC_1SLV_PCLKS, DIV_CLK_DCPOST_BUSP, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_C2SYNC_1SLV_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_C2SYNC_1SLV_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_C2SYNC_1SLV_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DCPOST_UID_LHM_ATB_DCFDCPOST_IPCLKPORT_I_CLK, MUX_CLKCMU_DCPOST_BUS_USER, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCFDCPOST_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCFDCPOST_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCFDCPOST_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCRD_IPCLKPORT_I_CLK, MUX_CLKCMU_DCPOST_BUS_USER, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCRD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCRD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCRD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_CIP2_ACLK, MUX_CLKCMU_DCPOST_BUS_USER, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_CIP2_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_CIP2_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_CIP2_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_C2SYNC_1SLV_ACLK, MUX_CLKCMU_DCPOST_BUS_USER, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_C2SYNC_1SLV_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_C2SYNC_1SLV_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_C2SYNC_1SLV_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AXI2APB_DCPOST_ACLK, DIV_CLK_DCPOST_BUSP, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AXI2APB_DCPOST_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AXI2APB_DCPOST_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AXI2APB_DCPOST_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK, DIV_CLK_DPU_BUSP, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_BTM_DPUD0_IPCLKPORT_I_PCLK, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_BTM_DPUD1_IPCLKPORT_I_PCLK, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_AXI2APB_DPUP1_IPCLKPORT_ACLK, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_AXI2APB_DPUP0_IPCLKPORT_ACLK, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_XIU_P_DPU_IPCLKPORT_ACLK, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_XIU_P_DPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_XIU_P_DPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_XIU_P_DPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKS, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_AD_APB_DECON1_IPCLKPORT_PCLKS, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON1_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON1_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_AD_APB_DPP_IPCLKPORT_PCLKS, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPP_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPP_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPP_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_BTM_DPUD2_IPCLKPORT_I_PCLK, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD2_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD2_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_RSTnSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_AD_APB_DECON2_IPCLKPORT_PCLKS, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON2_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON2_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON2_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_IPCLKPORT_PCLKS, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_S_IPCLKPORT_PCLKS, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_S_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_S_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_S_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_IPCLKPORT_PCLKS, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_S_IPCLKPORT_PCLKS, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_S_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_S_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_S_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_IPCLKPORT_PCLKS, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_S_IPCLKPORT_PCLKS, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_S_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_S_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_S_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_wrapper_for_s5i6211_hsi_dcphy_combo_top_IPCLKPORT_PCLK, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_WRAPPER_FOR_S5I6211_HSI_DCPHY_COMBO_TOP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_WRAPPER_FOR_S5I6211_HSI_DCPHY_COMBO_TOP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_WRAPPER_FOR_S5I6211_HSI_DCPHY_COMBO_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_PGEN_IPCLKPORT_PCLKS, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_PGEN_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_PGEN_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_PGEN_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSPM_UID_DSPM_CMU_DSPM_IPCLKPORT_PCLK, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_CLK_BLK_DSPM_UID_DSPM_CMU_DSPM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSPM_UID_DSPM_CMU_DSPM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSPM_UID_DSPM_CMU_DSPM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_SYSREG_DSPM_IPCLKPORT_PCLK, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSREG_DSPM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSREG_DSPM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSREG_DSPM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_AXI2APB_DSPM_IPCLKPORT_ACLK, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AXI2APB_DSPM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AXI2APB_DSPM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AXI2APB_DSPM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_ACLK, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_PCLK, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_SYSMMU_DSPM0_IPCLKPORT_CLK, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_ACLK, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_LHM_AXI_P_DSPM_IPCLKPORT_I_CLK, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_DSPM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_DSPM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_DSPM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_PCLK, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_LHS_ACEL_D0_DSPM_IPCLKPORT_I_CLK, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D0_DSPM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D0_DSPM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D0_DSPM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_RSTnSYNC_CLK_DSPM_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_RSTnSYNC_CLK_DSPM_BUSP_IPCLKPORT_CLK, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_LHM_AXI_P_IVADSPM_IPCLKPORT_I_CLK, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_IVADSPM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_IVADSPM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_IVADSPM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMIVA_IPCLKPORT_I_CLK, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMIVA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMIVA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMIVA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_WRAP2_CONV_DSPM_IPCLKPORT_I_CLK, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_WRAP2_CONV_DSPM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_WRAP2_CONV_DSPM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_WRAP2_CONV_DSPM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKM, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKS, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKM, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKS, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_AD_APB_DSPM2_IPCLKPORT_PCLKM, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM2_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM2_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM2_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_AD_APB_DSPM2_IPCLKPORT_PCLKS, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM2_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM2_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM2_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKS, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKM, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKS, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKM, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_ACLK, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_PCLK, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_LHS_ACEL_D1_DSPM_IPCLKPORT_I_CLK, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D1_DSPM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D1_DSPM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D1_DSPM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_ACLK, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_PCLK, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_SYSMMU_DSPM1_IPCLKPORT_CLK, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLKCMU_DSPS_BUS, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_CLKCMU_DSPS_BUS_CG_VAL, CLK_CON_GAT_CLKCMU_DSPS_BUS_MANUAL, CLK_CON_GAT_CLKCMU_DSPS_BUS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_ADM_APB_DSPM_IPCLKPORT_PCLKM, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_ADM_APB_DSPM_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_ADM_APB_DSPM_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_ADM_APB_DSPM_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_LHM_AXI_D0_DSPSDSPM_IPCLKPORT_I_CLK, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D0_DSPSDSPM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D0_DSPSDSPM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D0_DSPSDSPM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_LHM_AXI_D1_DSPSDSPM_IPCLKPORT_I_CLK, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D1_DSPSDSPM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D1_DSPSDSPM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D1_DSPSDSPM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_XIU_P_DSPM_IPCLKPORT_ACLK, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_XIU_P_DSPM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_XIU_P_DSPM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_XIU_P_DSPM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_PGEN_lite_DSPM_IPCLKPORT_CLK, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PGEN_LITE_DSPM_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PGEN_LITE_DSPM_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PGEN_LITE_DSPM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_PPMU_DSPM2_IPCLKPORT_ACLK, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_PPMU_DSPM2_IPCLKPORT_PCLK, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_SYSMMU_DSPM2_IPCLKPORT_CLK, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_BTM_DSPM2_IPCLKPORT_I_PCLK, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM2_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM2_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_LHS_ACEL_D2_DSPM_IPCLKPORT_I_CLK, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D2_DSPM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D2_DSPM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D2_DSPM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKM, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKS, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_AD_APB_DSPM5_IPCLKPORT_PCLKM, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM5_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM5_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM5_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_AD_APB_DSPM5_IPCLKPORT_PCLKS, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM5_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM5_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM5_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_AXI2AHB_DSPM_IPCLKPORT_CLK, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AXI2AHB_DSPM_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AXI2AHB_DSPM_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AXI2AHB_DSPM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_CNN_IPCLKPORT_ASYNCDAPM_DAPCLK, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_CNN_IPCLKPORT_ASYNCDAPM_DAPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_CNN_IPCLKPORT_ASYNCDAPM_DAPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_CNN_IPCLKPORT_ASYNCDAPM_DAPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_BAAW_DSPM_IPCLKPORT_I_PCLK, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BAAW_DSPM_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BAAW_DSPM_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BAAW_DSPM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_CNN_IPCLKPORT_HCLK, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_CNN_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_CNN_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_CNN_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_BTM_DSPM2_IPCLKPORT_I_ACLK, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM2_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM2_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM2_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_CNN_IPCLKPORT_Clk, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_CNN_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_CNN_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_CNN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_SCORE_MASTER_IPCLKPORT_i_CLK, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SCORE_MASTER_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SCORE_MASTER_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SCORE_MASTER_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_AD_AXI_DSPM1_IPCLKPORT_ACLKS, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM1_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM1_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM1_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_AD_AXI_DSPM1_IPCLKPORT_ACLKM, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM1_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM1_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM1_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_AD_AXI_DSPM2_IPCLKPORT_ACLKM, MUX_CLKCMU_DSPM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM2_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM2_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM2_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPM_UID_AD_AXI_DSPM2_IPCLKPORT_ACLKS, DIV_CLK_DSPM_BUSP, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM2_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM2_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM2_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSPS_UID_DSPS_CMU_DSPS_IPCLKPORT_PCLK, DIV_CLK_DSPS_BUSP, CLK_CON_GAT_CLK_BLK_DSPS_UID_DSPS_CMU_DSPS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSPS_UID_DSPS_CMU_DSPS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSPS_UID_DSPS_CMU_DSPS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPS_UID_AXI2APB_DSPS_IPCLKPORT_ACLK, DIV_CLK_DSPS_BUSP, CLK_CON_GAT_GOUT_BLK_DSPS_UID_AXI2APB_DSPS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPS_UID_AXI2APB_DSPS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPS_UID_AXI2APB_DSPS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPS_UID_LHM_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK, DIV_CLK_DSPS_BUSP, CLK_CON_GAT_GOUT_BLK_DSPS_UID_LHM_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPS_UID_LHM_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPS_UID_LHM_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPS_UID_SYSREG_DSPS_IPCLKPORT_PCLK, DIV_CLK_DSPS_BUSP, CLK_CON_GAT_GOUT_BLK_DSPS_UID_SYSREG_DSPS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPS_UID_SYSREG_DSPS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPS_UID_SYSREG_DSPS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_DSPS_UID_RSTnSYNC_CLK_DSPS_BUSP_IPCLKPORT_CLK, DIV_CLK_DSPS_BUSP, CLK_CON_GAT_GOUT_BLK_DSPS_UID_RSTNSYNC_CLK_DSPS_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSPS_UID_RSTNSYNC_CLK_DSPS_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSPS_UID_RSTNSYNC_CLK_DSPS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, MUX_CLKCMU_FSYS0_UFS_EMBD_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USB30DRD_ref_clk, MUX_CLKCMU_FSYS0_USB30DRD_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USB30DRD_REF_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USB30DRD_REF_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USB30DRD_REF_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL, MUX_CLKCMU_FSYS0_USBDP_DEBUG_USER, CLK_CON_GAT_CLK_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_CG_VAL, CLK_CON_GAT_CLK_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_MANUAL, CLK_CON_GAT_CLK_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK, MUX_CLKCMU_FSYS0_DPGTC_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN, MUX_CLKCMU_FSYS1_MMC_CARD_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_ieee1500_wrapper_for_pcieg2_phy_x1_inst_0_i_scl_apb_pclk, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_i_PCLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_i_PCLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_aclk, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_phy_refclk_in, MUX_CLKCMU_FSYS1_PCIE_USER, CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_slv_aclk, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_dbi_aclk, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_pcie_sub_ctrl_inst_0_i_driver_apb_clk, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_pipe2_digital_x1_wrap_inst_0_i_apb_pclk_scl, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_RSTnSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO, MUX_CLKCMU_FSYS1_UFS_CARD_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_IA_GEN2_IPCLKPORT_i_CLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_IA_GEN3_IPCLKPORT_i_CLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_SYSMMU_FSYS1_IPCLKPORT_CLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSMMU_FSYS1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSMMU_FSYS1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSMMU_FSYS1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_PGEN_LITE_FSYS1_IPCLKPORT_CLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PGEN_LITE_FSYS1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PGEN_LITE_FSYS1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PGEN_LITE_FSYS1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_dbi_aclk, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_DBI_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_DBI_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_DBI_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_ieee1500_wrapper_for_qchannel_wrapper_for_pcieg3_phy_x1_top_inst_0_i_apb_pclk, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_IEEE1500_WRAPPER_FOR_QCHANNEL_WRAPPER_FOR_PCIEG3_PHY_X1_TOP_INST_0_I_APB_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_IEEE1500_WRAPPER_FOR_QCHANNEL_WRAPPER_FOR_PCIEG3_PHY_X1_TOP_INST_0_I_APB_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_IEEE1500_WRAPPER_FOR_QCHANNEL_WRAPPER_FOR_PCIEG3_PHY_X1_TOP_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_LT_PCIE3_pcie_sub_ctrl_inst_0_i_driver_apb_clk, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_LT_PCIE3_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_LT_PCIE3_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_LT_PCIE3_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_phy_refclk_in, MUX_CLKCMU_FSYS1_PCIE_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PHY_REFCLK_IN_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PHY_REFCLK_IN_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_pipe42_pcie_pcs_x1_wrap_inst_0_i_apb_pclk, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PIPE42_PCIE_PCS_X1_WRAP_INST_0_I_APB_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PIPE42_PCIE_PCS_X1_WRAP_INST_0_I_APB_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PIPE42_PCIE_PCS_X1_WRAP_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_slv_aclk, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_SLV_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_SLV_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_SLV_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_DBI_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_DBI_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_DBI_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_DBI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_SLV_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_SLV_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_SLV_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_SLV_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_SLV_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_SLV_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_SLV_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_SLV_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_DBI_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_DBI_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_DBI_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_DBI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_mstr_aclk, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_mstr_aclk, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_MSTR_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_MSTR_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_MSTR_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_i_ACLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_i_ACLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3D_UID_HPM_G3D0_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D0_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D0_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D0_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_RSTnSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK, MUX_CLKCMU_EMBEDDED_G3D_USER, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK, MUX_CLKCMU_EMBEDDED_G3D_USER, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK, MUX_CLKCMU_EMBEDDED_G3D_USER, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK, DIV_CLK_IVA_BUSP, CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK, DIV_CLK_IVA_BUSP, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK, DIV_CLK_IVA_BUSP, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_IVA_UID_PPMU_IVA_IPCLKPORT_PCLK, DIV_CLK_IVA_BUSP, CLK_CON_GAT_GOUT_BLK_IVA_UID_PPMU_IVA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_PPMU_IVA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_PPMU_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK, DIV_CLK_IVA_BUSP, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_IVA_UID_AD_APB_IVA0_IPCLKPORT_PCLKS, DIV_CLK_IVA_BUSP, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA0_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA0_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK, DIV_CLK_IVA_BUSP, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK, DIV_CLK_IVA_BUSP, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK, DIV_CLK_IVA_BUSP, CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_IVA_UID_RSTnSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK, DIV_CLK_IVA_BUSP, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_IVA_UID_ADM_DAP_IVA_IPCLKPORT_dapclkm, DIV_CLK_IVA_DEBUG, CLK_CON_GAT_GOUT_BLK_IVA_UID_ADM_DAP_IVA_IPCLKPORT_DAPCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_ADM_DAP_IVA_IPCLKPORT_DAPCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_ADM_DAP_IVA_IPCLKPORT_DAPCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_IVA_UID_RSTnSYNC_CLK_IVA_DEBUG_IPCLKPORT_CLK, DIV_CLK_IVA_DEBUG, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_DEBUG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_DEBUG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_DEBUG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_IVA_UID_AD_APB_IVA1_IPCLKPORT_PCLKS, DIV_CLK_IVA_BUSP, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA1_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA1_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_IVA_UID_AD_APB_IVA2_IPCLKPORT_PCLKS, DIV_CLK_IVA_BUSP, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA2_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA2_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA2_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_IVA_UID_IVA_IPCLKPORT_dap_clk, DIV_CLK_IVA_DEBUG, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_DAP_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_DAP_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_DAP_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_IVA_UID_PGEN_lite_IVA_IPCLKPORT_CLK, DIV_CLK_IVA_BUSP, CLK_CON_GAT_GOUT_BLK_IVA_UID_PGEN_LITE_IVA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_PGEN_LITE_IVA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_PGEN_LITE_IVA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_IVA_UID_TREX_RB_IVA_IPCLKPORT_pclk, DIV_CLK_IVA_BUSP, CLK_CON_GAT_GOUT_BLK_IVA_UID_TREX_RB_IVA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_TREX_RB_IVA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_TREX_RB_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_i_PCLK_S0, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P0_IPCLKPORT_ACLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P1_IPCLKPORT_ACLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI00_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI00_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI01_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI02_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI03_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI04_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI05_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK, DIV_CLK_PERIC0_UART_DBG, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_XIU_P_PERIC0_IPCLKPORT_ACLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_XIU_P_PERIC0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_XIU_P_PERIC0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_XIU_P_PERIC0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI01_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI02_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI03_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI04_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI05_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_UART_DBG, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI00_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI01_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI02_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI03_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI04_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI05_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_PERIC0_USI00_USI, MUX_CLKCMU_PERIC0_IP_USER, CLK_CON_GAT_GATE_CLK_PERIC0_USI00_USI_CG_VAL, CLK_CON_GAT_GATE_CLK_PERIC0_USI00_USI_MANUAL, CLK_CON_GAT_GATE_CLK_PERIC0_USI00_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_PERIC0_USI01_USI, MUX_CLKCMU_PERIC0_IP_USER, CLK_CON_GAT_GATE_CLK_PERIC0_USI01_USI_CG_VAL, CLK_CON_GAT_GATE_CLK_PERIC0_USI01_USI_MANUAL, CLK_CON_GAT_GATE_CLK_PERIC0_USI01_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_PERIC0_USI02_USI, MUX_CLKCMU_PERIC0_IP_USER, CLK_CON_GAT_GATE_CLK_PERIC0_USI02_USI_CG_VAL, CLK_CON_GAT_GATE_CLK_PERIC0_USI02_USI_MANUAL, CLK_CON_GAT_GATE_CLK_PERIC0_USI02_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_PERIC0_USI03_USI, MUX_CLKCMU_PERIC0_IP_USER, CLK_CON_GAT_GATE_CLK_PERIC0_USI03_USI_CG_VAL, CLK_CON_GAT_GATE_CLK_PERIC0_USI03_USI_MANUAL, CLK_CON_GAT_GATE_CLK_PERIC0_USI03_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_PERIC0_USI04_USI, MUX_CLKCMU_PERIC0_IP_USER, CLK_CON_GAT_GATE_CLK_PERIC0_USI04_USI_CG_VAL, CLK_CON_GAT_GATE_CLK_PERIC0_USI04_USI_MANUAL, CLK_CON_GAT_GATE_CLK_PERIC0_USI04_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_PERIC0_USI05_USI, MUX_CLKCMU_PERIC0_IP_USER, CLK_CON_GAT_GATE_CLK_PERIC0_USI05_USI_CG_VAL, CLK_CON_GAT_GATE_CLK_PERIC0_USI05_USI_MANUAL, CLK_CON_GAT_GATE_CLK_PERIC0_USI05_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_PERIC0_USI_I2C, MUX_CLKCMU_PERIC0_IP_USER, CLK_CON_GAT_GATE_CLK_PERIC0_USI_I2C_CG_VAL, CLK_CON_GAT_GATE_CLK_PERIC0_USI_I2C_MANUAL, CLK_CON_GAT_GATE_CLK_PERIC0_USI_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_PERIC0_UART_DBG, MUX_CLKCMU_PERIC0_IP_USER, CLK_CON_GAT_GATE_CLK_PERIC0_UART_DBG_CG_VAL, CLK_CON_GAT_GATE_CLK_PERIC0_UART_DBG_MANUAL, CLK_CON_GAT_GATE_CLK_PERIC0_UART_DBG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_PERIC0_USI12_USI, MUX_CLKCMU_PERIC0_IP_USER, CLK_CON_GAT_GATE_CLK_PERIC0_USI12_USI_CG_VAL, CLK_CON_GAT_GATE_CLK_PERIC0_USI12_USI_MANUAL, CLK_CON_GAT_GATE_CLK_PERIC0_USI12_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_PERIC0_USI13_USI, MUX_CLKCMU_PERIC0_IP_USER, CLK_CON_GAT_GATE_CLK_PERIC0_USI13_USI_CG_VAL, CLK_CON_GAT_GATE_CLK_PERIC0_USI13_USI_MANUAL, CLK_CON_GAT_GATE_CLK_PERIC0_USI13_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_PERIC0_USI14_USI, MUX_CLKCMU_PERIC0_IP_USER, CLK_CON_GAT_GATE_CLK_PERIC0_USI14_USI_CG_VAL, CLK_CON_GAT_GATE_CLK_PERIC0_USI14_USI_MANUAL, CLK_CON_GAT_GATE_CLK_PERIC0_USI14_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI12_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI12_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI13_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI14_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI12_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI12_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI13_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_USI14_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI13_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI14_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI06_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI07_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI08_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI09_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI10_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_USI06_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK, DIV_CLK_PERIC1_UART_BT, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_SPI_CAM0_IPCLKPORT_CLK, DIV_CLK_PERIC1_SPI_CAM0, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPI_CAM0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPI_CAM0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPI_CAM0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_I2C_CAM0_IPCLKPORT_CLK, DIV_CLK_PERIC1_I2C_CAM0, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_I2C_CAM1_IPCLKPORT_CLK, DIV_CLK_PERIC1_I2C_CAM1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_I2C_CAM2_IPCLKPORT_CLK, DIV_CLK_PERIC1_I2C_CAM2, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_I2C_CAM3_IPCLKPORT_CLK, DIV_CLK_PERIC1_I2C_CAM3, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM3_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM3_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_USI07_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_USI08_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_USI09_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_USI10_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_I2C_CAM0, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_I2C_CAM1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_I2C_CAM2, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_I2C_CAM3, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_SPI_CAM0, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_UART_BT, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI06_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI07_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI08_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI09_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI10_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_PERIC1_UART_BT, MUX_CLKCMU_PERIC1_IP_USER, CLK_CON_GAT_GATE_CLK_PERIC1_UART_BT_CG_VAL, CLK_CON_GAT_GATE_CLK_PERIC1_UART_BT_MANUAL, CLK_CON_GAT_GATE_CLK_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_PERIC1_USI_I2C, MUX_CLKCMU_PERIC1_IP_USER, CLK_CON_GAT_GATE_CLK_PERIC1_USI_I2C_CG_VAL, CLK_CON_GAT_GATE_CLK_PERIC1_USI_I2C_MANUAL, CLK_CON_GAT_GATE_CLK_PERIC1_USI_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_PERIC1_USI06_USI, MUX_CLKCMU_PERIC1_IP_USER, CLK_CON_GAT_GATE_CLK_PERIC1_USI06_USI_CG_VAL, CLK_CON_GAT_GATE_CLK_PERIC1_USI06_USI_MANUAL, CLK_CON_GAT_GATE_CLK_PERIC1_USI06_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_PERIC1_USI07_USI, MUX_CLKCMU_PERIC1_IP_USER, CLK_CON_GAT_GATE_CLK_PERIC1_USI07_USI_CG_VAL, CLK_CON_GAT_GATE_CLK_PERIC1_USI07_USI_MANUAL, CLK_CON_GAT_GATE_CLK_PERIC1_USI07_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_PERIC1_USI08_USI, MUX_CLKCMU_PERIC1_IP_USER, CLK_CON_GAT_GATE_CLK_PERIC1_USI08_USI_CG_VAL, CLK_CON_GAT_GATE_CLK_PERIC1_USI08_USI_MANUAL, CLK_CON_GAT_GATE_CLK_PERIC1_USI08_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_PERIC1_I2C_CAM0, MUX_CLKCMU_PERIC1_IP_USER, CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM0_CG_VAL, CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM0_MANUAL, CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_PERIC1_I2C_CAM1, MUX_CLKCMU_PERIC1_IP_USER, CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM1_CG_VAL, CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM1_MANUAL, CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_PERIC1_I2C_CAM2, MUX_CLKCMU_PERIC1_IP_USER, CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM2_CG_VAL, CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM2_MANUAL, CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_PERIC1_I2C_CAM3, MUX_CLKCMU_PERIC1_IP_USER, CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM3_CG_VAL, CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM3_MANUAL, CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_PERIC1_SPI_CAM0, MUX_CLKCMU_PERIC1_IP_USER, CLK_CON_GAT_GATE_CLK_PERIC1_SPI_CAM0_CG_VAL, CLK_CON_GAT_GATE_CLK_PERIC1_SPI_CAM0_MANUAL, CLK_CON_GAT_GATE_CLK_PERIC1_SPI_CAM0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_PERIC1_USI09_USI, MUX_CLKCMU_PERIC1_IP_USER, CLK_CON_GAT_GATE_CLK_PERIC1_USI09_USI_CG_VAL, CLK_CON_GAT_GATE_CLK_PERIC1_USI09_USI_MANUAL, CLK_CON_GAT_GATE_CLK_PERIC1_USI09_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_PERIC1_USI10_USI, MUX_CLKCMU_PERIC1_IP_USER, CLK_CON_GAT_GATE_CLK_PERIC1_USI10_USI_CG_VAL, CLK_CON_GAT_GATE_CLK_PERIC1_USI10_USI_MANUAL, CLK_CON_GAT_GATE_CLK_PERIC1_USI10_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLK_PERIC1_USI11_USI, MUX_CLKCMU_PERIC1_IP_USER, CLK_CON_GAT_GATE_CLK_PERIC1_USI11_USI_CG_VAL, CLK_CON_GAT_GATE_CLK_PERIC1_USI11_USI_MANUAL, CLK_CON_GAT_GATE_CLK_PERIC1_USI11_USI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI11_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI11_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_USI11_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_AXI2APB_PERISP_IPCLKPORT_ACLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_RSTnSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_RSTnSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK, MUX_CLK_PERIS_GIC, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM, MUX_CLK_PERIS_GIC, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK, MUX_CLK_PERIS_GIC, CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK, MUX_CLK_S2D_CORE, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_S2D_UID_RSTnSYNC_CLK_S2D_CORE_IPCLKPORT_CLK, MUX_CLK_S2D_CORE, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_RSTnSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK, DIV_CLK_VTS_DMIC_IF, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_CLK, DIV_CLK_VTS_DMIC_IF, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_DIV2_CLK, DIV_CLK_VTS_DMIC_DIV2, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GOUT_BLK_VTS_UID_RSTnSYNC_CLK_VTS_DMIC_IPCLKPORT_CLK, DIV_CLK_VTS_DMIC_IF, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_u_DMIC_CLK_MUX_IPCLKPORT_D0, DIV_CLK_VTS_DMIC, CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_MUX_IPCLKPORT_D0_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_MUX_IPCLKPORT_D0_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_MUX_IPCLKPORT_D0_ENABLE_AUTOMATIC_CLKGATING),
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|
};
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|
/*====================The section of FIXED RATEs===================*/
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|
unsigned int cmucal_fixed_rate_size = 68;
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|
|
|
|
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struct cmucal_clk_fixed_rate cmucal_fixed_rate_list[] = {
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FIXEDRATE(OSCCLK_RCO_APM, 26000000, EMPTY_CAL_ID),
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|
FIXEDRATE(PAD_CLK_APM_BUS, 100000000, EMPTY_CAL_ID),
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|
FIXEDRATE(CLK_DLL_DCO, 100000000, EMPTY_CAL_ID),
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|
FIXEDRATE(OSCCLK_AUD, 26000000, EMPTY_CAL_ID),
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|
FIXEDRATE(CLKIO_AUD_UAIF0, 10000000, EMPTY_CAL_ID),
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|
FIXEDRATE(CLKIO_AUD_UAIF1, 10000000, EMPTY_CAL_ID),
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|
FIXEDRATE(CLKIO_AUD_UAIF2, 10000000, EMPTY_CAL_ID),
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|
FIXEDRATE(CLKIO_AUD_UAIF3, 100000000, EMPTY_CAL_ID),
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|
FIXEDRATE(OSCCLK_BUS1, 26000000, EMPTY_CAL_ID),
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|
FIXEDRATE(PAD_CLK_BUS1_BUS, 100000000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_BUSC, 26000000, EMPTY_CAL_ID),
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|
FIXEDRATE(OSCCLK_RCO_CHUB, 26000000, EMPTY_CAL_ID),
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|
FIXEDRATE(RTCCLK_CHUB, 100000000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_RCO_CMGP, 26000000, EMPTY_CAL_ID),
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|
FIXEDRATE(OSCCLK_CMGP, 100000000, EMPTY_CAL_ID),
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|
FIXEDRATE(OSCCLK_CMU, 26000000, EMPTY_CAL_ID),
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|
FIXEDRATE(OSCCLK_CORE, 26000000, EMPTY_CAL_ID),
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|
FIXEDRATE(OSCCLK_CPUCL0, 26000000, EMPTY_CAL_ID),
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|
FIXEDRATE(PAD_CLK_CPUCL0_DBG_ATCLK, 100000000, EMPTY_CAL_ID),
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FIXEDRATE(PAD_CLK_CPUCL0_DBG_PCLKDBG, 100000000, EMPTY_CAL_ID),
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|
FIXEDRATE(OSCCLK_EMBEDDED_CPUCL0, 26000000, EMPTY_CAL_ID),
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|
FIXEDRATE(SCLK_OUT, 1150000000, EMPTY_CAL_ID),
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|
FIXEDRATE(ACLK_OUT, 100000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(ACLKP_OUT, 100000000, EMPTY_CAL_ID),
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|
FIXEDRATE(OSCCLK_CPUCL1, 26000000, EMPTY_CAL_ID),
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|
FIXEDRATE(CLK_CLUSTER1_DIV_ACLK, 100000000, EMPTY_CAL_ID),
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|
FIXEDRATE(CLK_CLUSTER1_DIV_ATCLK, 100000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_EMBEDDED_CPUCL1, 100000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_DCF, 26000000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_DCPOST, 26000000, EMPTY_CAL_ID),
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FIXEDRATE(PAD_CLK_DCPOST_BUSD, 100000000, EMPTY_CAL_ID),
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|
FIXEDRATE(OSCCLK_DCRD, 26000000, EMPTY_CAL_ID),
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|
FIXEDRATE(OSCCLK_DPU, 26000000, EMPTY_CAL_ID),
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|
FIXEDRATE(CLK_DEBUG_DECON0, 100000000, EMPTY_CAL_ID),
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|
FIXEDRATE(CLK_DEBUG_DECON1, 100000000, EMPTY_CAL_ID),
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FIXEDRATE(CLK_DEBUG_DECON2, 100000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_DSPM, 26000000, EMPTY_CAL_ID),
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|
FIXEDRATE(PAD_CLK_DSPM_BUSD, 100000000, EMPTY_CAL_ID),
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|
FIXEDRATE(PAD_CLK_DSPM_BUSP, 100000000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_DSPS, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_FSYS0, 26000000, EMPTY_CAL_ID),
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FIXEDRATE(PAD_CLK_FSYS0_UFS_EMBD, 100000000, EMPTY_CAL_ID),
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FIXEDRATE(USBDPPHY_TXCLK_CH0, 100000000, EMPTY_CAL_ID),
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FIXEDRATE(USBDPPHY_RXCLK_CH0, 100000000, EMPTY_CAL_ID),
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|
FIXEDRATE(USBDPPHY_DP_TXCLK, 100000000, EMPTY_CAL_ID),
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FIXEDRATE(USB20PHY_PHY_CLOCK, 100000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(USBDPPHY_VCOCLK_DIV40_MON, 100000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_FSYS1, 26000000, EMPTY_CAL_ID),
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|
FIXEDRATE(PAD_CLK_FSYS1_BUS, 100000000, EMPTY_CAL_ID),
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|
FIXEDRATE(PAD_CLK_FSYS1_MMC_CARD, 100000000, EMPTY_CAL_ID),
|
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FIXEDRATE(PAD_CLK_FSYS1_UFS_CARD, 100000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_G2D, 26000000, EMPTY_CAL_ID),
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|
FIXEDRATE(OSCCLK_G3D, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_EMBEDDED_G3D, 100000000, EMPTY_CAL_ID),
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|
FIXEDRATE(CLK_G3D_GPU_FEEDBACK, 800000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_ISPHQ, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_ISPLP, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_ISPPRE, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_IVA, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_MFC, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_MIF, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_PERIC0, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_PERIC1, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_PERIS, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_S2D, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_RCO_VTS, 26000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(RTCCLK_VTS, 32767, EMPTY_CAL_ID),
|
|
FIXEDRATE(CLK_RCO_VTS, 49152000, EMPTY_CAL_ID),
|
|
};
|
|
|
|
/*====================The section of FIXED FACTORs===================*/
|
|
unsigned int cmucal_fixed_factor_size = 5;
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|
|
|
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struct cmucal_clk_fixed_factor cmucal_fixed_factor_list[] = {
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FIXEDFACTOR(CLKCMU_FSYS1_PCIE, GATE_CLKCMU_FSYS1_PCIE, 7, CLK_CON_DIV_CLKCMU_FSYS1_PCIE_ENABLE_AUTOMATIC_CLKGATING),
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FIXEDFACTOR(CLKCMU_OTP, OSCCLK_CMU, 7, CLK_CON_DIV_CLKCMU_OTP_ENABLE_AUTOMATIC_CLKGATING),
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FIXEDFACTOR(CLKCMU_FSYS0_USBDP_DEBUG, GATE_CLKCMU_FSYS0_USBDP_DEBUG, 7, CLK_CON_DIV_CLKCMU_FSYS0_USBDP_DEBUG_ENABLE_AUTOMATIC_CLKGATING),
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FIXEDFACTOR(CLK_MIF_BUSD, CLKMUX_MIF_DDRPHY2X, 3, CLK_CON_DIV_CLK_MIF_BUSD_ENABLE_AUTOMATIC_CLKGATING),
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FIXEDFACTOR(CLK_MIF_BUSD_S2D, CLKCMU_MIF_DDRPHY2X_S2D, 3, CLK_CON_DIV_CLK_MIF_BUSD_S2D_ENABLE_AUTOMATIC_CLKGATING),
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};
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