7300 lines
359 KiB
C
Executable File
7300 lines
359 KiB
C
Executable File
#ifndef __CMUCAL_SFR_H__
|
|
#define __CMUCAL_SFR_H__
|
|
|
|
#include "../cmucal.h"
|
|
|
|
/*=================CMUCAL version: S5E9810================================*/
|
|
|
|
/*====================The section of SFR Block===================*/
|
|
enum sfr_block_id {
|
|
APM = SFR_BLOCK_TYPE,
|
|
AUD,
|
|
BUS1,
|
|
BUSC,
|
|
CHUB,
|
|
CMGP,
|
|
CMU,
|
|
CORE,
|
|
CPUCL0,
|
|
CPUCL1,
|
|
DCF,
|
|
DCPOST,
|
|
DCRD,
|
|
DPU,
|
|
DSPM,
|
|
DSPS,
|
|
FSYS0,
|
|
FSYS1,
|
|
G2D,
|
|
G3D,
|
|
ISPHQ,
|
|
ISPLP,
|
|
ISPPRE,
|
|
IVA,
|
|
MFC,
|
|
MIF,
|
|
PERIC0,
|
|
PERIC1,
|
|
PERIS,
|
|
S2D,
|
|
VTS,
|
|
end_of_sfr_block,
|
|
num_of_sfr_block = end_of_sfr_block - SFR_BLOCK_TYPE,
|
|
};
|
|
|
|
/*====================The section of SFR===================*/
|
|
enum sfr_id {
|
|
PLL_CON0_MUX_CLKCMU_APM_BUS_USER = SFR_TYPE,
|
|
PLL_CON2_MUX_CLKCMU_APM_BUS_USER,
|
|
CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0,
|
|
CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT1,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLKCMU_APM_DLL_CHUB,
|
|
CLK_CON_GAT_GATE_CLKCMU_APM_DLL_VTS,
|
|
CLK_CON_MUX_MUX_CLK_APM_BUS,
|
|
CLK_CON_DIV_CLKCMU_APM_DLL_CMGP,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CHUB_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CHUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CHUB2CP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CHUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_P_APM2CMGP_IPCLKPORT_I_CLK,
|
|
PLL_CON0_MUX_DLL_USER,
|
|
PLL_CON2_MUX_DLL_USER,
|
|
CLK_CON_GAT_GATE_CLKCMU_APM_DLL_CMGP,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_APM_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_CHUB_IPCLKPORT_I_CLK,
|
|
CLK_CON_DIV_CLKCMU_APM_DLL_VTS,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
|
|
CLK_CON_DIV_DIV_CLK_APM_BUS,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CHUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2VTS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK,
|
|
QCH_CON_APBIF_GPIO_ALIVE_QCH,
|
|
QCH_CON_APBIF_PMU_ALIVE_QCH,
|
|
QCH_CON_APBIF_RTC_QCH,
|
|
QCH_CON_APBIF_TOP_RTC_QCH,
|
|
QCH_CON_APM_CMU_APM_QCH,
|
|
QCH_CON_GREBEINTEGRATION_QCH_GREBE,
|
|
QCH_CON_GREBEINTEGRATION_QCH_DBG,
|
|
QCH_CON_INTMEM_QCH,
|
|
QCH_CON_LHM_AXI_P_APM_QCH,
|
|
QCH_CON_LHM_AXI_P_APM_CHUB_QCH,
|
|
QCH_CON_LHM_AXI_P_APM_CP_QCH,
|
|
QCH_CON_LHM_AXI_P_APM_GNSS_QCH,
|
|
QCH_CON_LHS_AXI_D_APM_QCH,
|
|
QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH,
|
|
QCH_CON_LHS_AXI_LP_CHUB_QCH,
|
|
QCH_CON_LHS_AXI_P_APM2CMGP_QCH,
|
|
QCH_CON_MAILBOX_AP2CHUB_QCH,
|
|
QCH_CON_MAILBOX_AP2CP_QCH,
|
|
QCH_CON_MAILBOX_AP2CP_S_QCH,
|
|
QCH_CON_MAILBOX_AP2GNSS_QCH,
|
|
QCH_CON_MAILBOX_AP2VTS_QCH,
|
|
QCH_CON_MAILBOX_APM2AP_QCH,
|
|
QCH_CON_MAILBOX_APM2CHUB_QCH,
|
|
QCH_CON_MAILBOX_APM2CP_QCH,
|
|
QCH_CON_MAILBOX_APM2GNSS_QCH,
|
|
QCH_CON_MAILBOX_CHUB2CP_QCH,
|
|
QCH_CON_MAILBOX_GNSS2CHUB_QCH,
|
|
QCH_CON_MAILBOX_GNSS2CP_QCH,
|
|
QCH_CON_PEM_QCH,
|
|
QCH_CON_PGEN_APM_QCH,
|
|
QCH_CON_PMU_INTR_GEN_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH,
|
|
QCH_CON_SPEEDY_APM_QCH,
|
|
QCH_CON_SPEEDY_SUB_APM_QCH,
|
|
QCH_CON_SYSREG_APM_QCH,
|
|
QCH_CON_WDT_APM_QCH,
|
|
PLL_CON0_PLL_AUD,
|
|
PLL_CON3_PLL_AUD,
|
|
PLL_LOCKTIME_PLL_AUD,
|
|
CLK_CON_DIV_DIV_CLK_AUD_PLL,
|
|
CLK_CON_DIV_DIV_CLK_AUD_AUDIF,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_ATCLK,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG,
|
|
CLK_CON_DIV_DIV_CLK_AUD_DSIF,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF0,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF1,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF2,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF3,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF3,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF2,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF1,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF0,
|
|
PLL_CON0_MUX_CLKCMU_AUD_CPU_USER,
|
|
PLL_CON2_MUX_CLKCMU_AUD_CPU_USER,
|
|
CLK_CON_MUX_MUX_CLK_AUD_CPU,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_ATB_AUD_IPCLKPORT_I_CLK,
|
|
CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT0,
|
|
CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT1,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ATCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK,
|
|
CLK_CON_DIV_DIV_CLK_AUD_BUS,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2,
|
|
CLK_CON_DIV_DIV_CLK_AUD_BUSP,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_DIV_DIV_CLK_AUD_DMIC,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ATB,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_DAP_IPCLKPORT_DAPCLK,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK,
|
|
CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_XIU_P_AUD_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI2APB_AUD_IPCLKPORT_ACLK,
|
|
QCH_CON_ABOX_QCH_ACLK,
|
|
QCH_CON_ABOX_QCH_BCLK_DSIF,
|
|
QCH_CON_ABOX_QCH_BCLK0,
|
|
QCH_CON_ABOX_QCH_BCLK1,
|
|
QCH_CON_ABOX_QCH_BCLK2,
|
|
QCH_CON_ABOX_QCH_BCLK3,
|
|
DMYQCH_CON_ABOX_QCH_DUMMY,
|
|
QCH_CON_ABOX_QCH_CCLK_ASB,
|
|
QCH_CON_ABOX_QCH_CCLK_ATB,
|
|
QCH_CON_AUD_CMU_AUD_QCH,
|
|
QCH_CON_BTM_AUD_QCH,
|
|
DMYQCH_CON_DFTMUX_AUD_QCH,
|
|
DMYQCH_CON_DMIC_QCH,
|
|
QCH_CON_GPIO_AUD_QCH,
|
|
QCH_CON_LHM_AXI_P_AUD_QCH,
|
|
QCH_CON_LHS_ATB_AUD_QCH,
|
|
QCH_CON_LHS_AXI_D_AUD_QCH,
|
|
QCH_CON_PPMU_AUD_QCH,
|
|
QCH_CON_SYSMMU_AUD_QCH,
|
|
QCH_CON_SYSREG_AUD_QCH,
|
|
QCH_CON_TREX_AUD_QCH,
|
|
QCH_CON_WDT_AUD_QCH,
|
|
PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER,
|
|
PLL_CON2_MUX_CLKCMU_BUS1_BUS_USER,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK,
|
|
CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT0,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK,
|
|
CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT1,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUS_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_CHUB_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_BUS1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CHUB_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CSSYS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_CHUB_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D_BUS1_IPCLKPORT_ACLK,
|
|
QCH_CON_BAAW_P_CHUB_QCH,
|
|
QCH_CON_BAAW_P_GNSS_QCH,
|
|
QCH_CON_BUS1_CMU_BUS1_QCH,
|
|
QCH_CON_LHM_AXI_D_APM_QCH,
|
|
QCH_CON_LHM_AXI_D_CHUB_QCH,
|
|
QCH_CON_LHM_AXI_D_GNSS_QCH,
|
|
QCH_CON_LHM_AXI_G_CSSYS_QCH,
|
|
QCH_CON_LHS_AXI_D_BUS1_QCH,
|
|
QCH_CON_LHS_AXI_P_CHUB_QCH,
|
|
QCH_CON_LHS_AXI_P_CSSYS_QCH,
|
|
QCH_CON_LHS_AXI_P_GNSS_QCH,
|
|
QCH_CON_SYSREG_BUS1_QCH,
|
|
QCH_CON_TREX_P_BUS1_QCH,
|
|
CLK_CON_DIV_DIV_CLK_BUSC_BUSP,
|
|
PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER,
|
|
PLL_CON2_MUX_CLKCMU_BUSC_BUS_USER,
|
|
CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT0,
|
|
CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT1,
|
|
CLK_CON_GAT_CLK_BLK_BUSC_UID_HPM_BUSC_IPCLKPORT_HPM_TARGETCLK_C,
|
|
QCH_CON_BUSC_CMU_BUSC_QCH,
|
|
QCH_CON_BUSIF_CMUTOPC_QCH,
|
|
QCH_CON_BUSIF_HPMBUSC_QCH,
|
|
QCH_CON_LHM_ACEL_D0_DSPM_QCH,
|
|
QCH_CON_LHM_ACEL_D0_G2D_QCH,
|
|
QCH_CON_LHM_ACEL_D1_DSPM_QCH,
|
|
QCH_CON_LHM_ACEL_D1_G2D_QCH,
|
|
QCH_CON_LHM_ACEL_D2_DSPM_QCH,
|
|
QCH_CON_LHM_ACEL_D2_G2D_QCH,
|
|
QCH_CON_LHM_ACEL_D_FSYS0_QCH,
|
|
QCH_CON_LHM_ACEL_D_FSYS1_QCH,
|
|
QCH_CON_LHM_ACEL_D_IVA_QCH,
|
|
QCH_CON_LHM_AXI_D0_DPU_QCH,
|
|
QCH_CON_LHM_AXI_D0_ISPLP_QCH,
|
|
QCH_CON_LHM_AXI_D0_MFC_QCH,
|
|
QCH_CON_LHM_AXI_D1_DPU_QCH,
|
|
QCH_CON_LHM_AXI_D1_ISPLP_QCH,
|
|
QCH_CON_LHM_AXI_D1_MFC_QCH,
|
|
QCH_CON_LHM_AXI_D2_DPU_QCH,
|
|
QCH_CON_LHM_AXI_D_AUD_QCH,
|
|
QCH_CON_LHM_AXI_D_BUS1_QCH,
|
|
QCH_CON_LHM_AXI_D_DCF_QCH,
|
|
QCH_CON_LHM_AXI_D_DCRD_QCH,
|
|
QCH_CON_LHM_AXI_D_ISPHQ_QCH,
|
|
QCH_CON_LHM_AXI_D_ISPPRE_QCH,
|
|
QCH_CON_LHS_AXI_D_IVASC_QCH,
|
|
QCH_CON_LHS_AXI_P_AUD_QCH,
|
|
QCH_CON_LHS_AXI_P_DCF_QCH,
|
|
QCH_CON_LHS_AXI_P_DCRD_QCH,
|
|
QCH_CON_LHS_AXI_P_DPU_QCH,
|
|
QCH_CON_LHS_AXI_P_DSPM_QCH,
|
|
QCH_CON_LHS_AXI_P_FSYS0_QCH,
|
|
QCH_CON_LHS_AXI_P_FSYS1_QCH,
|
|
QCH_CON_LHS_AXI_P_G2D_QCH,
|
|
QCH_CON_LHS_AXI_P_ISPHQ_QCH,
|
|
QCH_CON_LHS_AXI_P_ISPLP_QCH,
|
|
QCH_CON_LHS_AXI_P_ISPPRE_QCH,
|
|
QCH_CON_LHS_AXI_P_IVA_QCH,
|
|
QCH_CON_LHS_AXI_P_MFC_QCH,
|
|
QCH_CON_LHS_AXI_P_MIF0_QCH,
|
|
QCH_CON_LHS_AXI_P_MIF1_QCH,
|
|
QCH_CON_LHS_AXI_P_MIF2_QCH,
|
|
QCH_CON_LHS_AXI_P_MIF3_QCH,
|
|
QCH_CON_LHS_AXI_P_PERIC0_QCH,
|
|
QCH_CON_LHS_AXI_P_PERIC1_QCH,
|
|
QCH_CON_LHS_AXI_P_PERIS_QCH,
|
|
QCH_CON_PDMA0_QCH,
|
|
QCH_CON_PGEN_LITE_BUSC_QCH,
|
|
QCH_CON_PGEN_PDMA0_QCH,
|
|
QCH_CON_PPFW_QCH,
|
|
QCH_CON_SBIC_QCH,
|
|
QCH_CON_SIREX_QCH,
|
|
QCH_CON_SPDMA_QCH,
|
|
QCH_CON_SYSREG_BUSC_QCH,
|
|
QCH_CON_TREX_D_BUSC_QCH,
|
|
QCH_CON_TREX_P_BUSC_QCH,
|
|
QCH_CON_TREX_RB_BUSC_QCH,
|
|
PLL_CON0_MUX_CLKCMU_CHUB_BUS_USER,
|
|
PLL_CON2_MUX_CLKCMU_CHUB_BUS_USER,
|
|
CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT0,
|
|
CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT1,
|
|
PLL_CON0_MUX_CLKCMU_CHUB_DLL_BUS_USER,
|
|
PLL_CON2_MUX_CLKCMU_CHUB_DLL_BUS_USER,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_BUS,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_USI01,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_I2C,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_USI00,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI00_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI01_IPCLKPORT_CLK,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_I2C,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_USI00,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_USI01,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_BUS,
|
|
CLK_CON_GAT_GATE_CLK_CHUB_I2C,
|
|
CLK_CON_GAT_GATE_CLK_CHUB_USI00,
|
|
CLK_CON_GAT_GATE_CLK_CHUB_USI01,
|
|
CLK_CON_MUX_CLK_CHUB_TIMER_FCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB00_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB01_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB00_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB01_IPCLKPORT_IPCLK,
|
|
QCH_CON_ASYNCAHBM_CHUB_QCH,
|
|
QCH_CON_BAAW_D_CHUB_QCH,
|
|
QCH_CON_BAAW_P_APM_CHUB_QCH,
|
|
QCH_CON_BAAW_S_CHUB_QCH,
|
|
QCH_CON_CHUB_CMU_CHUB_QCH,
|
|
QCH_CON_CM4_CHUB_QCH,
|
|
QCH_CON_GPIO_CHUB_QCH,
|
|
QCH_CON_I2C_CHUB00_QCH,
|
|
QCH_CON_I2C_CHUB01_QCH,
|
|
QCH_CON_LHM_AXI_LP_CHUB_QCH,
|
|
QCH_CON_LHM_AXI_P_CHUB_QCH,
|
|
QCH_CON_LHS_AXI_D_CHUB_QCH,
|
|
QCH_CON_LHS_AXI_P_APM_CHUB_QCH,
|
|
QCH_CON_PDMA_CHUB_QCH,
|
|
QCH_CON_PWM_CHUB_QCH,
|
|
QCH_CON_SWEEPER_D_CHUB_QCH,
|
|
QCH_CON_SWEEPER_P_APM_CHUB_QCH,
|
|
QCH_CON_SYSREG_CHUB_QCH,
|
|
QCH_CON_TIMER_CHUB_QCH,
|
|
QCH_CON_USI_CHUB00_QCH,
|
|
QCH_CON_USI_CHUB01_QCH,
|
|
QCH_CON_WDT_CHUB_QCH,
|
|
PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER,
|
|
PLL_CON2_MUX_CLKCMU_CMGP_BUS_USER,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK,
|
|
CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT0,
|
|
CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT1,
|
|
CLK_CON_MUX_MUX_CLK_I2C_CMGP,
|
|
CLK_CON_DIV_DIV_CLK_I2C_CMGP,
|
|
CLK_CON_DIV_DIV_CLK_USI_CMGP01,
|
|
CLK_CON_MUX_MUX_CLK_USI_CMGP00,
|
|
CLK_CON_MUX_MUX_CLK_USI_CMGP01,
|
|
CLK_CON_DIV_DIV_CLK_USI_CMGP00,
|
|
CLK_CON_MUX_MUX_CLK_USI_CMGP02,
|
|
CLK_CON_MUX_MUX_CLK_USI_CMGP03,
|
|
CLK_CON_DIV_DIV_CLK_USI_CMGP02,
|
|
CLK_CON_DIV_DIV_CLK_USI_CMGP03,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP00_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP00_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP01_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP02_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP03_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP01_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP02_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP03_IPCLKPORT_CLK,
|
|
PLL_CON0_MUX_CLKCMU_CMGP_DLL_USER,
|
|
PLL_CON2_MUX_CLKCMU_CMGP_DLL_USER,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_BUS,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_XIU_P_CMGP_IPCLKPORT_ACLK,
|
|
CLK_CON_MUX_CLK_CMGP_ADC,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_ADC,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_P_APM2CMGP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GATE_CLK_I2C_CMGP,
|
|
CLK_CON_GAT_GATE_CLK_USI_CMGP00,
|
|
CLK_CON_GAT_GATE_CLK_USI_CMGP01,
|
|
CLK_CON_GAT_GATE_CLK_USI_CMGP02,
|
|
CLK_CON_GAT_GATE_CLK_USI_CMGP03,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_CHUB_IPCLKPORT_PCLK,
|
|
QCH_CON_ADC_CMGP_QCH_S0,
|
|
QCH_CON_ADC_CMGP_QCH_S1,
|
|
DMYQCH_CON_ADC_CMGP_QCH_ADC,
|
|
QCH_CON_CMGP_CMU_CMGP_QCH,
|
|
QCH_CON_GPIO_CMGP_QCH,
|
|
QCH_CON_I2C_CMGP00_QCH,
|
|
QCH_CON_I2C_CMGP01_QCH,
|
|
QCH_CON_I2C_CMGP02_QCH,
|
|
QCH_CON_I2C_CMGP03_QCH,
|
|
QCH_CON_LHM_AXI_P_APM2CMGP_QCH,
|
|
QCH_CON_SYSREG_CMGP_QCH,
|
|
QCH_CON_SYSREG_CMGP2CHUB_QCH,
|
|
QCH_CON_SYSREG_CMGP2CP_QCH,
|
|
QCH_CON_SYSREG_CMGP2GNSS_QCH,
|
|
QCH_CON_SYSREG_CMGP2PMU_AP_QCH,
|
|
QCH_CON_SYSREG_CMGP2PMU_CHUB_QCH,
|
|
QCH_CON_USI_CMGP00_QCH,
|
|
QCH_CON_USI_CMGP01_QCH,
|
|
QCH_CON_USI_CMGP02_QCH,
|
|
QCH_CON_USI_CMGP03_QCH,
|
|
CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
|
|
CLK_CON_DIV_CLKCMU_APM_BUS,
|
|
CLK_CON_DIV_DIV_PLL_SHARED0_DIV2,
|
|
CLK_CON_DIV_CLKCMU_G3D_SWITCH,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_BUS,
|
|
CLK_CON_DIV_CLKCMU_PERIS_BUS,
|
|
CLK_CON_DIV_CLKCMU_FSYS0_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPU_BUS,
|
|
PLL_CON0_PLL_SHARED1,
|
|
PLL_LOCKTIME_PLL_SHARED1,
|
|
CLK_CON_DIV_DIV_PLL_SHARED1_DIV2,
|
|
CLK_CON_GAT_CLKCMU_MIF_SWITCH,
|
|
CLK_CON_DIV_CLKCMU_BUS1_BUS,
|
|
CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS,
|
|
CLK_CON_DIV_DIV_PLL_SHARED2_DIV2,
|
|
CLK_CON_DIV_DIV_PLL_SHARED3_DIV2,
|
|
CLK_CON_DIV_DIV_PLL_SHARED4_DIV2,
|
|
PLL_CON0_PLL_SHARED4,
|
|
PLL_LOCKTIME_PLL_SHARED4,
|
|
CLK_CON_DIV_DIV_PLL_SHARED0_DIV4,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC_BUS,
|
|
CLK_CON_DIV_CLKCMU_MFC_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_G2D_G2D,
|
|
CLK_CON_DIV_CLKCMU_G2D_G2D,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS0_USB30DRD,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS0_USB30DRD,
|
|
CLK_CON_DIV_CLKCMU_FSYS0_USB30DRD,
|
|
CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD,
|
|
CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD,
|
|
CLK_CON_DIV_CLKCMU_FSYS1_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPU_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS,
|
|
CLK_CON_DIV_CLKCMU_CMGP_BUS,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSPM_BUS,
|
|
CLK_CON_DIV_CLKCMU_DSPM_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
|
|
PLL_CON0_PLL_SHARED3,
|
|
PLL_LOCKTIME_PLL_SHARED3,
|
|
CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS,
|
|
CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS,
|
|
CLK_CON_DIV_CLKCMU_BUSC_BUS,
|
|
CLK_CON_MUX_MUX_CLKCMU_G2D_G2D,
|
|
CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS,
|
|
PLL_CON0_PLL_SHARED2,
|
|
PLL_LOCKTIME_PLL_SHARED2,
|
|
PLL_CON0_PLL_SHARED0,
|
|
PLL_LOCKTIME_PLL_SHARED0,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD,
|
|
CLK_CON_MUX_MUX_CLKCMU_DSPM_BUS,
|
|
CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
|
|
CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
|
|
CLK_CON_DIV_CLKCMU_CORE_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
|
|
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
|
|
CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
|
|
CLK_CON_MUX_MUX_CLKCMU_ISPPRE_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_ISPPRE_BUS,
|
|
CLK_CON_DIV_CLKCMU_ISPPRE_BUS,
|
|
CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS,
|
|
CLK_CON_DIV_CLKCMU_ISPLP_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS,
|
|
CLK_CON_DIV_CLKCMU_ISPHQ_BUS,
|
|
CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_CPU,
|
|
CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
|
|
CLK_CON_DIV_CLKCMU_AUD_CPU,
|
|
CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
|
|
CLK_CON_DIV_CLKCMU_G2D_MSCL,
|
|
CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL,
|
|
CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT0,
|
|
CLK_CON_MUX_MUX_CLKCMU_HPM,
|
|
CLK_CON_DIV_CLKCMU_HPM,
|
|
CLK_CON_GAT_GATE_CLKCMU_HPM,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE,
|
|
CLK_CON_DIV_CLKCMU_FSYS1_PCIE,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,
|
|
CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS,
|
|
CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT1,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK0,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK1,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK2,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK3,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3,
|
|
CLK_CON_DIV_CLKCMU_OTP,
|
|
CLK_CON_MUX_MUX_CLKCMU_IVA_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_IVA_BUS,
|
|
CLK_CON_DIV_CLKCMU_IVA_BUS,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD,
|
|
CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD,
|
|
CLK_CON_MUX_MUX_CMU_CMUREF,
|
|
CLK_CON_DIV_DIV_PLL_SHARED1_DIV4,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS,
|
|
CLK_CON_DIV_CLKCMU_FSYS0_DPGTC,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC,
|
|
CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0,
|
|
CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1,
|
|
CLK_CON_DIV_CLKCMU_MODEM_SHARED0,
|
|
CLK_CON_DIV_CLKCMU_MODEM_SHARED1,
|
|
CLK_CON_DIV_CLKCMU_DCRD_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_DCRD_BUS,
|
|
CLK_CON_MUX_MUX_CLKCMU_DCRD_BUS,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE,
|
|
CLK_CON_DIV_DIV_CLK_CMU_CMUREF,
|
|
CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS,
|
|
CLK_CON_DIV_CLKCMU_CHUB_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS,
|
|
CLK_CON_DIV_CLKCMU_DCF_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_DCF_BUS,
|
|
CLK_CON_MUX_MUX_CLKCMU_DCF_BUS,
|
|
CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS,
|
|
CLK_CON_MUX_MUX_CLK_CMU_CMUREF,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
|
|
CLK_CON_MUX_MUX_CLKCMU_VTS_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_VTS_BUS,
|
|
CLK_CON_DIV_CLKCMU_VTS_BUS,
|
|
CLK_CON_MUX_MUX_CLKCMU_ISPLP_VRA,
|
|
CLK_CON_GAT_GATE_CLKCMU_ISPLP_VRA,
|
|
CLK_CON_DIV_CLKCMU_ISPLP_VRA,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC_WFD,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC_WFD,
|
|
CLK_CON_DIV_CLKCMU_MFC_WFD,
|
|
CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP,
|
|
CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
|
|
CLK_CON_DIV_CLKCMU_MIF_BUSP,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_IP,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_IP,
|
|
CLK_CON_MUX_MUX_CLKCMU_DCPOST_BUS,
|
|
CLK_CON_GAT_GATE_CLKCMU_DCPOST_BUS,
|
|
CLK_CON_DIV_CLKCMU_DCPOST_BUS,
|
|
PLL_CON0_PLL_MMC,
|
|
PLL_CON3_PLL_MMC,
|
|
PLL_LOCKTIME_PLL_MMC,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDP_DEBUG,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDP_DEBUG,
|
|
CLK_CON_DIV_CLKCMU_FSYS0_USBDP_DEBUG,
|
|
CLK_CON_DIV_CLKCMU_ISPLP_GDC,
|
|
CLK_CON_GAT_GATE_CLKCMU_ISPLP_GDC,
|
|
CLK_CON_MUX_MUX_CLKCMU_ISPLP_GDC,
|
|
CLK_CON_MUX_MUX_CLKCMU_DSPS_AUD,
|
|
CLK_CON_DIV_CLKCMU_DSPS_AUD,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSPS_AUD,
|
|
CLK_CON_DIV_DIV_PLL_SHARED1_DIV3,
|
|
CLK_CON_DIV_DIV_PLL_SHARED0_DIV3,
|
|
CLK_CON_MUX_CLKCMU_DPU_BUS,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPU,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPU,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPU_BUS,
|
|
DMYQCH_CON_CMU_CMU_CMUREF_QCH,
|
|
DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0,
|
|
DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1,
|
|
DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2,
|
|
DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3,
|
|
DMYQCH_CON_OTP_QCH,
|
|
CLK_CON_DIV_DIV_CLK_CORE_BUSP,
|
|
CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMUPPC_CCI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK,
|
|
PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
|
|
PLL_CON2_MUX_CLKCMU_CORE_BUS_USER,
|
|
CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT0,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK,
|
|
CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT1,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CP_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_G3D_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_IO_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_DP_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BPS_P_G3D_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK,
|
|
QCH_CON_ACE_SLICE_G3D0_QCH,
|
|
QCH_CON_ACE_SLICE_G3D1_QCH,
|
|
QCH_CON_ACE_SLICE_G3D2_QCH,
|
|
QCH_CON_ACE_SLICE_G3D3_QCH,
|
|
QCH_CON_BAAW_CP_QCH,
|
|
QCH_CON_BDU_QCH,
|
|
QCH_CON_BUSIF_HPMCORE_QCH,
|
|
DMYQCH_CON_CCI_QCH,
|
|
QCH_CON_CORE_CMU_CORE_QCH,
|
|
QCH_CON_LHM_ACE_D0_G3D_QCH,
|
|
QCH_CON_LHM_ACE_D1_G3D_QCH,
|
|
QCH_CON_LHM_ACE_D2_G3D_QCH,
|
|
QCH_CON_LHM_ACE_D3_G3D_QCH,
|
|
QCH_CON_LHM_ACE_D_CPUCL0_QCH,
|
|
QCH_CON_LHM_AXI_D_CP_QCH,
|
|
QCH_CON_LHM_AXI_P_CLUSTER0_QCH,
|
|
QCH_CON_LHS_ATB_T_BDU_QCH,
|
|
QCH_CON_LHS_AXI_P_APM_QCH,
|
|
QCH_CON_LHS_AXI_P_CP_QCH,
|
|
QCH_CON_LHS_AXI_P_CPUCL0_QCH,
|
|
QCH_CON_LHS_AXI_P_CPUCL1_QCH,
|
|
QCH_CON_LHS_AXI_P_G3D_QCH,
|
|
QCH_CON_PPCFW_G3D_QCH,
|
|
QCH_CON_PPFW_DP_QCH,
|
|
QCH_CON_PPFW_G3D_QCH,
|
|
QCH_CON_PPFW_IO_QCH,
|
|
QCH_CON_PPMU_CPUCL0_QCH,
|
|
QCH_CON_PPMU_CPUCL1_QCH,
|
|
QCH_CON_PPMU_G3D0_QCH,
|
|
QCH_CON_PPMU_G3D1_QCH,
|
|
QCH_CON_PPMU_G3D2_QCH,
|
|
QCH_CON_PPMU_G3D3_QCH,
|
|
QCH_CON_SYSREG_CORE_QCH,
|
|
QCH_CON_TREX_D_CORE_QCH,
|
|
QCH_CON_TREX_P0_CORE_QCH,
|
|
QCH_CON_TREX_P1_CORE_QCH,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_PLL,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF,
|
|
PLL_CON0_PLL_CPUCL0,
|
|
PLL_LOCKTIME_PLL_CPUCL0,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER,
|
|
PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK,
|
|
CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT0,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK,
|
|
CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT1,
|
|
CLK_CON_GAT_GATE_CLK_CPUCL0_CPU,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_CPU,
|
|
CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT0,
|
|
CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT1,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER,
|
|
PLL_CON2_MUX_CLKCMU_CPUCL0_DBG_BUS_USER,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_BDU_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER0_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER1_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER0_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER1_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_DSPM_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CSSYS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_P_CSSYS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI_DS_64TO32_G_CSSYS_IPCLKPORT_ACLK,
|
|
CLK_CON_MUX_MUX_CLK_CLUSTER0_SCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK,
|
|
CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLK,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLKP,
|
|
CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLKP,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_P_CLUSTER0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLKP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_SCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKS,
|
|
DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH,
|
|
QCH_CON_BUSIF_HPMCPUCL0_QCH,
|
|
QCH_CON_CLUSTER0_QCH_SCLK,
|
|
QCH_CON_CLUSTER0_QCH_ATCLK,
|
|
QCH_CON_CLUSTER0_QCH_PDBGCLK,
|
|
QCH_CON_CLUSTER0_QCH_GIC,
|
|
QCH_CON_CLUSTER0_QCH_DBG_PD,
|
|
QCH_CON_CLUSTER0_QCH_PCLK,
|
|
DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK,
|
|
QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH,
|
|
QCH_CON_CPUCL0_CMU_CPUCL0_QCH,
|
|
QCH_CON_CSSYS_QCH,
|
|
QCH_CON_DUMPPC_CLUSTER0_QCH,
|
|
QCH_CON_DUMPPC_CLUSTER1_QCH,
|
|
QCH_CON_LHM_ATB_T0_CLUSTER0_QCH,
|
|
QCH_CON_LHM_ATB_T0_CLUSTER1_QCH,
|
|
QCH_CON_LHM_ATB_T1_CLUSTER0_QCH,
|
|
QCH_CON_LHM_ATB_T1_CLUSTER1_QCH,
|
|
QCH_CON_LHM_ATB_T2_CLUSTER0_QCH,
|
|
QCH_CON_LHM_ATB_T2_CLUSTER1_QCH,
|
|
QCH_CON_LHM_ATB_T3_CLUSTER0_QCH,
|
|
QCH_CON_LHM_ATB_T3_CLUSTER1_QCH,
|
|
QCH_CON_LHM_ATB_T_AUD_QCH,
|
|
QCH_CON_LHM_ATB_T_BDU_QCH,
|
|
QCH_CON_LHM_AXI_P_CPUCL0_QCH,
|
|
QCH_CON_LHM_AXI_P_CSSYS_QCH,
|
|
QCH_CON_LHS_ACE_D_CLUSTER0_QCH,
|
|
QCH_CON_LHS_ATB_T0_CLUSTER0_QCH,
|
|
QCH_CON_LHS_ATB_T1_CLUSTER0_QCH,
|
|
QCH_CON_LHS_ATB_T2_CLUSTER0_QCH,
|
|
QCH_CON_LHS_ATB_T3_CLUSTER0_QCH,
|
|
QCH_CON_LHS_AXI_G_CSSYS_QCH,
|
|
QCH_CON_LHS_AXI_G_ETR_QCH,
|
|
QCH_CON_LHS_AXI_P_CLUSTER0_QCH,
|
|
QCH_CON_SECJTAG_QCH,
|
|
QCH_CON_SYSREG_CPUCL0_QCH,
|
|
PLL_CON0_PLL_CPUCL1,
|
|
PLL_LOCKTIME_PLL_CPUCL1,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER,
|
|
PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_PLL,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK,
|
|
CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT0,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_0_IPCLKPORT_HPM_TARGETCLK_C,
|
|
CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT1,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK,
|
|
CLK_CON_GAT_GATE_CLK_CPUCL1_CPU,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_CPU,
|
|
CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT0,
|
|
CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT1,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CLUSTER1_IPCLKPORT_PCLKDBG,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_1_IPCLKPORT_HPM_TARGETCLK_C,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_2_IPCLKPORT_HPM_TARGETCLK_C,
|
|
QCH_CON_BUSIF_HPMCPUCL1_QCH,
|
|
DMYQCH_CON_CLUSTER1_QCH_CPU,
|
|
QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1,
|
|
QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1,
|
|
QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1,
|
|
QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1,
|
|
DMYQCH_CON_CLUSTER1_QCH_PCLKDBG,
|
|
QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH,
|
|
QCH_CON_CPUCL1_CMU_CPUCL1_QCH,
|
|
QCH_CON_LHM_AXI_P_CPUCL1_QCH,
|
|
QCH_CON_SYSREG_CPUCL1_QCH,
|
|
CLK_CON_DIV_DIV_CLK_DCF_BUSP,
|
|
PLL_CON0_MUX_CLKCMU_DCF_BUS_USER,
|
|
PLL_CON2_MUX_CLKCMU_DCF_BUS_USER,
|
|
CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT0,
|
|
CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT1,
|
|
QCH_CON_BTM_DCF_QCH,
|
|
QCH_CON_DCF_CMU_DCF_QCH,
|
|
QCH_CON_IS_DCF_QCH_CIP,
|
|
QCH_CON_IS_DCF_QCH_QE,
|
|
QCH_CON_IS_DCF_QCH_SYSREG,
|
|
QCH_CON_IS_DCF_QCH_PPMU,
|
|
QCH_CON_IS_DCF_QCH_SYSMMU,
|
|
QCH_CON_IS_DCF_QCH_C2SYNC_2SLV,
|
|
QCH_CON_IS_DCF_QCH_PGEN_LITE,
|
|
QCH_CON_LHM_ATB_DCPOSTDCF_QCH,
|
|
QCH_CON_LHM_ATB_ISPHQDCF_QCH,
|
|
QCH_CON_LHM_AXI_D_DCPOSTDCF_QCH,
|
|
QCH_CON_LHM_AXI_P_DCF_QCH,
|
|
QCH_CON_LHS_ATB_DCFDCPOST_QCH,
|
|
QCH_CON_LHS_ATB_DCFISPLP_QCH,
|
|
QCH_CON_LHS_AXI_D_DCF_QCH,
|
|
QCH_CON_LHS_AXI_P_DCFDCPOST_QCH,
|
|
PLL_CON0_MUX_CLKCMU_DCPOST_BUS_USER,
|
|
PLL_CON2_MUX_CLKCMU_DCPOST_BUS_USER,
|
|
CLK_CON_DIV_DIV_CLK_DCPOST_BUSP,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCF_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_AXI_D_DCPOSTDCF_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCRDDCPOST_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_SYSREG_DCPOST_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_CIP2_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_CIP2_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_AXI_P_DCFDCPOST_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSP_IPCLKPORT_CLK,
|
|
CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT0,
|
|
CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT1,
|
|
CLK_CON_GAT_CLK_BLK_DCPOST_UID_DCPOST_CMU_DCPOST_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_C2SYNC_1SLV_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_C2SYNC_1SLV_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCFDCPOST_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCRD_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_CIP2_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_C2SYNC_1SLV_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AXI2APB_DCPOST_ACLK,
|
|
QCH_CON_DCPOST_CMU_DCPOST_QCH,
|
|
QCH_CON_IS_DCPOST_QCH_SYSREG,
|
|
QCH_CON_IS_DCPOST_QCH_CIP2,
|
|
QCH_CON_IS_DCPOST_QCH_QE,
|
|
QCH_CON_IS_DCPOST_QCH_C2SYNC_1SLV_CLK,
|
|
QCH_CON_LHM_ATB_DCFDCPOST_QCH,
|
|
QCH_CON_LHM_ATB_DCRDDCPOST_QCH,
|
|
QCH_CON_LHM_AXI_P_DCFDCPOST_QCH,
|
|
QCH_CON_LHS_ATB_DCPOSTDCF_QCH,
|
|
QCH_CON_LHS_ATB_DCPOSTDCRD_QCH,
|
|
QCH_CON_LHS_AXI_D_DCPOSTDCF_QCH,
|
|
CLK_CON_DIV_DIV_CLK_DCRD_BUSP,
|
|
PLL_CON0_MUX_CLKCMU_DCRD_BUS_USER,
|
|
PLL_CON2_MUX_CLKCMU_DCRD_BUS_USER,
|
|
CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT0,
|
|
CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT1,
|
|
CLK_CON_DIV_DIV_CLK_DCRD_BUSD_HALF,
|
|
QCH_CON_BTM_DCRD_QCH,
|
|
QCH_CON_DCRD_CMU_DCRD_QCH,
|
|
QCH_CON_IS_DCRD_QCH_DCP,
|
|
QCH_CON_IS_DCRD_QCH_PPMU,
|
|
QCH_CON_IS_DCRD_QCH_SYSMMU,
|
|
QCH_CON_IS_DCRD_QCH_SYSREG,
|
|
QCH_CON_IS_DCRD_QCH_PGEN_LITE,
|
|
QCH_CON_IS_DCRD_QCH_DCP_C2C,
|
|
QCH_CON_IS_DCRD_QCH_DCP_DIV2,
|
|
QCH_CON_LHM_ATB_DCPOSTDCRD_QCH,
|
|
QCH_CON_LHM_AXI_P_DCRD_QCH,
|
|
QCH_CON_LHS_ATB_DCRDDCPOST_QCH,
|
|
QCH_CON_LHS_ATB_DCRDISPLP_QCH,
|
|
QCH_CON_LHS_AXI_D_DCRD_QCH,
|
|
PLL_CON0_MUX_CLKCMU_DPU_BUS_USER,
|
|
PLL_CON2_MUX_CLKCMU_DPU_BUS_USER,
|
|
CLK_CON_DIV_DIV_CLK_DPU_BUSP,
|
|
CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK,
|
|
CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT0,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD0_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD1_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_XIU_P_DPU_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON1_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPP_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD2_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON2_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_S_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_S_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_S_IPCLKPORT_PCLKS,
|
|
CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT1,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_WRAPPER_FOR_S5I6211_HSI_DCPHY_COMBO_TOP_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_PGEN_IPCLKPORT_PCLKS,
|
|
QCH_CON_BTM_DPUD0_QCH,
|
|
QCH_CON_BTM_DPUD1_QCH,
|
|
QCH_CON_BTM_DPUD2_QCH,
|
|
QCH_CON_DPU_QCH_DPU,
|
|
QCH_CON_DPU_QCH_DPU_DMA,
|
|
QCH_CON_DPU_QCH_DPU_DPP,
|
|
QCH_CON_DPU_QCH_DPU_WB_MUX,
|
|
QCH_CON_DPU_CMU_DPU_QCH,
|
|
QCH_CON_LHM_AXI_P_DPU_QCH,
|
|
QCH_CON_LHS_AXI_D0_DPU_QCH,
|
|
QCH_CON_LHS_AXI_D1_DPU_QCH,
|
|
QCH_CON_LHS_AXI_D2_DPU_QCH,
|
|
QCH_CON_PPMU_DPUD0_QCH,
|
|
QCH_CON_PPMU_DPUD1_QCH,
|
|
QCH_CON_PPMU_DPUD2_QCH,
|
|
QCH_CON_SYSMMU_DPUD0_QCH,
|
|
QCH_CON_SYSMMU_DPUD1_QCH,
|
|
QCH_CON_SYSMMU_DPUD2_QCH,
|
|
QCH_CON_SYSREG_DPU_QCH,
|
|
CLK_CON_DIV_DIV_CLK_DSPM_BUSP,
|
|
PLL_CON0_MUX_CLKCMU_DSPM_BUS_USER,
|
|
PLL_CON2_MUX_CLKCMU_DSPM_BUS_USER,
|
|
CLK_CON_GAT_CLK_BLK_DSPM_UID_DSPM_CMU_DSPM_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSREG_DSPM_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AXI2APB_DSPM_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_DSPM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_PCLK,
|
|
CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT0,
|
|
CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT1,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D0_DSPM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSD_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_IVADSPM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMIVA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_WRAP2_CONV_DSPM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKS,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKM,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D1_DSPM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLKCMU_DSPS_BUS,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_ADM_APB_DSPM_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D0_DSPSDSPM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D1_DSPSDSPM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_XIU_P_DSPM_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_PGEN_LITE_DSPM_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D2_DSPM_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_SCORE_MASTER_IPCLKPORT_I_CLK,
|
|
DMYQCH_CON_ADM_APB_DSPM_QCH,
|
|
QCH_CON_BTM_DSPM0_QCH,
|
|
QCH_CON_BTM_DSPM1_QCH,
|
|
QCH_CON_DSPM_CMU_DSPM_QCH,
|
|
QCH_CON_LHM_AXI_D0_DSPSDSPM_QCH,
|
|
QCH_CON_LHM_AXI_D1_DSPSDSPM_QCH,
|
|
QCH_CON_LHM_AXI_P_DSPM_QCH,
|
|
QCH_CON_LHM_AXI_P_IVADSPM_QCH,
|
|
QCH_CON_LHS_ACEL_D0_DSPM_QCH,
|
|
QCH_CON_LHS_ACEL_D1_DSPM_QCH,
|
|
QCH_CON_LHS_ACEL_D2_DSPM_QCH,
|
|
QCH_CON_LHS_AXI_P_DSPMDSPS_QCH,
|
|
QCH_CON_LHS_AXI_P_DSPMIVA_QCH,
|
|
QCH_CON_PGEN_LITE_DSPM_QCH,
|
|
QCH_CON_PPMU_DSPM0_QCH,
|
|
QCH_CON_PPMU_DSPM1_QCH,
|
|
QCH_CON_SCORE_MASTER_QCH,
|
|
QCH_CON_SYSMMU_DSPM0_QCH,
|
|
QCH_CON_SYSMMU_DSPM1_QCH,
|
|
QCH_CON_SYSREG_DSPM_QCH,
|
|
CLK_CON_DIV_DIV_CLK_DSPS_BUSP,
|
|
PLL_CON0_MUX_CLKCMU_DSPS_BUS_USER,
|
|
PLL_CON2_MUX_CLKCMU_DSPS_BUS_USER,
|
|
CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT0,
|
|
CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT1,
|
|
CLK_CON_GAT_CLK_BLK_DSPS_UID_DSPS_CMU_DSPS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPS_UID_AXI2APB_DSPS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPS_UID_LHM_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPS_UID_SYSREG_DSPS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_DSPS_UID_RSTNSYNC_CLK_DSPS_BUSP_IPCLKPORT_CLK,
|
|
PLL_CON0_MUX_CLKCMU_DSPS_AUD_USER,
|
|
PLL_CON2_MUX_CLKCMU_DSPS_AUD_USER,
|
|
CLK_CON_MUX_MUX_CLK_DSPS_BUS,
|
|
QCH_CON_DSPS_CMU_DSPS_QCH,
|
|
QCH_CON_LHM_AXI_D_IVADSPS_QCH,
|
|
QCH_CON_LHM_AXI_P_DSPMDSPS_QCH,
|
|
QCH_CON_LHS_AXI_D0_DSPSDSPM_QCH,
|
|
QCH_CON_LHS_AXI_D1_DSPSDSPM_QCH,
|
|
QCH_CON_LHS_AXI_D_DSPSIVA_QCH,
|
|
QCH_CON_SCORE_KNIGHT_QCH,
|
|
QCH_CON_SYSREG_DSPS_QCH,
|
|
PLL_CON0_MUX_CLKCMU_FSYS0_UFS_EMBD_USER,
|
|
PLL_CON2_MUX_CLKCMU_FSYS0_UFS_EMBD_USER,
|
|
PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER,
|
|
PLL_CON2_MUX_CLKCMU_FSYS0_BUS_USER,
|
|
PLL_CON0_MUX_CLKCMU_FSYS0_USB30DRD_USER,
|
|
PLL_CON2_MUX_CLKCMU_FSYS0_USB30DRD_USER,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USB30DRD_REF_CLK,
|
|
CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT0,
|
|
CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT1,
|
|
PLL_CON0_MUX_CLKCMU_FSYS0_DPGTC_USER,
|
|
PLL_CON2_MUX_CLKCMU_FSYS0_DPGTC_USER,
|
|
PLL_CON0_MUX_CLKCMU_FSYS0_USBDP_DEBUG_USER,
|
|
PLL_CON2_MUX_CLKCMU_FSYS0_USBDP_DEBUG_USER,
|
|
CLK_CON_GAT_CLK_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK,
|
|
QCH_CON_BTM_FSYS0_QCH,
|
|
QCH_CON_DP_LINK_QCH,
|
|
QCH_CON_DP_LINK_QCH_GTC,
|
|
QCH_CON_ETR_MIU_QCH_PCLK,
|
|
QCH_CON_ETR_MIU_QCH_ACLK,
|
|
QCH_CON_FSYS0_CMU_FSYS0_QCH,
|
|
QCH_CON_GPIO_FSYS0_QCH,
|
|
QCH_CON_LHM_AXI_G_ETR_QCH,
|
|
QCH_CON_LHM_AXI_P_FSYS0_QCH,
|
|
QCH_CON_LHS_ACEL_D_FSYS0_QCH,
|
|
QCH_CON_PGEN_LITE_FSYS0_QCH,
|
|
QCH_CON_PPMU_FSYS0_QCH,
|
|
QCH_CON_SYSREG_FSYS0_QCH,
|
|
QCH_CON_UFS_EMBD_QCH,
|
|
QCH_CON_UFS_EMBD_QCH_FMP,
|
|
QCH_CON_USB30DRD_QCH_USB30DRD_LINK,
|
|
QCH_CON_USB30DRD_QCH_USBPCS,
|
|
QCH_CON_USB30DRD_QCH_USB30DRD_CTRL,
|
|
QCH_CON_USB30DRD_QCH_USBDPPHY,
|
|
DMYQCH_CON_USB30DRD_QCH_SOC_PLL,
|
|
PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER,
|
|
PLL_CON2_MUX_CLKCMU_FSYS1_BUS_USER,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK,
|
|
PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER,
|
|
PLL_CON2_MUX_CLKCMU_FSYS1_MMC_CARD_USER,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK,
|
|
CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT0,
|
|
CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL,
|
|
CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT1,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK,
|
|
PLL_CON0_MUX_CLKCMU_FSYS1_PCIE_USER,
|
|
PLL_CON2_MUX_CLKCMU_FSYS1_PCIE_USER,
|
|
PLL_CON0_MUX_CLKCMU_FSYS1_UFS_CARD_USER,
|
|
PLL_CON2_MUX_CLKCMU_FSYS1_UFS_CARD_USER,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSMMU_FSYS1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PGEN_LITE_FSYS1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_DBI_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_IEEE1500_WRAPPER_FOR_QCHANNEL_WRAPPER_FOR_PCIEG3_PHY_X1_TOP_INST_0_I_APB_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_LT_PCIE3_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PHY_REFCLK_IN,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PIPE42_PCIE_PCS_X1_WRAP_INST_0_I_APB_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_SLV_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_DBI_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_SLV_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_SLV_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_DBI_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_MSTR_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK,
|
|
QCH_CON_ADM_AHB_SSS_QCH,
|
|
QCH_CON_BTM_FSYS1_QCH,
|
|
QCH_CON_FSYS1_CMU_FSYS1_QCH,
|
|
QCH_CON_GPIO_FSYS1_QCH,
|
|
QCH_CON_LHM_AXI_P_FSYS1_QCH,
|
|
QCH_CON_LHS_ACEL_D_FSYS1_QCH,
|
|
QCH_CON_MMC_CARD_QCH,
|
|
QCH_CON_PCIE_GEN2_QCH_MSTR,
|
|
QCH_CON_PCIE_GEN2_QCH_PCS,
|
|
QCH_CON_PCIE_GEN2_QCH_PHY,
|
|
QCH_CON_PCIE_GEN2_QCH_DBI,
|
|
QCH_CON_PCIE_GEN2_QCH_APB,
|
|
DMYQCH_CON_PCIE_GEN2_QCH_SOCPLL,
|
|
QCH_CON_PCIE_GEN3_QCH_MSTR,
|
|
QCH_CON_PCIE_GEN3_QCH_PCS,
|
|
QCH_CON_PCIE_GEN3_QCH_DBI,
|
|
QCH_CON_PCIE_GEN3_QCH_APB,
|
|
DMYQCH_CON_PCIE_GEN3_QCH_SOCPLL,
|
|
QCH_CON_PCIE_GEN3_QCH_PHY,
|
|
QCH_CON_PCIE_IA_GEN2_QCH,
|
|
QCH_CON_PCIE_IA_GEN3_QCH,
|
|
QCH_CON_PGEN_LITE_FSYS1_QCH,
|
|
QCH_CON_PPMU_FSYS1_QCH,
|
|
QCH_CON_RTIC_QCH,
|
|
QCH_CON_SSS_QCH,
|
|
QCH_CON_SYSMMU_FSYS1_QCH,
|
|
QCH_CON_SYSREG_FSYS1_QCH,
|
|
QCH_CON_UFS_CARD_QCH,
|
|
QCH_CON_UFS_CARD_QCH_FMP,
|
|
PLL_CON0_MUX_CLKCMU_G2D_G2D_USER,
|
|
PLL_CON2_MUX_CLKCMU_G2D_G2D_USER,
|
|
CLK_CON_DIV_DIV_CLK_G2D_BUSP,
|
|
PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER,
|
|
PLL_CON2_MUX_CLKCMU_G2D_MSCL_USER,
|
|
CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT0,
|
|
CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT1,
|
|
QCH_CON_ASTC_QCH,
|
|
QCH_CON_BTM_G2DD0_QCH,
|
|
QCH_CON_BTM_G2DD1_QCH,
|
|
QCH_CON_BTM_G2DD2_QCH,
|
|
QCH_CON_G2D_QCH,
|
|
QCH_CON_G2D_CMU_G2D_QCH,
|
|
QCH_CON_JPEG_QCH,
|
|
QCH_CON_LHM_AXI_P_G2D_QCH,
|
|
QCH_CON_LHS_ACEL_D0_G2D_QCH,
|
|
QCH_CON_LHS_ACEL_D1_G2D_QCH,
|
|
QCH_CON_LHS_ACEL_D2_G2D_QCH,
|
|
QCH_CON_MSCL_QCH,
|
|
QCH_CON_PGEN100_LITE_G2D_QCH,
|
|
QCH_CON_PPMU_G2DD0_QCH,
|
|
QCH_CON_PPMU_G2DD1_QCH,
|
|
QCH_CON_PPMU_G2DD2_QCH,
|
|
QCH_CON_QE_ASTC_QCH,
|
|
QCH_CON_QE_JPEG_QCH,
|
|
QCH_CON_QE_MSCL_QCH,
|
|
QCH_CON_SYSMMU_G2DD0_QCH,
|
|
QCH_CON_SYSMMU_G2DD1_QCH,
|
|
QCH_CON_SYSMMU_G2DD2_QCH,
|
|
QCH_CON_SYSREG_G2D_QCH,
|
|
CLK_CON_DIV_DIV_CLK_G3D_BUSP,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK,
|
|
CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT0,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D0_IPCLKPORT_HPM_TARGETCLK_C,
|
|
PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER,
|
|
PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER,
|
|
CLK_CON_MUX_MUX_CLK_G3D_BUSD,
|
|
CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT1,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK,
|
|
PLL_CON0_PLL_G3D,
|
|
PLL_LOCKTIME_PLL_G3D,
|
|
CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT0,
|
|
CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT1,
|
|
PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_USER,
|
|
PLL_CON2_MUX_CLKCMU_EMBEDDED_G3D_USER,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK,
|
|
CLK_CON_DIV_DIV_CLK_G3D_BUSD,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK,
|
|
QCH_CON_BUSIF_HPMG3D_QCH,
|
|
QCH_CON_G3D_CMU_G3D_QCH,
|
|
QCH_CON_GPU_QCH,
|
|
QCH_CON_LHM_AXI_G3DSFR_QCH,
|
|
QCH_CON_LHM_AXI_P_G3D_QCH,
|
|
QCH_CON_LHS_ACE_D0_G3D_QCH,
|
|
QCH_CON_LHS_ACE_D1_G3D_QCH,
|
|
QCH_CON_LHS_ACE_D2_G3D_QCH,
|
|
QCH_CON_LHS_ACE_D3_G3D_QCH,
|
|
QCH_CON_LHS_AXI_G3DSFR_QCH,
|
|
QCH_CON_PGEN_LITE_G3D_QCH,
|
|
QCH_CON_SYSREG_G3D_QCH,
|
|
PLL_CON0_MUX_CLKCMU_ISPHQ_BUS_USER,
|
|
PLL_CON2_MUX_CLKCMU_ISPHQ_BUS_USER,
|
|
CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP,
|
|
CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT0,
|
|
CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT1,
|
|
QCH_CON_BTM_ISPHQ_QCH,
|
|
QCH_CON_ISPHQ_CMU_ISPHQ_QCH,
|
|
QCH_CON_IS_ISPHQ_QCH_ISPHQ,
|
|
QCH_CON_IS_ISPHQ_QCH_SYSMMU_ISPHQ,
|
|
QCH_CON_IS_ISPHQ_QCH_PPMU_ISPHQ,
|
|
QCH_CON_IS_ISPHQ_QCH_PGEN_LITE_ISPHQ,
|
|
QCH_CON_IS_ISPHQ_QCH_ISPHQ_C2COM,
|
|
QCH_CON_LHM_ATB_ISPLPISPHQ_QCH,
|
|
QCH_CON_LHM_ATB_ISPPREISPHQ_QCH,
|
|
QCH_CON_LHM_AXI_P_ISPHQ_QCH,
|
|
QCH_CON_LHS_ATB_ISPHQDCF_QCH,
|
|
QCH_CON_LHS_ATB_ISPHQISPLP_QCH,
|
|
QCH_CON_LHS_AXI_D_ISPHQ_QCH,
|
|
QCH_CON_SYSREG_ISPHQ_QCH,
|
|
PLL_CON0_MUX_CLKCMU_ISPLP_BUS_USER,
|
|
PLL_CON2_MUX_CLKCMU_ISPLP_BUS_USER,
|
|
CLK_CON_DIV_DIV_CLK_ISPLP_BUSP,
|
|
CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT0,
|
|
CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT1,
|
|
PLL_CON0_MUX_CLKCMU_ISPLP_VRA_USER,
|
|
PLL_CON2_MUX_CLKCMU_ISPLP_VRA_USER,
|
|
PLL_CON0_MUX_CLKCMU_ISPLP_GDC_USER,
|
|
PLL_CON2_MUX_CLKCMU_ISPLP_GDC_USER,
|
|
QCH_CON_BTM_ISPLP0_QCH,
|
|
QCH_CON_BTM_ISPLP1_QCH,
|
|
QCH_CON_ISPLP_CMU_ISPLP_QCH,
|
|
QCH_CON_IS_ISPLP_QCH_MC_SCALER,
|
|
QCH_CON_IS_ISPLP_QCH_ISPLP,
|
|
QCH_CON_IS_ISPLP_QCH_QE_ISPLP,
|
|
QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP0,
|
|
QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP0,
|
|
QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP1,
|
|
QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP1,
|
|
QCH_CON_IS_ISPLP_QCH_QE_VRA,
|
|
QCH_CON_IS_ISPLP_QCH_VRA,
|
|
QCH_CON_IS_ISPLP_QCH_GDC,
|
|
QCH_CON_IS_ISPLP_QCH_PGEN_LITE,
|
|
QCH_CON_IS_ISPLP_QCH_QE_GDC,
|
|
QCH_CON_IS_ISPLP_QCH_ISPLP_C2,
|
|
QCH_CON_LHM_ATB_DCFISPLP_QCH,
|
|
QCH_CON_LHM_ATB_DCRDISPLP_QCH,
|
|
QCH_CON_LHM_ATB_ISPHQISPLP_QCH,
|
|
QCH_CON_LHM_ATB_ISPPREISPLP_QCH,
|
|
QCH_CON_LHM_AXI_P_ISPLP_QCH,
|
|
QCH_CON_LHS_ATB_ISPLPISPHQ_QCH,
|
|
QCH_CON_LHS_AXI_D0_ISPLP_QCH,
|
|
QCH_CON_LHS_AXI_D1_ISPLP_QCH,
|
|
QCH_CON_SYSREG_ISPLP_QCH,
|
|
PLL_CON0_MUX_CLKCMU_ISPPRE_BUS_USER,
|
|
PLL_CON2_MUX_CLKCMU_ISPPRE_BUS_USER,
|
|
CLK_CON_DIV_DIV_CLK_ISPPRE_BUSP,
|
|
CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT0,
|
|
CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT1,
|
|
QCH_CON_BTM_ISPPRE_QCH,
|
|
QCH_CON_ISPPRE_CMU_ISPPRE_QCH,
|
|
QCH_CON_IS_ISPPRE_QCH_CSIS0,
|
|
QCH_CON_IS_ISPPRE_QCH_CSIS1,
|
|
QCH_CON_IS_ISPPRE_QCH_CSIS2,
|
|
QCH_CON_IS_ISPPRE_QCH_CSIS3,
|
|
QCH_CON_IS_ISPPRE_QCH_PPMU_ISPPRE,
|
|
QCH_CON_IS_ISPPRE_QCH_PDP_DMA,
|
|
QCH_CON_IS_ISPPRE_QCH_SYSMMU_ISPPRE,
|
|
QCH_CON_IS_ISPPRE_QCH_QE_PDP,
|
|
QCH_CON_IS_ISPPRE_QCH_QE_3AA,
|
|
QCH_CON_IS_ISPPRE_QCH_QE_3AAM,
|
|
QCH_CON_IS_ISPPRE_QCH_3AA,
|
|
QCH_CON_IS_ISPPRE_QCH_3AAM,
|
|
QCH_CON_IS_ISPPRE_QCH_PDP_CORE0,
|
|
QCH_CON_IS_ISPPRE_QCH_PDP_CORE1,
|
|
QCH_CON_IS_ISPPRE_QCH_PGEN_LITE,
|
|
QCH_CON_IS_ISPPRE_QCH_QE_PDP_STAT,
|
|
QCH_CON_IS_ISPPRE_QCH_PGEN_LITE1,
|
|
QCH_CON_LHM_AXI_P_ISPPRE_QCH,
|
|
QCH_CON_LHS_ATB_ISPPREISPHQ_QCH,
|
|
QCH_CON_LHS_ATB_ISPPREISPLP_QCH,
|
|
QCH_CON_LHS_AXI_D_ISPPRE_QCH,
|
|
QCH_CON_SYSREG_ISPPRE_QCH_SYSREG,
|
|
PLL_CON0_MUX_CLKCMU_IVA_BUS_USER,
|
|
PLL_CON2_MUX_CLKCMU_IVA_BUS_USER,
|
|
CLK_CON_DIV_DIV_CLK_IVA_BUSP,
|
|
CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK,
|
|
CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT0,
|
|
CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT1,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_PPMU_IVA_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA0_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_DIV_DIV_CLK_IVA_DEBUG,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_ADM_DAP_IVA_IPCLKPORT_DAPCLKM,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_DEBUG_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA1_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA2_IPCLKPORT_PCLKS,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_PGEN_LITE_IVA_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_TREX_RB_IVA_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_DAP_CLK,
|
|
DMYQCH_CON_ADM_DAP_IVA_QCH,
|
|
QCH_CON_BTM_IVA_QCH,
|
|
QCH_CON_IVA_QCH_IVA,
|
|
QCH_CON_IVA_QCH_IVA_DEBUG,
|
|
QCH_CON_IVA_CMU_IVA_QCH,
|
|
QCH_CON_IVA_INTMEM_QCH,
|
|
QCH_CON_LHM_AXI_D_DSPSIVA_QCH,
|
|
QCH_CON_LHM_AXI_D_IVASC_QCH,
|
|
QCH_CON_LHM_AXI_P_DSPMIVA_QCH,
|
|
QCH_CON_LHM_AXI_P_IVA_QCH,
|
|
QCH_CON_LHS_ACEL_D_IVA_QCH,
|
|
QCH_CON_LHS_AXI_D_IVADSPS_QCH,
|
|
QCH_CON_LHS_AXI_P_IVADSPM_QCH,
|
|
QCH_CON_PGEN_LITE_IVA_QCH,
|
|
QCH_CON_PPMU_IVA_QCH,
|
|
QCH_CON_SYSMMU_IVA_QCH,
|
|
QCH_CON_SYSREG_IVA_QCH,
|
|
QCH_CON_TREX_RB_IVA_QCH,
|
|
PLL_CON0_MUX_CLKCMU_MFC_BUS_USER,
|
|
PLL_CON2_MUX_CLKCMU_MFC_BUS_USER,
|
|
CLK_CON_DIV_DIV_CLK_MFC_BUSP,
|
|
CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT0,
|
|
CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT1,
|
|
PLL_CON0_MUX_CLKCMU_MFC_WFD_USER,
|
|
PLL_CON2_MUX_CLKCMU_MFC_WFD_USER,
|
|
QCH_CON_BTM_MFCD0_QCH,
|
|
QCH_CON_BTM_MFCD1_QCH,
|
|
QCH_CON_LHM_AXI_P_MFC_QCH,
|
|
QCH_CON_LHS_AXI_D0_MFC_QCH,
|
|
QCH_CON_LHS_AXI_D1_MFC_QCH,
|
|
QCH_CON_LH_ATB_QCH_MI,
|
|
QCH_CON_LH_ATB_QCH_SI,
|
|
QCH_CON_MFC_QCH,
|
|
QCH_CON_MFC_CMU_MFC_QCH,
|
|
QCH_CON_PGEN100_LITE_MFC_QCH,
|
|
QCH_CON_PPMU_MFCD0_QCH,
|
|
QCH_CON_PPMU_MFCD1_QCH,
|
|
QCH_CON_PPMU_MFCD2_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MI_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_SI_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH,
|
|
QCH_CON_RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH,
|
|
QCH_CON_SYSMMU_MFCD0_QCH,
|
|
QCH_CON_SYSMMU_MFCD1_QCH,
|
|
QCH_CON_SYSREG_MFC_QCH,
|
|
QCH_CON_WFD_QCH,
|
|
PLL_CON0_PLL_MIF,
|
|
PLL_LOCKTIME_PLL_MIF,
|
|
CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X,
|
|
CLK_CON_DIV_CLK_MIF_BUSD,
|
|
CLK_CON_DIV_DIV_CLK_MIF_PRE,
|
|
CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT0,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C,
|
|
CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT1,
|
|
CLK_CON_MUX_MUX_MIF_CMUREF,
|
|
PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER,
|
|
PLL_CON2_MUX_CLKCMU_MIF_BUSP_USER,
|
|
QCH_CON_APBBR_DDRPHY_QCH,
|
|
QCH_CON_APBBR_DMC_QCH,
|
|
QCH_CON_APBBR_DMCTZ_QCH,
|
|
QCH_CON_BUSIF_HPMMIF_QCH,
|
|
DMYQCH_CON_CMU_MIF_CMUREF_QCH,
|
|
QCH_CON_DMC_QCH,
|
|
QCH_CON_LHM_AXI_P_MIF_QCH,
|
|
QCH_CON_MIF_CMU_MIF_QCH,
|
|
QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG_QCH,
|
|
QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS_QCH,
|
|
QCH_CON_SYSREG_MIF_QCH,
|
|
PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER,
|
|
PLL_CON2_MUX_CLKCMU_PERIC0_BUS_USER,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P0_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
|
|
CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0,
|
|
CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT1,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_XIU_P_PERIC0_IPCLKPORT_ACLK,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_I2C_IPCLKPORT_CLK,
|
|
PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER,
|
|
PLL_CON2_MUX_CLKCMU_PERIC0_IP_USER,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI00_USI,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI01_USI,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI02_USI,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI03_USI,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI04_USI,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI05_USI,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI_I2C,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_UART_DBG,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI12_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI12_USI,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI13_USI,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI14_USI,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_IPCLK,
|
|
QCH_CON_GPIO_PERIC0_QCH,
|
|
QCH_CON_LHM_AXI_P_PERIC0_QCH,
|
|
QCH_CON_PERIC0_CMU_PERIC0_QCH,
|
|
QCH_CON_PWM_QCH,
|
|
QCH_CON_SYSREG_PERIC0_QCH,
|
|
QCH_CON_UART_DBG_QCH,
|
|
QCH_CON_USI00_I2C_QCH,
|
|
QCH_CON_USI00_USI_QCH,
|
|
QCH_CON_USI01_I2C_QCH,
|
|
QCH_CON_USI01_USI_QCH,
|
|
QCH_CON_USI02_I2C_QCH,
|
|
QCH_CON_USI02_USI_QCH,
|
|
QCH_CON_USI03_I2C_QCH,
|
|
QCH_CON_USI03_USI_QCH,
|
|
QCH_CON_USI04_I2C_QCH,
|
|
QCH_CON_USI04_USI_QCH,
|
|
QCH_CON_USI05_I2C_QCH,
|
|
QCH_CON_USI05_USI_QCH,
|
|
QCH_CON_USI12_I2C_QCH,
|
|
QCH_CON_USI12_USI_QCH,
|
|
QCH_CON_USI13_I2C_QCH,
|
|
QCH_CON_USI13_USI_QCH,
|
|
QCH_CON_USI14_I2C_QCH,
|
|
QCH_CON_USI14_USI_QCH,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK,
|
|
PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER,
|
|
PLL_CON2_MUX_CLKCMU_PERIC1_BUS_USER,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
|
|
CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_PCLK,
|
|
CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT1,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPI_CAM0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM0_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM1_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM2_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM3_IPCLKPORT_CLK,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM0,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM1,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM2,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM3,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_SPI_CAM0,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_I2C_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_I2C_IPCLKPORT_CLK,
|
|
PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER,
|
|
PLL_CON2_MUX_CLKCMU_PERIC1_IP_USER,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_UART_BT,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI_I2C,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI06_USI,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI07_USI,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI08_USI,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM0,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM1,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM2,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM3,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_SPI_CAM0,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI09_USI,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI10_USI,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI11_USI,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_IPCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_I2C_IPCLKPORT_CLK,
|
|
QCH_CON_GPIO_PERIC1_QCH,
|
|
QCH_CON_I2C_CAM0_QCH,
|
|
QCH_CON_I2C_CAM1_QCH,
|
|
QCH_CON_I2C_CAM2_QCH,
|
|
QCH_CON_I2C_CAM3_QCH,
|
|
QCH_CON_LHM_AXI_P_PERIC1_QCH,
|
|
QCH_CON_PERIC1_CMU_PERIC1_QCH,
|
|
QCH_CON_SPI_CAM0_QCH,
|
|
QCH_CON_SYSREG_PERIC1_QCH,
|
|
QCH_CON_UART_BT_QCH,
|
|
QCH_CON_USI06_I2C_QCH,
|
|
QCH_CON_USI06_USI_QCH,
|
|
QCH_CON_USI07_I2C_QCH,
|
|
QCH_CON_USI07_USI_QCH,
|
|
QCH_CON_USI08_I2C_QCH,
|
|
QCH_CON_USI08_USI_QCH,
|
|
QCH_CON_USI09_I2C_QCH,
|
|
QCH_CON_USI09_USI_QCH,
|
|
QCH_CON_USI10_I2C_QCH,
|
|
QCH_CON_USI10_USI_QCH,
|
|
QCH_CON_USI11_I2C_QCH,
|
|
QCH_CON_USI11_USI_QCH,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK,
|
|
PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER,
|
|
PLL_CON2_MUX_CLKCMU_PERIS_BUS_USER,
|
|
CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT0,
|
|
CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT1,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK,
|
|
CLK_CON_MUX_MUX_CLK_PERIS_GIC,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
|
|
QCH_CON_BUSIF_TMU_QCH,
|
|
QCH_CON_GIC_QCH,
|
|
QCH_CON_LHM_AXI_P_PERIS_QCH,
|
|
QCH_CON_MCT_QCH,
|
|
QCH_CON_OTP_CON_BIRA_QCH,
|
|
QCH_CON_OTP_CON_TOP_QCH,
|
|
QCH_CON_PERIS_CMU_PERIS_QCH,
|
|
QCH_CON_SYSREG_PERIS_QCH,
|
|
QCH_CON_WDT_CLUSTER0_QCH,
|
|
QCH_CON_WDT_CLUSTER1_QCH,
|
|
PLL_CON0_PLL_MIF_S2D,
|
|
PLL_LOCKTIME_PLL_MIF_S2D,
|
|
CLK_CON_MUX_CLKCMU_MIF_DDRPHY2X_S2D,
|
|
CLK_CON_DIV_CLK_MIF_BUSD_S2D,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK,
|
|
CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK,
|
|
CLK_CON_MUX_MUX_CLK_S2D_CORE,
|
|
QCH_CON_S2D_CMU_S2D_QCH,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC,
|
|
CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT0,
|
|
CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT1,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_CLK,
|
|
PLL_CON0_MUX_CLKCMU_VTS_BUS_USER,
|
|
PLL_CON2_MUX_CLKCMU_VTS_BUS_USER,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_DIV2_CLK,
|
|
PLL_CON0_MUX_CLKCMU_VTS_DLL_USER,
|
|
PLL_CON2_MUX_CLKCMU_VTS_DLL_USER,
|
|
CLK_CON_MUX_MUX_CLK_VTS_BUS,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IPCLKPORT_CLK,
|
|
CLK_CON_DIV_DIV_CLK_VTS_BUS,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_MUX_IPCLKPORT_D0,
|
|
QCH_CON_AHB_BUSMATRIX_QCH_SYS,
|
|
QCH_CON_ASYNCAHBM_VTS_QCH,
|
|
QCH_CON_CORTEXM4INTEGRATION_QCH_CPU,
|
|
QCH_CON_DMIC_AHB0_QCH_PCLK,
|
|
QCH_CON_DMIC_AHB1_QCH_PCLK,
|
|
QCH_CON_DMIC_IF_QCH_PCLK,
|
|
DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK,
|
|
QCH_CON_GPIO_VTS_QCH,
|
|
QCH_CON_HWACG_SYS_DMIC0_QCH,
|
|
QCH_CON_HWACG_SYS_DMIC1_QCH,
|
|
QCH_CON_MAILBOX_VTS2CHUB_QCH,
|
|
QCH_CON_SYSREG_VTS_QCH,
|
|
QCH_CON_VTS_CMU_VTS_QCH,
|
|
QCH_CON_WDT_VTS_QCH,
|
|
DMYQCH_CON_U_DMIC_CLK_MUX_QCH,
|
|
/*====================The section of controller option SFR===================*/
|
|
APM_CMU_APM_CONTROLLER_OPTION,
|
|
AUD_CMU_AUD_CONTROLLER_OPTION,
|
|
BUS1_CMU_BUS1_CONTROLLER_OPTION,
|
|
BUSC_CMU_BUSC_CONTROLLER_OPTION,
|
|
CHUB_CMU_CHUB_CONTROLLER_OPTION,
|
|
CMGP_CMU_CMGP_CONTROLLER_OPTION,
|
|
CMU_CMU_CMU_CONTROLLER_OPTION,
|
|
CORE_CMU_CORE_CONTROLLER_OPTION,
|
|
CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION,
|
|
CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION,
|
|
DCF_CMU_DCF_CONTROLLER_OPTION,
|
|
DCPOST_CMU_DCPOST_CONTROLLER_OPTION,
|
|
DCRD_CMU_DCRD_CONTROLLER_OPTION,
|
|
DPU_CMU_DPU_CONTROLLER_OPTION,
|
|
DSPM_CMU_DSPM_CONTROLLER_OPTION,
|
|
DSPS_CMU_DSPS_CONTROLLER_OPTION,
|
|
FSYS0_CMU_FSYS0_CONTROLLER_OPTION,
|
|
FSYS1_CMU_FSYS1_CONTROLLER_OPTION,
|
|
G2D_CMU_G2D_CONTROLLER_OPTION,
|
|
G3D_CMU_G3D_CONTROLLER_OPTION,
|
|
ISPHQ_CMU_ISPHQ_CONTROLLER_OPTION,
|
|
ISPLP_CMU_ISPLP_CONTROLLER_OPTION,
|
|
ISPPRE_CMU_ISPPRE_CONTROLLER_OPTION,
|
|
IVA_CMU_IVA_CONTROLLER_OPTION,
|
|
MFC_CMU_MFC_CONTROLLER_OPTION,
|
|
MIF_CMU_MIF_CONTROLLER_OPTION,
|
|
PERIC0_CMU_PERIC0_CONTROLLER_OPTION,
|
|
PERIC1_CMU_PERIC1_CONTROLLER_OPTION,
|
|
PERIS_CMU_PERIS_CONTROLLER_OPTION,
|
|
S2D_CMU_S2D_CONTROLLER_OPTION,
|
|
VTS_CMU_VTS_CONTROLLER_OPTION,
|
|
end_of_sfr,
|
|
num_of_sfr = end_of_sfr - SFR_TYPE,
|
|
};
|
|
|
|
/*====================The section of SFR access===================*/
|
|
enum sfr_access_id {
|
|
PLL_CON0_MUX_CLKCMU_APM_BUS_USER_BUSY = SFR_ACCESS_TYPE,
|
|
PLL_CON0_MUX_CLKCMU_APM_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_APM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLKCMU_APM_DLL_CHUB_CG_VAL,
|
|
CLK_CON_GAT_CLKCMU_APM_DLL_CHUB_MANUAL,
|
|
CLK_CON_GAT_CLKCMU_APM_DLL_CHUB_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_APM_DLL_VTS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_APM_DLL_VTS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_APM_DLL_VTS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_APM_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_APM_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_APM_BUS_SELECT,
|
|
CLK_CON_DIV_CLKCMU_APM_DLL_CMGP_BUSY,
|
|
CLK_CON_DIV_CLKCMU_APM_DLL_CMGP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_APM_DLL_CMGP_DIVRATIO,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CHUB_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CHUB_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CHUB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CHUB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CHUB2CP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CHUB2CP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CHUB2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CHUB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CHUB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_P_APM2CMGP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_P_APM2CMGP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_P_APM2CMGP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_DLL_USER_BUSY,
|
|
PLL_CON0_MUX_DLL_USER_MUX_SEL,
|
|
PLL_CON2_MUX_DLL_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_APM_DLL_CMGP_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_APM_DLL_CMGP_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_APM_DLL_CMGP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_APM_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_APM_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_APM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_CHUB_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_CHUB_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_APM_DLL_VTS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_APM_DLL_VTS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_APM_DLL_VTS_DIVRATIO,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_APM_BUS_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_APM_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_APM_BUS_DIVRATIO,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CHUB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CHUB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2VTS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2VTS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_APBIF_GPIO_ALIVE_QCH_ENABLE,
|
|
QCH_CON_APBIF_GPIO_ALIVE_QCH_CLOCK_REQ,
|
|
QCH_CON_APBIF_GPIO_ALIVE_QCH_EXPIRE_VAL,
|
|
QCH_CON_APBIF_GPIO_ALIVE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APBIF_PMU_ALIVE_QCH_ENABLE,
|
|
QCH_CON_APBIF_PMU_ALIVE_QCH_CLOCK_REQ,
|
|
QCH_CON_APBIF_PMU_ALIVE_QCH_EXPIRE_VAL,
|
|
QCH_CON_APBIF_PMU_ALIVE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APBIF_RTC_QCH_ENABLE,
|
|
QCH_CON_APBIF_RTC_QCH_CLOCK_REQ,
|
|
QCH_CON_APBIF_RTC_QCH_EXPIRE_VAL,
|
|
QCH_CON_APBIF_RTC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APBIF_TOP_RTC_QCH_ENABLE,
|
|
QCH_CON_APBIF_TOP_RTC_QCH_CLOCK_REQ,
|
|
QCH_CON_APBIF_TOP_RTC_QCH_EXPIRE_VAL,
|
|
QCH_CON_APBIF_TOP_RTC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APM_CMU_APM_QCH_ENABLE,
|
|
QCH_CON_APM_CMU_APM_QCH_CLOCK_REQ,
|
|
QCH_CON_APM_CMU_APM_QCH_EXPIRE_VAL,
|
|
QCH_CON_APM_CMU_APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GREBEINTEGRATION_QCH_GREBE_ENABLE,
|
|
QCH_CON_GREBEINTEGRATION_QCH_GREBE_CLOCK_REQ,
|
|
QCH_CON_GREBEINTEGRATION_QCH_GREBE_EXPIRE_VAL,
|
|
QCH_CON_GREBEINTEGRATION_QCH_GREBE_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GREBEINTEGRATION_QCH_DBG_ENABLE,
|
|
QCH_CON_GREBEINTEGRATION_QCH_DBG_CLOCK_REQ,
|
|
QCH_CON_GREBEINTEGRATION_QCH_DBG_EXPIRE_VAL,
|
|
QCH_CON_GREBEINTEGRATION_QCH_DBG_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_INTMEM_QCH_ENABLE,
|
|
QCH_CON_INTMEM_QCH_CLOCK_REQ,
|
|
QCH_CON_INTMEM_QCH_EXPIRE_VAL,
|
|
QCH_CON_INTMEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_APM_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_APM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_APM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_APM_CHUB_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_APM_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_APM_CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_APM_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_APM_CP_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_APM_CP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_APM_CP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_APM_CP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_APM_GNSS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_APM_GNSS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_APM_GNSS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_APM_GNSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_APM_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_APM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_APM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_LP_CHUB_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_LP_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_LP_CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_LP_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_APM2CMGP_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_APM2CMGP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_APM2CMGP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_APM2CMGP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_AP2CHUB_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_AP2CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_AP2CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_AP2CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_AP2CP_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_AP2CP_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_AP2CP_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_AP2CP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_AP2CP_S_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_AP2CP_S_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_AP2CP_S_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_AP2CP_S_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_AP2GNSS_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_AP2GNSS_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_AP2GNSS_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_AP2GNSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_AP2VTS_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_AP2VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_AP2VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_AP2VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_APM2AP_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_APM2AP_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_APM2AP_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_APM2AP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_APM2CHUB_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_APM2CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_APM2CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_APM2CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_APM2CP_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_APM2CP_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_APM2CP_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_APM2CP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_APM2GNSS_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_APM2GNSS_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_APM2GNSS_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_APM2GNSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_CHUB2CP_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_CHUB2CP_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_CHUB2CP_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_CHUB2CP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_GNSS2CHUB_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_GNSS2CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_GNSS2CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_GNSS2CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_GNSS2CP_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_GNSS2CP_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_GNSS2CP_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_GNSS2CP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PEM_QCH_ENABLE,
|
|
QCH_CON_PEM_QCH_CLOCK_REQ,
|
|
QCH_CON_PEM_QCH_EXPIRE_VAL,
|
|
QCH_CON_PEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PGEN_APM_QCH_ENABLE,
|
|
QCH_CON_PGEN_APM_QCH_CLOCK_REQ,
|
|
QCH_CON_PGEN_APM_QCH_EXPIRE_VAL,
|
|
QCH_CON_PGEN_APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PMU_INTR_GEN_QCH_ENABLE,
|
|
QCH_CON_PMU_INTR_GEN_QCH_CLOCK_REQ,
|
|
QCH_CON_PMU_INTR_GEN_QCH_EXPIRE_VAL,
|
|
QCH_CON_PMU_INTR_GEN_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SPEEDY_APM_QCH_ENABLE,
|
|
QCH_CON_SPEEDY_APM_QCH_CLOCK_REQ,
|
|
QCH_CON_SPEEDY_APM_QCH_EXPIRE_VAL,
|
|
QCH_CON_SPEEDY_APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SPEEDY_SUB_APM_QCH_ENABLE,
|
|
QCH_CON_SPEEDY_SUB_APM_QCH_CLOCK_REQ,
|
|
QCH_CON_SPEEDY_SUB_APM_QCH_EXPIRE_VAL,
|
|
QCH_CON_SPEEDY_SUB_APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_APM_QCH_ENABLE,
|
|
QCH_CON_SYSREG_APM_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_APM_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WDT_APM_QCH_ENABLE,
|
|
QCH_CON_WDT_APM_QCH_CLOCK_REQ,
|
|
QCH_CON_WDT_APM_QCH_EXPIRE_VAL,
|
|
QCH_CON_WDT_APM_QCH_IGNORE_FORCE_PM_EN,
|
|
PLL_CON0_PLL_AUD_DIV_P,
|
|
PLL_CON0_PLL_AUD_DIV_M,
|
|
PLL_CON0_PLL_AUD_DIV_S,
|
|
PLL_CON0_PLL_AUD_ENABLE,
|
|
PLL_CON0_PLL_AUD_STABLE,
|
|
PLL_CON3_PLL_AUD_DIV_K,
|
|
PLL_LOCKTIME_PLL_AUD_PLL_LOCK_TIME,
|
|
CLK_CON_DIV_DIV_CLK_AUD_PLL_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_PLL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_PLL_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_AUDIF_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_AUDIF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_AUDIF_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_ATCLK_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_ATCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_ATCLK_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_DSIF_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_DSIF_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF0_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF0_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF1_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF1_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF2_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF2_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF3_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_UAIF3_DIVRATIO,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF3_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF3_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF2_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF2_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF1_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF1_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF0_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_UAIF0_SELECT,
|
|
PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_AUD_CPU_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_CPU_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_AUD_CPU_SELECT,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_ATB_AUD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_ATB_AUD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_ATB_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ATCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ATCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_AUD_BUS_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_BUS_DIVRATIO,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_BUSP_DIVRATIO,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_DMIC_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_AUD_DMIC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_AUD_DMIC_DIVRATIO,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ATB_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ATB_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ATB_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_DAP_IPCLKPORT_DAPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_DAP_IPCLKPORT_DAPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_DAP_IPCLKPORT_DAPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_BUSY,
|
|
CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_SELECT,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_XIU_P_AUD_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_XIU_P_AUD_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_XIU_P_AUD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI2APB_AUD_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI2APB_AUD_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI2APB_AUD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_ABOX_QCH_ACLK_ENABLE,
|
|
QCH_CON_ABOX_QCH_ACLK_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_ACLK_EXPIRE_VAL,
|
|
QCH_CON_ABOX_QCH_ACLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_BCLK_DSIF_ENABLE,
|
|
QCH_CON_ABOX_QCH_BCLK_DSIF_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_BCLK_DSIF_EXPIRE_VAL,
|
|
QCH_CON_ABOX_QCH_BCLK_DSIF_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_BCLK0_ENABLE,
|
|
QCH_CON_ABOX_QCH_BCLK0_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_BCLK0_EXPIRE_VAL,
|
|
QCH_CON_ABOX_QCH_BCLK0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_BCLK1_ENABLE,
|
|
QCH_CON_ABOX_QCH_BCLK1_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_BCLK1_EXPIRE_VAL,
|
|
QCH_CON_ABOX_QCH_BCLK1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_BCLK2_ENABLE,
|
|
QCH_CON_ABOX_QCH_BCLK2_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_BCLK2_EXPIRE_VAL,
|
|
QCH_CON_ABOX_QCH_BCLK2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_BCLK3_ENABLE,
|
|
QCH_CON_ABOX_QCH_BCLK3_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_BCLK3_EXPIRE_VAL,
|
|
QCH_CON_ABOX_QCH_BCLK3_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ABOX_QCH_DUMMY_ENABLE,
|
|
DMYQCH_CON_ABOX_QCH_DUMMY_CLOCK_REQ,
|
|
DMYQCH_CON_ABOX_QCH_DUMMY_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_CCLK_ASB_ENABLE,
|
|
QCH_CON_ABOX_QCH_CCLK_ASB_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_CCLK_ASB_EXPIRE_VAL,
|
|
QCH_CON_ABOX_QCH_CCLK_ASB_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ABOX_QCH_CCLK_ATB_ENABLE,
|
|
QCH_CON_ABOX_QCH_CCLK_ATB_CLOCK_REQ,
|
|
QCH_CON_ABOX_QCH_CCLK_ATB_EXPIRE_VAL,
|
|
QCH_CON_ABOX_QCH_CCLK_ATB_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_AUD_CMU_AUD_QCH_ENABLE,
|
|
QCH_CON_AUD_CMU_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_AUD_CMU_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_AUD_CMU_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BTM_AUD_QCH_ENABLE,
|
|
QCH_CON_BTM_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_BTM_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_BTM_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DFTMUX_AUD_QCH_ENABLE,
|
|
DMYQCH_CON_DFTMUX_AUD_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_DFTMUX_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DMIC_QCH_ENABLE,
|
|
DMYQCH_CON_DMIC_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_DMIC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GPIO_AUD_QCH_ENABLE,
|
|
QCH_CON_GPIO_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_GPIO_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_GPIO_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_AUD_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_AUD_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_AUD_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_AUD_QCH_ENABLE,
|
|
QCH_CON_PPMU_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_AUD_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_AUD_QCH_ENABLE,
|
|
QCH_CON_SYSREG_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_AUD_QCH_ENABLE,
|
|
QCH_CON_TREX_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_TREX_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WDT_AUD_QCH_ENABLE,
|
|
QCH_CON_WDT_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_WDT_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_WDT_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_BUS1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUS_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUS_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_CHUB_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_CHUB_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_BUS1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_BUS1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_BUS1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CHUB_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CHUB_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CSSYS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CSSYS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_CHUB_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_CHUB_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_CHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D_BUS1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D_BUS1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D_BUS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_BAAW_P_CHUB_QCH_ENABLE,
|
|
QCH_CON_BAAW_P_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_BAAW_P_CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_BAAW_P_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BAAW_P_GNSS_QCH_ENABLE,
|
|
QCH_CON_BAAW_P_GNSS_QCH_CLOCK_REQ,
|
|
QCH_CON_BAAW_P_GNSS_QCH_EXPIRE_VAL,
|
|
QCH_CON_BAAW_P_GNSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUS1_CMU_BUS1_QCH_ENABLE,
|
|
QCH_CON_BUS1_CMU_BUS1_QCH_CLOCK_REQ,
|
|
QCH_CON_BUS1_CMU_BUS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUS1_CMU_BUS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_APM_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_APM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_APM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_CHUB_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_GNSS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_GNSS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_GNSS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_GNSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_G_CSSYS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_G_CSSYS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_G_CSSYS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_BUS1_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_BUS1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_BUS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_BUS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_CHUB_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_CSSYS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_CSSYS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_CSSYS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_CSSYS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_GNSS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_GNSS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_GNSS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_GNSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_BUS1_QCH_ENABLE,
|
|
QCH_CON_SYSREG_BUS1_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_BUS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_BUS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_P_BUS1_QCH_ENABLE,
|
|
QCH_CON_TREX_P_BUS1_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_P_BUS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_TREX_P_BUS1_QCH_IGNORE_FORCE_PM_EN,
|
|
CLK_CON_DIV_DIV_CLK_BUSC_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_BUSC_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_BUSC_BUSP_DIVRATIO,
|
|
PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_BUSC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_BUSC_UID_HPM_BUSC_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_BUSC_UID_HPM_BUSC_IPCLKPORT_HPM_TARGETCLK_C_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_BUSC_UID_HPM_BUSC_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_BUSC_CMU_BUSC_QCH_ENABLE,
|
|
QCH_CON_BUSC_CMU_BUSC_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSC_CMU_BUSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSC_CMU_BUSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_CMUTOPC_QCH_ENABLE,
|
|
QCH_CON_BUSIF_CMUTOPC_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_CMUTOPC_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_CMUTOPC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_HPMBUSC_QCH_ENABLE,
|
|
QCH_CON_BUSIF_HPMBUSC_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_HPMBUSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_HPMBUSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACEL_D0_DSPM_QCH_ENABLE,
|
|
QCH_CON_LHM_ACEL_D0_DSPM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACEL_D0_DSPM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACEL_D0_DSPM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACEL_D0_G2D_QCH_ENABLE,
|
|
QCH_CON_LHM_ACEL_D0_G2D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACEL_D0_G2D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACEL_D0_G2D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACEL_D1_DSPM_QCH_ENABLE,
|
|
QCH_CON_LHM_ACEL_D1_DSPM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACEL_D1_DSPM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACEL_D1_DSPM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACEL_D1_G2D_QCH_ENABLE,
|
|
QCH_CON_LHM_ACEL_D1_G2D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACEL_D1_G2D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACEL_D1_G2D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACEL_D2_DSPM_QCH_ENABLE,
|
|
QCH_CON_LHM_ACEL_D2_DSPM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACEL_D2_DSPM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACEL_D2_DSPM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACEL_D2_G2D_QCH_ENABLE,
|
|
QCH_CON_LHM_ACEL_D2_G2D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACEL_D2_G2D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACEL_D2_G2D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACEL_D_FSYS0_QCH_ENABLE,
|
|
QCH_CON_LHM_ACEL_D_FSYS0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACEL_D_FSYS0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACEL_D_FSYS0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACEL_D_FSYS1_QCH_ENABLE,
|
|
QCH_CON_LHM_ACEL_D_FSYS1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACEL_D_FSYS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACEL_D_FSYS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACEL_D_IVA_QCH_ENABLE,
|
|
QCH_CON_LHM_ACEL_D_IVA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACEL_D_IVA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACEL_D_IVA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D0_DPU_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D0_DPU_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D0_DPU_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D0_DPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D0_ISPLP_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D0_ISPLP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D0_ISPLP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D0_ISPLP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D0_MFC_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D0_MFC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D0_MFC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D0_MFC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D1_DPU_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D1_DPU_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D1_DPU_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D1_DPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D1_ISPLP_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D1_ISPLP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D1_ISPLP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D1_ISPLP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D1_MFC_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D1_MFC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D1_MFC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D1_MFC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D2_DPU_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D2_DPU_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D2_DPU_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D2_DPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_AUD_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_BUS1_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_BUS1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_BUS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_BUS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_DCF_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_DCF_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_DCF_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_DCF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_DCRD_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_DCRD_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_DCRD_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_DCRD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_ISPHQ_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_ISPHQ_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_ISPHQ_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_ISPHQ_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_ISPPRE_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_ISPPRE_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_ISPPRE_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_ISPPRE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_IVASC_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_IVASC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_IVASC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_IVASC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_AUD_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_DCF_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_DCF_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_DCF_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_DCF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_DCRD_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_DCRD_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_DCRD_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_DCRD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_DPU_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_DPU_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_DPU_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_DPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_DSPM_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_DSPM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_DSPM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_DSPM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_FSYS0_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_FSYS0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_FSYS0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_FSYS0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_FSYS1_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_FSYS1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_FSYS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_FSYS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_G2D_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_G2D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_G2D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_G2D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_ISPHQ_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_ISPHQ_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_ISPHQ_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_ISPHQ_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_ISPLP_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_ISPLP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_ISPLP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_ISPLP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_ISPPRE_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_ISPPRE_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_ISPPRE_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_ISPPRE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_IVA_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_IVA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_IVA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_IVA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_MFC_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_MFC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_MFC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_MFC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_MIF0_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_MIF0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_MIF0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_MIF0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_MIF1_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_MIF1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_MIF1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_MIF1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_MIF2_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_MIF2_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_MIF2_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_MIF2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_MIF3_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_MIF3_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_MIF3_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_MIF3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_PERIC0_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_PERIC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_PERIC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_PERIC1_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_PERIC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_PERIC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_PERIS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_PERIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_PERIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_PERIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PDMA0_QCH_ENABLE,
|
|
QCH_CON_PDMA0_QCH_CLOCK_REQ,
|
|
QCH_CON_PDMA0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PDMA0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PGEN_LITE_BUSC_QCH_ENABLE,
|
|
QCH_CON_PGEN_LITE_BUSC_QCH_CLOCK_REQ,
|
|
QCH_CON_PGEN_LITE_BUSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_PGEN_LITE_BUSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PGEN_PDMA0_QCH_ENABLE,
|
|
QCH_CON_PGEN_PDMA0_QCH_CLOCK_REQ,
|
|
QCH_CON_PGEN_PDMA0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PGEN_PDMA0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPFW_QCH_ENABLE,
|
|
QCH_CON_PPFW_QCH_CLOCK_REQ,
|
|
QCH_CON_PPFW_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPFW_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SBIC_QCH_ENABLE,
|
|
QCH_CON_SBIC_QCH_CLOCK_REQ,
|
|
QCH_CON_SBIC_QCH_EXPIRE_VAL,
|
|
QCH_CON_SBIC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SIREX_QCH_ENABLE,
|
|
QCH_CON_SIREX_QCH_CLOCK_REQ,
|
|
QCH_CON_SIREX_QCH_EXPIRE_VAL,
|
|
QCH_CON_SIREX_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SPDMA_QCH_ENABLE,
|
|
QCH_CON_SPDMA_QCH_CLOCK_REQ,
|
|
QCH_CON_SPDMA_QCH_EXPIRE_VAL,
|
|
QCH_CON_SPDMA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_BUSC_QCH_ENABLE,
|
|
QCH_CON_SYSREG_BUSC_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_BUSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_BUSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_D_BUSC_QCH_ENABLE,
|
|
QCH_CON_TREX_D_BUSC_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_D_BUSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_TREX_D_BUSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_P_BUSC_QCH_ENABLE,
|
|
QCH_CON_TREX_P_BUSC_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_P_BUSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_TREX_P_BUSC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_RB_BUSC_QCH_ENABLE,
|
|
QCH_CON_TREX_RB_BUSC_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_RB_BUSC_QCH_EXPIRE_VAL,
|
|
QCH_CON_TREX_RB_BUSC_QCH_IGNORE_FORCE_PM_EN,
|
|
PLL_CON0_MUX_CLKCMU_CHUB_BUS_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_CHUB_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_CHUB_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_CHUB_DLL_BUS_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_CHUB_DLL_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_CHUB_DLL_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_BUS_SELECT,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_USI01_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_USI01_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_USI01_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_I2C_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_I2C_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_USI00_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_USI00_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_USI00_DIVRATIO,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI00_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI00_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI00_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI01_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI01_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI01_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_I2C_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_I2C_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_USI00_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_USI00_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_USI00_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_USI01_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_USI01_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CHUB_USI01_SELECT,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_BUS_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CHUB_BUS_DIVRATIO,
|
|
CLK_CON_GAT_GATE_CLK_CHUB_I2C_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_CHUB_I2C_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_CHUB_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_CHUB_USI00_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_CHUB_USI00_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_CHUB_USI00_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_CHUB_USI01_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_CHUB_USI01_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_CHUB_USI01_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLK_CHUB_TIMER_FCLK_BUSY,
|
|
CLK_CON_MUX_CLK_CHUB_TIMER_FCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLK_CHUB_TIMER_FCLK_SELECT,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB00_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB00_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB01_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB01_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB01_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB00_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB00_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB01_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB01_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB01_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_ASYNCAHBM_CHUB_QCH_ENABLE,
|
|
QCH_CON_ASYNCAHBM_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_ASYNCAHBM_CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_ASYNCAHBM_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BAAW_D_CHUB_QCH_ENABLE,
|
|
QCH_CON_BAAW_D_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_BAAW_D_CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_BAAW_D_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BAAW_P_APM_CHUB_QCH_ENABLE,
|
|
QCH_CON_BAAW_P_APM_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_BAAW_P_APM_CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_BAAW_P_APM_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BAAW_S_CHUB_QCH_ENABLE,
|
|
QCH_CON_BAAW_S_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_BAAW_S_CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_BAAW_S_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CHUB_CMU_CHUB_QCH_ENABLE,
|
|
QCH_CON_CHUB_CMU_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_CHUB_CMU_CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_CHUB_CMU_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CM4_CHUB_QCH_ENABLE,
|
|
QCH_CON_CM4_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_CM4_CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_CM4_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GPIO_CHUB_QCH_ENABLE,
|
|
QCH_CON_GPIO_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_GPIO_CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_GPIO_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I2C_CHUB00_QCH_ENABLE,
|
|
QCH_CON_I2C_CHUB00_QCH_CLOCK_REQ,
|
|
QCH_CON_I2C_CHUB00_QCH_EXPIRE_VAL,
|
|
QCH_CON_I2C_CHUB00_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I2C_CHUB01_QCH_ENABLE,
|
|
QCH_CON_I2C_CHUB01_QCH_CLOCK_REQ,
|
|
QCH_CON_I2C_CHUB01_QCH_EXPIRE_VAL,
|
|
QCH_CON_I2C_CHUB01_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_LP_CHUB_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_LP_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_LP_CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_LP_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_CHUB_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_CHUB_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_APM_CHUB_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_APM_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_APM_CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_APM_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PDMA_CHUB_QCH_ENABLE,
|
|
QCH_CON_PDMA_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_PDMA_CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_PDMA_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PWM_CHUB_QCH_ENABLE,
|
|
QCH_CON_PWM_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_PWM_CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_PWM_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SWEEPER_D_CHUB_QCH_ENABLE,
|
|
QCH_CON_SWEEPER_D_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_SWEEPER_D_CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_SWEEPER_D_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SWEEPER_P_APM_CHUB_QCH_ENABLE,
|
|
QCH_CON_SWEEPER_P_APM_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_SWEEPER_P_APM_CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_SWEEPER_P_APM_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CHUB_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TIMER_CHUB_QCH_ENABLE,
|
|
QCH_CON_TIMER_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_TIMER_CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_TIMER_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI_CHUB00_QCH_ENABLE,
|
|
QCH_CON_USI_CHUB00_QCH_CLOCK_REQ,
|
|
QCH_CON_USI_CHUB00_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI_CHUB00_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI_CHUB01_QCH_ENABLE,
|
|
QCH_CON_USI_CHUB01_QCH_CLOCK_REQ,
|
|
QCH_CON_USI_CHUB01_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI_CHUB01_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WDT_CHUB_QCH_ENABLE,
|
|
QCH_CON_WDT_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_WDT_CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_WDT_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_CMGP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_I2C_CMGP_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_I2C_CMGP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_I2C_CMGP_SELECT,
|
|
CLK_CON_DIV_DIV_CLK_I2C_CMGP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_I2C_CMGP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_I2C_CMGP_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_USI_CMGP01_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_USI_CMGP01_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_USI_CMGP01_DIVRATIO,
|
|
CLK_CON_MUX_MUX_CLK_USI_CMGP00_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_USI_CMGP00_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_USI_CMGP00_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_USI_CMGP01_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_USI_CMGP01_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_USI_CMGP01_SELECT,
|
|
CLK_CON_DIV_DIV_CLK_USI_CMGP00_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_USI_CMGP00_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_USI_CMGP00_DIVRATIO,
|
|
CLK_CON_MUX_MUX_CLK_USI_CMGP02_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_USI_CMGP02_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_USI_CMGP02_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_USI_CMGP03_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_USI_CMGP03_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_USI_CMGP03_SELECT,
|
|
CLK_CON_DIV_DIV_CLK_USI_CMGP02_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_USI_CMGP02_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_USI_CMGP02_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_USI_CMGP03_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_USI_CMGP03_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_USI_CMGP03_DIVRATIO,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP00_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP00_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP00_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP00_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP00_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP00_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP01_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP01_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP01_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP02_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP02_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP02_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP03_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP03_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP03_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP01_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP01_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP01_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP02_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP02_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP02_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP03_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP03_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP03_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_CMGP_DLL_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_CMGP_DLL_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_CMGP_DLL_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CMGP_BUS_SELECT,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_XIU_P_CMGP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_XIU_P_CMGP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_XIU_P_CMGP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLK_CMGP_ADC_BUSY,
|
|
CLK_CON_MUX_CLK_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLK_CMGP_ADC_SELECT,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_ADC_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CMGP_ADC_DIVRATIO,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_P_APM2CMGP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_P_APM2CMGP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_P_APM2CMGP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_I2C_CMGP_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_I2C_CMGP_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_I2C_CMGP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_USI_CMGP00_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_USI_CMGP00_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_USI_CMGP00_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_USI_CMGP01_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_USI_CMGP01_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_USI_CMGP01_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_USI_CMGP02_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_USI_CMGP02_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_USI_CMGP02_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_USI_CMGP03_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_USI_CMGP03_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_USI_CMGP03_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_CHUB_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_CHUB_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_ADC_CMGP_QCH_S0_ENABLE,
|
|
QCH_CON_ADC_CMGP_QCH_S0_CLOCK_REQ,
|
|
QCH_CON_ADC_CMGP_QCH_S0_EXPIRE_VAL,
|
|
QCH_CON_ADC_CMGP_QCH_S0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ADC_CMGP_QCH_S1_ENABLE,
|
|
QCH_CON_ADC_CMGP_QCH_S1_CLOCK_REQ,
|
|
QCH_CON_ADC_CMGP_QCH_S1_EXPIRE_VAL,
|
|
QCH_CON_ADC_CMGP_QCH_S1_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_ADC_CMGP_QCH_ADC_ENABLE,
|
|
DMYQCH_CON_ADC_CMGP_QCH_ADC_CLOCK_REQ,
|
|
DMYQCH_CON_ADC_CMGP_QCH_ADC_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CMGP_CMU_CMGP_QCH_ENABLE,
|
|
QCH_CON_CMGP_CMU_CMGP_QCH_CLOCK_REQ,
|
|
QCH_CON_CMGP_CMU_CMGP_QCH_EXPIRE_VAL,
|
|
QCH_CON_CMGP_CMU_CMGP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GPIO_CMGP_QCH_ENABLE,
|
|
QCH_CON_GPIO_CMGP_QCH_CLOCK_REQ,
|
|
QCH_CON_GPIO_CMGP_QCH_EXPIRE_VAL,
|
|
QCH_CON_GPIO_CMGP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I2C_CMGP00_QCH_ENABLE,
|
|
QCH_CON_I2C_CMGP00_QCH_CLOCK_REQ,
|
|
QCH_CON_I2C_CMGP00_QCH_EXPIRE_VAL,
|
|
QCH_CON_I2C_CMGP00_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I2C_CMGP01_QCH_ENABLE,
|
|
QCH_CON_I2C_CMGP01_QCH_CLOCK_REQ,
|
|
QCH_CON_I2C_CMGP01_QCH_EXPIRE_VAL,
|
|
QCH_CON_I2C_CMGP01_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I2C_CMGP02_QCH_ENABLE,
|
|
QCH_CON_I2C_CMGP02_QCH_CLOCK_REQ,
|
|
QCH_CON_I2C_CMGP02_QCH_EXPIRE_VAL,
|
|
QCH_CON_I2C_CMGP02_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I2C_CMGP03_QCH_ENABLE,
|
|
QCH_CON_I2C_CMGP03_QCH_CLOCK_REQ,
|
|
QCH_CON_I2C_CMGP03_QCH_EXPIRE_VAL,
|
|
QCH_CON_I2C_CMGP03_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_APM2CMGP_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_APM2CMGP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_APM2CMGP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_APM2CMGP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CMGP_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CMGP_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CMGP_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_CMGP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CMGP2CHUB_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CMGP2CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CMGP2CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_CMGP2CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CMGP2CP_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CMGP2CP_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CMGP2CP_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_CMGP2CP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CMGP2GNSS_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CMGP2GNSS_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CMGP2GNSS_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_CMGP2GNSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CMGP2PMU_AP_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CMGP2PMU_AP_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CMGP2PMU_AP_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_CMGP2PMU_AP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CMGP2PMU_CHUB_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CMGP2PMU_CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CMGP2PMU_CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_CMGP2PMU_CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI_CMGP00_QCH_ENABLE,
|
|
QCH_CON_USI_CMGP00_QCH_CLOCK_REQ,
|
|
QCH_CON_USI_CMGP00_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI_CMGP00_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI_CMGP01_QCH_ENABLE,
|
|
QCH_CON_USI_CMGP01_QCH_CLOCK_REQ,
|
|
QCH_CON_USI_CMGP01_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI_CMGP01_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI_CMGP02_QCH_ENABLE,
|
|
QCH_CON_USI_CMGP02_QCH_CLOCK_REQ,
|
|
QCH_CON_USI_CMGP02_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI_CMGP02_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI_CMGP03_QCH_ENABLE,
|
|
QCH_CON_USI_CMGP03_QCH_CLOCK_REQ,
|
|
QCH_CON_USI_CMGP03_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI_CMGP03_QCH_IGNORE_FORCE_PM_EN,
|
|
CLK_CON_GAT_GATE_CLKCMU_APM_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_APM_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_APM_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_APM_BUS_DIVRATIO,
|
|
CLK_CON_DIV_DIV_PLL_SHARED0_DIV2_BUSY,
|
|
CLK_CON_DIV_DIV_PLL_SHARED0_DIV2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_PLL_SHARED0_DIV2_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_G3D_SWITCH_BUSY,
|
|
CLK_CON_DIV_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_G3D_SWITCH_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_PERIS_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIS_BUS_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_FSYS0_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_FSYS0_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_FSYS0_BUS_DIVRATIO,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPU_BUS_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPU_BUS_DIVRATIO,
|
|
PLL_CON0_PLL_SHARED1_DIV_P,
|
|
PLL_CON0_PLL_SHARED1_DIV_M,
|
|
PLL_CON0_PLL_SHARED1_DIV_S,
|
|
PLL_CON0_PLL_SHARED1_ENABLE,
|
|
PLL_CON0_PLL_SHARED1_STABLE,
|
|
PLL_LOCKTIME_PLL_SHARED1_PLL_LOCK_TIME,
|
|
CLK_CON_DIV_DIV_PLL_SHARED1_DIV2_BUSY,
|
|
CLK_CON_DIV_DIV_PLL_SHARED1_DIV2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_PLL_SHARED1_DIV2_DIVRATIO,
|
|
CLK_CON_GAT_CLKCMU_MIF_SWITCH_CG_VAL,
|
|
CLK_CON_GAT_CLKCMU_MIF_SWITCH_MANUAL,
|
|
CLK_CON_GAT_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_BUS1_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_BUS1_BUS_DIVRATIO,
|
|
CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_SELECT,
|
|
CLK_CON_DIV_DIV_PLL_SHARED2_DIV2_BUSY,
|
|
CLK_CON_DIV_DIV_PLL_SHARED2_DIV2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_PLL_SHARED2_DIV2_DIVRATIO,
|
|
CLK_CON_DIV_DIV_PLL_SHARED3_DIV2_BUSY,
|
|
CLK_CON_DIV_DIV_PLL_SHARED3_DIV2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_PLL_SHARED3_DIV2_DIVRATIO,
|
|
CLK_CON_DIV_DIV_PLL_SHARED4_DIV2_BUSY,
|
|
CLK_CON_DIV_DIV_PLL_SHARED4_DIV2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_PLL_SHARED4_DIV2_DIVRATIO,
|
|
PLL_CON0_PLL_SHARED4_DIV_P,
|
|
PLL_CON0_PLL_SHARED4_DIV_M,
|
|
PLL_CON0_PLL_SHARED4_DIV_S,
|
|
PLL_CON0_PLL_SHARED4_ENABLE,
|
|
PLL_CON0_PLL_SHARED4_STABLE,
|
|
PLL_LOCKTIME_PLL_SHARED4_PLL_LOCK_TIME,
|
|
CLK_CON_DIV_DIV_PLL_SHARED0_DIV4_BUSY,
|
|
CLK_CON_DIV_DIV_PLL_SHARED0_DIV4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_PLL_SHARED0_DIV4_DIVRATIO,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC_BUS_SELECT,
|
|
CLK_CON_DIV_CLKCMU_MFC_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_MFC_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_MFC_BUS_DIVRATIO,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_G2D_G2D_BUSY,
|
|
CLK_CON_DIV_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_G2D_G2D_DIVRATIO,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS0_USB30DRD_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS0_USB30DRD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS0_USB30DRD_SELECT,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS0_USB30DRD_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS0_USB30DRD_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS0_USB30DRD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_FSYS0_USB30DRD_BUSY,
|
|
CLK_CON_DIV_CLKCMU_FSYS0_USB30DRD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_FSYS0_USB30DRD_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD_BUSY,
|
|
CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD_DIVRATIO,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD_SELECT,
|
|
CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD_BUSY,
|
|
CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_FSYS1_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_FSYS1_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_FSYS1_BUS_DIVRATIO,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CMGP_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CMGP_BUS_DIVRATIO,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_SELECT,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSPM_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSPM_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSPM_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_DSPM_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_DSPM_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_DSPM_BUS_DIVRATIO,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_BUS_DIVRATIO,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_PLL_SHARED3_DIV_P,
|
|
PLL_CON0_PLL_SHARED3_DIV_M,
|
|
PLL_CON0_PLL_SHARED3_DIV_S,
|
|
PLL_CON0_PLL_SHARED3_ENABLE,
|
|
PLL_CON0_PLL_SHARED3_STABLE,
|
|
PLL_LOCKTIME_PLL_SHARED3_PLL_LOCK_TIME,
|
|
CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_SELECT,
|
|
CLK_CON_DIV_CLKCMU_BUSC_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_BUSC_BUS_DIVRATIO,
|
|
CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_SELECT,
|
|
CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_PLL_SHARED2_DIV_P,
|
|
PLL_CON0_PLL_SHARED2_DIV_M,
|
|
PLL_CON0_PLL_SHARED2_DIV_S,
|
|
PLL_CON0_PLL_SHARED2_ENABLE,
|
|
PLL_CON0_PLL_SHARED2_STABLE,
|
|
PLL_LOCKTIME_PLL_SHARED2_PLL_LOCK_TIME,
|
|
PLL_CON0_PLL_SHARED0_DIV_P,
|
|
PLL_CON0_PLL_SHARED0_DIV_M,
|
|
PLL_CON0_PLL_SHARED0_DIV_S,
|
|
PLL_CON0_PLL_SHARED0_ENABLE,
|
|
PLL_CON0_PLL_SHARED0_STABLE,
|
|
PLL_LOCKTIME_PLL_SHARED0_PLL_LOCK_TIME,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_DSPM_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_DSPM_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DSPM_BUS_SELECT,
|
|
CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_DIVRATIO,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_SELECT,
|
|
CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CORE_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CORE_BUS_DIVRATIO,
|
|
CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_ISPPRE_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_ISPPRE_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_ISPPRE_BUS_SELECT,
|
|
CLK_CON_GAT_GATE_CLKCMU_ISPPRE_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_ISPPRE_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_ISPPRE_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_ISPPRE_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_ISPPRE_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_ISPPRE_BUS_DIVRATIO,
|
|
CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS_SELECT,
|
|
CLK_CON_DIV_CLKCMU_ISPLP_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_ISPLP_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_ISPLP_BUS_DIVRATIO,
|
|
CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_ISPHQ_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_ISPHQ_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_ISPHQ_BUS_DIVRATIO,
|
|
CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS_SELECT,
|
|
CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_SELECT,
|
|
CLK_CON_DIV_CLKCMU_AUD_CPU_BUSY,
|
|
CLK_CON_DIV_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_AUD_CPU_DIVRATIO,
|
|
CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_G2D_MSCL_BUSY,
|
|
CLK_CON_DIV_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_G2D_MSCL_DIVRATIO,
|
|
CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_SELECT,
|
|
CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_HPM_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_HPM_SELECT,
|
|
CLK_CON_DIV_CLKCMU_HPM_BUSY,
|
|
CLK_CON_DIV_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_HPM_DIVRATIO,
|
|
CLK_CON_GAT_GATE_CLKCMU_HPM_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HPM_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_FSYS1_PCIE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_SELECT,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_DIVRATIO,
|
|
CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_SELECT,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK0_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK0_DIVRATIO,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK1_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK1_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK2_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK2_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK3_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CIS_CLK3_DIVRATIO,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_SELECT,
|
|
CLK_CON_DIV_CLKCMU_OTP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_IVA_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_IVA_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_IVA_BUS_SELECT,
|
|
CLK_CON_GAT_GATE_CLKCMU_IVA_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_IVA_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_IVA_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_IVA_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_IVA_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_IVA_BUS_DIVRATIO,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD_SELECT,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD_BUSY,
|
|
CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD_DIVRATIO,
|
|
CLK_CON_MUX_MUX_CMU_CMUREF_BUSY,
|
|
CLK_CON_MUX_MUX_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CMU_CMUREF_SELECT,
|
|
CLK_CON_DIV_DIV_PLL_SHARED1_DIV4_BUSY,
|
|
CLK_CON_DIV_DIV_PLL_SHARED1_DIV4_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_PLL_SHARED1_DIV4_DIVRATIO,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_SELECT,
|
|
CLK_CON_DIV_CLKCMU_FSYS0_DPGTC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_FSYS0_DPGTC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_FSYS0_DPGTC_DIVRATIO,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_MODEM_SHARED0_BUSY,
|
|
CLK_CON_DIV_CLKCMU_MODEM_SHARED0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_MODEM_SHARED0_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_MODEM_SHARED1_BUSY,
|
|
CLK_CON_DIV_CLKCMU_MODEM_SHARED1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_MODEM_SHARED1_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_DCRD_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_DCRD_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_DCRD_BUS_DIVRATIO,
|
|
CLK_CON_GAT_GATE_CLKCMU_DCRD_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DCRD_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DCRD_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DCRD_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_DCRD_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DCRD_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE_SELECT,
|
|
CLK_CON_DIV_DIV_CLK_CMU_CMUREF_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CMU_CMUREF_DIVRATIO,
|
|
CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS_SELECT,
|
|
CLK_CON_DIV_CLKCMU_CHUB_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_CHUB_BUS_DIVRATIO,
|
|
CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_DCF_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_DCF_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_DCF_BUS_DIVRATIO,
|
|
CLK_CON_GAT_GATE_CLKCMU_DCF_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DCF_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DCF_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DCF_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_DCF_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DCF_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_APM_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_APM_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS_SELECT,
|
|
CLK_CON_MUX_MUX_CLK_CMU_CMUREF_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CMU_CMUREF_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_VTS_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_VTS_BUS_SELECT,
|
|
CLK_CON_GAT_GATE_CLKCMU_VTS_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_VTS_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_VTS_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_VTS_BUS_DIVRATIO,
|
|
CLK_CON_MUX_MUX_CLKCMU_ISPLP_VRA_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_ISPLP_VRA_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_ISPLP_VRA_SELECT,
|
|
CLK_CON_GAT_GATE_CLKCMU_ISPLP_VRA_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_ISPLP_VRA_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_ISPLP_VRA_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_ISPLP_VRA_BUSY,
|
|
CLK_CON_DIV_CLKCMU_ISPLP_VRA_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_ISPLP_VRA_DIVRATIO,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC_WFD_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_MFC_WFD_SELECT,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC_WFD_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC_WFD_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_MFC_WFD_BUSY,
|
|
CLK_CON_DIV_CLKCMU_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_MFC_WFD_DIVRATIO,
|
|
CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_SELECT,
|
|
CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_MIF_BUSP_BUSY,
|
|
CLK_CON_DIV_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_MIF_BUSP_DIVRATIO,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_IP_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_IP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIC0_IP_DIVRATIO,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP_SELECT,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP_SELECT,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_IP_BUSY,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_IP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_PERIC1_IP_DIVRATIO,
|
|
CLK_CON_MUX_MUX_CLKCMU_DCPOST_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_DCPOST_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DCPOST_BUS_SELECT,
|
|
CLK_CON_GAT_GATE_CLKCMU_DCPOST_BUS_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DCPOST_BUS_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DCPOST_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_DCPOST_BUS_BUSY,
|
|
CLK_CON_DIV_CLKCMU_DCPOST_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_DCPOST_BUS_DIVRATIO,
|
|
PLL_CON0_PLL_MMC_DIV_P,
|
|
PLL_CON0_PLL_MMC_DIV_M,
|
|
PLL_CON0_PLL_MMC_DIV_S,
|
|
PLL_CON0_PLL_MMC_ENABLE,
|
|
PLL_CON0_PLL_MMC_STABLE,
|
|
PLL_CON3_PLL_MMC_DIV_K,
|
|
PLL_LOCKTIME_PLL_MMC_PLL_LOCK_TIME,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDP_DEBUG_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDP_DEBUG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDP_DEBUG_SELECT,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDP_DEBUG_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDP_DEBUG_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDP_DEBUG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_FSYS0_USBDP_DEBUG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_ISPLP_GDC_BUSY,
|
|
CLK_CON_DIV_CLKCMU_ISPLP_GDC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_ISPLP_GDC_DIVRATIO,
|
|
CLK_CON_GAT_GATE_CLKCMU_ISPLP_GDC_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_ISPLP_GDC_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_ISPLP_GDC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_ISPLP_GDC_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_ISPLP_GDC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_ISPLP_GDC_SELECT,
|
|
CLK_CON_MUX_MUX_CLKCMU_DSPS_AUD_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_DSPS_AUD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DSPS_AUD_SELECT,
|
|
CLK_CON_DIV_CLKCMU_DSPS_AUD_BUSY,
|
|
CLK_CON_DIV_CLKCMU_DSPS_AUD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_CLKCMU_DSPS_AUD_DIVRATIO,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSPS_AUD_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSPS_AUD_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DSPS_AUD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_PLL_SHARED1_DIV3_BUSY,
|
|
CLK_CON_DIV_DIV_PLL_SHARED1_DIV3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_PLL_SHARED1_DIV3_DIVRATIO,
|
|
CLK_CON_DIV_DIV_PLL_SHARED0_DIV3_BUSY,
|
|
CLK_CON_DIV_DIV_PLL_SHARED0_DIV3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_PLL_SHARED0_DIV3_DIVRATIO,
|
|
CLK_CON_MUX_CLKCMU_DPU_BUS_BUSY,
|
|
CLK_CON_MUX_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_DPU_BUS_SELECT,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPU_BUSY,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLKCMU_DPU_DIVRATIO,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPU_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPU_MANUAL,
|
|
CLK_CON_GAT_GATE_CLKCMU_DPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_SELECT,
|
|
DMYQCH_CON_CMU_CMU_CMUREF_QCH_ENABLE,
|
|
DMYQCH_CON_CMU_CMU_CMUREF_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CMU_CMU_CMUREF_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_ENABLE,
|
|
DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_CLOCK_REQ,
|
|
DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_ENABLE,
|
|
DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_CLOCK_REQ,
|
|
DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_ENABLE,
|
|
DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_CLOCK_REQ,
|
|
DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_ENABLE,
|
|
DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_CLOCK_REQ,
|
|
DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_OTP_QCH_ENABLE,
|
|
DMYQCH_CON_OTP_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_OTP_QCH_IGNORE_FORCE_PM_EN,
|
|
CLK_CON_DIV_DIV_CLK_CORE_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CORE_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CORE_BUSP_DIVRATIO,
|
|
CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMUPPC_CCI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMUPPC_CCI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMUPPC_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_CORE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CP_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CP_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_G3D_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_G3D_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_G3D_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_IO_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_IO_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_IO_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_DP_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_DP_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_DP_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BPS_P_G3D_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BPS_P_G3D_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_BPS_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_ACE_SLICE_G3D0_QCH_ENABLE,
|
|
QCH_CON_ACE_SLICE_G3D0_QCH_CLOCK_REQ,
|
|
QCH_CON_ACE_SLICE_G3D0_QCH_EXPIRE_VAL,
|
|
QCH_CON_ACE_SLICE_G3D0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ACE_SLICE_G3D1_QCH_ENABLE,
|
|
QCH_CON_ACE_SLICE_G3D1_QCH_CLOCK_REQ,
|
|
QCH_CON_ACE_SLICE_G3D1_QCH_EXPIRE_VAL,
|
|
QCH_CON_ACE_SLICE_G3D1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ACE_SLICE_G3D2_QCH_ENABLE,
|
|
QCH_CON_ACE_SLICE_G3D2_QCH_CLOCK_REQ,
|
|
QCH_CON_ACE_SLICE_G3D2_QCH_EXPIRE_VAL,
|
|
QCH_CON_ACE_SLICE_G3D2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ACE_SLICE_G3D3_QCH_ENABLE,
|
|
QCH_CON_ACE_SLICE_G3D3_QCH_CLOCK_REQ,
|
|
QCH_CON_ACE_SLICE_G3D3_QCH_EXPIRE_VAL,
|
|
QCH_CON_ACE_SLICE_G3D3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BAAW_CP_QCH_ENABLE,
|
|
QCH_CON_BAAW_CP_QCH_CLOCK_REQ,
|
|
QCH_CON_BAAW_CP_QCH_EXPIRE_VAL,
|
|
QCH_CON_BAAW_CP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BDU_QCH_ENABLE,
|
|
QCH_CON_BDU_QCH_CLOCK_REQ,
|
|
QCH_CON_BDU_QCH_EXPIRE_VAL,
|
|
QCH_CON_BDU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_HPMCORE_QCH_ENABLE,
|
|
QCH_CON_BUSIF_HPMCORE_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_HPMCORE_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_HPMCORE_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CCI_QCH_ENABLE,
|
|
DMYQCH_CON_CCI_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CCI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CORE_CMU_CORE_QCH_ENABLE,
|
|
QCH_CON_CORE_CMU_CORE_QCH_CLOCK_REQ,
|
|
QCH_CON_CORE_CMU_CORE_QCH_EXPIRE_VAL,
|
|
QCH_CON_CORE_CMU_CORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACE_D0_G3D_QCH_ENABLE,
|
|
QCH_CON_LHM_ACE_D0_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACE_D0_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACE_D0_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACE_D1_G3D_QCH_ENABLE,
|
|
QCH_CON_LHM_ACE_D1_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACE_D1_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACE_D1_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACE_D2_G3D_QCH_ENABLE,
|
|
QCH_CON_LHM_ACE_D2_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACE_D2_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACE_D2_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACE_D3_G3D_QCH_ENABLE,
|
|
QCH_CON_LHM_ACE_D3_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACE_D3_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACE_D3_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ACE_D_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_LHM_ACE_D_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ACE_D_CPUCL0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ACE_D_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_CP_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_CP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_CP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_CP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_T_BDU_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_T_BDU_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_T_BDU_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_T_BDU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_APM_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_APM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_APM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_APM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_CP_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_CP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_CP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_CP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_CPUCL0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_CPUCL1_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_CPUCL1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_CPUCL1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_CPUCL1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_G3D_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPCFW_G3D_QCH_ENABLE,
|
|
QCH_CON_PPCFW_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_PPCFW_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPCFW_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPFW_DP_QCH_ENABLE,
|
|
QCH_CON_PPFW_DP_QCH_CLOCK_REQ,
|
|
QCH_CON_PPFW_DP_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPFW_DP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPFW_G3D_QCH_ENABLE,
|
|
QCH_CON_PPFW_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_PPFW_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPFW_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPFW_IO_QCH_ENABLE,
|
|
QCH_CON_PPFW_IO_QCH_CLOCK_REQ,
|
|
QCH_CON_PPFW_IO_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPFW_IO_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_PPMU_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_CPUCL0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_CPUCL1_QCH_ENABLE,
|
|
QCH_CON_PPMU_CPUCL1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_CPUCL1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_G3D0_QCH_ENABLE,
|
|
QCH_CON_PPMU_G3D0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_G3D0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_G3D0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_G3D1_QCH_ENABLE,
|
|
QCH_CON_PPMU_G3D1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_G3D1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_G3D1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_G3D2_QCH_ENABLE,
|
|
QCH_CON_PPMU_G3D2_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_G3D2_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_G3D2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_G3D3_QCH_ENABLE,
|
|
QCH_CON_PPMU_G3D3_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_G3D3_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_G3D3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CORE_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CORE_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CORE_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_CORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_D_CORE_QCH_ENABLE,
|
|
QCH_CON_TREX_D_CORE_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_D_CORE_QCH_EXPIRE_VAL,
|
|
QCH_CON_TREX_D_CORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_P0_CORE_QCH_ENABLE,
|
|
QCH_CON_TREX_P0_CORE_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_P0_CORE_QCH_EXPIRE_VAL,
|
|
QCH_CON_TREX_P0_CORE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_P1_CORE_QCH_ENABLE,
|
|
QCH_CON_TREX_P1_CORE_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_P1_CORE_QCH_EXPIRE_VAL,
|
|
QCH_CON_TREX_P1_CORE_QCH_IGNORE_FORCE_PM_EN,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_SELECT,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_DIVRATIO,
|
|
PLL_CON0_PLL_CPUCL0_DIV_P,
|
|
PLL_CON0_PLL_CPUCL0_DIV_M,
|
|
PLL_CON0_PLL_CPUCL0_DIV_S,
|
|
PLL_CON0_PLL_CPUCL0_ENABLE,
|
|
PLL_CON0_PLL_CPUCL0_STABLE,
|
|
PLL_LOCKTIME_PLL_CPUCL0_PLL_LOCK_TIME,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_DIVRATIO,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_CPUCL0_CPU_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_CPUCL0_CPU_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_CPUCL0_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_DIVRATIO,
|
|
CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_DIVRATIO,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_DIVRATIO,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_BDU_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_BDU_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_BDU_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER0_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER0_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER1_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER1_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_DIVRATIO,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER0_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER0_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER1_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER1_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_DSPM_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_DSPM_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_DSPM_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CSSYS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CSSYS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_P_CSSYS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_P_CSSYS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_P_CSSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI_DS_64TO32_G_CSSYS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI_DS_64TO32_G_CSSYS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI_DS_64TO32_G_CSSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CLUSTER0_SCLK_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CLUSTER0_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CLUSTER0_SCLK_SELECT,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLK_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLK_SELECT,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLKP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLKP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLKP_DIVRATIO,
|
|
CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLKP_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLKP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLKP_SELECT,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_P_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_P_CLUSTER0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_P_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLKP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLKP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLKP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_SCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_SCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH_ENABLE,
|
|
DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_HPMCPUCL0_QCH_ENABLE,
|
|
QCH_CON_BUSIF_HPMCPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_HPMCPUCL0_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_HPMCPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLUSTER0_QCH_SCLK_ENABLE,
|
|
QCH_CON_CLUSTER0_QCH_SCLK_CLOCK_REQ,
|
|
QCH_CON_CLUSTER0_QCH_SCLK_EXPIRE_VAL,
|
|
QCH_CON_CLUSTER0_QCH_SCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLUSTER0_QCH_ATCLK_ENABLE,
|
|
QCH_CON_CLUSTER0_QCH_ATCLK_CLOCK_REQ,
|
|
QCH_CON_CLUSTER0_QCH_ATCLK_EXPIRE_VAL,
|
|
QCH_CON_CLUSTER0_QCH_ATCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLUSTER0_QCH_PDBGCLK_ENABLE,
|
|
QCH_CON_CLUSTER0_QCH_PDBGCLK_CLOCK_REQ,
|
|
QCH_CON_CLUSTER0_QCH_PDBGCLK_EXPIRE_VAL,
|
|
QCH_CON_CLUSTER0_QCH_PDBGCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLUSTER0_QCH_GIC_ENABLE,
|
|
QCH_CON_CLUSTER0_QCH_GIC_CLOCK_REQ,
|
|
QCH_CON_CLUSTER0_QCH_GIC_EXPIRE_VAL,
|
|
QCH_CON_CLUSTER0_QCH_GIC_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLUSTER0_QCH_DBG_PD_ENABLE,
|
|
QCH_CON_CLUSTER0_QCH_DBG_PD_CLOCK_REQ,
|
|
QCH_CON_CLUSTER0_QCH_DBG_PD_EXPIRE_VAL,
|
|
QCH_CON_CLUSTER0_QCH_DBG_PD_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLUSTER0_QCH_PCLK_ENABLE,
|
|
QCH_CON_CLUSTER0_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_CLUSTER0_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_CLUSTER0_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_ENABLE,
|
|
DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_CLOCK_REQ,
|
|
DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_ENABLE,
|
|
QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_CLOCK_REQ,
|
|
QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_EXPIRE_VAL,
|
|
QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CPUCL0_CMU_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_CPUCL0_CMU_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_CPUCL0_CMU_CPUCL0_QCH_EXPIRE_VAL,
|
|
QCH_CON_CPUCL0_CMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CSSYS_QCH_ENABLE,
|
|
QCH_CON_CSSYS_QCH_CLOCK_REQ,
|
|
QCH_CON_CSSYS_QCH_EXPIRE_VAL,
|
|
QCH_CON_CSSYS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DUMPPC_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_DUMPPC_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_DUMPPC_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_DUMPPC_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DUMPPC_CLUSTER1_QCH_ENABLE,
|
|
QCH_CON_DUMPPC_CLUSTER1_QCH_CLOCK_REQ,
|
|
QCH_CON_DUMPPC_CLUSTER1_QCH_EXPIRE_VAL,
|
|
QCH_CON_DUMPPC_CLUSTER1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_T0_CLUSTER1_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_T0_CLUSTER1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_T0_CLUSTER1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_T0_CLUSTER1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_T1_CLUSTER1_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_T1_CLUSTER1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_T1_CLUSTER1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_T1_CLUSTER1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_T2_CLUSTER1_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_T2_CLUSTER1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_T2_CLUSTER1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_T2_CLUSTER1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_T3_CLUSTER1_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_T3_CLUSTER1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_T3_CLUSTER1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_T3_CLUSTER1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_T_AUD_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_T_AUD_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_T_AUD_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_T_AUD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_T_BDU_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_T_BDU_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_T_BDU_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_T_BDU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_CPUCL0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_CSSYS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_CSSYS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_CSSYS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_CSSYS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ACE_D_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHS_ACE_D_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ACE_D_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ACE_D_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_G_CSSYS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_G_CSSYS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_G_CSSYS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_G_ETR_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_G_ETR_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_G_ETR_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_G_ETR_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SECJTAG_QCH_ENABLE,
|
|
QCH_CON_SECJTAG_QCH_CLOCK_REQ,
|
|
QCH_CON_SECJTAG_QCH_EXPIRE_VAL,
|
|
QCH_CON_SECJTAG_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CPUCL0_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CPUCL0_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CPUCL0_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_CPUCL0_QCH_IGNORE_FORCE_PM_EN,
|
|
PLL_CON0_PLL_CPUCL1_DIV_P,
|
|
PLL_CON0_PLL_CPUCL1_DIV_M,
|
|
PLL_CON0_PLL_CPUCL1_DIV_S,
|
|
PLL_CON0_PLL_CPUCL1_ENABLE,
|
|
PLL_CON0_PLL_CPUCL1_STABLE,
|
|
PLL_LOCKTIME_PLL_CPUCL1_PLL_LOCK_TIME,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_SELECT,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_DIVRATIO,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_0_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_0_IPCLKPORT_HPM_TARGETCLK_C_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_0_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK_DIVRATIO,
|
|
CLK_CON_GAT_GATE_CLK_CPUCL1_CPU_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_CPUCL1_CPU_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_CPUCL1_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_DIVRATIO,
|
|
CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_DIVRATIO,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CLUSTER1_IPCLKPORT_PCLKDBG_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CLUSTER1_IPCLKPORT_PCLKDBG_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CLUSTER1_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_1_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_1_IPCLKPORT_HPM_TARGETCLK_C_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_1_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_2_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_2_IPCLKPORT_HPM_TARGETCLK_C_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_2_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_BUSIF_HPMCPUCL1_QCH_ENABLE,
|
|
QCH_CON_BUSIF_HPMCPUCL1_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_HPMCPUCL1_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_HPMCPUCL1_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CLUSTER1_QCH_CPU_ENABLE,
|
|
DMYQCH_CON_CLUSTER1_QCH_CPU_CLOCK_REQ,
|
|
DMYQCH_CON_CLUSTER1_QCH_CPU_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1_ENABLE,
|
|
QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1_CLOCK_REQ,
|
|
QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1_EXPIRE_VAL,
|
|
QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1_ENABLE,
|
|
QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1_CLOCK_REQ,
|
|
QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1_EXPIRE_VAL,
|
|
QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1_ENABLE,
|
|
QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1_CLOCK_REQ,
|
|
QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1_EXPIRE_VAL,
|
|
QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1_ENABLE,
|
|
QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1_CLOCK_REQ,
|
|
QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1_EXPIRE_VAL,
|
|
QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CLUSTER1_QCH_PCLKDBG_ENABLE,
|
|
DMYQCH_CON_CLUSTER1_QCH_PCLKDBG_CLOCK_REQ,
|
|
DMYQCH_CON_CLUSTER1_QCH_PCLKDBG_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_ENABLE,
|
|
QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_CLOCK_REQ,
|
|
QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_EXPIRE_VAL,
|
|
QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CPUCL1_CMU_CPUCL1_QCH_ENABLE,
|
|
QCH_CON_CPUCL1_CMU_CPUCL1_QCH_CLOCK_REQ,
|
|
QCH_CON_CPUCL1_CMU_CPUCL1_QCH_EXPIRE_VAL,
|
|
QCH_CON_CPUCL1_CMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_CPUCL1_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_CPUCL1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_CPUCL1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_CPUCL1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_CPUCL1_QCH_ENABLE,
|
|
QCH_CON_SYSREG_CPUCL1_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_CPUCL1_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_CPUCL1_QCH_IGNORE_FORCE_PM_EN,
|
|
CLK_CON_DIV_DIV_CLK_DCF_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_DCF_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DCF_BUSP_DIVRATIO,
|
|
PLL_CON0_MUX_CLKCMU_DCF_BUS_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_DCF_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_DCF_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_BTM_DCF_QCH_ENABLE,
|
|
QCH_CON_BTM_DCF_QCH_CLOCK_REQ,
|
|
QCH_CON_BTM_DCF_QCH_EXPIRE_VAL,
|
|
QCH_CON_BTM_DCF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DCF_CMU_DCF_QCH_ENABLE,
|
|
QCH_CON_DCF_CMU_DCF_QCH_CLOCK_REQ,
|
|
QCH_CON_DCF_CMU_DCF_QCH_EXPIRE_VAL,
|
|
QCH_CON_DCF_CMU_DCF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_DCF_QCH_CIP_ENABLE,
|
|
QCH_CON_IS_DCF_QCH_CIP_CLOCK_REQ,
|
|
QCH_CON_IS_DCF_QCH_CIP_EXPIRE_VAL,
|
|
QCH_CON_IS_DCF_QCH_CIP_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_DCF_QCH_QE_ENABLE,
|
|
QCH_CON_IS_DCF_QCH_QE_CLOCK_REQ,
|
|
QCH_CON_IS_DCF_QCH_QE_EXPIRE_VAL,
|
|
QCH_CON_IS_DCF_QCH_QE_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_DCF_QCH_SYSREG_ENABLE,
|
|
QCH_CON_IS_DCF_QCH_SYSREG_CLOCK_REQ,
|
|
QCH_CON_IS_DCF_QCH_SYSREG_EXPIRE_VAL,
|
|
QCH_CON_IS_DCF_QCH_SYSREG_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_DCF_QCH_PPMU_ENABLE,
|
|
QCH_CON_IS_DCF_QCH_PPMU_CLOCK_REQ,
|
|
QCH_CON_IS_DCF_QCH_PPMU_EXPIRE_VAL,
|
|
QCH_CON_IS_DCF_QCH_PPMU_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_DCF_QCH_SYSMMU_ENABLE,
|
|
QCH_CON_IS_DCF_QCH_SYSMMU_CLOCK_REQ,
|
|
QCH_CON_IS_DCF_QCH_SYSMMU_EXPIRE_VAL,
|
|
QCH_CON_IS_DCF_QCH_SYSMMU_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_DCF_QCH_C2SYNC_2SLV_ENABLE,
|
|
QCH_CON_IS_DCF_QCH_C2SYNC_2SLV_CLOCK_REQ,
|
|
QCH_CON_IS_DCF_QCH_C2SYNC_2SLV_EXPIRE_VAL,
|
|
QCH_CON_IS_DCF_QCH_C2SYNC_2SLV_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_DCF_QCH_PGEN_LITE_ENABLE,
|
|
QCH_CON_IS_DCF_QCH_PGEN_LITE_CLOCK_REQ,
|
|
QCH_CON_IS_DCF_QCH_PGEN_LITE_EXPIRE_VAL,
|
|
QCH_CON_IS_DCF_QCH_PGEN_LITE_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_DCPOSTDCF_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_DCPOSTDCF_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_DCPOSTDCF_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_DCPOSTDCF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_ISPHQDCF_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_ISPHQDCF_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_ISPHQDCF_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_ISPHQDCF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_DCPOSTDCF_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_DCPOSTDCF_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_DCPOSTDCF_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_DCPOSTDCF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_DCF_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_DCF_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_DCF_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_DCF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_DCFDCPOST_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_DCFDCPOST_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_DCFDCPOST_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_DCFDCPOST_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_DCFISPLP_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_DCFISPLP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_DCFISPLP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_DCFISPLP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_DCF_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_DCF_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_DCF_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_DCF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_DCFDCPOST_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_DCFDCPOST_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_DCFDCPOST_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_DCFDCPOST_QCH_IGNORE_FORCE_PM_EN,
|
|
PLL_CON0_MUX_CLKCMU_DCPOST_BUS_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_DCPOST_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_DCPOST_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DCPOST_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_DCPOST_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DCPOST_BUSP_DIVRATIO,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCF_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCF_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_AXI_D_DCPOSTDCF_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_AXI_D_DCPOSTDCF_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_AXI_D_DCPOSTDCF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCRDDCPOST_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCRDDCPOST_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCRDDCPOST_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_SYSREG_DCPOST_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_SYSREG_DCPOST_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_SYSREG_DCPOST_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_CIP2_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_CIP2_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_CIP2_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_CIP2_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_CIP2_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_CIP2_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_AXI_P_DCFDCPOST_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_AXI_P_DCFDCPOST_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_AXI_P_DCFDCPOST_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DCPOST_UID_DCPOST_CMU_DCPOST_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DCPOST_UID_DCPOST_CMU_DCPOST_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DCPOST_UID_DCPOST_CMU_DCPOST_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_C2SYNC_1SLV_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_C2SYNC_1SLV_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_C2SYNC_1SLV_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_C2SYNC_1SLV_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_C2SYNC_1SLV_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_C2SYNC_1SLV_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCFDCPOST_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCFDCPOST_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCFDCPOST_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCRD_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCRD_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCRD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_CIP2_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_CIP2_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_CIP2_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_C2SYNC_1SLV_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_C2SYNC_1SLV_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_C2SYNC_1SLV_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AXI2APB_DCPOST_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AXI2APB_DCPOST_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AXI2APB_DCPOST_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_DCPOST_CMU_DCPOST_QCH_ENABLE,
|
|
QCH_CON_DCPOST_CMU_DCPOST_QCH_CLOCK_REQ,
|
|
QCH_CON_DCPOST_CMU_DCPOST_QCH_EXPIRE_VAL,
|
|
QCH_CON_DCPOST_CMU_DCPOST_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_DCPOST_QCH_SYSREG_ENABLE,
|
|
QCH_CON_IS_DCPOST_QCH_SYSREG_CLOCK_REQ,
|
|
QCH_CON_IS_DCPOST_QCH_SYSREG_EXPIRE_VAL,
|
|
QCH_CON_IS_DCPOST_QCH_SYSREG_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_DCPOST_QCH_CIP2_ENABLE,
|
|
QCH_CON_IS_DCPOST_QCH_CIP2_CLOCK_REQ,
|
|
QCH_CON_IS_DCPOST_QCH_CIP2_EXPIRE_VAL,
|
|
QCH_CON_IS_DCPOST_QCH_CIP2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_DCPOST_QCH_QE_ENABLE,
|
|
QCH_CON_IS_DCPOST_QCH_QE_CLOCK_REQ,
|
|
QCH_CON_IS_DCPOST_QCH_QE_EXPIRE_VAL,
|
|
QCH_CON_IS_DCPOST_QCH_QE_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_DCPOST_QCH_C2SYNC_1SLV_CLK_ENABLE,
|
|
QCH_CON_IS_DCPOST_QCH_C2SYNC_1SLV_CLK_CLOCK_REQ,
|
|
QCH_CON_IS_DCPOST_QCH_C2SYNC_1SLV_CLK_EXPIRE_VAL,
|
|
QCH_CON_IS_DCPOST_QCH_C2SYNC_1SLV_CLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_DCFDCPOST_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_DCFDCPOST_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_DCFDCPOST_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_DCFDCPOST_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_DCRDDCPOST_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_DCRDDCPOST_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_DCRDDCPOST_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_DCRDDCPOST_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_DCFDCPOST_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_DCFDCPOST_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_DCFDCPOST_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_DCFDCPOST_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_DCPOSTDCF_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_DCPOSTDCF_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_DCPOSTDCF_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_DCPOSTDCF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_DCPOSTDCRD_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_DCPOSTDCRD_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_DCPOSTDCRD_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_DCPOSTDCRD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_DCPOSTDCF_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_DCPOSTDCF_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_DCPOSTDCF_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_DCPOSTDCF_QCH_IGNORE_FORCE_PM_EN,
|
|
CLK_CON_DIV_DIV_CLK_DCRD_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_DCRD_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DCRD_BUSP_DIVRATIO,
|
|
PLL_CON0_MUX_CLKCMU_DCRD_BUS_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_DCRD_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_DCRD_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DCRD_BUSD_HALF_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_DCRD_BUSD_HALF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DCRD_BUSD_HALF_DIVRATIO,
|
|
QCH_CON_BTM_DCRD_QCH_ENABLE,
|
|
QCH_CON_BTM_DCRD_QCH_CLOCK_REQ,
|
|
QCH_CON_BTM_DCRD_QCH_EXPIRE_VAL,
|
|
QCH_CON_BTM_DCRD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DCRD_CMU_DCRD_QCH_ENABLE,
|
|
QCH_CON_DCRD_CMU_DCRD_QCH_CLOCK_REQ,
|
|
QCH_CON_DCRD_CMU_DCRD_QCH_EXPIRE_VAL,
|
|
QCH_CON_DCRD_CMU_DCRD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_DCRD_QCH_DCP_ENABLE,
|
|
QCH_CON_IS_DCRD_QCH_DCP_CLOCK_REQ,
|
|
QCH_CON_IS_DCRD_QCH_DCP_EXPIRE_VAL,
|
|
QCH_CON_IS_DCRD_QCH_DCP_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_DCRD_QCH_PPMU_ENABLE,
|
|
QCH_CON_IS_DCRD_QCH_PPMU_CLOCK_REQ,
|
|
QCH_CON_IS_DCRD_QCH_PPMU_EXPIRE_VAL,
|
|
QCH_CON_IS_DCRD_QCH_PPMU_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_DCRD_QCH_SYSMMU_ENABLE,
|
|
QCH_CON_IS_DCRD_QCH_SYSMMU_CLOCK_REQ,
|
|
QCH_CON_IS_DCRD_QCH_SYSMMU_EXPIRE_VAL,
|
|
QCH_CON_IS_DCRD_QCH_SYSMMU_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_DCRD_QCH_SYSREG_ENABLE,
|
|
QCH_CON_IS_DCRD_QCH_SYSREG_CLOCK_REQ,
|
|
QCH_CON_IS_DCRD_QCH_SYSREG_EXPIRE_VAL,
|
|
QCH_CON_IS_DCRD_QCH_SYSREG_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_DCRD_QCH_PGEN_LITE_ENABLE,
|
|
QCH_CON_IS_DCRD_QCH_PGEN_LITE_CLOCK_REQ,
|
|
QCH_CON_IS_DCRD_QCH_PGEN_LITE_EXPIRE_VAL,
|
|
QCH_CON_IS_DCRD_QCH_PGEN_LITE_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_DCRD_QCH_DCP_C2C_ENABLE,
|
|
QCH_CON_IS_DCRD_QCH_DCP_C2C_CLOCK_REQ,
|
|
QCH_CON_IS_DCRD_QCH_DCP_C2C_EXPIRE_VAL,
|
|
QCH_CON_IS_DCRD_QCH_DCP_C2C_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_DCRD_QCH_DCP_DIV2_ENABLE,
|
|
QCH_CON_IS_DCRD_QCH_DCP_DIV2_CLOCK_REQ,
|
|
QCH_CON_IS_DCRD_QCH_DCP_DIV2_EXPIRE_VAL,
|
|
QCH_CON_IS_DCRD_QCH_DCP_DIV2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_DCPOSTDCRD_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_DCPOSTDCRD_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_DCPOSTDCRD_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_DCPOSTDCRD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_DCRD_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_DCRD_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_DCRD_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_DCRD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_DCRDDCPOST_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_DCRDDCPOST_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_DCRDDCPOST_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_DCRDDCPOST_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_DCRDISPLP_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_DCRDISPLP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_DCRDISPLP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_DCRDISPLP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_DCRD_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_DCRD_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_DCRD_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_DCRD_QCH_IGNORE_FORCE_PM_EN,
|
|
PLL_CON0_MUX_CLKCMU_DPU_BUS_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_DPU_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_DPU_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DPU_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_DPU_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DPU_BUSP_DIVRATIO,
|
|
CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD0_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD0_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD1_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD1_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_XIU_P_DPU_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_XIU_P_DPU_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_XIU_P_DPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON1_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON1_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPP_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPP_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPP_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD2_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD2_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON2_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON2_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON2_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_S_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_S_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_S_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_S_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_S_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_S_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_S_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_S_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_S_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_WRAPPER_FOR_S5I6211_HSI_DCPHY_COMBO_TOP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_WRAPPER_FOR_S5I6211_HSI_DCPHY_COMBO_TOP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_WRAPPER_FOR_S5I6211_HSI_DCPHY_COMBO_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_PGEN_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_PGEN_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_PGEN_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_BTM_DPUD0_QCH_ENABLE,
|
|
QCH_CON_BTM_DPUD0_QCH_CLOCK_REQ,
|
|
QCH_CON_BTM_DPUD0_QCH_EXPIRE_VAL,
|
|
QCH_CON_BTM_DPUD0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BTM_DPUD1_QCH_ENABLE,
|
|
QCH_CON_BTM_DPUD1_QCH_CLOCK_REQ,
|
|
QCH_CON_BTM_DPUD1_QCH_EXPIRE_VAL,
|
|
QCH_CON_BTM_DPUD1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BTM_DPUD2_QCH_ENABLE,
|
|
QCH_CON_BTM_DPUD2_QCH_CLOCK_REQ,
|
|
QCH_CON_BTM_DPUD2_QCH_EXPIRE_VAL,
|
|
QCH_CON_BTM_DPUD2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPU_QCH_DPU_ENABLE,
|
|
QCH_CON_DPU_QCH_DPU_CLOCK_REQ,
|
|
QCH_CON_DPU_QCH_DPU_EXPIRE_VAL,
|
|
QCH_CON_DPU_QCH_DPU_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPU_QCH_DPU_DMA_ENABLE,
|
|
QCH_CON_DPU_QCH_DPU_DMA_CLOCK_REQ,
|
|
QCH_CON_DPU_QCH_DPU_DMA_EXPIRE_VAL,
|
|
QCH_CON_DPU_QCH_DPU_DMA_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPU_QCH_DPU_DPP_ENABLE,
|
|
QCH_CON_DPU_QCH_DPU_DPP_CLOCK_REQ,
|
|
QCH_CON_DPU_QCH_DPU_DPP_EXPIRE_VAL,
|
|
QCH_CON_DPU_QCH_DPU_DPP_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPU_QCH_DPU_WB_MUX_ENABLE,
|
|
QCH_CON_DPU_QCH_DPU_WB_MUX_CLOCK_REQ,
|
|
QCH_CON_DPU_QCH_DPU_WB_MUX_EXPIRE_VAL,
|
|
QCH_CON_DPU_QCH_DPU_WB_MUX_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DPU_CMU_DPU_QCH_ENABLE,
|
|
QCH_CON_DPU_CMU_DPU_QCH_CLOCK_REQ,
|
|
QCH_CON_DPU_CMU_DPU_QCH_EXPIRE_VAL,
|
|
QCH_CON_DPU_CMU_DPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_DPU_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_DPU_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_DPU_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_DPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D0_DPU_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D0_DPU_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D0_DPU_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D0_DPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D1_DPU_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D1_DPU_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D1_DPU_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D1_DPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D2_DPU_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D2_DPU_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D2_DPU_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D2_DPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_DPUD0_QCH_ENABLE,
|
|
QCH_CON_PPMU_DPUD0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_DPUD0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_DPUD0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_DPUD1_QCH_ENABLE,
|
|
QCH_CON_PPMU_DPUD1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_DPUD1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_DPUD1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_DPUD2_QCH_ENABLE,
|
|
QCH_CON_PPMU_DPUD2_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_DPUD2_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_DPUD2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_DPUD0_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_DPUD0_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_DPUD0_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_DPUD0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_DPUD1_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_DPUD1_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_DPUD1_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_DPUD1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_DPUD2_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_DPUD2_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_DPUD2_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_DPUD2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_DPU_QCH_ENABLE,
|
|
QCH_CON_SYSREG_DPU_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_DPU_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_DPU_QCH_IGNORE_FORCE_PM_EN,
|
|
CLK_CON_DIV_DIV_CLK_DSPM_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_DSPM_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DSPM_BUSP_DIVRATIO,
|
|
PLL_CON0_MUX_CLKCMU_DSPM_BUS_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_DSPM_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_DSPM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSPM_UID_DSPM_CMU_DSPM_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSPM_UID_DSPM_CMU_DSPM_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSPM_UID_DSPM_CMU_DSPM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSREG_DSPM_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSREG_DSPM_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSREG_DSPM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AXI2APB_DSPM_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AXI2APB_DSPM_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AXI2APB_DSPM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_DSPM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_DSPM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_DSPM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D0_DSPM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D0_DSPM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D0_DSPM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSD_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSD_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_IVADSPM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_IVADSPM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_IVADSPM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMIVA_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMIVA_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMIVA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_WRAP2_CONV_DSPM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_WRAP2_CONV_DSPM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_WRAP2_CONV_DSPM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D1_DSPM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D1_DSPM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D1_DSPM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLKCMU_DSPS_BUS_CG_VAL,
|
|
CLK_CON_GAT_CLKCMU_DSPS_BUS_MANUAL,
|
|
CLK_CON_GAT_CLKCMU_DSPS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_ADM_APB_DSPM_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_ADM_APB_DSPM_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_ADM_APB_DSPM_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D0_DSPSDSPM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D0_DSPSDSPM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D0_DSPSDSPM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D1_DSPSDSPM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D1_DSPSDSPM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D1_DSPSDSPM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_XIU_P_DSPM_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_XIU_P_DSPM_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_XIU_P_DSPM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_PGEN_LITE_DSPM_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_PGEN_LITE_DSPM_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_PGEN_LITE_DSPM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D2_DSPM_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D2_DSPM_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D2_DSPM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_SCORE_MASTER_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_SCORE_MASTER_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPM_UID_SCORE_MASTER_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
DMYQCH_CON_ADM_APB_DSPM_QCH_ENABLE,
|
|
DMYQCH_CON_ADM_APB_DSPM_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_ADM_APB_DSPM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BTM_DSPM0_QCH_ENABLE,
|
|
QCH_CON_BTM_DSPM0_QCH_CLOCK_REQ,
|
|
QCH_CON_BTM_DSPM0_QCH_EXPIRE_VAL,
|
|
QCH_CON_BTM_DSPM0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BTM_DSPM1_QCH_ENABLE,
|
|
QCH_CON_BTM_DSPM1_QCH_CLOCK_REQ,
|
|
QCH_CON_BTM_DSPM1_QCH_EXPIRE_VAL,
|
|
QCH_CON_BTM_DSPM1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DSPM_CMU_DSPM_QCH_ENABLE,
|
|
QCH_CON_DSPM_CMU_DSPM_QCH_CLOCK_REQ,
|
|
QCH_CON_DSPM_CMU_DSPM_QCH_EXPIRE_VAL,
|
|
QCH_CON_DSPM_CMU_DSPM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D0_DSPSDSPM_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D0_DSPSDSPM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D0_DSPSDSPM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D0_DSPSDSPM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D1_DSPSDSPM_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D1_DSPSDSPM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D1_DSPSDSPM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D1_DSPSDSPM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_DSPM_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_DSPM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_DSPM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_DSPM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_IVADSPM_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_IVADSPM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_IVADSPM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_IVADSPM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ACEL_D0_DSPM_QCH_ENABLE,
|
|
QCH_CON_LHS_ACEL_D0_DSPM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ACEL_D0_DSPM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ACEL_D0_DSPM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ACEL_D1_DSPM_QCH_ENABLE,
|
|
QCH_CON_LHS_ACEL_D1_DSPM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ACEL_D1_DSPM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ACEL_D1_DSPM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ACEL_D2_DSPM_QCH_ENABLE,
|
|
QCH_CON_LHS_ACEL_D2_DSPM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ACEL_D2_DSPM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ACEL_D2_DSPM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_DSPMDSPS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_DSPMDSPS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_DSPMDSPS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_DSPMDSPS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_DSPMIVA_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_DSPMIVA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_DSPMIVA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_DSPMIVA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PGEN_LITE_DSPM_QCH_ENABLE,
|
|
QCH_CON_PGEN_LITE_DSPM_QCH_CLOCK_REQ,
|
|
QCH_CON_PGEN_LITE_DSPM_QCH_EXPIRE_VAL,
|
|
QCH_CON_PGEN_LITE_DSPM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_DSPM0_QCH_ENABLE,
|
|
QCH_CON_PPMU_DSPM0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_DSPM0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_DSPM0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_DSPM1_QCH_ENABLE,
|
|
QCH_CON_PPMU_DSPM1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_DSPM1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_DSPM1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SCORE_MASTER_QCH_ENABLE,
|
|
QCH_CON_SCORE_MASTER_QCH_CLOCK_REQ,
|
|
QCH_CON_SCORE_MASTER_QCH_EXPIRE_VAL,
|
|
QCH_CON_SCORE_MASTER_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_DSPM0_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_DSPM0_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_DSPM0_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_DSPM0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_DSPM1_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_DSPM1_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_DSPM1_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_DSPM1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_DSPM_QCH_ENABLE,
|
|
QCH_CON_SYSREG_DSPM_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_DSPM_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_DSPM_QCH_IGNORE_FORCE_PM_EN,
|
|
CLK_CON_DIV_DIV_CLK_DSPS_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_DSPS_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_DSPS_BUSP_DIVRATIO,
|
|
PLL_CON0_MUX_CLKCMU_DSPS_BUS_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_DSPS_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_DSPS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_DSPS_UID_DSPS_CMU_DSPS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_DSPS_UID_DSPS_CMU_DSPS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_DSPS_UID_DSPS_CMU_DSPS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPS_UID_AXI2APB_DSPS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPS_UID_AXI2APB_DSPS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPS_UID_AXI2APB_DSPS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPS_UID_LHM_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPS_UID_LHM_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPS_UID_LHM_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPS_UID_SYSREG_DSPS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPS_UID_SYSREG_DSPS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPS_UID_SYSREG_DSPS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_DSPS_UID_RSTNSYNC_CLK_DSPS_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPS_UID_RSTNSYNC_CLK_DSPS_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_DSPS_UID_RSTNSYNC_CLK_DSPS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_DSPS_AUD_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_DSPS_AUD_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_DSPS_AUD_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_DSPS_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_DSPS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_DSPS_BUS_SELECT,
|
|
QCH_CON_DSPS_CMU_DSPS_QCH_ENABLE,
|
|
QCH_CON_DSPS_CMU_DSPS_QCH_CLOCK_REQ,
|
|
QCH_CON_DSPS_CMU_DSPS_QCH_EXPIRE_VAL,
|
|
QCH_CON_DSPS_CMU_DSPS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_IVADSPS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_IVADSPS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_IVADSPS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_IVADSPS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_DSPMDSPS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_DSPMDSPS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_DSPMDSPS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_DSPMDSPS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D0_DSPSDSPM_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D0_DSPSDSPM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D0_DSPSDSPM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D0_DSPSDSPM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D1_DSPSDSPM_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D1_DSPSDSPM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D1_DSPSDSPM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D1_DSPSDSPM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_DSPSIVA_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_DSPSIVA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_DSPSIVA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_DSPSIVA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SCORE_KNIGHT_QCH_ENABLE,
|
|
QCH_CON_SCORE_KNIGHT_QCH_CLOCK_REQ,
|
|
QCH_CON_SCORE_KNIGHT_QCH_EXPIRE_VAL,
|
|
QCH_CON_SCORE_KNIGHT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_DSPS_QCH_ENABLE,
|
|
QCH_CON_SYSREG_DSPS_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_DSPS_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_DSPS_QCH_IGNORE_FORCE_PM_EN,
|
|
PLL_CON0_MUX_CLKCMU_FSYS0_UFS_EMBD_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_FSYS0_UFS_EMBD_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_FSYS0_UFS_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_FSYS0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_FSYS0_USB30DRD_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_FSYS0_USB30DRD_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_FSYS0_USB30DRD_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USB30DRD_REF_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USB30DRD_REF_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USB30DRD_REF_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_FSYS0_DPGTC_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_FSYS0_DPGTC_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_FSYS0_DPGTC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_FSYS0_USBDP_DEBUG_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_FSYS0_USBDP_DEBUG_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_FSYS0_USBDP_DEBUG_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_BTM_FSYS0_QCH_ENABLE,
|
|
QCH_CON_BTM_FSYS0_QCH_CLOCK_REQ,
|
|
QCH_CON_BTM_FSYS0_QCH_EXPIRE_VAL,
|
|
QCH_CON_BTM_FSYS0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DP_LINK_QCH_ENABLE,
|
|
QCH_CON_DP_LINK_QCH_CLOCK_REQ,
|
|
QCH_CON_DP_LINK_QCH_EXPIRE_VAL,
|
|
QCH_CON_DP_LINK_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DP_LINK_QCH_GTC_ENABLE,
|
|
QCH_CON_DP_LINK_QCH_GTC_CLOCK_REQ,
|
|
QCH_CON_DP_LINK_QCH_GTC_EXPIRE_VAL,
|
|
QCH_CON_DP_LINK_QCH_GTC_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ETR_MIU_QCH_PCLK_ENABLE,
|
|
QCH_CON_ETR_MIU_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_ETR_MIU_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_ETR_MIU_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ETR_MIU_QCH_ACLK_ENABLE,
|
|
QCH_CON_ETR_MIU_QCH_ACLK_CLOCK_REQ,
|
|
QCH_CON_ETR_MIU_QCH_ACLK_EXPIRE_VAL,
|
|
QCH_CON_ETR_MIU_QCH_ACLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_FSYS0_CMU_FSYS0_QCH_ENABLE,
|
|
QCH_CON_FSYS0_CMU_FSYS0_QCH_CLOCK_REQ,
|
|
QCH_CON_FSYS0_CMU_FSYS0_QCH_EXPIRE_VAL,
|
|
QCH_CON_FSYS0_CMU_FSYS0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GPIO_FSYS0_QCH_ENABLE,
|
|
QCH_CON_GPIO_FSYS0_QCH_CLOCK_REQ,
|
|
QCH_CON_GPIO_FSYS0_QCH_EXPIRE_VAL,
|
|
QCH_CON_GPIO_FSYS0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_G_ETR_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_G_ETR_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_G_ETR_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_G_ETR_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_FSYS0_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_FSYS0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_FSYS0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_FSYS0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ACEL_D_FSYS0_QCH_ENABLE,
|
|
QCH_CON_LHS_ACEL_D_FSYS0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ACEL_D_FSYS0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ACEL_D_FSYS0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PGEN_LITE_FSYS0_QCH_ENABLE,
|
|
QCH_CON_PGEN_LITE_FSYS0_QCH_CLOCK_REQ,
|
|
QCH_CON_PGEN_LITE_FSYS0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PGEN_LITE_FSYS0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_FSYS0_QCH_ENABLE,
|
|
QCH_CON_PPMU_FSYS0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_FSYS0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_FSYS0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_FSYS0_QCH_ENABLE,
|
|
QCH_CON_SYSREG_FSYS0_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_FSYS0_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_FSYS0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_UFS_EMBD_QCH_ENABLE,
|
|
QCH_CON_UFS_EMBD_QCH_CLOCK_REQ,
|
|
QCH_CON_UFS_EMBD_QCH_EXPIRE_VAL,
|
|
QCH_CON_UFS_EMBD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_UFS_EMBD_QCH_FMP_ENABLE,
|
|
QCH_CON_UFS_EMBD_QCH_FMP_CLOCK_REQ,
|
|
QCH_CON_UFS_EMBD_QCH_FMP_EXPIRE_VAL,
|
|
QCH_CON_UFS_EMBD_QCH_FMP_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USB30DRD_QCH_USB30DRD_LINK_ENABLE,
|
|
QCH_CON_USB30DRD_QCH_USB30DRD_LINK_CLOCK_REQ,
|
|
QCH_CON_USB30DRD_QCH_USB30DRD_LINK_EXPIRE_VAL,
|
|
QCH_CON_USB30DRD_QCH_USB30DRD_LINK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USB30DRD_QCH_USBPCS_ENABLE,
|
|
QCH_CON_USB30DRD_QCH_USBPCS_CLOCK_REQ,
|
|
QCH_CON_USB30DRD_QCH_USBPCS_EXPIRE_VAL,
|
|
QCH_CON_USB30DRD_QCH_USBPCS_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USB30DRD_QCH_USB30DRD_CTRL_ENABLE,
|
|
QCH_CON_USB30DRD_QCH_USB30DRD_CTRL_CLOCK_REQ,
|
|
QCH_CON_USB30DRD_QCH_USB30DRD_CTRL_EXPIRE_VAL,
|
|
QCH_CON_USB30DRD_QCH_USB30DRD_CTRL_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USB30DRD_QCH_USBDPPHY_ENABLE,
|
|
QCH_CON_USB30DRD_QCH_USBDPPHY_CLOCK_REQ,
|
|
QCH_CON_USB30DRD_QCH_USBDPPHY_EXPIRE_VAL,
|
|
QCH_CON_USB30DRD_QCH_USBDPPHY_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_USB30DRD_QCH_SOC_PLL_ENABLE,
|
|
DMYQCH_CON_USB30DRD_QCH_SOC_PLL_CLOCK_REQ,
|
|
DMYQCH_CON_USB30DRD_QCH_SOC_PLL_IGNORE_FORCE_PM_EN,
|
|
PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_FSYS1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_FSYS1_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_FSYS1_PCIE_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_FSYS1_PCIE_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_FSYS1_PCIE_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_FSYS1_UFS_CARD_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_FSYS1_UFS_CARD_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_FSYS1_UFS_CARD_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSMMU_FSYS1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSMMU_FSYS1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSMMU_FSYS1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PGEN_LITE_FSYS1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PGEN_LITE_FSYS1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PGEN_LITE_FSYS1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_DBI_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_DBI_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_DBI_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_IEEE1500_WRAPPER_FOR_QCHANNEL_WRAPPER_FOR_PCIEG3_PHY_X1_TOP_INST_0_I_APB_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_IEEE1500_WRAPPER_FOR_QCHANNEL_WRAPPER_FOR_PCIEG3_PHY_X1_TOP_INST_0_I_APB_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_IEEE1500_WRAPPER_FOR_QCHANNEL_WRAPPER_FOR_PCIEG3_PHY_X1_TOP_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_LT_PCIE3_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_LT_PCIE3_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_LT_PCIE3_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PHY_REFCLK_IN_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PHY_REFCLK_IN_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PIPE42_PCIE_PCS_X1_WRAP_INST_0_I_APB_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PIPE42_PCIE_PCS_X1_WRAP_INST_0_I_APB_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PIPE42_PCIE_PCS_X1_WRAP_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_SLV_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_SLV_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_SLV_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_DBI_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_DBI_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_DBI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_SLV_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_SLV_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_SLV_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_SLV_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_SLV_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_SLV_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_DBI_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_DBI_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_DBI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_MSTR_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_MSTR_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_MSTR_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_ADM_AHB_SSS_QCH_ENABLE,
|
|
QCH_CON_ADM_AHB_SSS_QCH_CLOCK_REQ,
|
|
QCH_CON_ADM_AHB_SSS_QCH_EXPIRE_VAL,
|
|
QCH_CON_ADM_AHB_SSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BTM_FSYS1_QCH_ENABLE,
|
|
QCH_CON_BTM_FSYS1_QCH_CLOCK_REQ,
|
|
QCH_CON_BTM_FSYS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_BTM_FSYS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_FSYS1_CMU_FSYS1_QCH_ENABLE,
|
|
QCH_CON_FSYS1_CMU_FSYS1_QCH_CLOCK_REQ,
|
|
QCH_CON_FSYS1_CMU_FSYS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_FSYS1_CMU_FSYS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GPIO_FSYS1_QCH_ENABLE,
|
|
QCH_CON_GPIO_FSYS1_QCH_CLOCK_REQ,
|
|
QCH_CON_GPIO_FSYS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_GPIO_FSYS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_FSYS1_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_FSYS1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_FSYS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_FSYS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ACEL_D_FSYS1_QCH_ENABLE,
|
|
QCH_CON_LHS_ACEL_D_FSYS1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ACEL_D_FSYS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ACEL_D_FSYS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MMC_CARD_QCH_ENABLE,
|
|
QCH_CON_MMC_CARD_QCH_CLOCK_REQ,
|
|
QCH_CON_MMC_CARD_QCH_EXPIRE_VAL,
|
|
QCH_CON_MMC_CARD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN2_QCH_MSTR_ENABLE,
|
|
QCH_CON_PCIE_GEN2_QCH_MSTR_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN2_QCH_MSTR_EXPIRE_VAL,
|
|
QCH_CON_PCIE_GEN2_QCH_MSTR_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN2_QCH_PCS_ENABLE,
|
|
QCH_CON_PCIE_GEN2_QCH_PCS_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN2_QCH_PCS_EXPIRE_VAL,
|
|
QCH_CON_PCIE_GEN2_QCH_PCS_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN2_QCH_PHY_ENABLE,
|
|
QCH_CON_PCIE_GEN2_QCH_PHY_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN2_QCH_PHY_EXPIRE_VAL,
|
|
QCH_CON_PCIE_GEN2_QCH_PHY_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN2_QCH_DBI_ENABLE,
|
|
QCH_CON_PCIE_GEN2_QCH_DBI_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN2_QCH_DBI_EXPIRE_VAL,
|
|
QCH_CON_PCIE_GEN2_QCH_DBI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN2_QCH_APB_ENABLE,
|
|
QCH_CON_PCIE_GEN2_QCH_APB_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN2_QCH_APB_EXPIRE_VAL,
|
|
QCH_CON_PCIE_GEN2_QCH_APB_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_PCIE_GEN2_QCH_SOCPLL_ENABLE,
|
|
DMYQCH_CON_PCIE_GEN2_QCH_SOCPLL_CLOCK_REQ,
|
|
DMYQCH_CON_PCIE_GEN2_QCH_SOCPLL_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN3_QCH_MSTR_ENABLE,
|
|
QCH_CON_PCIE_GEN3_QCH_MSTR_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN3_QCH_MSTR_EXPIRE_VAL,
|
|
QCH_CON_PCIE_GEN3_QCH_MSTR_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN3_QCH_PCS_ENABLE,
|
|
QCH_CON_PCIE_GEN3_QCH_PCS_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN3_QCH_PCS_EXPIRE_VAL,
|
|
QCH_CON_PCIE_GEN3_QCH_PCS_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN3_QCH_DBI_ENABLE,
|
|
QCH_CON_PCIE_GEN3_QCH_DBI_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN3_QCH_DBI_EXPIRE_VAL,
|
|
QCH_CON_PCIE_GEN3_QCH_DBI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN3_QCH_APB_ENABLE,
|
|
QCH_CON_PCIE_GEN3_QCH_APB_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN3_QCH_APB_EXPIRE_VAL,
|
|
QCH_CON_PCIE_GEN3_QCH_APB_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_PCIE_GEN3_QCH_SOCPLL_ENABLE,
|
|
DMYQCH_CON_PCIE_GEN3_QCH_SOCPLL_CLOCK_REQ,
|
|
DMYQCH_CON_PCIE_GEN3_QCH_SOCPLL_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_GEN3_QCH_PHY_ENABLE,
|
|
QCH_CON_PCIE_GEN3_QCH_PHY_CLOCK_REQ,
|
|
QCH_CON_PCIE_GEN3_QCH_PHY_EXPIRE_VAL,
|
|
QCH_CON_PCIE_GEN3_QCH_PHY_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_IA_GEN2_QCH_ENABLE,
|
|
QCH_CON_PCIE_IA_GEN2_QCH_CLOCK_REQ,
|
|
QCH_CON_PCIE_IA_GEN2_QCH_EXPIRE_VAL,
|
|
QCH_CON_PCIE_IA_GEN2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PCIE_IA_GEN3_QCH_ENABLE,
|
|
QCH_CON_PCIE_IA_GEN3_QCH_CLOCK_REQ,
|
|
QCH_CON_PCIE_IA_GEN3_QCH_EXPIRE_VAL,
|
|
QCH_CON_PCIE_IA_GEN3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PGEN_LITE_FSYS1_QCH_ENABLE,
|
|
QCH_CON_PGEN_LITE_FSYS1_QCH_CLOCK_REQ,
|
|
QCH_CON_PGEN_LITE_FSYS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PGEN_LITE_FSYS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_FSYS1_QCH_ENABLE,
|
|
QCH_CON_PPMU_FSYS1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_FSYS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_FSYS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RTIC_QCH_ENABLE,
|
|
QCH_CON_RTIC_QCH_CLOCK_REQ,
|
|
QCH_CON_RTIC_QCH_EXPIRE_VAL,
|
|
QCH_CON_RTIC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SSS_QCH_ENABLE,
|
|
QCH_CON_SSS_QCH_CLOCK_REQ,
|
|
QCH_CON_SSS_QCH_EXPIRE_VAL,
|
|
QCH_CON_SSS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_FSYS1_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_FSYS1_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_FSYS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_FSYS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_FSYS1_QCH_ENABLE,
|
|
QCH_CON_SYSREG_FSYS1_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_FSYS1_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_FSYS1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_UFS_CARD_QCH_ENABLE,
|
|
QCH_CON_UFS_CARD_QCH_CLOCK_REQ,
|
|
QCH_CON_UFS_CARD_QCH_EXPIRE_VAL,
|
|
QCH_CON_UFS_CARD_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_UFS_CARD_QCH_FMP_ENABLE,
|
|
QCH_CON_UFS_CARD_QCH_FMP_CLOCK_REQ,
|
|
QCH_CON_UFS_CARD_QCH_FMP_EXPIRE_VAL,
|
|
QCH_CON_UFS_CARD_QCH_FMP_IGNORE_FORCE_PM_EN,
|
|
PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_G2D_G2D_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_G2D_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_G2D_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_G2D_BUSP_DIVRATIO,
|
|
PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_G2D_MSCL_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_ASTC_QCH_ENABLE,
|
|
QCH_CON_ASTC_QCH_CLOCK_REQ,
|
|
QCH_CON_ASTC_QCH_EXPIRE_VAL,
|
|
QCH_CON_ASTC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BTM_G2DD0_QCH_ENABLE,
|
|
QCH_CON_BTM_G2DD0_QCH_CLOCK_REQ,
|
|
QCH_CON_BTM_G2DD0_QCH_EXPIRE_VAL,
|
|
QCH_CON_BTM_G2DD0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BTM_G2DD1_QCH_ENABLE,
|
|
QCH_CON_BTM_G2DD1_QCH_CLOCK_REQ,
|
|
QCH_CON_BTM_G2DD1_QCH_EXPIRE_VAL,
|
|
QCH_CON_BTM_G2DD1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BTM_G2DD2_QCH_ENABLE,
|
|
QCH_CON_BTM_G2DD2_QCH_CLOCK_REQ,
|
|
QCH_CON_BTM_G2DD2_QCH_EXPIRE_VAL,
|
|
QCH_CON_BTM_G2DD2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_G2D_QCH_ENABLE,
|
|
QCH_CON_G2D_QCH_CLOCK_REQ,
|
|
QCH_CON_G2D_QCH_EXPIRE_VAL,
|
|
QCH_CON_G2D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_G2D_CMU_G2D_QCH_ENABLE,
|
|
QCH_CON_G2D_CMU_G2D_QCH_CLOCK_REQ,
|
|
QCH_CON_G2D_CMU_G2D_QCH_EXPIRE_VAL,
|
|
QCH_CON_G2D_CMU_G2D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_JPEG_QCH_ENABLE,
|
|
QCH_CON_JPEG_QCH_CLOCK_REQ,
|
|
QCH_CON_JPEG_QCH_EXPIRE_VAL,
|
|
QCH_CON_JPEG_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_G2D_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_G2D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_G2D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_G2D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ACEL_D0_G2D_QCH_ENABLE,
|
|
QCH_CON_LHS_ACEL_D0_G2D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ACEL_D0_G2D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ACEL_D0_G2D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ACEL_D1_G2D_QCH_ENABLE,
|
|
QCH_CON_LHS_ACEL_D1_G2D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ACEL_D1_G2D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ACEL_D1_G2D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ACEL_D2_G2D_QCH_ENABLE,
|
|
QCH_CON_LHS_ACEL_D2_G2D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ACEL_D2_G2D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ACEL_D2_G2D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MSCL_QCH_ENABLE,
|
|
QCH_CON_MSCL_QCH_CLOCK_REQ,
|
|
QCH_CON_MSCL_QCH_EXPIRE_VAL,
|
|
QCH_CON_MSCL_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PGEN100_LITE_G2D_QCH_ENABLE,
|
|
QCH_CON_PGEN100_LITE_G2D_QCH_CLOCK_REQ,
|
|
QCH_CON_PGEN100_LITE_G2D_QCH_EXPIRE_VAL,
|
|
QCH_CON_PGEN100_LITE_G2D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_G2DD0_QCH_ENABLE,
|
|
QCH_CON_PPMU_G2DD0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_G2DD0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_G2DD0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_G2DD1_QCH_ENABLE,
|
|
QCH_CON_PPMU_G2DD1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_G2DD1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_G2DD1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_G2DD2_QCH_ENABLE,
|
|
QCH_CON_PPMU_G2DD2_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_G2DD2_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_G2DD2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_ASTC_QCH_ENABLE,
|
|
QCH_CON_QE_ASTC_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_ASTC_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_ASTC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_JPEG_QCH_ENABLE,
|
|
QCH_CON_QE_JPEG_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_JPEG_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_JPEG_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QE_MSCL_QCH_ENABLE,
|
|
QCH_CON_QE_MSCL_QCH_CLOCK_REQ,
|
|
QCH_CON_QE_MSCL_QCH_EXPIRE_VAL,
|
|
QCH_CON_QE_MSCL_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_G2DD0_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_G2DD0_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_G2DD0_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_G2DD0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_G2DD1_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_G2DD1_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_G2DD1_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_G2DD1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_G2DD2_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_G2DD2_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_G2DD2_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_G2DD2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_G2D_QCH_ENABLE,
|
|
QCH_CON_SYSREG_G2D_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_G2D_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_G2D_QCH_IGNORE_FORCE_PM_EN,
|
|
CLK_CON_DIV_DIV_CLK_G3D_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_G3D_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_G3D_BUSP_DIVRATIO,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D0_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D0_IPCLKPORT_HPM_TARGETCLK_C_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D0_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_G3D_BUSD_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_G3D_BUSD_SELECT,
|
|
CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_PLL_G3D_DIV_P,
|
|
PLL_CON0_PLL_G3D_DIV_M,
|
|
PLL_CON0_PLL_G3D_DIV_S,
|
|
PLL_CON0_PLL_G3D_ENABLE,
|
|
PLL_CON0_PLL_G3D_STABLE,
|
|
PLL_LOCKTIME_PLL_G3D_PLL_LOCK_TIME,
|
|
CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_EMBEDDED_G3D_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_G3D_BUSD_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_G3D_BUSD_DIVRATIO,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_BUSIF_HPMG3D_QCH_ENABLE,
|
|
QCH_CON_BUSIF_HPMG3D_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_HPMG3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_HPMG3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_G3D_CMU_G3D_QCH_ENABLE,
|
|
QCH_CON_G3D_CMU_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_G3D_CMU_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_G3D_CMU_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GPU_QCH_ENABLE,
|
|
QCH_CON_GPU_QCH_CLOCK_REQ,
|
|
QCH_CON_GPU_QCH_EXPIRE_VAL,
|
|
QCH_CON_GPU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_G3DSFR_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_G3DSFR_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_G3DSFR_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_G3DSFR_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_G3D_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ACE_D0_G3D_QCH_ENABLE,
|
|
QCH_CON_LHS_ACE_D0_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ACE_D0_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ACE_D0_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ACE_D1_G3D_QCH_ENABLE,
|
|
QCH_CON_LHS_ACE_D1_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ACE_D1_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ACE_D1_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ACE_D2_G3D_QCH_ENABLE,
|
|
QCH_CON_LHS_ACE_D2_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ACE_D2_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ACE_D2_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ACE_D3_G3D_QCH_ENABLE,
|
|
QCH_CON_LHS_ACE_D3_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ACE_D3_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ACE_D3_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_G3DSFR_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_G3DSFR_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_G3DSFR_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_G3DSFR_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PGEN_LITE_G3D_QCH_ENABLE,
|
|
QCH_CON_PGEN_LITE_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_PGEN_LITE_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_PGEN_LITE_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_G3D_QCH_ENABLE,
|
|
QCH_CON_SYSREG_G3D_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_G3D_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_G3D_QCH_IGNORE_FORCE_PM_EN,
|
|
PLL_CON0_MUX_CLKCMU_ISPHQ_BUS_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_ISPHQ_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_ISPHQ_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP_DIVRATIO,
|
|
CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_BTM_ISPHQ_QCH_ENABLE,
|
|
QCH_CON_BTM_ISPHQ_QCH_CLOCK_REQ,
|
|
QCH_CON_BTM_ISPHQ_QCH_EXPIRE_VAL,
|
|
QCH_CON_BTM_ISPHQ_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ISPHQ_CMU_ISPHQ_QCH_ENABLE,
|
|
QCH_CON_ISPHQ_CMU_ISPHQ_QCH_CLOCK_REQ,
|
|
QCH_CON_ISPHQ_CMU_ISPHQ_QCH_EXPIRE_VAL,
|
|
QCH_CON_ISPHQ_CMU_ISPHQ_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPHQ_QCH_ISPHQ_ENABLE,
|
|
QCH_CON_IS_ISPHQ_QCH_ISPHQ_CLOCK_REQ,
|
|
QCH_CON_IS_ISPHQ_QCH_ISPHQ_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPHQ_QCH_ISPHQ_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPHQ_QCH_SYSMMU_ISPHQ_ENABLE,
|
|
QCH_CON_IS_ISPHQ_QCH_SYSMMU_ISPHQ_CLOCK_REQ,
|
|
QCH_CON_IS_ISPHQ_QCH_SYSMMU_ISPHQ_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPHQ_QCH_SYSMMU_ISPHQ_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPHQ_QCH_PPMU_ISPHQ_ENABLE,
|
|
QCH_CON_IS_ISPHQ_QCH_PPMU_ISPHQ_CLOCK_REQ,
|
|
QCH_CON_IS_ISPHQ_QCH_PPMU_ISPHQ_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPHQ_QCH_PPMU_ISPHQ_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPHQ_QCH_PGEN_LITE_ISPHQ_ENABLE,
|
|
QCH_CON_IS_ISPHQ_QCH_PGEN_LITE_ISPHQ_CLOCK_REQ,
|
|
QCH_CON_IS_ISPHQ_QCH_PGEN_LITE_ISPHQ_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPHQ_QCH_PGEN_LITE_ISPHQ_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPHQ_QCH_ISPHQ_C2COM_ENABLE,
|
|
QCH_CON_IS_ISPHQ_QCH_ISPHQ_C2COM_CLOCK_REQ,
|
|
QCH_CON_IS_ISPHQ_QCH_ISPHQ_C2COM_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPHQ_QCH_ISPHQ_C2COM_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_ISPLPISPHQ_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_ISPLPISPHQ_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_ISPLPISPHQ_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_ISPLPISPHQ_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_ISPPREISPHQ_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_ISPPREISPHQ_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_ISPPREISPHQ_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_ISPPREISPHQ_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_ISPHQ_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_ISPHQ_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_ISPHQ_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_ISPHQ_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_ISPHQDCF_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_ISPHQDCF_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_ISPHQDCF_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_ISPHQDCF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_ISPHQISPLP_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_ISPHQISPLP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_ISPHQISPLP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_ISPHQISPLP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_ISPHQ_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_ISPHQ_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_ISPHQ_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_ISPHQ_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_ISPHQ_QCH_ENABLE,
|
|
QCH_CON_SYSREG_ISPHQ_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_ISPHQ_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_ISPHQ_QCH_IGNORE_FORCE_PM_EN,
|
|
PLL_CON0_MUX_CLKCMU_ISPLP_BUS_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_ISPLP_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_ISPLP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_ISPLP_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_ISPLP_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_ISPLP_BUSP_DIVRATIO,
|
|
CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_ISPLP_VRA_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_ISPLP_VRA_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_ISPLP_VRA_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_ISPLP_GDC_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_ISPLP_GDC_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_ISPLP_GDC_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_BTM_ISPLP0_QCH_ENABLE,
|
|
QCH_CON_BTM_ISPLP0_QCH_CLOCK_REQ,
|
|
QCH_CON_BTM_ISPLP0_QCH_EXPIRE_VAL,
|
|
QCH_CON_BTM_ISPLP0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BTM_ISPLP1_QCH_ENABLE,
|
|
QCH_CON_BTM_ISPLP1_QCH_CLOCK_REQ,
|
|
QCH_CON_BTM_ISPLP1_QCH_EXPIRE_VAL,
|
|
QCH_CON_BTM_ISPLP1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ISPLP_CMU_ISPLP_QCH_ENABLE,
|
|
QCH_CON_ISPLP_CMU_ISPLP_QCH_CLOCK_REQ,
|
|
QCH_CON_ISPLP_CMU_ISPLP_QCH_EXPIRE_VAL,
|
|
QCH_CON_ISPLP_CMU_ISPLP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPLP_QCH_MC_SCALER_ENABLE,
|
|
QCH_CON_IS_ISPLP_QCH_MC_SCALER_CLOCK_REQ,
|
|
QCH_CON_IS_ISPLP_QCH_MC_SCALER_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPLP_QCH_MC_SCALER_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPLP_QCH_ISPLP_ENABLE,
|
|
QCH_CON_IS_ISPLP_QCH_ISPLP_CLOCK_REQ,
|
|
QCH_CON_IS_ISPLP_QCH_ISPLP_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPLP_QCH_ISPLP_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPLP_QCH_QE_ISPLP_ENABLE,
|
|
QCH_CON_IS_ISPLP_QCH_QE_ISPLP_CLOCK_REQ,
|
|
QCH_CON_IS_ISPLP_QCH_QE_ISPLP_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPLP_QCH_QE_ISPLP_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP0_ENABLE,
|
|
QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP0_CLOCK_REQ,
|
|
QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP0_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP0_ENABLE,
|
|
QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP0_CLOCK_REQ,
|
|
QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP0_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP1_ENABLE,
|
|
QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP1_CLOCK_REQ,
|
|
QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP1_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP1_ENABLE,
|
|
QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP1_CLOCK_REQ,
|
|
QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP1_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPLP_QCH_QE_VRA_ENABLE,
|
|
QCH_CON_IS_ISPLP_QCH_QE_VRA_CLOCK_REQ,
|
|
QCH_CON_IS_ISPLP_QCH_QE_VRA_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPLP_QCH_QE_VRA_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPLP_QCH_VRA_ENABLE,
|
|
QCH_CON_IS_ISPLP_QCH_VRA_CLOCK_REQ,
|
|
QCH_CON_IS_ISPLP_QCH_VRA_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPLP_QCH_VRA_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPLP_QCH_GDC_ENABLE,
|
|
QCH_CON_IS_ISPLP_QCH_GDC_CLOCK_REQ,
|
|
QCH_CON_IS_ISPLP_QCH_GDC_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPLP_QCH_GDC_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPLP_QCH_PGEN_LITE_ENABLE,
|
|
QCH_CON_IS_ISPLP_QCH_PGEN_LITE_CLOCK_REQ,
|
|
QCH_CON_IS_ISPLP_QCH_PGEN_LITE_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPLP_QCH_PGEN_LITE_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPLP_QCH_QE_GDC_ENABLE,
|
|
QCH_CON_IS_ISPLP_QCH_QE_GDC_CLOCK_REQ,
|
|
QCH_CON_IS_ISPLP_QCH_QE_GDC_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPLP_QCH_QE_GDC_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPLP_QCH_ISPLP_C2_ENABLE,
|
|
QCH_CON_IS_ISPLP_QCH_ISPLP_C2_CLOCK_REQ,
|
|
QCH_CON_IS_ISPLP_QCH_ISPLP_C2_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPLP_QCH_ISPLP_C2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_DCFISPLP_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_DCFISPLP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_DCFISPLP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_DCFISPLP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_DCRDISPLP_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_DCRDISPLP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_DCRDISPLP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_DCRDISPLP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_ISPHQISPLP_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_ISPHQISPLP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_ISPHQISPLP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_ISPHQISPLP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_ATB_ISPPREISPLP_QCH_ENABLE,
|
|
QCH_CON_LHM_ATB_ISPPREISPLP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_ATB_ISPPREISPLP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_ATB_ISPPREISPLP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_ISPLP_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_ISPLP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_ISPLP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_ISPLP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_ISPLPISPHQ_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_ISPLPISPHQ_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_ISPLPISPHQ_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_ISPLPISPHQ_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D0_ISPLP_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D0_ISPLP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D0_ISPLP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D0_ISPLP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D1_ISPLP_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D1_ISPLP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D1_ISPLP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D1_ISPLP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_ISPLP_QCH_ENABLE,
|
|
QCH_CON_SYSREG_ISPLP_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_ISPLP_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_ISPLP_QCH_IGNORE_FORCE_PM_EN,
|
|
PLL_CON0_MUX_CLKCMU_ISPPRE_BUS_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_ISPPRE_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_ISPPRE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_ISPPRE_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_ISPPRE_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_ISPPRE_BUSP_DIVRATIO,
|
|
CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_BTM_ISPPRE_QCH_ENABLE,
|
|
QCH_CON_BTM_ISPPRE_QCH_CLOCK_REQ,
|
|
QCH_CON_BTM_ISPPRE_QCH_EXPIRE_VAL,
|
|
QCH_CON_BTM_ISPPRE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ISPPRE_CMU_ISPPRE_QCH_ENABLE,
|
|
QCH_CON_ISPPRE_CMU_ISPPRE_QCH_CLOCK_REQ,
|
|
QCH_CON_ISPPRE_CMU_ISPPRE_QCH_EXPIRE_VAL,
|
|
QCH_CON_ISPPRE_CMU_ISPPRE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPPRE_QCH_CSIS0_ENABLE,
|
|
QCH_CON_IS_ISPPRE_QCH_CSIS0_CLOCK_REQ,
|
|
QCH_CON_IS_ISPPRE_QCH_CSIS0_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPPRE_QCH_CSIS0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPPRE_QCH_CSIS1_ENABLE,
|
|
QCH_CON_IS_ISPPRE_QCH_CSIS1_CLOCK_REQ,
|
|
QCH_CON_IS_ISPPRE_QCH_CSIS1_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPPRE_QCH_CSIS1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPPRE_QCH_CSIS2_ENABLE,
|
|
QCH_CON_IS_ISPPRE_QCH_CSIS2_CLOCK_REQ,
|
|
QCH_CON_IS_ISPPRE_QCH_CSIS2_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPPRE_QCH_CSIS2_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPPRE_QCH_CSIS3_ENABLE,
|
|
QCH_CON_IS_ISPPRE_QCH_CSIS3_CLOCK_REQ,
|
|
QCH_CON_IS_ISPPRE_QCH_CSIS3_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPPRE_QCH_CSIS3_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPPRE_QCH_PPMU_ISPPRE_ENABLE,
|
|
QCH_CON_IS_ISPPRE_QCH_PPMU_ISPPRE_CLOCK_REQ,
|
|
QCH_CON_IS_ISPPRE_QCH_PPMU_ISPPRE_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPPRE_QCH_PPMU_ISPPRE_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPPRE_QCH_PDP_DMA_ENABLE,
|
|
QCH_CON_IS_ISPPRE_QCH_PDP_DMA_CLOCK_REQ,
|
|
QCH_CON_IS_ISPPRE_QCH_PDP_DMA_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPPRE_QCH_PDP_DMA_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPPRE_QCH_SYSMMU_ISPPRE_ENABLE,
|
|
QCH_CON_IS_ISPPRE_QCH_SYSMMU_ISPPRE_CLOCK_REQ,
|
|
QCH_CON_IS_ISPPRE_QCH_SYSMMU_ISPPRE_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPPRE_QCH_SYSMMU_ISPPRE_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPPRE_QCH_QE_PDP_ENABLE,
|
|
QCH_CON_IS_ISPPRE_QCH_QE_PDP_CLOCK_REQ,
|
|
QCH_CON_IS_ISPPRE_QCH_QE_PDP_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPPRE_QCH_QE_PDP_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPPRE_QCH_QE_3AA_ENABLE,
|
|
QCH_CON_IS_ISPPRE_QCH_QE_3AA_CLOCK_REQ,
|
|
QCH_CON_IS_ISPPRE_QCH_QE_3AA_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPPRE_QCH_QE_3AA_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPPRE_QCH_QE_3AAM_ENABLE,
|
|
QCH_CON_IS_ISPPRE_QCH_QE_3AAM_CLOCK_REQ,
|
|
QCH_CON_IS_ISPPRE_QCH_QE_3AAM_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPPRE_QCH_QE_3AAM_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPPRE_QCH_3AA_ENABLE,
|
|
QCH_CON_IS_ISPPRE_QCH_3AA_CLOCK_REQ,
|
|
QCH_CON_IS_ISPPRE_QCH_3AA_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPPRE_QCH_3AA_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPPRE_QCH_3AAM_ENABLE,
|
|
QCH_CON_IS_ISPPRE_QCH_3AAM_CLOCK_REQ,
|
|
QCH_CON_IS_ISPPRE_QCH_3AAM_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPPRE_QCH_3AAM_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPPRE_QCH_PDP_CORE0_ENABLE,
|
|
QCH_CON_IS_ISPPRE_QCH_PDP_CORE0_CLOCK_REQ,
|
|
QCH_CON_IS_ISPPRE_QCH_PDP_CORE0_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPPRE_QCH_PDP_CORE0_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPPRE_QCH_PDP_CORE1_ENABLE,
|
|
QCH_CON_IS_ISPPRE_QCH_PDP_CORE1_CLOCK_REQ,
|
|
QCH_CON_IS_ISPPRE_QCH_PDP_CORE1_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPPRE_QCH_PDP_CORE1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPPRE_QCH_PGEN_LITE_ENABLE,
|
|
QCH_CON_IS_ISPPRE_QCH_PGEN_LITE_CLOCK_REQ,
|
|
QCH_CON_IS_ISPPRE_QCH_PGEN_LITE_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPPRE_QCH_PGEN_LITE_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPPRE_QCH_QE_PDP_STAT_ENABLE,
|
|
QCH_CON_IS_ISPPRE_QCH_QE_PDP_STAT_CLOCK_REQ,
|
|
QCH_CON_IS_ISPPRE_QCH_QE_PDP_STAT_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPPRE_QCH_QE_PDP_STAT_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IS_ISPPRE_QCH_PGEN_LITE1_ENABLE,
|
|
QCH_CON_IS_ISPPRE_QCH_PGEN_LITE1_CLOCK_REQ,
|
|
QCH_CON_IS_ISPPRE_QCH_PGEN_LITE1_EXPIRE_VAL,
|
|
QCH_CON_IS_ISPPRE_QCH_PGEN_LITE1_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_ISPPRE_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_ISPPRE_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_ISPPRE_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_ISPPRE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_ISPPREISPHQ_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_ISPPREISPHQ_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_ISPPREISPHQ_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_ISPPREISPHQ_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ATB_ISPPREISPLP_QCH_ENABLE,
|
|
QCH_CON_LHS_ATB_ISPPREISPLP_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ATB_ISPPREISPLP_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ATB_ISPPREISPLP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_ISPPRE_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_ISPPRE_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_ISPPRE_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_ISPPRE_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_ISPPRE_QCH_SYSREG_ENABLE,
|
|
QCH_CON_SYSREG_ISPPRE_QCH_SYSREG_CLOCK_REQ,
|
|
QCH_CON_SYSREG_ISPPRE_QCH_SYSREG_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_ISPPRE_QCH_SYSREG_IGNORE_FORCE_PM_EN,
|
|
PLL_CON0_MUX_CLKCMU_IVA_BUS_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_IVA_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_IVA_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_IVA_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_IVA_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_IVA_BUSP_DIVRATIO,
|
|
CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_PPMU_IVA_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_PPMU_IVA_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_PPMU_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA0_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA0_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_IVA_DEBUG_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_IVA_DEBUG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_IVA_DEBUG_DIVRATIO,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_ADM_DAP_IVA_IPCLKPORT_DAPCLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_ADM_DAP_IVA_IPCLKPORT_DAPCLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_ADM_DAP_IVA_IPCLKPORT_DAPCLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_DEBUG_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_DEBUG_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_DEBUG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA1_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA1_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA2_IPCLKPORT_PCLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA2_IPCLKPORT_PCLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA2_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_PGEN_LITE_IVA_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_PGEN_LITE_IVA_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_PGEN_LITE_IVA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_TREX_RB_IVA_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_TREX_RB_IVA_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_TREX_RB_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_DAP_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_DAP_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_DAP_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
DMYQCH_CON_ADM_DAP_IVA_QCH_ENABLE,
|
|
DMYQCH_CON_ADM_DAP_IVA_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_ADM_DAP_IVA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BTM_IVA_QCH_ENABLE,
|
|
QCH_CON_BTM_IVA_QCH_CLOCK_REQ,
|
|
QCH_CON_BTM_IVA_QCH_EXPIRE_VAL,
|
|
QCH_CON_BTM_IVA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IVA_QCH_IVA_ENABLE,
|
|
QCH_CON_IVA_QCH_IVA_CLOCK_REQ,
|
|
QCH_CON_IVA_QCH_IVA_EXPIRE_VAL,
|
|
QCH_CON_IVA_QCH_IVA_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IVA_QCH_IVA_DEBUG_ENABLE,
|
|
QCH_CON_IVA_QCH_IVA_DEBUG_CLOCK_REQ,
|
|
QCH_CON_IVA_QCH_IVA_DEBUG_EXPIRE_VAL,
|
|
QCH_CON_IVA_QCH_IVA_DEBUG_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IVA_CMU_IVA_QCH_ENABLE,
|
|
QCH_CON_IVA_CMU_IVA_QCH_CLOCK_REQ,
|
|
QCH_CON_IVA_CMU_IVA_QCH_EXPIRE_VAL,
|
|
QCH_CON_IVA_CMU_IVA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_IVA_INTMEM_QCH_ENABLE,
|
|
QCH_CON_IVA_INTMEM_QCH_CLOCK_REQ,
|
|
QCH_CON_IVA_INTMEM_QCH_EXPIRE_VAL,
|
|
QCH_CON_IVA_INTMEM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_DSPSIVA_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_DSPSIVA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_DSPSIVA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_DSPSIVA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_D_IVASC_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_D_IVASC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_D_IVASC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_D_IVASC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_DSPMIVA_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_DSPMIVA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_DSPMIVA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_DSPMIVA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_IVA_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_IVA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_IVA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_IVA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_ACEL_D_IVA_QCH_ENABLE,
|
|
QCH_CON_LHS_ACEL_D_IVA_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_ACEL_D_IVA_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_ACEL_D_IVA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D_IVADSPS_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D_IVADSPS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D_IVADSPS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D_IVADSPS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_P_IVADSPM_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_P_IVADSPM_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_P_IVADSPM_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_P_IVADSPM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PGEN_LITE_IVA_QCH_ENABLE,
|
|
QCH_CON_PGEN_LITE_IVA_QCH_CLOCK_REQ,
|
|
QCH_CON_PGEN_LITE_IVA_QCH_EXPIRE_VAL,
|
|
QCH_CON_PGEN_LITE_IVA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_IVA_QCH_ENABLE,
|
|
QCH_CON_PPMU_IVA_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_IVA_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_IVA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_IVA_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_IVA_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_IVA_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_IVA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_IVA_QCH_ENABLE,
|
|
QCH_CON_SYSREG_IVA_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_IVA_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_IVA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_TREX_RB_IVA_QCH_ENABLE,
|
|
QCH_CON_TREX_RB_IVA_QCH_CLOCK_REQ,
|
|
QCH_CON_TREX_RB_IVA_QCH_EXPIRE_VAL,
|
|
QCH_CON_TREX_RB_IVA_QCH_IGNORE_FORCE_PM_EN,
|
|
PLL_CON0_MUX_CLKCMU_MFC_BUS_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_MFC_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_MFC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_MFC_BUSP_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_MFC_BUSP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_MFC_BUSP_DIVRATIO,
|
|
CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_MFC_WFD_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_MFC_WFD_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_MFC_WFD_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_BTM_MFCD0_QCH_ENABLE,
|
|
QCH_CON_BTM_MFCD0_QCH_CLOCK_REQ,
|
|
QCH_CON_BTM_MFCD0_QCH_EXPIRE_VAL,
|
|
QCH_CON_BTM_MFCD0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BTM_MFCD1_QCH_ENABLE,
|
|
QCH_CON_BTM_MFCD1_QCH_CLOCK_REQ,
|
|
QCH_CON_BTM_MFCD1_QCH_EXPIRE_VAL,
|
|
QCH_CON_BTM_MFCD1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_MFC_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_MFC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_MFC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_MFC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D0_MFC_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D0_MFC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D0_MFC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D0_MFC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHS_AXI_D1_MFC_QCH_ENABLE,
|
|
QCH_CON_LHS_AXI_D1_MFC_QCH_CLOCK_REQ,
|
|
QCH_CON_LHS_AXI_D1_MFC_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHS_AXI_D1_MFC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ATB_QCH_MI_ENABLE,
|
|
QCH_CON_LH_ATB_QCH_MI_CLOCK_REQ,
|
|
QCH_CON_LH_ATB_QCH_MI_EXPIRE_VAL,
|
|
QCH_CON_LH_ATB_QCH_MI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LH_ATB_QCH_SI_ENABLE,
|
|
QCH_CON_LH_ATB_QCH_SI_CLOCK_REQ,
|
|
QCH_CON_LH_ATB_QCH_SI_EXPIRE_VAL,
|
|
QCH_CON_LH_ATB_QCH_SI_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MFC_QCH_ENABLE,
|
|
QCH_CON_MFC_QCH_CLOCK_REQ,
|
|
QCH_CON_MFC_QCH_EXPIRE_VAL,
|
|
QCH_CON_MFC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MFC_CMU_MFC_QCH_ENABLE,
|
|
QCH_CON_MFC_CMU_MFC_QCH_CLOCK_REQ,
|
|
QCH_CON_MFC_CMU_MFC_QCH_EXPIRE_VAL,
|
|
QCH_CON_MFC_CMU_MFC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PGEN100_LITE_MFC_QCH_ENABLE,
|
|
QCH_CON_PGEN100_LITE_MFC_QCH_CLOCK_REQ,
|
|
QCH_CON_PGEN100_LITE_MFC_QCH_EXPIRE_VAL,
|
|
QCH_CON_PGEN100_LITE_MFC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_MFCD0_QCH_ENABLE,
|
|
QCH_CON_PPMU_MFCD0_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_MFCD0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_MFCD0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_MFCD1_QCH_ENABLE,
|
|
QCH_CON_PPMU_MFCD1_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_MFCD1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_MFCD1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PPMU_MFCD2_QCH_ENABLE,
|
|
QCH_CON_PPMU_MFCD2_QCH_CLOCK_REQ,
|
|
QCH_CON_PPMU_MFCD2_QCH_EXPIRE_VAL,
|
|
QCH_CON_PPMU_MFCD2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MI_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MI_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MI_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MI_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_SI_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_SI_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_SI_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_SI_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH_ENABLE,
|
|
QCH_CON_RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH_CLOCK_REQ,
|
|
QCH_CON_RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH_EXPIRE_VAL,
|
|
QCH_CON_RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_MFCD0_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_MFCD0_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_MFCD0_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_MFCD0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSMMU_MFCD1_QCH_ENABLE,
|
|
QCH_CON_SYSMMU_MFCD1_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSMMU_MFCD1_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSMMU_MFCD1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_MFC_QCH_ENABLE,
|
|
QCH_CON_SYSREG_MFC_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_MFC_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_MFC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WFD_QCH_ENABLE,
|
|
QCH_CON_WFD_QCH_CLOCK_REQ,
|
|
QCH_CON_WFD_QCH_EXPIRE_VAL,
|
|
QCH_CON_WFD_QCH_IGNORE_FORCE_PM_EN,
|
|
PLL_CON0_PLL_MIF_DIV_P,
|
|
PLL_CON0_PLL_MIF_DIV_M,
|
|
PLL_CON0_PLL_MIF_DIV_S,
|
|
PLL_CON0_PLL_MIF_ENABLE,
|
|
PLL_CON0_PLL_MIF_STABLE,
|
|
PLL_LOCKTIME_PLL_MIF_PLL_LOCK_TIME,
|
|
CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X_BUSY,
|
|
CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X_SELECT,
|
|
CLK_CON_DIV_CLK_MIF_BUSD_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_MIF_PRE_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_MIF_PRE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_MIF_PRE_DIVRATIO,
|
|
CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_MIF_CMUREF_BUSY,
|
|
CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_MIF_CMUREF_SELECT,
|
|
PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_MIF_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_APBBR_DDRPHY_QCH_ENABLE,
|
|
QCH_CON_APBBR_DDRPHY_QCH_CLOCK_REQ,
|
|
QCH_CON_APBBR_DDRPHY_QCH_EXPIRE_VAL,
|
|
QCH_CON_APBBR_DDRPHY_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APBBR_DMC_QCH_ENABLE,
|
|
QCH_CON_APBBR_DMC_QCH_CLOCK_REQ,
|
|
QCH_CON_APBBR_DMC_QCH_EXPIRE_VAL,
|
|
QCH_CON_APBBR_DMC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_APBBR_DMCTZ_QCH_ENABLE,
|
|
QCH_CON_APBBR_DMCTZ_QCH_CLOCK_REQ,
|
|
QCH_CON_APBBR_DMCTZ_QCH_EXPIRE_VAL,
|
|
QCH_CON_APBBR_DMCTZ_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_BUSIF_HPMMIF_QCH_ENABLE,
|
|
QCH_CON_BUSIF_HPMMIF_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_HPMMIF_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_HPMMIF_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_CMU_MIF_CMUREF_QCH_ENABLE,
|
|
DMYQCH_CON_CMU_MIF_CMUREF_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_CMU_MIF_CMUREF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMC_QCH_ENABLE,
|
|
QCH_CON_DMC_QCH_CLOCK_REQ,
|
|
QCH_CON_DMC_QCH_EXPIRE_VAL,
|
|
QCH_CON_DMC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_MIF_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_MIF_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_MIF_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_MIF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MIF_CMU_MIF_QCH_ENABLE,
|
|
QCH_CON_MIF_CMU_MIF_QCH_CLOCK_REQ,
|
|
QCH_CON_MIF_CMU_MIF_QCH_EXPIRE_VAL,
|
|
QCH_CON_MIF_CMU_MIF_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG_QCH_ENABLE,
|
|
QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG_QCH_CLOCK_REQ,
|
|
QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG_QCH_EXPIRE_VAL,
|
|
QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS_QCH_ENABLE,
|
|
QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS_QCH_CLOCK_REQ,
|
|
QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS_QCH_EXPIRE_VAL,
|
|
QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_MIF_QCH_ENABLE,
|
|
QCH_CON_SYSREG_MIF_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_MIF_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_MIF_QCH_IGNORE_FORCE_PM_EN,
|
|
PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_PERIC0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_XIU_P_PERIC0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_XIU_P_PERIC0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_XIU_P_PERIC0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG_DIVRATIO,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_PERIC0_IP_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI00_USI_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI00_USI_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI00_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI01_USI_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI01_USI_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI01_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI02_USI_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI02_USI_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI02_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI03_USI_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI03_USI_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI03_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI04_USI_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI04_USI_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI04_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI05_USI_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI05_USI_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI05_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI_I2C_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI_I2C_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_UART_DBG_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_UART_DBG_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_UART_DBG_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI12_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI12_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI12_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_DIVRATIO,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI12_USI_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI12_USI_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI12_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI13_USI_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI13_USI_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI13_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI14_USI_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI14_USI_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC0_USI14_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_GPIO_PERIC0_QCH_ENABLE,
|
|
QCH_CON_GPIO_PERIC0_QCH_CLOCK_REQ,
|
|
QCH_CON_GPIO_PERIC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_GPIO_PERIC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_PERIC0_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_PERIC0_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_PERIC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC0_CMU_PERIC0_QCH_ENABLE,
|
|
QCH_CON_PERIC0_CMU_PERIC0_QCH_CLOCK_REQ,
|
|
QCH_CON_PERIC0_CMU_PERIC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_PERIC0_CMU_PERIC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PWM_QCH_ENABLE,
|
|
QCH_CON_PWM_QCH_CLOCK_REQ,
|
|
QCH_CON_PWM_QCH_EXPIRE_VAL,
|
|
QCH_CON_PWM_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_PERIC0_QCH_ENABLE,
|
|
QCH_CON_SYSREG_PERIC0_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_PERIC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_PERIC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_UART_DBG_QCH_ENABLE,
|
|
QCH_CON_UART_DBG_QCH_CLOCK_REQ,
|
|
QCH_CON_UART_DBG_QCH_EXPIRE_VAL,
|
|
QCH_CON_UART_DBG_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI00_I2C_QCH_ENABLE,
|
|
QCH_CON_USI00_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI00_I2C_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI00_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI00_USI_QCH_ENABLE,
|
|
QCH_CON_USI00_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI00_USI_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI00_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI01_I2C_QCH_ENABLE,
|
|
QCH_CON_USI01_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI01_I2C_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI01_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI01_USI_QCH_ENABLE,
|
|
QCH_CON_USI01_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI01_USI_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI01_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI02_I2C_QCH_ENABLE,
|
|
QCH_CON_USI02_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI02_I2C_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI02_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI02_USI_QCH_ENABLE,
|
|
QCH_CON_USI02_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI02_USI_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI02_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI03_I2C_QCH_ENABLE,
|
|
QCH_CON_USI03_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI03_I2C_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI03_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI03_USI_QCH_ENABLE,
|
|
QCH_CON_USI03_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI03_USI_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI03_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI04_I2C_QCH_ENABLE,
|
|
QCH_CON_USI04_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI04_I2C_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI04_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI04_USI_QCH_ENABLE,
|
|
QCH_CON_USI04_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI04_USI_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI04_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI05_I2C_QCH_ENABLE,
|
|
QCH_CON_USI05_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI05_I2C_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI05_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI05_USI_QCH_ENABLE,
|
|
QCH_CON_USI05_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI05_USI_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI05_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI12_I2C_QCH_ENABLE,
|
|
QCH_CON_USI12_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI12_I2C_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI12_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI12_USI_QCH_ENABLE,
|
|
QCH_CON_USI12_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI12_USI_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI12_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI13_I2C_QCH_ENABLE,
|
|
QCH_CON_USI13_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI13_I2C_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI13_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI13_USI_QCH_ENABLE,
|
|
QCH_CON_USI13_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI13_USI_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI13_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI14_I2C_QCH_ENABLE,
|
|
QCH_CON_USI14_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI14_I2C_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI14_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI14_USI_QCH_ENABLE,
|
|
QCH_CON_USI14_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI14_USI_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI14_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_PERIC1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPI_CAM0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPI_CAM0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPI_CAM0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM0_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM0_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM1_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM1_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM2_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM2_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM3_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM3_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM0_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM0_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM1_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM1_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM2_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM2_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM3_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM3_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_SPI_CAM0_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_SPI_CAM0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_SPI_CAM0_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI_DIVRATIO,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_PERIC1_IP_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_UART_BT_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_UART_BT_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI_I2C_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI_I2C_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI_I2C_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI06_USI_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI06_USI_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI06_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI07_USI_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI07_USI_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI07_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI08_USI_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI08_USI_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI08_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM0_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM0_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM1_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM1_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM2_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM2_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM3_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM3_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM3_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_SPI_CAM0_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_SPI_CAM0_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_SPI_CAM0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI09_USI_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI09_USI_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI09_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI10_USI_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI10_USI_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI10_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_DIVRATIO,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI11_USI_CG_VAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI11_USI_MANUAL,
|
|
CLK_CON_GAT_GATE_CLK_PERIC1_USI11_USI_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_IPCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_IPCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_I2C_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_I2C_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_GPIO_PERIC1_QCH_ENABLE,
|
|
QCH_CON_GPIO_PERIC1_QCH_CLOCK_REQ,
|
|
QCH_CON_GPIO_PERIC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_GPIO_PERIC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I2C_CAM0_QCH_ENABLE,
|
|
QCH_CON_I2C_CAM0_QCH_CLOCK_REQ,
|
|
QCH_CON_I2C_CAM0_QCH_EXPIRE_VAL,
|
|
QCH_CON_I2C_CAM0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I2C_CAM1_QCH_ENABLE,
|
|
QCH_CON_I2C_CAM1_QCH_CLOCK_REQ,
|
|
QCH_CON_I2C_CAM1_QCH_EXPIRE_VAL,
|
|
QCH_CON_I2C_CAM1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I2C_CAM2_QCH_ENABLE,
|
|
QCH_CON_I2C_CAM2_QCH_CLOCK_REQ,
|
|
QCH_CON_I2C_CAM2_QCH_EXPIRE_VAL,
|
|
QCH_CON_I2C_CAM2_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_I2C_CAM3_QCH_ENABLE,
|
|
QCH_CON_I2C_CAM3_QCH_CLOCK_REQ,
|
|
QCH_CON_I2C_CAM3_QCH_EXPIRE_VAL,
|
|
QCH_CON_I2C_CAM3_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_PERIC1_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_PERIC1_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_PERIC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIC1_CMU_PERIC1_QCH_ENABLE,
|
|
QCH_CON_PERIC1_CMU_PERIC1_QCH_CLOCK_REQ,
|
|
QCH_CON_PERIC1_CMU_PERIC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_PERIC1_CMU_PERIC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SPI_CAM0_QCH_ENABLE,
|
|
QCH_CON_SPI_CAM0_QCH_CLOCK_REQ,
|
|
QCH_CON_SPI_CAM0_QCH_EXPIRE_VAL,
|
|
QCH_CON_SPI_CAM0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_PERIC1_QCH_ENABLE,
|
|
QCH_CON_SYSREG_PERIC1_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_PERIC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_PERIC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_UART_BT_QCH_ENABLE,
|
|
QCH_CON_UART_BT_QCH_CLOCK_REQ,
|
|
QCH_CON_UART_BT_QCH_EXPIRE_VAL,
|
|
QCH_CON_UART_BT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI06_I2C_QCH_ENABLE,
|
|
QCH_CON_USI06_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI06_I2C_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI06_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI06_USI_QCH_ENABLE,
|
|
QCH_CON_USI06_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI06_USI_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI06_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI07_I2C_QCH_ENABLE,
|
|
QCH_CON_USI07_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI07_I2C_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI07_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI07_USI_QCH_ENABLE,
|
|
QCH_CON_USI07_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI07_USI_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI07_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI08_I2C_QCH_ENABLE,
|
|
QCH_CON_USI08_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI08_I2C_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI08_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI08_USI_QCH_ENABLE,
|
|
QCH_CON_USI08_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI08_USI_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI08_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI09_I2C_QCH_ENABLE,
|
|
QCH_CON_USI09_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI09_I2C_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI09_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI09_USI_QCH_ENABLE,
|
|
QCH_CON_USI09_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI09_USI_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI09_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI10_I2C_QCH_ENABLE,
|
|
QCH_CON_USI10_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI10_I2C_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI10_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI10_USI_QCH_ENABLE,
|
|
QCH_CON_USI10_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI10_USI_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI10_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI11_I2C_QCH_ENABLE,
|
|
QCH_CON_USI11_I2C_QCH_CLOCK_REQ,
|
|
QCH_CON_USI11_I2C_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI11_I2C_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_USI11_USI_QCH_ENABLE,
|
|
QCH_CON_USI11_USI_QCH_CLOCK_REQ,
|
|
QCH_CON_USI11_USI_QCH_EXPIRE_VAL,
|
|
QCH_CON_USI11_USI_QCH_IGNORE_FORCE_PM_EN,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_PERIS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIS_GIC_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_PERIS_GIC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_PERIS_GIC_SELECT,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_BUSIF_TMU_QCH_ENABLE,
|
|
QCH_CON_BUSIF_TMU_QCH_CLOCK_REQ,
|
|
QCH_CON_BUSIF_TMU_QCH_EXPIRE_VAL,
|
|
QCH_CON_BUSIF_TMU_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GIC_QCH_ENABLE,
|
|
QCH_CON_GIC_QCH_CLOCK_REQ,
|
|
QCH_CON_GIC_QCH_EXPIRE_VAL,
|
|
QCH_CON_GIC_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_LHM_AXI_P_PERIS_QCH_ENABLE,
|
|
QCH_CON_LHM_AXI_P_PERIS_QCH_CLOCK_REQ,
|
|
QCH_CON_LHM_AXI_P_PERIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_LHM_AXI_P_PERIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MCT_QCH_ENABLE,
|
|
QCH_CON_MCT_QCH_CLOCK_REQ,
|
|
QCH_CON_MCT_QCH_EXPIRE_VAL,
|
|
QCH_CON_MCT_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_OTP_CON_BIRA_QCH_ENABLE,
|
|
QCH_CON_OTP_CON_BIRA_QCH_CLOCK_REQ,
|
|
QCH_CON_OTP_CON_BIRA_QCH_EXPIRE_VAL,
|
|
QCH_CON_OTP_CON_BIRA_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_OTP_CON_TOP_QCH_ENABLE,
|
|
QCH_CON_OTP_CON_TOP_QCH_CLOCK_REQ,
|
|
QCH_CON_OTP_CON_TOP_QCH_EXPIRE_VAL,
|
|
QCH_CON_OTP_CON_TOP_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_PERIS_CMU_PERIS_QCH_ENABLE,
|
|
QCH_CON_PERIS_CMU_PERIS_QCH_CLOCK_REQ,
|
|
QCH_CON_PERIS_CMU_PERIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_PERIS_CMU_PERIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_PERIS_QCH_ENABLE,
|
|
QCH_CON_SYSREG_PERIS_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_PERIS_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_PERIS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WDT_CLUSTER0_QCH_ENABLE,
|
|
QCH_CON_WDT_CLUSTER0_QCH_CLOCK_REQ,
|
|
QCH_CON_WDT_CLUSTER0_QCH_EXPIRE_VAL,
|
|
QCH_CON_WDT_CLUSTER0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WDT_CLUSTER1_QCH_ENABLE,
|
|
QCH_CON_WDT_CLUSTER1_QCH_CLOCK_REQ,
|
|
QCH_CON_WDT_CLUSTER1_QCH_EXPIRE_VAL,
|
|
QCH_CON_WDT_CLUSTER1_QCH_IGNORE_FORCE_PM_EN,
|
|
PLL_CON0_PLL_MIF_S2D_DIV_P,
|
|
PLL_CON0_PLL_MIF_S2D_DIV_M,
|
|
PLL_CON0_PLL_MIF_S2D_DIV_S,
|
|
PLL_CON0_PLL_MIF_S2D_ENABLE,
|
|
PLL_CON0_PLL_MIF_S2D_STABLE,
|
|
PLL_LOCKTIME_PLL_MIF_S2D_PLL_LOCK_TIME,
|
|
CLK_CON_MUX_CLKCMU_MIF_DDRPHY2X_S2D_BUSY,
|
|
CLK_CON_MUX_CLKCMU_MIF_DDRPHY2X_S2D_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_CLKCMU_MIF_DDRPHY2X_S2D_SELECT,
|
|
CLK_CON_DIV_CLK_MIF_BUSD_S2D_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_S2D_CORE_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_S2D_CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_S2D_CORE_SELECT,
|
|
QCH_CON_S2D_CMU_S2D_QCH_ENABLE,
|
|
QCH_CON_S2D_CMU_S2D_QCH_CLOCK_REQ,
|
|
QCH_CON_S2D_CMU_S2D_QCH_EXPIRE_VAL,
|
|
QCH_CON_S2D_CMU_S2D_QCH_IGNORE_FORCE_PM_EN,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIVRATIO,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIVRATIO,
|
|
CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT0_SELECT,
|
|
CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT0_BUSY,
|
|
CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT1_SELECT,
|
|
CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT1_BUSY,
|
|
CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2_DIVRATIO,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_VTS_BUS_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_VTS_BUS_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_VTS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
PLL_CON0_MUX_CLKCMU_VTS_DLL_USER_BUSY,
|
|
PLL_CON0_MUX_CLKCMU_VTS_DLL_USER_MUX_SEL,
|
|
PLL_CON2_MUX_CLKCMU_VTS_DLL_USER_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_VTS_BUS_BUSY,
|
|
CLK_CON_MUX_MUX_CLK_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_MUX_MUX_CLK_VTS_BUS_SELECT,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IPCLKPORT_CLK_CG_VAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IPCLKPORT_CLK_MANUAL,
|
|
CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_VTS_BUS_BUSY,
|
|
CLK_CON_DIV_DIV_CLK_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING,
|
|
CLK_CON_DIV_DIV_CLK_VTS_BUS_DIVRATIO,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_MUX_IPCLKPORT_D0_CG_VAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_MUX_IPCLKPORT_D0_MANUAL,
|
|
CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_MUX_IPCLKPORT_D0_ENABLE_AUTOMATIC_CLKGATING,
|
|
QCH_CON_AHB_BUSMATRIX_QCH_SYS_ENABLE,
|
|
QCH_CON_AHB_BUSMATRIX_QCH_SYS_CLOCK_REQ,
|
|
QCH_CON_AHB_BUSMATRIX_QCH_SYS_EXPIRE_VAL,
|
|
QCH_CON_AHB_BUSMATRIX_QCH_SYS_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_ASYNCAHBM_VTS_QCH_ENABLE,
|
|
QCH_CON_ASYNCAHBM_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_ASYNCAHBM_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_ASYNCAHBM_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_ENABLE,
|
|
QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_CLOCK_REQ,
|
|
QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_EXPIRE_VAL,
|
|
QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMIC_AHB0_QCH_PCLK_ENABLE,
|
|
QCH_CON_DMIC_AHB0_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DMIC_AHB0_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_DMIC_AHB0_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMIC_AHB1_QCH_PCLK_ENABLE,
|
|
QCH_CON_DMIC_AHB1_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DMIC_AHB1_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_DMIC_AHB1_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_DMIC_IF_QCH_PCLK_ENABLE,
|
|
QCH_CON_DMIC_IF_QCH_PCLK_CLOCK_REQ,
|
|
QCH_CON_DMIC_IF_QCH_PCLK_EXPIRE_VAL,
|
|
QCH_CON_DMIC_IF_QCH_PCLK_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK_ENABLE,
|
|
DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK_CLOCK_REQ,
|
|
DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_GPIO_VTS_QCH_ENABLE,
|
|
QCH_CON_GPIO_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_GPIO_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_GPIO_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HWACG_SYS_DMIC0_QCH_ENABLE,
|
|
QCH_CON_HWACG_SYS_DMIC0_QCH_CLOCK_REQ,
|
|
QCH_CON_HWACG_SYS_DMIC0_QCH_EXPIRE_VAL,
|
|
QCH_CON_HWACG_SYS_DMIC0_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_HWACG_SYS_DMIC1_QCH_ENABLE,
|
|
QCH_CON_HWACG_SYS_DMIC1_QCH_CLOCK_REQ,
|
|
QCH_CON_HWACG_SYS_DMIC1_QCH_EXPIRE_VAL,
|
|
QCH_CON_HWACG_SYS_DMIC1_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_MAILBOX_VTS2CHUB_QCH_ENABLE,
|
|
QCH_CON_MAILBOX_VTS2CHUB_QCH_CLOCK_REQ,
|
|
QCH_CON_MAILBOX_VTS2CHUB_QCH_EXPIRE_VAL,
|
|
QCH_CON_MAILBOX_VTS2CHUB_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_SYSREG_VTS_QCH_ENABLE,
|
|
QCH_CON_SYSREG_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_SYSREG_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_SYSREG_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_VTS_CMU_VTS_QCH_ENABLE,
|
|
QCH_CON_VTS_CMU_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_VTS_CMU_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_VTS_CMU_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
QCH_CON_WDT_VTS_QCH_ENABLE,
|
|
QCH_CON_WDT_VTS_QCH_CLOCK_REQ,
|
|
QCH_CON_WDT_VTS_QCH_EXPIRE_VAL,
|
|
QCH_CON_WDT_VTS_QCH_IGNORE_FORCE_PM_EN,
|
|
DMYQCH_CON_U_DMIC_CLK_MUX_QCH_ENABLE,
|
|
DMYQCH_CON_U_DMIC_CLK_MUX_QCH_CLOCK_REQ,
|
|
DMYQCH_CON_U_DMIC_CLK_MUX_QCH_IGNORE_FORCE_PM_EN,
|
|
/*====================The section of controller option SFR access===================*/
|
|
APM_ENABLE_POWER_MANAGEMENT,
|
|
APM_ENABLE_AUTOMATIC_CLKGATING,
|
|
AUD_ENABLE_POWER_MANAGEMENT,
|
|
AUD_ENABLE_AUTOMATIC_CLKGATING,
|
|
BUS1_ENABLE_POWER_MANAGEMENT,
|
|
BUS1_ENABLE_AUTOMATIC_CLKGATING,
|
|
BUSC_ENABLE_POWER_MANAGEMENT,
|
|
BUSC_ENABLE_AUTOMATIC_CLKGATING,
|
|
CHUB_ENABLE_POWER_MANAGEMENT,
|
|
CHUB_ENABLE_AUTOMATIC_CLKGATING,
|
|
CMGP_ENABLE_POWER_MANAGEMENT,
|
|
CMGP_ENABLE_AUTOMATIC_CLKGATING,
|
|
CMU_ENABLE_POWER_MANAGEMENT,
|
|
CMU_ENABLE_AUTOMATIC_CLKGATING,
|
|
CORE_ENABLE_POWER_MANAGEMENT,
|
|
CORE_ENABLE_AUTOMATIC_CLKGATING,
|
|
CPUCL0_ENABLE_POWER_MANAGEMENT,
|
|
CPUCL0_ENABLE_AUTOMATIC_CLKGATING,
|
|
CPUCL1_ENABLE_POWER_MANAGEMENT,
|
|
CPUCL1_ENABLE_AUTOMATIC_CLKGATING,
|
|
DCF_ENABLE_POWER_MANAGEMENT,
|
|
DCF_ENABLE_AUTOMATIC_CLKGATING,
|
|
DCPOST_ENABLE_POWER_MANAGEMENT,
|
|
DCPOST_ENABLE_AUTOMATIC_CLKGATING,
|
|
DCRD_ENABLE_POWER_MANAGEMENT,
|
|
DCRD_ENABLE_AUTOMATIC_CLKGATING,
|
|
DPU_ENABLE_POWER_MANAGEMENT,
|
|
DPU_ENABLE_AUTOMATIC_CLKGATING,
|
|
DSPM_ENABLE_POWER_MANAGEMENT,
|
|
DSPM_ENABLE_AUTOMATIC_CLKGATING,
|
|
DSPS_ENABLE_POWER_MANAGEMENT,
|
|
DSPS_ENABLE_AUTOMATIC_CLKGATING,
|
|
FSYS0_ENABLE_POWER_MANAGEMENT,
|
|
FSYS0_ENABLE_AUTOMATIC_CLKGATING,
|
|
FSYS1_ENABLE_POWER_MANAGEMENT,
|
|
FSYS1_ENABLE_AUTOMATIC_CLKGATING,
|
|
G2D_ENABLE_POWER_MANAGEMENT,
|
|
G2D_ENABLE_AUTOMATIC_CLKGATING,
|
|
G3D_ENABLE_POWER_MANAGEMENT,
|
|
G3D_ENABLE_AUTOMATIC_CLKGATING,
|
|
ISPHQ_ENABLE_POWER_MANAGEMENT,
|
|
ISPHQ_ENABLE_AUTOMATIC_CLKGATING,
|
|
ISPLP_ENABLE_POWER_MANAGEMENT,
|
|
ISPLP_ENABLE_AUTOMATIC_CLKGATING,
|
|
ISPPRE_ENABLE_POWER_MANAGEMENT,
|
|
ISPPRE_ENABLE_AUTOMATIC_CLKGATING,
|
|
IVA_ENABLE_POWER_MANAGEMENT,
|
|
IVA_ENABLE_AUTOMATIC_CLKGATING,
|
|
MFC_ENABLE_POWER_MANAGEMENT,
|
|
MFC_ENABLE_AUTOMATIC_CLKGATING,
|
|
MIF_ENABLE_POWER_MANAGEMENT,
|
|
MIF_ENABLE_AUTOMATIC_CLKGATING,
|
|
PERIC0_ENABLE_POWER_MANAGEMENT,
|
|
PERIC0_ENABLE_AUTOMATIC_CLKGATING,
|
|
PERIC1_ENABLE_POWER_MANAGEMENT,
|
|
PERIC1_ENABLE_AUTOMATIC_CLKGATING,
|
|
PERIS_ENABLE_POWER_MANAGEMENT,
|
|
PERIS_ENABLE_AUTOMATIC_CLKGATING,
|
|
S2D_ENABLE_POWER_MANAGEMENT,
|
|
S2D_ENABLE_AUTOMATIC_CLKGATING,
|
|
VTS_ENABLE_POWER_MANAGEMENT,
|
|
VTS_ENABLE_AUTOMATIC_CLKGATING,
|
|
end_of_sfr_access,
|
|
num_of_sfr_access = end_of_sfr_access - SFR_ACCESS_TYPE,
|
|
};
|
|
#endif |