7300 lines
708 KiB
C
Executable File
7300 lines
708 KiB
C
Executable File
#include "../cmucal.h"
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#include "cmucal-sfr.h"
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/*=================CMUCAL version: S5E9810================================*/
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/*====================The section of SFR Block instance===================*/
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struct sfr_block cmucal_sfr_block_list[] __initdata = {
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SFR_BLOCK(APM, 0x14000000, 0x8000),
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SFR_BLOCK(AUD, 0x17c00000, 0x8000),
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SFR_BLOCK(BUS1, 0x1a400000, 0x8000),
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SFR_BLOCK(BUSC, 0x1a200000, 0x8000),
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SFR_BLOCK(CHUB, 0x13a00000, 0x8000),
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SFR_BLOCK(CMGP, 0x14200000, 0x8000),
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SFR_BLOCK(CMU, 0x1a240000, 0x8000),
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SFR_BLOCK(CORE, 0x1a020000, 0x8000),
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SFR_BLOCK(CPUCL0, 0x1d000000, 0x8000),
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SFR_BLOCK(CPUCL1, 0x1d100000, 0x8000),
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SFR_BLOCK(DCF, 0x16a00000, 0x8000),
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SFR_BLOCK(DCPOST, 0x16b00000, 0x8000),
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SFR_BLOCK(DCRD, 0x16800000, 0x8000),
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SFR_BLOCK(DPU, 0x16000000, 0x8000),
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SFR_BLOCK(DSPM, 0x16c00000, 0x8000),
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SFR_BLOCK(DSPS, 0x16f00000, 0x8000),
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SFR_BLOCK(FSYS0, 0x11000000, 0x8000),
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SFR_BLOCK(FSYS1, 0x11400000, 0x8000),
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SFR_BLOCK(G2D, 0x17600000, 0x8000),
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SFR_BLOCK(G3D, 0x17400000, 0x8000),
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SFR_BLOCK(ISPHQ, 0x16600000, 0x8000),
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SFR_BLOCK(ISPLP, 0x16400000, 0x8000),
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SFR_BLOCK(ISPPRE, 0x16200000, 0x8000),
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SFR_BLOCK(IVA, 0x17000000, 0x8000),
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SFR_BLOCK(MFC, 0x17800000, 0x8000),
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SFR_BLOCK(MIF, 0x1b800000, 0x8000),
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SFR_BLOCK(PERIC0, 0x10400000, 0x8000),
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SFR_BLOCK(PERIC1, 0x10800000, 0x8000),
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SFR_BLOCK(PERIS, 0x10020000, 0x8000),
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SFR_BLOCK(S2D, 0x14400000, 0x8000),
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SFR_BLOCK(VTS, 0x13800000, 0x8000),
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};
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unsigned int cmucal_sfr_block_size = 31;
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/*====================The section of SFR instance===================*/
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struct sfr cmucal_sfr_list[] __initdata = {
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SFR(PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 0x0100, APM),
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SFR(PLL_CON2_MUX_CLKCMU_APM_BUS_USER, 0x0108, APM),
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SFR(CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0, 0x0810, APM),
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SFR(CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT1, 0x0814, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, 0x2044, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK, 0x2040, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK, 0x2090, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 0x20a0, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, 0x209c, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK, 0x2068, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK, 0x2070, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK, 0x2074, APM),
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SFR(CLK_CON_GAT_CLKCMU_APM_DLL_CHUB, 0x2000, APM),
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SFR(CLK_CON_GAT_GATE_CLKCMU_APM_DLL_VTS, 0x2014, APM),
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SFR(CLK_CON_MUX_MUX_CLK_APM_BUS, 0x1000, APM),
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SFR(CLK_CON_DIV_CLKCMU_APM_DLL_CMGP, 0x1800, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, 0x201c, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, 0x202c, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, 0x2030, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CHUB_IPCLKPORT_I_CLK, 0x2034, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK, 0x203c, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CP_IPCLKPORT_I_CLK, 0x2038, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK, 0x2048, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CHUB_IPCLKPORT_PCLK, 0x206c, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CHUB2CP_IPCLKPORT_PCLK, 0x2078, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CHUB_IPCLKPORT_PCLK, 0x207c, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CP_IPCLKPORT_PCLK, 0x2080, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, 0x208c, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK, 0x2084, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, 0x2094, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 0x20a4, APM),
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SFR(CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, 0x2004, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_P_APM2CMGP_IPCLKPORT_I_CLK, 0x2050, APM),
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SFR(PLL_CON0_MUX_DLL_USER, 0x0120, APM),
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SFR(PLL_CON2_MUX_DLL_USER, 0x0168, APM),
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SFR(CLK_CON_GAT_GATE_CLKCMU_APM_DLL_CMGP, 0x2010, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_APM_IPCLKPORT_CLK, 0x2088, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_CHUB_IPCLKPORT_I_CLK, 0x204c, APM),
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SFR(CLK_CON_DIV_CLKCMU_APM_DLL_VTS, 0x1804, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, 0x2028, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, 0x2018, APM),
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SFR(CLK_CON_DIV_DIV_CLK_APM_BUS, 0x1808, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, 0x2020, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK, 0x2024, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK, 0x2058, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK, 0x205c, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK, 0x2060, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CHUB_IPCLKPORT_PCLK, 0x2054, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2VTS_IPCLKPORT_PCLK, 0x2064, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK, 0x2098, APM),
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SFR(QCH_CON_APBIF_GPIO_ALIVE_QCH, 0x3020, APM),
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SFR(QCH_CON_APBIF_PMU_ALIVE_QCH, 0x3024, APM),
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SFR(QCH_CON_APBIF_RTC_QCH, 0x3028, APM),
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SFR(QCH_CON_APBIF_TOP_RTC_QCH, 0x302c, APM),
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SFR(QCH_CON_APM_CMU_APM_QCH, 0x3030, APM),
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SFR(QCH_CON_GREBEINTEGRATION_QCH_GREBE, 0x3038, APM),
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SFR(QCH_CON_GREBEINTEGRATION_QCH_DBG, 0x3034, APM),
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SFR(QCH_CON_INTMEM_QCH, 0x303c, APM),
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SFR(QCH_CON_LHM_AXI_P_APM_QCH, 0x304c, APM),
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SFR(QCH_CON_LHM_AXI_P_APM_CHUB_QCH, 0x3040, APM),
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SFR(QCH_CON_LHM_AXI_P_APM_CP_QCH, 0x3044, APM),
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SFR(QCH_CON_LHM_AXI_P_APM_GNSS_QCH, 0x3048, APM),
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SFR(QCH_CON_LHS_AXI_D_APM_QCH, 0x3050, APM),
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SFR(QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH, 0x3054, APM),
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SFR(QCH_CON_LHS_AXI_LP_CHUB_QCH, 0x3058, APM),
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SFR(QCH_CON_LHS_AXI_P_APM2CMGP_QCH, 0x305c, APM),
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SFR(QCH_CON_MAILBOX_AP2CHUB_QCH, 0x3060, APM),
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SFR(QCH_CON_MAILBOX_AP2CP_QCH, 0x3064, APM),
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SFR(QCH_CON_MAILBOX_AP2CP_S_QCH, 0x3068, APM),
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SFR(QCH_CON_MAILBOX_AP2GNSS_QCH, 0x306c, APM),
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SFR(QCH_CON_MAILBOX_AP2VTS_QCH, 0x3070, APM),
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SFR(QCH_CON_MAILBOX_APM2AP_QCH, 0x3074, APM),
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SFR(QCH_CON_MAILBOX_APM2CHUB_QCH, 0x3078, APM),
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SFR(QCH_CON_MAILBOX_APM2CP_QCH, 0x307c, APM),
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SFR(QCH_CON_MAILBOX_APM2GNSS_QCH, 0x3080, APM),
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SFR(QCH_CON_MAILBOX_CHUB2CP_QCH, 0x3084, APM),
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SFR(QCH_CON_MAILBOX_GNSS2CHUB_QCH, 0x3088, APM),
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SFR(QCH_CON_MAILBOX_GNSS2CP_QCH, 0x308c, APM),
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SFR(QCH_CON_PEM_QCH, 0x3090, APM),
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SFR(QCH_CON_PGEN_APM_QCH, 0x3094, APM),
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SFR(QCH_CON_PMU_INTR_GEN_QCH, 0x3098, APM),
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SFR(QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH, 0x309c, APM),
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SFR(QCH_CON_SPEEDY_APM_QCH, 0x30a0, APM),
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SFR(QCH_CON_SPEEDY_SUB_APM_QCH, 0x30a4, APM),
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SFR(QCH_CON_SYSREG_APM_QCH, 0x30a8, APM),
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SFR(QCH_CON_WDT_APM_QCH, 0x30ac, APM),
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SFR(PLL_CON0_PLL_AUD, 0x0120, AUD),
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SFR(PLL_CON3_PLL_AUD, 0x018c, AUD),
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SFR(PLL_LOCKTIME_PLL_AUD, 0x0000, AUD),
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SFR(CLK_CON_DIV_DIV_CLK_AUD_PLL, 0x1820, AUD),
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SFR(CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0x1800, AUD),
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SFR(CLK_CON_DIV_DIV_CLK_AUD_CPU_ATCLK, 0x1810, AUD),
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SFR(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0x1814, AUD),
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SFR(CLK_CON_DIV_DIV_CLK_AUD_DSIF, 0x181c, AUD),
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SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0x1824, AUD),
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SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0x1828, AUD),
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SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0x182c, AUD),
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SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 0x1830, AUD),
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SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 0x1010, AUD),
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SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0x100c, AUD),
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SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0x1008, AUD),
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SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0x1004, AUD),
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SFR(PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 0x0100, AUD),
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SFR(PLL_CON2_MUX_CLKCMU_AUD_CPU_USER, 0x0108, AUD),
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SFR(CLK_CON_MUX_MUX_CLK_AUD_CPU, 0x1000, AUD),
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SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0, 0x201c, AUD),
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SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1, 0x2020, AUD),
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SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3, 0x2028, AUD),
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SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF, 0x2018, AUD),
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SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_ATB_AUD_IPCLKPORT_I_CLK, 0x2058, AUD),
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SFR(CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT0, 0x0810, AUD),
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SFR(CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT1, 0x0814, AUD),
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SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ATCLK_IPCLKPORT_CLK, 0x2080, AUD),
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SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK, 0x2088, AUD),
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SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK, 0x208c, AUD),
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SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK, 0x2090, AUD),
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SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK, 0x2094, AUD),
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SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK, 0x2098, AUD),
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SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK, 0x209c, AUD),
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SFR(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0x180c, AUD),
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SFR(CLK_CON_DIV_DIV_CLK_AUD_BUS, 0x1804, AUD),
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SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2, 0x2024, AUD),
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SFR(CLK_CON_DIV_DIV_CLK_AUD_BUSP, 0x1808, AUD),
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SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK, 0x2054, AUD),
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SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS, 0x2064, AUD),
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SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK, 0x2074, AUD),
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SFR(CLK_CON_DIV_DIV_CLK_AUD_DMIC, 0x1818, AUD),
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SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_IPCLKPORT_CLK, 0x2008, AUD),
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SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ATB, 0x2030, AUD),
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SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_DAP_IPCLKPORT_DAPCLK, 0x2010, AUD),
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SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK, 0x2004, AUD),
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SFR(CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU, 0x1014, AUD),
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SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_XIU_P_AUD_IPCLKPORT_ACLK, 0x20b4, AUD),
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SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_IPCLKPORT_PCLKS, 0x203c, AUD),
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SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI2APB_AUD_IPCLKPORT_ACLK, 0x2040, AUD),
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SFR(QCH_CON_ABOX_QCH_ACLK, 0x3024, AUD),
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SFR(QCH_CON_ABOX_QCH_BCLK_DSIF, 0x3038, AUD),
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SFR(QCH_CON_ABOX_QCH_BCLK0, 0x3028, AUD),
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SFR(QCH_CON_ABOX_QCH_BCLK1, 0x302c, AUD),
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SFR(QCH_CON_ABOX_QCH_BCLK2, 0x3030, AUD),
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SFR(QCH_CON_ABOX_QCH_BCLK3, 0x3034, AUD),
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SFR(DMYQCH_CON_ABOX_QCH_DUMMY, 0x3000, AUD),
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SFR(QCH_CON_ABOX_QCH_CCLK_ASB, 0x303c, AUD),
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SFR(QCH_CON_ABOX_QCH_CCLK_ATB, 0x3040, AUD),
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SFR(QCH_CON_AUD_CMU_AUD_QCH, 0x3044, AUD),
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SFR(QCH_CON_BTM_AUD_QCH, 0x3048, AUD),
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SFR(DMYQCH_CON_DFTMUX_AUD_QCH, 0x3004, AUD),
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SFR(DMYQCH_CON_DMIC_QCH, 0x3008, AUD),
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SFR(QCH_CON_GPIO_AUD_QCH, 0x304c, AUD),
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SFR(QCH_CON_LHM_AXI_P_AUD_QCH, 0x3050, AUD),
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SFR(QCH_CON_LHS_ATB_AUD_QCH, 0x3054, AUD),
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SFR(QCH_CON_LHS_AXI_D_AUD_QCH, 0x3058, AUD),
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SFR(QCH_CON_PPMU_AUD_QCH, 0x305c, AUD),
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SFR(QCH_CON_SYSMMU_AUD_QCH, 0x3060, AUD),
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SFR(QCH_CON_SYSREG_AUD_QCH, 0x3064, AUD),
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SFR(QCH_CON_TREX_AUD_QCH, 0x3068, AUD),
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SFR(QCH_CON_WDT_AUD_QCH, 0x306c, AUD),
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SFR(PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER, 0x0100, BUS1),
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SFR(PLL_CON2_MUX_CLKCMU_BUS1_BUS_USER, 0x0108, BUS1),
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SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK, 0x201c, BUS1),
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SFR(CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT0, 0x0810, BUS1),
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SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK, 0x2014, BUS1),
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SFR(CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT1, 0x0814, BUS1),
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SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUS_IPCLKPORT_CLK, 0x2038, BUS1),
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SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK, 0x2004, BUS1),
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SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK, 0x2008, BUS1),
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SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_CHUB_IPCLKPORT_I_CLK, 0x2018, BUS1),
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SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK, 0x2020, BUS1),
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SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_BUS1_IPCLKPORT_I_CLK, 0x2024, BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CHUB_IPCLKPORT_I_CLK, 0x202c, BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CSSYS_IPCLKPORT_I_CLK, 0x2030, BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK, 0x2034, BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK, 0x203c, BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK, 0x2040, BUS1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK, 0x2000, BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK, 0x2010, BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_CHUB_IPCLKPORT_I_PCLK, 0x200c, BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1, 0x2044, BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D_BUS1_IPCLKPORT_ACLK, 0x2048, BUS1),
|
|
SFR(QCH_CON_BAAW_P_CHUB_QCH, 0x3028, BUS1),
|
|
SFR(QCH_CON_BAAW_P_GNSS_QCH, 0x302c, BUS1),
|
|
SFR(QCH_CON_BUS1_CMU_BUS1_QCH, 0x3030, BUS1),
|
|
SFR(QCH_CON_LHM_AXI_D_APM_QCH, 0x3034, BUS1),
|
|
SFR(QCH_CON_LHM_AXI_D_CHUB_QCH, 0x3038, BUS1),
|
|
SFR(QCH_CON_LHM_AXI_D_GNSS_QCH, 0x303c, BUS1),
|
|
SFR(QCH_CON_LHM_AXI_G_CSSYS_QCH, 0x3040, BUS1),
|
|
SFR(QCH_CON_LHS_AXI_D_BUS1_QCH, 0x3044, BUS1),
|
|
SFR(QCH_CON_LHS_AXI_P_CHUB_QCH, 0x304c, BUS1),
|
|
SFR(QCH_CON_LHS_AXI_P_CSSYS_QCH, 0x3050, BUS1),
|
|
SFR(QCH_CON_LHS_AXI_P_GNSS_QCH, 0x3054, BUS1),
|
|
SFR(QCH_CON_SYSREG_BUS1_QCH, 0x3058, BUS1),
|
|
SFR(QCH_CON_TREX_P_BUS1_QCH, 0x305c, BUS1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_BUSC_BUSP, 0x1800, BUSC),
|
|
SFR(PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER, 0x0140, BUSC),
|
|
SFR(PLL_CON2_MUX_CLKCMU_BUSC_BUS_USER, 0x0148, BUSC),
|
|
SFR(CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT0, 0x0810, BUSC),
|
|
SFR(CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT1, 0x0814, BUSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BUSC_UID_HPM_BUSC_IPCLKPORT_HPM_TARGETCLK_C, 0x2004, BUSC),
|
|
SFR(QCH_CON_BUSC_CMU_BUSC_QCH, 0x30b4, BUSC),
|
|
SFR(QCH_CON_BUSIF_CMUTOPC_QCH, 0x30b8, BUSC),
|
|
SFR(QCH_CON_BUSIF_HPMBUSC_QCH, 0x30bc, BUSC),
|
|
SFR(QCH_CON_LHM_ACEL_D0_DSPM_QCH, 0x30c0, BUSC),
|
|
SFR(QCH_CON_LHM_ACEL_D0_G2D_QCH, 0x30c4, BUSC),
|
|
SFR(QCH_CON_LHM_ACEL_D1_DSPM_QCH, 0x30c8, BUSC),
|
|
SFR(QCH_CON_LHM_ACEL_D1_G2D_QCH, 0x30cc, BUSC),
|
|
SFR(QCH_CON_LHM_ACEL_D2_DSPM_QCH, 0x30d0, BUSC),
|
|
SFR(QCH_CON_LHM_ACEL_D2_G2D_QCH, 0x30d4, BUSC),
|
|
SFR(QCH_CON_LHM_ACEL_D_FSYS0_QCH, 0x30d8, BUSC),
|
|
SFR(QCH_CON_LHM_ACEL_D_FSYS1_QCH, 0x30dc, BUSC),
|
|
SFR(QCH_CON_LHM_ACEL_D_IVA_QCH, 0x30e0, BUSC),
|
|
SFR(QCH_CON_LHM_AXI_D0_DPU_QCH, 0x30e4, BUSC),
|
|
SFR(QCH_CON_LHM_AXI_D0_ISPLP_QCH, 0x30e8, BUSC),
|
|
SFR(QCH_CON_LHM_AXI_D0_MFC_QCH, 0x30ec, BUSC),
|
|
SFR(QCH_CON_LHM_AXI_D1_DPU_QCH, 0x30f0, BUSC),
|
|
SFR(QCH_CON_LHM_AXI_D1_ISPLP_QCH, 0x30f4, BUSC),
|
|
SFR(QCH_CON_LHM_AXI_D1_MFC_QCH, 0x30f8, BUSC),
|
|
SFR(QCH_CON_LHM_AXI_D2_DPU_QCH, 0x30fc, BUSC),
|
|
SFR(QCH_CON_LHM_AXI_D_AUD_QCH, 0x3100, BUSC),
|
|
SFR(QCH_CON_LHM_AXI_D_BUS1_QCH, 0x3104, BUSC),
|
|
SFR(QCH_CON_LHM_AXI_D_DCF_QCH, 0x3108, BUSC),
|
|
SFR(QCH_CON_LHM_AXI_D_DCRD_QCH, 0x310c, BUSC),
|
|
SFR(QCH_CON_LHM_AXI_D_ISPHQ_QCH, 0x3110, BUSC),
|
|
SFR(QCH_CON_LHM_AXI_D_ISPPRE_QCH, 0x3114, BUSC),
|
|
SFR(QCH_CON_LHS_AXI_D_IVASC_QCH, 0x3118, BUSC),
|
|
SFR(QCH_CON_LHS_AXI_P_AUD_QCH, 0x311c, BUSC),
|
|
SFR(QCH_CON_LHS_AXI_P_DCF_QCH, 0x3120, BUSC),
|
|
SFR(QCH_CON_LHS_AXI_P_DCRD_QCH, 0x3124, BUSC),
|
|
SFR(QCH_CON_LHS_AXI_P_DPU_QCH, 0x3128, BUSC),
|
|
SFR(QCH_CON_LHS_AXI_P_DSPM_QCH, 0x312c, BUSC),
|
|
SFR(QCH_CON_LHS_AXI_P_FSYS0_QCH, 0x3130, BUSC),
|
|
SFR(QCH_CON_LHS_AXI_P_FSYS1_QCH, 0x3134, BUSC),
|
|
SFR(QCH_CON_LHS_AXI_P_G2D_QCH, 0x3138, BUSC),
|
|
SFR(QCH_CON_LHS_AXI_P_ISPHQ_QCH, 0x313c, BUSC),
|
|
SFR(QCH_CON_LHS_AXI_P_ISPLP_QCH, 0x3140, BUSC),
|
|
SFR(QCH_CON_LHS_AXI_P_ISPPRE_QCH, 0x3144, BUSC),
|
|
SFR(QCH_CON_LHS_AXI_P_IVA_QCH, 0x3148, BUSC),
|
|
SFR(QCH_CON_LHS_AXI_P_MFC_QCH, 0x314c, BUSC),
|
|
SFR(QCH_CON_LHS_AXI_P_MIF0_QCH, 0x3150, BUSC),
|
|
SFR(QCH_CON_LHS_AXI_P_MIF1_QCH, 0x3154, BUSC),
|
|
SFR(QCH_CON_LHS_AXI_P_MIF2_QCH, 0x3158, BUSC),
|
|
SFR(QCH_CON_LHS_AXI_P_MIF3_QCH, 0x315c, BUSC),
|
|
SFR(QCH_CON_LHS_AXI_P_PERIC0_QCH, 0x3160, BUSC),
|
|
SFR(QCH_CON_LHS_AXI_P_PERIC1_QCH, 0x3164, BUSC),
|
|
SFR(QCH_CON_LHS_AXI_P_PERIS_QCH, 0x3168, BUSC),
|
|
SFR(QCH_CON_PDMA0_QCH, 0x316c, BUSC),
|
|
SFR(QCH_CON_PGEN_LITE_BUSC_QCH, 0x3170, BUSC),
|
|
SFR(QCH_CON_PGEN_PDMA0_QCH, 0x3174, BUSC),
|
|
SFR(QCH_CON_PPFW_QCH, 0x3178, BUSC),
|
|
SFR(QCH_CON_SBIC_QCH, 0x317c, BUSC),
|
|
SFR(QCH_CON_SIREX_QCH, 0x3180, BUSC),
|
|
SFR(QCH_CON_SPDMA_QCH, 0x3184, BUSC),
|
|
SFR(QCH_CON_SYSREG_BUSC_QCH, 0x3188, BUSC),
|
|
SFR(QCH_CON_TREX_D_BUSC_QCH, 0x318c, BUSC),
|
|
SFR(QCH_CON_TREX_P_BUSC_QCH, 0x3190, BUSC),
|
|
SFR(QCH_CON_TREX_RB_BUSC_QCH, 0x3194, BUSC),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CHUB_BUS_USER, 0x0100, CHUB),
|
|
SFR(PLL_CON2_MUX_CLKCMU_CHUB_BUS_USER, 0x0108, CHUB),
|
|
SFR(CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT0, 0x0810, CHUB),
|
|
SFR(CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT1, 0x0814, CHUB),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CHUB_DLL_BUS_USER, 0x0120, CHUB),
|
|
SFR(PLL_CON2_MUX_CLKCMU_CHUB_DLL_BUS_USER, 0x0128, CHUB),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CHUB_BUS, 0x1004, CHUB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CHUB_USI01, 0x180c, CHUB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CHUB_I2C, 0x1804, CHUB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CHUB_USI00, 0x1808, CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK, 0x208c, CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI00_IPCLKPORT_CLK, 0x2090, CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI01_IPCLKPORT_CLK, 0x2094, CHUB),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CHUB_I2C, 0x1008, CHUB),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CHUB_USI00, 0x100c, CHUB),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CHUB_USI01, 0x1010, CHUB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CHUB_BUS, 0x1800, CHUB),
|
|
SFR(CLK_CON_GAT_GATE_CLK_CHUB_I2C, 0x200c, CHUB),
|
|
SFR(CLK_CON_GAT_GATE_CLK_CHUB_USI00, 0x2010, CHUB),
|
|
SFR(CLK_CON_GAT_GATE_CLK_CHUB_USI01, 0x2014, CHUB),
|
|
SFR(CLK_CON_MUX_CLK_CHUB_TIMER_FCLK, 0x1000, CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB00_IPCLKPORT_IPCLK, 0x2058, CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB01_IPCLKPORT_IPCLK, 0x2060, CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB00_IPCLKPORT_IPCLK, 0x20a8, CHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB01_IPCLKPORT_IPCLK, 0x20b0, CHUB),
|
|
SFR(QCH_CON_ASYNCAHBM_CHUB_QCH, 0x3010, CHUB),
|
|
SFR(QCH_CON_BAAW_D_CHUB_QCH, 0x3014, CHUB),
|
|
SFR(QCH_CON_BAAW_P_APM_CHUB_QCH, 0x3018, CHUB),
|
|
SFR(QCH_CON_BAAW_S_CHUB_QCH, 0x301c, CHUB),
|
|
SFR(QCH_CON_CHUB_CMU_CHUB_QCH, 0x3020, CHUB),
|
|
SFR(QCH_CON_CM4_CHUB_QCH, 0x3024, CHUB),
|
|
SFR(QCH_CON_GPIO_CHUB_QCH, 0x3028, CHUB),
|
|
SFR(QCH_CON_I2C_CHUB00_QCH, 0x302c, CHUB),
|
|
SFR(QCH_CON_I2C_CHUB01_QCH, 0x3030, CHUB),
|
|
SFR(QCH_CON_LHM_AXI_LP_CHUB_QCH, 0x3034, CHUB),
|
|
SFR(QCH_CON_LHM_AXI_P_CHUB_QCH, 0x3038, CHUB),
|
|
SFR(QCH_CON_LHS_AXI_D_CHUB_QCH, 0x303c, CHUB),
|
|
SFR(QCH_CON_LHS_AXI_P_APM_CHUB_QCH, 0x3040, CHUB),
|
|
SFR(QCH_CON_PDMA_CHUB_QCH, 0x3044, CHUB),
|
|
SFR(QCH_CON_PWM_CHUB_QCH, 0x3048, CHUB),
|
|
SFR(QCH_CON_SWEEPER_D_CHUB_QCH, 0x304c, CHUB),
|
|
SFR(QCH_CON_SWEEPER_P_APM_CHUB_QCH, 0x3050, CHUB),
|
|
SFR(QCH_CON_SYSREG_CHUB_QCH, 0x3054, CHUB),
|
|
SFR(QCH_CON_TIMER_CHUB_QCH, 0x3058, CHUB),
|
|
SFR(QCH_CON_USI_CHUB00_QCH, 0x305c, CHUB),
|
|
SFR(QCH_CON_USI_CHUB01_QCH, 0x3060, CHUB),
|
|
SFR(QCH_CON_WDT_CHUB_QCH, 0x3064, CHUB),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER, 0x0100, CMGP),
|
|
SFR(PLL_CON2_MUX_CLKCMU_CMGP_BUS_USER, 0x0108, CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK, 0x2000, CMGP),
|
|
SFR(CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT0, 0x0810, CMGP),
|
|
SFR(CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT1, 0x0814, CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLK_I2C_CMGP, 0x1008, CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_I2C_CMGP, 0x1804, CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_USI_CMGP01, 0x180c, CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLK_USI_CMGP00, 0x100c, CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLK_USI_CMGP01, 0x1010, CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_USI_CMGP00, 0x1808, CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLK_USI_CMGP02, 0x1014, CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLK_USI_CMGP03, 0x1018, CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_USI_CMGP02, 0x1810, CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_USI_CMGP03, 0x1814, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0, 0x2018, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1, 0x201c, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP0_IPCLKPORT_ACLK, 0x2020, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP1_IPCLKPORT_ACLK, 0x2024, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK, 0x2028, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK, 0x2030, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK, 0x2038, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK, 0x2040, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK, 0x2048, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK, 0x208c, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK, 0x2094, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK, 0x209c, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK, 0x20a4, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK, 0x20ac, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP00_IPCLKPORT_CLK, 0x2054, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK, 0x2050, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP00_IPCLKPORT_CLK, 0x2068, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP01_IPCLKPORT_CLK, 0x206c, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP02_IPCLKPORT_CLK, 0x2070, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP03_IPCLKPORT_CLK, 0x2074, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK, 0x207c, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK, 0x2080, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK, 0x2078, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP01_IPCLKPORT_CLK, 0x2058, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP02_IPCLKPORT_CLK, 0x205c, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP03_IPCLKPORT_CLK, 0x2060, CMGP),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CMGP_DLL_USER, 0x0120, CMGP),
|
|
SFR(PLL_CON2_MUX_CLKCMU_CMGP_DLL_USER, 0x0168, CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CMGP_BUS, 0x1004, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_XIU_P_CMGP_IPCLKPORT_ACLK, 0x20b0, CMGP),
|
|
SFR(CLK_CON_MUX_CLK_CMGP_ADC, 0x1000, CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0x1800, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK, 0x202c, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK, 0x2034, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK, 0x203c, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK, 0x2044, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_P_APM2CMGP_IPCLKPORT_I_CLK, 0x204c, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK, 0x2090, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK, 0x20a0, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK, 0x20a8, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK, 0x2098, CMGP),
|
|
SFR(CLK_CON_GAT_GATE_CLK_I2C_CMGP, 0x2004, CMGP),
|
|
SFR(CLK_CON_GAT_GATE_CLK_USI_CMGP00, 0x2008, CMGP),
|
|
SFR(CLK_CON_GAT_GATE_CLK_USI_CMGP01, 0x200c, CMGP),
|
|
SFR(CLK_CON_GAT_GATE_CLK_USI_CMGP02, 0x2010, CMGP),
|
|
SFR(CLK_CON_GAT_GATE_CLK_USI_CMGP03, 0x2014, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK, 0x2084, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_CHUB_IPCLKPORT_PCLK, 0x2088, CMGP),
|
|
SFR(QCH_CON_ADC_CMGP_QCH_S0, 0x3008, CMGP),
|
|
SFR(QCH_CON_ADC_CMGP_QCH_S1, 0x300c, CMGP),
|
|
SFR(DMYQCH_CON_ADC_CMGP_QCH_ADC, 0x3000, CMGP),
|
|
SFR(QCH_CON_CMGP_CMU_CMGP_QCH, 0x3010, CMGP),
|
|
SFR(QCH_CON_GPIO_CMGP_QCH, 0x3014, CMGP),
|
|
SFR(QCH_CON_I2C_CMGP00_QCH, 0x3018, CMGP),
|
|
SFR(QCH_CON_I2C_CMGP01_QCH, 0x301c, CMGP),
|
|
SFR(QCH_CON_I2C_CMGP02_QCH, 0x3020, CMGP),
|
|
SFR(QCH_CON_I2C_CMGP03_QCH, 0x3024, CMGP),
|
|
SFR(QCH_CON_LHM_AXI_P_APM2CMGP_QCH, 0x3028, CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP_QCH, 0x3040, CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2CHUB_QCH, 0x302c, CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2CP_QCH, 0x3030, CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2GNSS_QCH, 0x3034, CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2PMU_AP_QCH, 0x3038, CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2PMU_CHUB_QCH, 0x303c, CMGP),
|
|
SFR(QCH_CON_USI_CMGP00_QCH, 0x3044, CMGP),
|
|
SFR(QCH_CON_USI_CMGP01_QCH, 0x3048, CMGP),
|
|
SFR(QCH_CON_USI_CMGP02_QCH, 0x304c, CMGP),
|
|
SFR(QCH_CON_USI_CMGP03_QCH, 0x3050, CMGP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 0x2004, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_APM_BUS, 0x1800, CMU),
|
|
SFR(CLK_CON_DIV_DIV_PLL_SHARED0_DIV2, 0x18d4, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0x1878, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0x18b0, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIS_BUS, 0x18c0, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_FSYS0_BUS, 0x184c, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS, 0x2058, CMU),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_DPU_BUS, 0x18cc, CMU),
|
|
SFR(PLL_CON0_PLL_SHARED1, 0x01a0, CMU),
|
|
SFR(PLL_LOCKTIME_PLL_SHARED1, 0x0008, CMU),
|
|
SFR(CLK_CON_DIV_DIV_PLL_SHARED1_DIV2, 0x18e0, CMU),
|
|
SFR(CLK_CON_GAT_CLKCMU_MIF_SWITCH, 0x2000, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_BUS1_BUS, 0x1808, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0x100c, CMU),
|
|
SFR(CLK_CON_DIV_DIV_PLL_SHARED2_DIV2, 0x18ec, CMU),
|
|
SFR(CLK_CON_DIV_DIV_PLL_SHARED3_DIV2, 0x18f0, CMU),
|
|
SFR(CLK_CON_DIV_DIV_PLL_SHARED4_DIV2, 0x18f4, CMU),
|
|
SFR(PLL_CON0_PLL_SHARED4, 0x0320, CMU),
|
|
SFR(PLL_LOCKTIME_PLL_SHARED4, 0x0014, CMU),
|
|
SFR(CLK_CON_DIV_DIV_PLL_SHARED0_DIV4, 0x18dc, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MFC_BUS, 0x109c, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_MFC_BUS, 0x1898, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MFC_BUS, 0x20a4, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 0x207c, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_G2D_G2D, 0x1870, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS0_USB30DRD, 0x1060, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS0_USB30DRD, 0x2064, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_FSYS0_USB30DRD, 0x1858, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD, 0x1854, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD, 0x2060, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD, 0x105c, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD, 0x1864, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_FSYS1_BUS, 0x1860, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS, 0x206c, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD, 0x2070, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 0x204c, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 0x2084, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS, 0x20c8, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS, 0x2028, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_CMGP_BUS, 0x1824, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS, 0x1028, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DSPM_BUS, 0x2050, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_DSPM_BUS, 0x1844, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 0x20b8, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0x18b8, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 0x20c0, CMU),
|
|
SFR(PLL_CON0_PLL_SHARED3, 0x02a0, CMU),
|
|
SFR(PLL_LOCKTIME_PLL_SHARED3, 0x0010, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS, 0x2010, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS, 0x1010, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_BUSC_BUS, 0x180c, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0x1078, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 0x200c, CMU),
|
|
SFR(PLL_CON0_PLL_SHARED2, 0x0220, CMU),
|
|
SFR(PLL_LOCKTIME_PLL_SHARED2, 0x000c, CMU),
|
|
SFR(PLL_CON0_PLL_SHARED0, 0x0120, CMU),
|
|
SFR(PLL_LOCKTIME_PLL_SHARED0, 0x0004, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD, 0x106c, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_DSPM_BUS, 0x104c, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0x1834, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 0x2038, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 0x2034, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0x1034, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0x1830, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_CORE_BUS, 0x1828, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 0x202c, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0x102c, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0x10a8, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_ISPPRE_BUS, 0x1094, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_ISPPRE_BUS, 0x209c, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_ISPPRE_BUS, 0x1890, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS, 0x1088, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_ISPLP_BUS, 0x1884, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS, 0x2090, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_ISPHQ_BUS, 0x1880, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS, 0x1084, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS, 0x208c, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_AUD_CPU, 0x2008, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0x1008, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_AUD_CPU, 0x1804, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 0x2080, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_G2D_MSCL, 0x1874, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0x107c, CMU),
|
|
SFR(CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT0, 0x0810, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_HPM, 0x1080, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_HPM, 0x187c, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_HPM, 0x2088, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE, 0x2074, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_FSYS1_PCIE, 0x1868, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS, 0x1030, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 0x2030, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS, 0x182c, CMU),
|
|
SFR(CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT1, 0x0814, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS, 0x1054, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0x1018, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 0x2018, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_CIS_CLK0, 0x1814, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 0x201c, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 0x2024, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 0x2020, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_CIS_CLK1, 0x1818, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_CIS_CLK2, 0x181c, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_CIS_CLK3, 0x1820, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0x101c, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0x1020, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0x1024, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_OTP, 0x18ac, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_IVA_BUS, 0x1098, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_IVA_BUS, 0x20a0, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_IVA_BUS, 0x1894, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD, 0x1074, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD, 0x2078, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD, 0x186c, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CMU_CMUREF, 0x10c8, CMU),
|
|
SFR(CLK_CON_DIV_DIV_PLL_SHARED1_DIV4, 0x18e8, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0x10ac, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0x10b4, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS, 0x10bc, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_FSYS0_DPGTC, 0x1850, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC, 0x205c, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0, 0x20b0, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1, 0x20b4, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_MODEM_SHARED0, 0x18a4, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_MODEM_SHARED1, 0x18a8, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_DCRD_BUS, 0x1840, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DCRD_BUS, 0x2044, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_DCRD_BUS, 0x1044, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC, 0x1058, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE, 0x1070, CMU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0x18d0, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 0x1014, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_CHUB_BUS, 0x1810, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 0x2014, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_DCF_BUS, 0x1838, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DCF_BUS, 0x203c, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_DCF_BUS, 0x103c, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0x1004, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS, 0x1068, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CMU_CMUREF, 0x10c4, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0x1038, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_VTS_BUS, 0x10c0, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_VTS_BUS, 0x20cc, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_VTS_BUS, 0x18c4, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_ISPLP_VRA, 0x1090, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_ISPLP_VRA, 0x2098, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_ISPLP_VRA, 0x188c, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, 0x10a0, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MFC_WFD, 0x20a8, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_MFC_WFD, 0x189c, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0x10a4, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 0x20ac, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_MIF_BUSP, 0x18a0, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIC0_IP, 0x18b4, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0x10b0, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 0x20bc, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0x10b8, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 0x20c4, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIC1_IP, 0x18bc, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_DCPOST_BUS, 0x1040, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DCPOST_BUS, 0x2040, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_DCPOST_BUS, 0x183c, CMU),
|
|
SFR(PLL_CON0_PLL_MMC, 0x0100, CMU),
|
|
SFR(PLL_CON3_PLL_MMC, 0x010c, CMU),
|
|
SFR(PLL_LOCKTIME_PLL_MMC, 0x0000, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDP_DEBUG, 0x1064, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDP_DEBUG, 0x2068, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_FSYS0_USBDP_DEBUG, 0x185c, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_ISPLP_GDC, 0x1888, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_ISPLP_GDC, 0x2094, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_ISPLP_GDC, 0x108c, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_DSPS_AUD, 0x1050, CMU),
|
|
SFR(CLK_CON_DIV_CLKCMU_DSPS_AUD, 0x1848, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DSPS_AUD, 0x2054, CMU),
|
|
SFR(CLK_CON_DIV_DIV_PLL_SHARED1_DIV3, 0x18e4, CMU),
|
|
SFR(CLK_CON_DIV_DIV_PLL_SHARED0_DIV3, 0x18d8, CMU),
|
|
SFR(CLK_CON_MUX_CLKCMU_DPU_BUS, 0x1000, CMU),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_DPU, 0x18c8, CMU),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DPU, 0x2048, CMU),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0x1048, CMU),
|
|
SFR(DMYQCH_CON_CMU_CMU_CMUREF_QCH, 0x3000, CMU),
|
|
SFR(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0, 0x3004, CMU),
|
|
SFR(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1, 0x3008, CMU),
|
|
SFR(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2, 0x300c, CMU),
|
|
SFR(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3, 0x3010, CMU),
|
|
SFR(DMYQCH_CON_OTP_QCH, 0x3014, CMU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0x1800, CORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK, 0x2000, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK, 0x2120, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK, 0x203c, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMUPPC_CCI_IPCLKPORT_PCLK, 0x20e4, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK, 0x2130, CORE),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 0x0100, CORE),
|
|
SFR(PLL_CON2_MUX_CLKCMU_CORE_BUS_USER, 0x0108, CORE),
|
|
SFR(CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT0, 0x0810, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK, 0x206c, CORE),
|
|
SFR(CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT1, 0x0814, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_IPCLKPORT_PCLK, 0x20ec, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL1_IPCLKPORT_PCLK, 0x20f4, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK, 0x211c, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM, 0x2020, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK, 0x204c, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK, 0x2138, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK, 0x2040, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK, 0x20fc, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK, 0x2104, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK, 0x210c, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK, 0x2114, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK, 0x20b0, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK, 0x20a4, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK, 0x20a8, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK, 0x2128, CORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C, 0x2004, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK, 0x2064, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK, 0x20d0, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CP_IPCLKPORT_I_CLK, 0x20ac, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_G3D_IPCLKPORT_PCLKS, 0x2030, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_IO_IPCLKPORT_PCLKS, 0x2038, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK, 0x2044, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_DP_IPCLKPORT_PCLKS, 0x2028, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE, 0x2134, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE, 0x213c, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BPS_P_G3D_IPCLKPORT_I_CLK, 0x2060, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK, 0x20a0, CORE),
|
|
SFR(QCH_CON_ACE_SLICE_G3D0_QCH, 0x3044, CORE),
|
|
SFR(QCH_CON_ACE_SLICE_G3D1_QCH, 0x3048, CORE),
|
|
SFR(QCH_CON_ACE_SLICE_G3D2_QCH, 0x304c, CORE),
|
|
SFR(QCH_CON_ACE_SLICE_G3D3_QCH, 0x3050, CORE),
|
|
SFR(QCH_CON_BAAW_CP_QCH, 0x3054, CORE),
|
|
SFR(QCH_CON_BDU_QCH, 0x3058, CORE),
|
|
SFR(QCH_CON_BUSIF_HPMCORE_QCH, 0x305c, CORE),
|
|
SFR(DMYQCH_CON_CCI_QCH, 0x3000, CORE),
|
|
SFR(QCH_CON_CORE_CMU_CORE_QCH, 0x3060, CORE),
|
|
SFR(QCH_CON_LHM_ACE_D0_G3D_QCH, 0x3064, CORE),
|
|
SFR(QCH_CON_LHM_ACE_D1_G3D_QCH, 0x3068, CORE),
|
|
SFR(QCH_CON_LHM_ACE_D2_G3D_QCH, 0x306c, CORE),
|
|
SFR(QCH_CON_LHM_ACE_D3_G3D_QCH, 0x3070, CORE),
|
|
SFR(QCH_CON_LHM_ACE_D_CPUCL0_QCH, 0x3074, CORE),
|
|
SFR(QCH_CON_LHM_AXI_D_CP_QCH, 0x3078, CORE),
|
|
SFR(QCH_CON_LHM_AXI_P_CLUSTER0_QCH, 0x307c, CORE),
|
|
SFR(QCH_CON_LHS_ATB_T_BDU_QCH, 0x3080, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_APM_QCH, 0x3084, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_CP_QCH, 0x3090, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_CPUCL0_QCH, 0x3088, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_CPUCL1_QCH, 0x308c, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_G3D_QCH, 0x3094, CORE),
|
|
SFR(QCH_CON_PPCFW_G3D_QCH, 0x3098, CORE),
|
|
SFR(QCH_CON_PPFW_DP_QCH, 0x309c, CORE),
|
|
SFR(QCH_CON_PPFW_G3D_QCH, 0x30a0, CORE),
|
|
SFR(QCH_CON_PPFW_IO_QCH, 0x30a4, CORE),
|
|
SFR(QCH_CON_PPMU_CPUCL0_QCH, 0x30a8, CORE),
|
|
SFR(QCH_CON_PPMU_CPUCL1_QCH, 0x30ac, CORE),
|
|
SFR(QCH_CON_PPMU_G3D0_QCH, 0x30b0, CORE),
|
|
SFR(QCH_CON_PPMU_G3D1_QCH, 0x30b4, CORE),
|
|
SFR(QCH_CON_PPMU_G3D2_QCH, 0x30b8, CORE),
|
|
SFR(QCH_CON_PPMU_G3D3_QCH, 0x30bc, CORE),
|
|
SFR(QCH_CON_SYSREG_CORE_QCH, 0x30c0, CORE),
|
|
SFR(QCH_CON_TREX_D_CORE_QCH, 0x30c4, CORE),
|
|
SFR(QCH_CON_TREX_P0_CORE_QCH, 0x30c8, CORE),
|
|
SFR(QCH_CON_TREX_P1_CORE_QCH, 0x30cc, CORE),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL, 0x100c, CPUCL0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF, 0x1814, CPUCL0),
|
|
SFR(PLL_CON0_PLL_CPUCL0, 0x0140, CPUCL0),
|
|
SFR(PLL_LOCKTIME_PLL_CPUCL0, 0x0000, CPUCL0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, 0x0120, CPUCL0),
|
|
SFR(PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER, 0x0128, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK, 0x2058, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, 0x20e0, CPUCL0),
|
|
SFR(CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT0, 0x0810, CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C, 0x2014, CPUCL0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, 0x1800, CPUCL0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK, 0x1808, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK, 0x2064, CPUCL0),
|
|
SFR(CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT1, 0x0814, CPUCL0),
|
|
SFR(CLK_CON_GAT_GATE_CLK_CPUCL0_CPU, 0x202c, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK, 0x20d8, CPUCL0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG, 0x180c, CPUCL0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_CPU, 0x1818, CPUCL0),
|
|
SFR(CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT0, 0x0818, CPUCL0),
|
|
SFR(CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT1, 0x081c, CPUCL0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK, 0x1810, CPUCL0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER, 0x0100, CPUCL0),
|
|
SFR(PLL_CON2_MUX_CLKCMU_CPUCL0_DBG_BUS_USER, 0x0108, CPUCL0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG, 0x181c, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG, 0x206c, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_BDU_IPCLKPORT_PCLKS, 0x2038, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER0_IPCLKPORT_I_PCLK, 0x2070, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER1_IPCLKPORT_I_PCLK, 0x2074, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK, 0x2098, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK, 0x209c, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK, 0x2078, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK, 0x207c, CPUCL0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK, 0x1820, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER0_IPCLKPORT_PCLKS, 0x203c, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER1_IPCLKPORT_PCLKS, 0x2040, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK, 0x2080, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK, 0x2084, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK, 0x2088, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK, 0x208c, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK, 0x2090, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK, 0x2094, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK, 0x20c0, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK, 0x20bc, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK, 0x20dc, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLKS, 0x2034, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK, 0x20a0, CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK, 0x201c, CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK, 0x2018, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_DSPM_IPCLKPORT_PCLKS, 0x2044, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CSSYS_IPCLKPORT_I_CLK, 0x20a4, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_P_CSSYS_IPCLKPORT_ACLK, 0x205c, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CLUSTER0_IPCLKPORT_I_CLK, 0x20a8, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK, 0x20ac, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK, 0x20b0, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK, 0x20b4, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK, 0x20b8, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM, 0x2030, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI_DS_64TO32_G_CSSYS_IPCLKPORT_ACLK, 0x2060, CPUCL0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CLUSTER0_SCLK, 0x1008, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK, 0x20cc, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK, 0x20d0, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK, 0x20d4, CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK, 0x2010, CPUCL0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLK, 0x1000, CPUCL0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLKP, 0x1804, CPUCL0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLKP, 0x1004, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_P_CLUSTER0_IPCLKPORT_I_CLK, 0x20c4, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLKP_IPCLKPORT_CLK, 0x20c8, CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK, 0x2000, CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK, 0x2004, CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK, 0x2008, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK, 0x2068, CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_SCLK, 0x200c, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKM, 0x2048, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKS, 0x204c, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKM, 0x2050, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKS, 0x2054, CPUCL0),
|
|
SFR(DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH, 0x3000, CPUCL0),
|
|
SFR(QCH_CON_BUSIF_HPMCPUCL0_QCH, 0x3070, CPUCL0),
|
|
SFR(QCH_CON_CLUSTER0_QCH_SCLK, 0x3088, CPUCL0),
|
|
SFR(QCH_CON_CLUSTER0_QCH_ATCLK, 0x3074, CPUCL0),
|
|
SFR(QCH_CON_CLUSTER0_QCH_PDBGCLK, 0x3084, CPUCL0),
|
|
SFR(QCH_CON_CLUSTER0_QCH_GIC, 0x307c, CPUCL0),
|
|
SFR(QCH_CON_CLUSTER0_QCH_DBG_PD, 0x3078, CPUCL0),
|
|
SFR(QCH_CON_CLUSTER0_QCH_PCLK, 0x3080, CPUCL0),
|
|
SFR(DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK, 0x3004, CPUCL0),
|
|
SFR(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH, 0x308c, CPUCL0),
|
|
SFR(QCH_CON_CPUCL0_CMU_CPUCL0_QCH, 0x3090, CPUCL0),
|
|
SFR(QCH_CON_CSSYS_QCH, 0x3094, CPUCL0),
|
|
SFR(QCH_CON_DUMPPC_CLUSTER0_QCH, 0x3098, CPUCL0),
|
|
SFR(QCH_CON_DUMPPC_CLUSTER1_QCH, 0x309c, CPUCL0),
|
|
SFR(QCH_CON_LHM_ATB_T0_CLUSTER0_QCH, 0x30a0, CPUCL0),
|
|
SFR(QCH_CON_LHM_ATB_T0_CLUSTER1_QCH, 0x30a4, CPUCL0),
|
|
SFR(QCH_CON_LHM_ATB_T1_CLUSTER0_QCH, 0x30a8, CPUCL0),
|
|
SFR(QCH_CON_LHM_ATB_T1_CLUSTER1_QCH, 0x30ac, CPUCL0),
|
|
SFR(QCH_CON_LHM_ATB_T2_CLUSTER0_QCH, 0x30b0, CPUCL0),
|
|
SFR(QCH_CON_LHM_ATB_T2_CLUSTER1_QCH, 0x30b4, CPUCL0),
|
|
SFR(QCH_CON_LHM_ATB_T3_CLUSTER0_QCH, 0x30b8, CPUCL0),
|
|
SFR(QCH_CON_LHM_ATB_T3_CLUSTER1_QCH, 0x30bc, CPUCL0),
|
|
SFR(QCH_CON_LHM_ATB_T_AUD_QCH, 0x30c0, CPUCL0),
|
|
SFR(QCH_CON_LHM_ATB_T_BDU_QCH, 0x30c4, CPUCL0),
|
|
SFR(QCH_CON_LHM_AXI_P_CPUCL0_QCH, 0x30c8, CPUCL0),
|
|
SFR(QCH_CON_LHM_AXI_P_CSSYS_QCH, 0x30cc, CPUCL0),
|
|
SFR(QCH_CON_LHS_ACE_D_CLUSTER0_QCH, 0x30d0, CPUCL0),
|
|
SFR(QCH_CON_LHS_ATB_T0_CLUSTER0_QCH, 0x30d4, CPUCL0),
|
|
SFR(QCH_CON_LHS_ATB_T1_CLUSTER0_QCH, 0x30d8, CPUCL0),
|
|
SFR(QCH_CON_LHS_ATB_T2_CLUSTER0_QCH, 0x30dc, CPUCL0),
|
|
SFR(QCH_CON_LHS_ATB_T3_CLUSTER0_QCH, 0x30e0, CPUCL0),
|
|
SFR(QCH_CON_LHS_AXI_G_CSSYS_QCH, 0x30e4, CPUCL0),
|
|
SFR(QCH_CON_LHS_AXI_G_ETR_QCH, 0x30e8, CPUCL0),
|
|
SFR(QCH_CON_LHS_AXI_P_CLUSTER0_QCH, 0x30ec, CPUCL0),
|
|
SFR(QCH_CON_SECJTAG_QCH, 0x30f0, CPUCL0),
|
|
SFR(QCH_CON_SYSREG_CPUCL0_QCH, 0x30f4, CPUCL0),
|
|
SFR(PLL_CON0_PLL_CPUCL1, 0x0120, CPUCL1),
|
|
SFR(PLL_LOCKTIME_PLL_CPUCL1, 0x0000, CPUCL1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, 0x0100, CPUCL1),
|
|
SFR(PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER, 0x0108, CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL, 0x1000, CPUCL1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF, 0x1808, CPUCL1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK, 0x1810, CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK, 0x2004, CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK, 0x2030, CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK, 0x2024, CPUCL1),
|
|
SFR(CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT0, 0x0810, CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_0_IPCLKPORT_HPM_TARGETCLK_C, 0x2008, CPUCL1),
|
|
SFR(CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT1, 0x0814, CPUCL1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, 0x1800, CPUCL1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK, 0x1804, CPUCL1),
|
|
SFR(CLK_CON_GAT_GATE_CLK_CPUCL1_CPU, 0x201c, CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK, 0x202c, CPUCL1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_CPU, 0x180c, CPUCL1),
|
|
SFR(CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT0, 0x0818, CPUCL1),
|
|
SFR(CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT1, 0x081c, CPUCL1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG, 0x1818, CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CLUSTER1_IPCLKPORT_PCLKDBG, 0x2000, CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK, 0x2020, CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK, 0x2028, CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_1_IPCLKPORT_HPM_TARGETCLK_C, 0x200c, CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_2_IPCLKPORT_HPM_TARGETCLK_C, 0x2010, CPUCL1),
|
|
SFR(QCH_CON_BUSIF_HPMCPUCL1_QCH, 0x301c, CPUCL1),
|
|
SFR(DMYQCH_CON_CLUSTER1_QCH_CPU, 0x3000, CPUCL1),
|
|
SFR(QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1, 0x3020, CPUCL1),
|
|
SFR(QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1, 0x3024, CPUCL1),
|
|
SFR(QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1, 0x3028, CPUCL1),
|
|
SFR(QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1, 0x302c, CPUCL1),
|
|
SFR(DMYQCH_CON_CLUSTER1_QCH_PCLKDBG, 0x3004, CPUCL1),
|
|
SFR(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH, 0x3030, CPUCL1),
|
|
SFR(QCH_CON_CPUCL1_CMU_CPUCL1_QCH, 0x3034, CPUCL1),
|
|
SFR(QCH_CON_LHM_AXI_P_CPUCL1_QCH, 0x3038, CPUCL1),
|
|
SFR(QCH_CON_SYSREG_CPUCL1_QCH, 0x303c, CPUCL1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DCF_BUSP, 0x1800, DCF),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DCF_BUS_USER, 0x0100, DCF),
|
|
SFR(PLL_CON2_MUX_CLKCMU_DCF_BUS_USER, 0x0108, DCF),
|
|
SFR(CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT0, 0x0818, DCF),
|
|
SFR(CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT1, 0x0814, DCF),
|
|
SFR(QCH_CON_BTM_DCF_QCH, 0x3020, DCF),
|
|
SFR(QCH_CON_DCF_CMU_DCF_QCH, 0x3024, DCF),
|
|
SFR(QCH_CON_IS_DCF_QCH_CIP, 0x302c, DCF),
|
|
SFR(QCH_CON_IS_DCF_QCH_QE, 0x3038, DCF),
|
|
SFR(QCH_CON_IS_DCF_QCH_SYSREG, 0x3040, DCF),
|
|
SFR(QCH_CON_IS_DCF_QCH_PPMU, 0x3034, DCF),
|
|
SFR(QCH_CON_IS_DCF_QCH_SYSMMU, 0x303c, DCF),
|
|
SFR(QCH_CON_IS_DCF_QCH_C2SYNC_2SLV, 0x3028, DCF),
|
|
SFR(QCH_CON_IS_DCF_QCH_PGEN_LITE, 0x3030, DCF),
|
|
SFR(QCH_CON_LHM_ATB_DCPOSTDCF_QCH, 0x3044, DCF),
|
|
SFR(QCH_CON_LHM_ATB_ISPHQDCF_QCH, 0x3048, DCF),
|
|
SFR(QCH_CON_LHM_AXI_D_DCPOSTDCF_QCH, 0x304c, DCF),
|
|
SFR(QCH_CON_LHM_AXI_P_DCF_QCH, 0x3050, DCF),
|
|
SFR(QCH_CON_LHS_ATB_DCFDCPOST_QCH, 0x3054, DCF),
|
|
SFR(QCH_CON_LHS_ATB_DCFISPLP_QCH, 0x3058, DCF),
|
|
SFR(QCH_CON_LHS_AXI_D_DCF_QCH, 0x305c, DCF),
|
|
SFR(QCH_CON_LHS_AXI_P_DCFDCPOST_QCH, 0x3060, DCF),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DCPOST_BUS_USER, 0x0100, DCPOST),
|
|
SFR(PLL_CON2_MUX_CLKCMU_DCPOST_BUS_USER, 0x0108, DCPOST),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DCPOST_BUSP, 0x1800, DCPOST),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCF_IPCLKPORT_I_CLK, 0x2038, DCPOST),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_AXI_D_DCPOSTDCF_IPCLKPORT_I_CLK, 0x2040, DCPOST),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCRDDCPOST_IPCLKPORT_I_CLK, 0x2030, DCPOST),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_SYSREG_DCPOST_PCLK, 0x2028, DCPOST),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_CIP2_PCLKM, 0x2008, DCPOST),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_CIP2_PCLKS, 0x2010, DCPOST),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_ACLK, 0x2020, DCPOST),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_PCLK, 0x2024, DCPOST),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_AXI_P_DCFDCPOST_IPCLKPORT_I_CLK, 0x2034, DCPOST),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSD_IPCLKPORT_CLK, 0x2044, DCPOST),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSP_IPCLKPORT_CLK, 0x2048, DCPOST),
|
|
SFR(CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT0, 0x0810, DCPOST),
|
|
SFR(CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT1, 0x0814, DCPOST),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DCPOST_UID_DCPOST_CMU_DCPOST_IPCLKPORT_PCLK, 0x2000, DCPOST),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_C2SYNC_1SLV_PCLKM, 0x2004, DCPOST),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_C2SYNC_1SLV_PCLKS, 0x200c, DCPOST),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCFDCPOST_IPCLKPORT_I_CLK, 0x202c, DCPOST),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCRD_IPCLKPORT_I_CLK, 0x203c, DCPOST),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_CIP2_ACLK, 0x201c, DCPOST),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_C2SYNC_1SLV_ACLK, 0x2018, DCPOST),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AXI2APB_DCPOST_ACLK, 0x2014, DCPOST),
|
|
SFR(QCH_CON_DCPOST_CMU_DCPOST_QCH, 0x3018, DCPOST),
|
|
SFR(QCH_CON_IS_DCPOST_QCH_SYSREG, 0x3028, DCPOST),
|
|
SFR(QCH_CON_IS_DCPOST_QCH_CIP2, 0x3020, DCPOST),
|
|
SFR(QCH_CON_IS_DCPOST_QCH_QE, 0x3024, DCPOST),
|
|
SFR(QCH_CON_IS_DCPOST_QCH_C2SYNC_1SLV_CLK, 0x301c, DCPOST),
|
|
SFR(QCH_CON_LHM_ATB_DCFDCPOST_QCH, 0x302c, DCPOST),
|
|
SFR(QCH_CON_LHM_ATB_DCRDDCPOST_QCH, 0x3030, DCPOST),
|
|
SFR(QCH_CON_LHM_AXI_P_DCFDCPOST_QCH, 0x3034, DCPOST),
|
|
SFR(QCH_CON_LHS_ATB_DCPOSTDCF_QCH, 0x3038, DCPOST),
|
|
SFR(QCH_CON_LHS_ATB_DCPOSTDCRD_QCH, 0x303c, DCPOST),
|
|
SFR(QCH_CON_LHS_AXI_D_DCPOSTDCF_QCH, 0x3040, DCPOST),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DCRD_BUSP, 0x1804, DCRD),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DCRD_BUS_USER, 0x0100, DCRD),
|
|
SFR(PLL_CON2_MUX_CLKCMU_DCRD_BUS_USER, 0x0108, DCRD),
|
|
SFR(CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT0, 0x0810, DCRD),
|
|
SFR(CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT1, 0x0814, DCRD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DCRD_BUSD_HALF, 0x1800, DCRD),
|
|
SFR(QCH_CON_BTM_DCRD_QCH, 0x3014, DCRD),
|
|
SFR(QCH_CON_DCRD_CMU_DCRD_QCH, 0x3018, DCRD),
|
|
SFR(QCH_CON_IS_DCRD_QCH_DCP, 0x301c, DCRD),
|
|
SFR(QCH_CON_IS_DCRD_QCH_PPMU, 0x302c, DCRD),
|
|
SFR(QCH_CON_IS_DCRD_QCH_SYSMMU, 0x3030, DCRD),
|
|
SFR(QCH_CON_IS_DCRD_QCH_SYSREG, 0x3034, DCRD),
|
|
SFR(QCH_CON_IS_DCRD_QCH_PGEN_LITE, 0x3028, DCRD),
|
|
SFR(QCH_CON_IS_DCRD_QCH_DCP_C2C, 0x3020, DCRD),
|
|
SFR(QCH_CON_IS_DCRD_QCH_DCP_DIV2, 0x3024, DCRD),
|
|
SFR(QCH_CON_LHM_ATB_DCPOSTDCRD_QCH, 0x3038, DCRD),
|
|
SFR(QCH_CON_LHM_AXI_P_DCRD_QCH, 0x303c, DCRD),
|
|
SFR(QCH_CON_LHS_ATB_DCRDDCPOST_QCH, 0x3040, DCRD),
|
|
SFR(QCH_CON_LHS_ATB_DCRDISPLP_QCH, 0x3044, DCRD),
|
|
SFR(QCH_CON_LHS_AXI_D_DCRD_QCH, 0x3048, DCRD),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DPU_BUS_USER, 0x0100, DPU),
|
|
SFR(PLL_CON2_MUX_CLKCMU_DPU_BUS_USER, 0x0108, DPU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0x1800, DPU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK, 0x2000, DPU),
|
|
SFR(CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT0, 0x0810, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD0_IPCLKPORT_I_PCLK, 0x2084, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD1_IPCLKPORT_I_PCLK, 0x208c, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK, 0x20e4, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP1_IPCLKPORT_ACLK, 0x207c, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP0_IPCLKPORT_ACLK, 0x2078, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK, 0x20a8, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_XIU_P_DPU_IPCLKPORT_ACLK, 0x20ec, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKS, 0x200c, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON1_IPCLKPORT_PCLKS, 0x2014, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS, 0x2044, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPP_IPCLKPORT_PCLKS, 0x2024, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD2_IPCLKPORT_I_PCLK, 0x2094, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS, 0x202c, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS, 0x203c, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK, 0x20bc, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK, 0x20c4, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK, 0x20cc, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK, 0x20d4, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS, 0x2040, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON2_IPCLKPORT_PCLKS, 0x201c, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_IPCLKPORT_PCLKS, 0x204c, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_S_IPCLKPORT_PCLKS, 0x2054, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_IPCLKPORT_PCLKS, 0x205c, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_S_IPCLKPORT_PCLKS, 0x2064, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_IPCLKPORT_PCLKS, 0x206c, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_S_IPCLKPORT_PCLKS, 0x2074, DPU),
|
|
SFR(CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT1, 0x0814, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_WRAPPER_FOR_S5I6211_HSI_DCPHY_COMBO_TOP_IPCLKPORT_PCLK, 0x20e8, DPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_PGEN_IPCLKPORT_PCLKS, 0x2034, DPU),
|
|
SFR(QCH_CON_BTM_DPUD0_QCH, 0x3010, DPU),
|
|
SFR(QCH_CON_BTM_DPUD1_QCH, 0x3014, DPU),
|
|
SFR(QCH_CON_BTM_DPUD2_QCH, 0x3018, DPU),
|
|
SFR(QCH_CON_DPU_QCH_DPU, 0x3020, DPU),
|
|
SFR(QCH_CON_DPU_QCH_DPU_DMA, 0x3024, DPU),
|
|
SFR(QCH_CON_DPU_QCH_DPU_DPP, 0x3028, DPU),
|
|
SFR(QCH_CON_DPU_QCH_DPU_WB_MUX, 0x302c, DPU),
|
|
SFR(QCH_CON_DPU_CMU_DPU_QCH, 0x301c, DPU),
|
|
SFR(QCH_CON_LHM_AXI_P_DPU_QCH, 0x3030, DPU),
|
|
SFR(QCH_CON_LHS_AXI_D0_DPU_QCH, 0x3034, DPU),
|
|
SFR(QCH_CON_LHS_AXI_D1_DPU_QCH, 0x3038, DPU),
|
|
SFR(QCH_CON_LHS_AXI_D2_DPU_QCH, 0x303c, DPU),
|
|
SFR(QCH_CON_PPMU_DPUD0_QCH, 0x3040, DPU),
|
|
SFR(QCH_CON_PPMU_DPUD1_QCH, 0x3044, DPU),
|
|
SFR(QCH_CON_PPMU_DPUD2_QCH, 0x3048, DPU),
|
|
SFR(QCH_CON_SYSMMU_DPUD0_QCH, 0x304c, DPU),
|
|
SFR(QCH_CON_SYSMMU_DPUD1_QCH, 0x3050, DPU),
|
|
SFR(QCH_CON_SYSMMU_DPUD2_QCH, 0x3054, DPU),
|
|
SFR(QCH_CON_SYSREG_DPU_QCH, 0x3058, DPU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DSPM_BUSP, 0x1800, DSPM),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DSPM_BUS_USER, 0x0100, DSPM),
|
|
SFR(PLL_CON2_MUX_CLKCMU_DSPM_BUS_USER, 0x0108, DSPM),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSPM_UID_DSPM_CMU_DSPM_IPCLKPORT_PCLK, 0x2004, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSREG_DSPM_IPCLKPORT_PCLK, 0x20dc, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AXI2APB_DSPM_IPCLKPORT_ACLK, 0x2058, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_ACLK, 0x20ac, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_PCLK, 0x20b0, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM0_IPCLKPORT_CLK, 0x20d0, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_ACLK, 0x2060, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_DSPM_IPCLKPORT_I_CLK, 0x208c, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_PCLK, 0x2064, DSPM),
|
|
SFR(CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT0, 0x0810, DSPM),
|
|
SFR(CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT1, 0x0814, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D0_DSPM_IPCLKPORT_I_CLK, 0x2094, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSD_IPCLKPORT_CLK, 0x20c4, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSP_IPCLKPORT_CLK, 0x20c8, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_IVADSPM_IPCLKPORT_I_CLK, 0x2090, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMIVA_IPCLKPORT_I_CLK, 0x20a4, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_WRAP2_CONV_DSPM_IPCLKPORT_I_CLK, 0x20e0, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKM, 0x200c, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKS, 0x2010, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKM, 0x2014, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKS, 0x2018, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKS, 0x2028, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKM, 0x2024, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKS, 0x2040, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKM, 0x203c, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_ACLK, 0x2068, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_PCLK, 0x206c, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D1_DSPM_IPCLKPORT_I_CLK, 0x2098, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK, 0x20a0, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_ACLK, 0x20b4, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_PCLK, 0x20b8, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM1_IPCLKPORT_CLK, 0x20d4, DSPM),
|
|
SFR(CLK_CON_GAT_CLKCMU_DSPS_BUS, 0x2000, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_ADM_APB_DSPM_IPCLKPORT_PCLKM, 0x2008, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D0_DSPSDSPM_IPCLKPORT_I_CLK, 0x2084, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D1_DSPSDSPM_IPCLKPORT_I_CLK, 0x2088, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_XIU_P_DSPM_IPCLKPORT_ACLK, 0x20e4, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_PGEN_LITE_DSPM_IPCLKPORT_CLK, 0x20a8, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D2_DSPM_IPCLKPORT_I_CLK, 0x209c, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKM, 0x202c, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKS, 0x2030, DSPM),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPM_UID_SCORE_MASTER_IPCLKPORT_I_CLK, 0x20cc, DSPM),
|
|
SFR(DMYQCH_CON_ADM_APB_DSPM_QCH, 0x3000, DSPM),
|
|
SFR(QCH_CON_BTM_DSPM0_QCH, 0x302c, DSPM),
|
|
SFR(QCH_CON_BTM_DSPM1_QCH, 0x3030, DSPM),
|
|
SFR(QCH_CON_DSPM_CMU_DSPM_QCH, 0x303c, DSPM),
|
|
SFR(QCH_CON_LHM_AXI_D0_DSPSDSPM_QCH, 0x3040, DSPM),
|
|
SFR(QCH_CON_LHM_AXI_D1_DSPSDSPM_QCH, 0x3044, DSPM),
|
|
SFR(QCH_CON_LHM_AXI_P_DSPM_QCH, 0x3048, DSPM),
|
|
SFR(QCH_CON_LHM_AXI_P_IVADSPM_QCH, 0x304c, DSPM),
|
|
SFR(QCH_CON_LHS_ACEL_D0_DSPM_QCH, 0x3050, DSPM),
|
|
SFR(QCH_CON_LHS_ACEL_D1_DSPM_QCH, 0x3054, DSPM),
|
|
SFR(QCH_CON_LHS_ACEL_D2_DSPM_QCH, 0x3058, DSPM),
|
|
SFR(QCH_CON_LHS_AXI_P_DSPMDSPS_QCH, 0x305c, DSPM),
|
|
SFR(QCH_CON_LHS_AXI_P_DSPMIVA_QCH, 0x3060, DSPM),
|
|
SFR(QCH_CON_PGEN_LITE_DSPM_QCH, 0x3064, DSPM),
|
|
SFR(QCH_CON_PPMU_DSPM0_QCH, 0x3068, DSPM),
|
|
SFR(QCH_CON_PPMU_DSPM1_QCH, 0x306c, DSPM),
|
|
SFR(QCH_CON_SCORE_MASTER_QCH, 0x3074, DSPM),
|
|
SFR(QCH_CON_SYSMMU_DSPM0_QCH, 0x3078, DSPM),
|
|
SFR(QCH_CON_SYSMMU_DSPM1_QCH, 0x307c, DSPM),
|
|
SFR(QCH_CON_SYSREG_DSPM_QCH, 0x3084, DSPM),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DSPS_BUSP, 0x1800, DSPS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DSPS_BUS_USER, 0x0120, DSPS),
|
|
SFR(PLL_CON2_MUX_CLKCMU_DSPS_BUS_USER, 0x0128, DSPS),
|
|
SFR(CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT0, 0x0810, DSPS),
|
|
SFR(CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT1, 0x0814, DSPS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSPS_UID_DSPS_CMU_DSPS_IPCLKPORT_PCLK, 0x2000, DSPS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPS_UID_AXI2APB_DSPS_IPCLKPORT_ACLK, 0x2004, DSPS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPS_UID_LHM_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK, 0x200c, DSPS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPS_UID_SYSREG_DSPS_IPCLKPORT_PCLK, 0x202c, DSPS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSPS_UID_RSTNSYNC_CLK_DSPS_BUSP_IPCLKPORT_CLK, 0x2024, DSPS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DSPS_AUD_USER, 0x0100, DSPS),
|
|
SFR(PLL_CON2_MUX_CLKCMU_DSPS_AUD_USER, 0x0108, DSPS),
|
|
SFR(CLK_CON_MUX_MUX_CLK_DSPS_BUS, 0x1000, DSPS),
|
|
SFR(QCH_CON_DSPS_CMU_DSPS_QCH, 0x3014, DSPS),
|
|
SFR(QCH_CON_LHM_AXI_D_IVADSPS_QCH, 0x3018, DSPS),
|
|
SFR(QCH_CON_LHM_AXI_P_DSPMDSPS_QCH, 0x301c, DSPS),
|
|
SFR(QCH_CON_LHS_AXI_D0_DSPSDSPM_QCH, 0x3020, DSPS),
|
|
SFR(QCH_CON_LHS_AXI_D1_DSPSDSPM_QCH, 0x3024, DSPS),
|
|
SFR(QCH_CON_LHS_AXI_D_DSPSIVA_QCH, 0x3028, DSPS),
|
|
SFR(QCH_CON_SCORE_KNIGHT_QCH, 0x3030, DSPS),
|
|
SFR(QCH_CON_SYSREG_DSPS_QCH, 0x3034, DSPS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_FSYS0_UFS_EMBD_USER, 0x0180, FSYS0),
|
|
SFR(PLL_CON2_MUX_CLKCMU_FSYS0_UFS_EMBD_USER, 0x01c8, FSYS0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER, 0x0100, FSYS0),
|
|
SFR(PLL_CON2_MUX_CLKCMU_FSYS0_BUS_USER, 0x0108, FSYS0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_FSYS0_USB30DRD_USER, 0x01e0, FSYS0),
|
|
SFR(PLL_CON2_MUX_CLKCMU_FSYS0_USB30DRD_USER, 0x0228, FSYS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, 0x205c, FSYS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USB30DRD_REF_CLK, 0x206c, FSYS0),
|
|
SFR(CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT0, 0x0810, FSYS0),
|
|
SFR(CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT1, 0x0814, FSYS0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_FSYS0_DPGTC_USER, 0x0120, FSYS0),
|
|
SFR(PLL_CON2_MUX_CLKCMU_FSYS0_DPGTC_USER, 0x0168, FSYS0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_FSYS0_USBDP_DEBUG_USER, 0x0240, FSYS0),
|
|
SFR(PLL_CON2_MUX_CLKCMU_FSYS0_USBDP_DEBUG_USER, 0x0288, FSYS0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL, 0x2008, FSYS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK, 0x2024, FSYS0),
|
|
SFR(QCH_CON_BTM_FSYS0_QCH, 0x3010, FSYS0),
|
|
SFR(QCH_CON_DP_LINK_QCH, 0x3014, FSYS0),
|
|
SFR(QCH_CON_DP_LINK_QCH_GTC, 0x3018, FSYS0),
|
|
SFR(QCH_CON_ETR_MIU_QCH_PCLK, 0x3020, FSYS0),
|
|
SFR(QCH_CON_ETR_MIU_QCH_ACLK, 0x301c, FSYS0),
|
|
SFR(QCH_CON_FSYS0_CMU_FSYS0_QCH, 0x3024, FSYS0),
|
|
SFR(QCH_CON_GPIO_FSYS0_QCH, 0x3028, FSYS0),
|
|
SFR(QCH_CON_LHM_AXI_G_ETR_QCH, 0x302c, FSYS0),
|
|
SFR(QCH_CON_LHM_AXI_P_FSYS0_QCH, 0x3030, FSYS0),
|
|
SFR(QCH_CON_LHS_ACEL_D_FSYS0_QCH, 0x3034, FSYS0),
|
|
SFR(QCH_CON_PGEN_LITE_FSYS0_QCH, 0x3038, FSYS0),
|
|
SFR(QCH_CON_PPMU_FSYS0_QCH, 0x303c, FSYS0),
|
|
SFR(QCH_CON_SYSREG_FSYS0_QCH, 0x3040, FSYS0),
|
|
SFR(QCH_CON_UFS_EMBD_QCH, 0x3044, FSYS0),
|
|
SFR(QCH_CON_UFS_EMBD_QCH_FMP, 0x3048, FSYS0),
|
|
SFR(QCH_CON_USB30DRD_QCH_USB30DRD_LINK, 0x3050, FSYS0),
|
|
SFR(QCH_CON_USB30DRD_QCH_USBPCS, 0x3058, FSYS0),
|
|
SFR(QCH_CON_USB30DRD_QCH_USB30DRD_CTRL, 0x304c, FSYS0),
|
|
SFR(QCH_CON_USB30DRD_QCH_USBDPPHY, 0x3054, FSYS0),
|
|
SFR(DMYQCH_CON_USB30DRD_QCH_SOC_PLL, 0x3000, FSYS0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER, 0x0100, FSYS1),
|
|
SFR(PLL_CON2_MUX_CLKCMU_FSYS1_BUS_USER, 0x0108, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK, 0x2020, FSYS1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER, 0x0120, FSYS1),
|
|
SFR(PLL_CON2_MUX_CLKCMU_FSYS1_MMC_CARD_USER, 0x0168, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN, 0x2034, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK, 0x203c, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK, 0x2094, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK, 0x208c, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK, 0x209c, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK, 0x2024, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK, 0x202c, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK, 0x2028, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK, 0x20ac, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK, 0x20c0, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_ACLK, 0x2078, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_PCLK, 0x207c, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK, 0x200c, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK, 0x2010, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK, 0x2008, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK, 0x2014, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK, 0x2018, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK, 0x201c, FSYS1),
|
|
SFR(CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT0, 0x0810, FSYS1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN, 0x2000, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK, 0x204c, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK, 0x2038, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 0x2044, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL, 0x2048, FSYS1),
|
|
SFR(CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT1, 0x0814, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK, 0x2080, FSYS1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_FSYS1_PCIE_USER, 0x0180, FSYS1),
|
|
SFR(PLL_CON2_MUX_CLKCMU_FSYS1_PCIE_USER, 0x01c8, FSYS1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_FSYS1_UFS_CARD_USER, 0x01e0, FSYS1),
|
|
SFR(PLL_CON2_MUX_CLKCMU_FSYS1_UFS_CARD_USER, 0x0228, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO, 0x20a4, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, 0x2004, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSMMU_FSYS1_IPCLKPORT_CLK, 0x2098, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PGEN_LITE_FSYS1_IPCLKPORT_CLK, 0x2074, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_DBI_ACLK, 0x2050, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_IEEE1500_WRAPPER_FOR_QCHANNEL_WRAPPER_FOR_PCIEG3_PHY_X1_TOP_INST_0_I_APB_PCLK, 0x2054, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_LT_PCIE3_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 0x2058, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PHY_REFCLK_IN, 0x2060, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PIPE42_PCIE_PCS_X1_WRAP_INST_0_I_APB_PCLK, 0x2064, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_SLV_ACLK, 0x2068, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_DBI_IPCLKPORT_ACLK, 0x20b0, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_SLV_IPCLKPORT_ACLK, 0x20bc, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_SLV_IPCLKPORT_ACLK, 0x20b4, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_DBI_IPCLKPORT_ACLK, 0x20b8, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK, 0x2040, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK, 0x2030, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_MSTR_ACLK, 0x205c, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK, 0x2088, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK, 0x2090, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK, 0x20a0, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK, 0x20a8, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK, 0x206c, FSYS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK, 0x2070, FSYS1),
|
|
SFR(QCH_CON_ADM_AHB_SSS_QCH, 0x3010, FSYS1),
|
|
SFR(QCH_CON_BTM_FSYS1_QCH, 0x3014, FSYS1),
|
|
SFR(QCH_CON_FSYS1_CMU_FSYS1_QCH, 0x3018, FSYS1),
|
|
SFR(QCH_CON_GPIO_FSYS1_QCH, 0x301c, FSYS1),
|
|
SFR(QCH_CON_LHM_AXI_P_FSYS1_QCH, 0x3020, FSYS1),
|
|
SFR(QCH_CON_LHS_ACEL_D_FSYS1_QCH, 0x3024, FSYS1),
|
|
SFR(QCH_CON_MMC_CARD_QCH, 0x3028, FSYS1),
|
|
SFR(QCH_CON_PCIE_GEN2_QCH_MSTR, 0x3034, FSYS1),
|
|
SFR(QCH_CON_PCIE_GEN2_QCH_PCS, 0x3038, FSYS1),
|
|
SFR(QCH_CON_PCIE_GEN2_QCH_PHY, 0x303c, FSYS1),
|
|
SFR(QCH_CON_PCIE_GEN2_QCH_DBI, 0x3030, FSYS1),
|
|
SFR(QCH_CON_PCIE_GEN2_QCH_APB, 0x302c, FSYS1),
|
|
SFR(DMYQCH_CON_PCIE_GEN2_QCH_SOCPLL, 0x3000, FSYS1),
|
|
SFR(QCH_CON_PCIE_GEN3_QCH_MSTR, 0x3048, FSYS1),
|
|
SFR(QCH_CON_PCIE_GEN3_QCH_PCS, 0x304c, FSYS1),
|
|
SFR(QCH_CON_PCIE_GEN3_QCH_DBI, 0x3044, FSYS1),
|
|
SFR(QCH_CON_PCIE_GEN3_QCH_APB, 0x3040, FSYS1),
|
|
SFR(DMYQCH_CON_PCIE_GEN3_QCH_SOCPLL, 0x3004, FSYS1),
|
|
SFR(QCH_CON_PCIE_GEN3_QCH_PHY, 0x3050, FSYS1),
|
|
SFR(QCH_CON_PCIE_IA_GEN2_QCH, 0x3054, FSYS1),
|
|
SFR(QCH_CON_PCIE_IA_GEN3_QCH, 0x3058, FSYS1),
|
|
SFR(QCH_CON_PGEN_LITE_FSYS1_QCH, 0x305c, FSYS1),
|
|
SFR(QCH_CON_PPMU_FSYS1_QCH, 0x3060, FSYS1),
|
|
SFR(QCH_CON_RTIC_QCH, 0x3064, FSYS1),
|
|
SFR(QCH_CON_SSS_QCH, 0x3068, FSYS1),
|
|
SFR(QCH_CON_SYSMMU_FSYS1_QCH, 0x306c, FSYS1),
|
|
SFR(QCH_CON_SYSREG_FSYS1_QCH, 0x3070, FSYS1),
|
|
SFR(QCH_CON_UFS_CARD_QCH, 0x3074, FSYS1),
|
|
SFR(QCH_CON_UFS_CARD_QCH_FMP, 0x3078, FSYS1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_G2D_G2D_USER, 0x0100, G2D),
|
|
SFR(PLL_CON2_MUX_CLKCMU_G2D_G2D_USER, 0x0108, G2D),
|
|
SFR(CLK_CON_DIV_DIV_CLK_G2D_BUSP, 0x1804, G2D),
|
|
SFR(PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER, 0x0120, G2D),
|
|
SFR(PLL_CON2_MUX_CLKCMU_G2D_MSCL_USER, 0x0128, G2D),
|
|
SFR(CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT0, 0x0810, G2D),
|
|
SFR(CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT1, 0x0814, G2D),
|
|
SFR(QCH_CON_ASTC_QCH, 0x3010, G2D),
|
|
SFR(QCH_CON_BTM_G2DD0_QCH, 0x3014, G2D),
|
|
SFR(QCH_CON_BTM_G2DD1_QCH, 0x3018, G2D),
|
|
SFR(QCH_CON_BTM_G2DD2_QCH, 0x301c, G2D),
|
|
SFR(QCH_CON_G2D_QCH, 0x3024, G2D),
|
|
SFR(QCH_CON_G2D_CMU_G2D_QCH, 0x3020, G2D),
|
|
SFR(QCH_CON_JPEG_QCH, 0x3028, G2D),
|
|
SFR(QCH_CON_LHM_AXI_P_G2D_QCH, 0x302c, G2D),
|
|
SFR(QCH_CON_LHS_ACEL_D0_G2D_QCH, 0x3030, G2D),
|
|
SFR(QCH_CON_LHS_ACEL_D1_G2D_QCH, 0x3034, G2D),
|
|
SFR(QCH_CON_LHS_ACEL_D2_G2D_QCH, 0x3038, G2D),
|
|
SFR(QCH_CON_MSCL_QCH, 0x303c, G2D),
|
|
SFR(QCH_CON_PGEN100_LITE_G2D_QCH, 0x3040, G2D),
|
|
SFR(QCH_CON_PPMU_G2DD0_QCH, 0x3044, G2D),
|
|
SFR(QCH_CON_PPMU_G2DD1_QCH, 0x3048, G2D),
|
|
SFR(QCH_CON_PPMU_G2DD2_QCH, 0x304c, G2D),
|
|
SFR(QCH_CON_QE_ASTC_QCH, 0x3050, G2D),
|
|
SFR(QCH_CON_QE_JPEG_QCH, 0x3054, G2D),
|
|
SFR(QCH_CON_QE_MSCL_QCH, 0x3058, G2D),
|
|
SFR(QCH_CON_SYSMMU_G2DD0_QCH, 0x305c, G2D),
|
|
SFR(QCH_CON_SYSMMU_G2DD1_QCH, 0x3060, G2D),
|
|
SFR(QCH_CON_SYSMMU_G2DD2_QCH, 0x3064, G2D),
|
|
SFR(QCH_CON_SYSREG_G2D_QCH, 0x3068, G2D),
|
|
SFR(CLK_CON_DIV_DIV_CLK_G3D_BUSP, 0x1804, G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK, 0x203c, G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK, 0x2028, G3D),
|
|
SFR(CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT0, 0x0810, G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK, 0x2018, G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D0_IPCLKPORT_HPM_TARGETCLK_C, 0x2008, G3D),
|
|
SFR(PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 0x0120, G3D),
|
|
SFR(PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER, 0x0128, G3D),
|
|
SFR(CLK_CON_MUX_MUX_CLK_G3D_BUSD, 0x1000, G3D),
|
|
SFR(CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT1, 0x0814, G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, 0x2038, G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK, 0x2034, G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK, 0x2000, G3D),
|
|
SFR(PLL_CON0_PLL_G3D, 0x0140, G3D),
|
|
SFR(PLL_LOCKTIME_PLL_G3D, 0x0000, G3D),
|
|
SFR(CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT0, 0x0818, G3D),
|
|
SFR(CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT1, 0x081c, G3D),
|
|
SFR(PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_USER, 0x0100, G3D),
|
|
SFR(PLL_CON2_MUX_CLKCMU_EMBEDDED_G3D_USER, 0x0108, G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK, 0x202c, G3D),
|
|
SFR(CLK_CON_DIV_DIV_CLK_G3D_BUSD, 0x1800, G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK, 0x2030, G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK, 0x2004, G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK, 0x2014, G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK, 0x2024, G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK, 0x2020, G3D),
|
|
SFR(QCH_CON_BUSIF_HPMG3D_QCH, 0x301c, G3D),
|
|
SFR(QCH_CON_G3D_CMU_G3D_QCH, 0x3020, G3D),
|
|
SFR(QCH_CON_GPU_QCH, 0x3024, G3D),
|
|
SFR(QCH_CON_LHM_AXI_G3DSFR_QCH, 0x3028, G3D),
|
|
SFR(QCH_CON_LHM_AXI_P_G3D_QCH, 0x302c, G3D),
|
|
SFR(QCH_CON_LHS_ACE_D0_G3D_QCH, 0x3030, G3D),
|
|
SFR(QCH_CON_LHS_ACE_D1_G3D_QCH, 0x3034, G3D),
|
|
SFR(QCH_CON_LHS_ACE_D2_G3D_QCH, 0x3038, G3D),
|
|
SFR(QCH_CON_LHS_ACE_D3_G3D_QCH, 0x303c, G3D),
|
|
SFR(QCH_CON_LHS_AXI_G3DSFR_QCH, 0x3040, G3D),
|
|
SFR(QCH_CON_PGEN_LITE_G3D_QCH, 0x3044, G3D),
|
|
SFR(QCH_CON_SYSREG_G3D_QCH, 0x3048, G3D),
|
|
SFR(PLL_CON0_MUX_CLKCMU_ISPHQ_BUS_USER, 0x0100, ISPHQ),
|
|
SFR(PLL_CON2_MUX_CLKCMU_ISPHQ_BUS_USER, 0x0108, ISPHQ),
|
|
SFR(CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP, 0x1800, ISPHQ),
|
|
SFR(CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT0, 0x0810, ISPHQ),
|
|
SFR(CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT1, 0x0814, ISPHQ),
|
|
SFR(QCH_CON_BTM_ISPHQ_QCH, 0x3018, ISPHQ),
|
|
SFR(QCH_CON_ISPHQ_CMU_ISPHQ_QCH, 0x301c, ISPHQ),
|
|
SFR(QCH_CON_IS_ISPHQ_QCH_ISPHQ, 0x3020, ISPHQ),
|
|
SFR(QCH_CON_IS_ISPHQ_QCH_SYSMMU_ISPHQ, 0x3030, ISPHQ),
|
|
SFR(QCH_CON_IS_ISPHQ_QCH_PPMU_ISPHQ, 0x302c, ISPHQ),
|
|
SFR(QCH_CON_IS_ISPHQ_QCH_PGEN_LITE_ISPHQ, 0x3028, ISPHQ),
|
|
SFR(QCH_CON_IS_ISPHQ_QCH_ISPHQ_C2COM, 0x3024, ISPHQ),
|
|
SFR(QCH_CON_LHM_ATB_ISPLPISPHQ_QCH, 0x3034, ISPHQ),
|
|
SFR(QCH_CON_LHM_ATB_ISPPREISPHQ_QCH, 0x3038, ISPHQ),
|
|
SFR(QCH_CON_LHM_AXI_P_ISPHQ_QCH, 0x303c, ISPHQ),
|
|
SFR(QCH_CON_LHS_ATB_ISPHQDCF_QCH, 0x3040, ISPHQ),
|
|
SFR(QCH_CON_LHS_ATB_ISPHQISPLP_QCH, 0x3044, ISPHQ),
|
|
SFR(QCH_CON_LHS_AXI_D_ISPHQ_QCH, 0x3048, ISPHQ),
|
|
SFR(QCH_CON_SYSREG_ISPHQ_QCH, 0x304c, ISPHQ),
|
|
SFR(PLL_CON0_MUX_CLKCMU_ISPLP_BUS_USER, 0x0100, ISPLP),
|
|
SFR(PLL_CON2_MUX_CLKCMU_ISPLP_BUS_USER, 0x0108, ISPLP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_ISPLP_BUSP, 0x1800, ISPLP),
|
|
SFR(CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT0, 0x0810, ISPLP),
|
|
SFR(CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT1, 0x0814, ISPLP),
|
|
SFR(PLL_CON0_MUX_CLKCMU_ISPLP_VRA_USER, 0x0140, ISPLP),
|
|
SFR(PLL_CON2_MUX_CLKCMU_ISPLP_VRA_USER, 0x0148, ISPLP),
|
|
SFR(PLL_CON0_MUX_CLKCMU_ISPLP_GDC_USER, 0x0120, ISPLP),
|
|
SFR(PLL_CON2_MUX_CLKCMU_ISPLP_GDC_USER, 0x0128, ISPLP),
|
|
SFR(QCH_CON_BTM_ISPLP0_QCH, 0x3020, ISPLP),
|
|
SFR(QCH_CON_BTM_ISPLP1_QCH, 0x3024, ISPLP),
|
|
SFR(QCH_CON_ISPLP_CMU_ISPLP_QCH, 0x3028, ISPLP),
|
|
SFR(QCH_CON_IS_ISPLP_QCH_MC_SCALER, 0x3038, ISPLP),
|
|
SFR(QCH_CON_IS_ISPLP_QCH_ISPLP, 0x3030, ISPLP),
|
|
SFR(QCH_CON_IS_ISPLP_QCH_QE_ISPLP, 0x304c, ISPLP),
|
|
SFR(QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP0, 0x305c, ISPLP),
|
|
SFR(QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP0, 0x3040, ISPLP),
|
|
SFR(QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP1, 0x3060, ISPLP),
|
|
SFR(QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP1, 0x3044, ISPLP),
|
|
SFR(QCH_CON_IS_ISPLP_QCH_QE_VRA, 0x3054, ISPLP),
|
|
SFR(QCH_CON_IS_ISPLP_QCH_VRA, 0x3064, ISPLP),
|
|
SFR(QCH_CON_IS_ISPLP_QCH_GDC, 0x302c, ISPLP),
|
|
SFR(QCH_CON_IS_ISPLP_QCH_PGEN_LITE, 0x303c, ISPLP),
|
|
SFR(QCH_CON_IS_ISPLP_QCH_QE_GDC, 0x3048, ISPLP),
|
|
SFR(QCH_CON_IS_ISPLP_QCH_ISPLP_C2, 0x3034, ISPLP),
|
|
SFR(QCH_CON_LHM_ATB_DCFISPLP_QCH, 0x3068, ISPLP),
|
|
SFR(QCH_CON_LHM_ATB_DCRDISPLP_QCH, 0x306c, ISPLP),
|
|
SFR(QCH_CON_LHM_ATB_ISPHQISPLP_QCH, 0x3070, ISPLP),
|
|
SFR(QCH_CON_LHM_ATB_ISPPREISPLP_QCH, 0x3074, ISPLP),
|
|
SFR(QCH_CON_LHM_AXI_P_ISPLP_QCH, 0x3078, ISPLP),
|
|
SFR(QCH_CON_LHS_ATB_ISPLPISPHQ_QCH, 0x307c, ISPLP),
|
|
SFR(QCH_CON_LHS_AXI_D0_ISPLP_QCH, 0x3080, ISPLP),
|
|
SFR(QCH_CON_LHS_AXI_D1_ISPLP_QCH, 0x3084, ISPLP),
|
|
SFR(QCH_CON_SYSREG_ISPLP_QCH, 0x3088, ISPLP),
|
|
SFR(PLL_CON0_MUX_CLKCMU_ISPPRE_BUS_USER, 0x0100, ISPPRE),
|
|
SFR(PLL_CON2_MUX_CLKCMU_ISPPRE_BUS_USER, 0x0108, ISPPRE),
|
|
SFR(CLK_CON_DIV_DIV_CLK_ISPPRE_BUSP, 0x1804, ISPPRE),
|
|
SFR(CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT0, 0x0810, ISPPRE),
|
|
SFR(CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT1, 0x0814, ISPPRE),
|
|
SFR(QCH_CON_BTM_ISPPRE_QCH, 0x3010, ISPPRE),
|
|
SFR(QCH_CON_ISPPRE_CMU_ISPPRE_QCH, 0x3014, ISPPRE),
|
|
SFR(QCH_CON_IS_ISPPRE_QCH_CSIS0, 0x3020, ISPPRE),
|
|
SFR(QCH_CON_IS_ISPPRE_QCH_CSIS1, 0x3024, ISPPRE),
|
|
SFR(QCH_CON_IS_ISPPRE_QCH_CSIS2, 0x3028, ISPPRE),
|
|
SFR(QCH_CON_IS_ISPPRE_QCH_CSIS3, 0x302c, ISPPRE),
|
|
SFR(QCH_CON_IS_ISPPRE_QCH_PPMU_ISPPRE, 0x3048, ISPPRE),
|
|
SFR(QCH_CON_IS_ISPPRE_QCH_PDP_DMA, 0x3038, ISPPRE),
|
|
SFR(QCH_CON_IS_ISPPRE_QCH_SYSMMU_ISPPRE, 0x305c, ISPPRE),
|
|
SFR(QCH_CON_IS_ISPPRE_QCH_QE_PDP, 0x3054, ISPPRE),
|
|
SFR(QCH_CON_IS_ISPPRE_QCH_QE_3AA, 0x304c, ISPPRE),
|
|
SFR(QCH_CON_IS_ISPPRE_QCH_QE_3AAM, 0x3050, ISPPRE),
|
|
SFR(QCH_CON_IS_ISPPRE_QCH_3AA, 0x3018, ISPPRE),
|
|
SFR(QCH_CON_IS_ISPPRE_QCH_3AAM, 0x301c, ISPPRE),
|
|
SFR(QCH_CON_IS_ISPPRE_QCH_PDP_CORE0, 0x3030, ISPPRE),
|
|
SFR(QCH_CON_IS_ISPPRE_QCH_PDP_CORE1, 0x3034, ISPPRE),
|
|
SFR(QCH_CON_IS_ISPPRE_QCH_PGEN_LITE, 0x3040, ISPPRE),
|
|
SFR(QCH_CON_IS_ISPPRE_QCH_QE_PDP_STAT, 0x3058, ISPPRE),
|
|
SFR(QCH_CON_IS_ISPPRE_QCH_PGEN_LITE1, 0x3044, ISPPRE),
|
|
SFR(QCH_CON_LHM_AXI_P_ISPPRE_QCH, 0x3060, ISPPRE),
|
|
SFR(QCH_CON_LHS_ATB_ISPPREISPHQ_QCH, 0x3064, ISPPRE),
|
|
SFR(QCH_CON_LHS_ATB_ISPPREISPLP_QCH, 0x3068, ISPPRE),
|
|
SFR(QCH_CON_LHS_AXI_D_ISPPRE_QCH, 0x306c, ISPPRE),
|
|
SFR(QCH_CON_SYSREG_ISPPRE_QCH_SYSREG, 0x3070, ISPPRE),
|
|
SFR(PLL_CON0_MUX_CLKCMU_IVA_BUS_USER, 0x0100, IVA),
|
|
SFR(PLL_CON2_MUX_CLKCMU_IVA_BUS_USER, 0x0108, IVA),
|
|
SFR(CLK_CON_DIV_DIV_CLK_IVA_BUSP, 0x1800, IVA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK, 0x2000, IVA),
|
|
SFR(CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT0, 0x0810, IVA),
|
|
SFR(CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT1, 0x0814, IVA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK, 0x2048, IVA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK, 0x202c, IVA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_PPMU_IVA_IPCLKPORT_PCLK, 0x2060, IVA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK, 0x2088, IVA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA0_IPCLKPORT_PCLKS, 0x200c, IVA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK, 0x2020, IVA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK, 0x2024, IVA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK, 0x2074, IVA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK, 0x2068, IVA),
|
|
SFR(CLK_CON_DIV_DIV_CLK_IVA_DEBUG, 0x1804, IVA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_ADM_DAP_IVA_IPCLKPORT_DAPCLKM, 0x2004, IVA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_DEBUG_IPCLKPORT_CLK, 0x206c, IVA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA1_IPCLKPORT_PCLKS, 0x2014, IVA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA2_IPCLKPORT_PCLKS, 0x201c, IVA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_PGEN_LITE_IVA_IPCLKPORT_CLK, 0x2058, IVA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_TREX_RB_IVA_IPCLKPORT_PCLK, 0x207c, IVA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_DAP_CLK, 0x2038, IVA),
|
|
SFR(DMYQCH_CON_ADM_DAP_IVA_QCH, 0x3000, IVA),
|
|
SFR(QCH_CON_BTM_IVA_QCH, 0x3020, IVA),
|
|
SFR(QCH_CON_IVA_QCH_IVA, 0x302c, IVA),
|
|
SFR(QCH_CON_IVA_QCH_IVA_DEBUG, 0x3030, IVA),
|
|
SFR(QCH_CON_IVA_CMU_IVA_QCH, 0x3024, IVA),
|
|
SFR(QCH_CON_IVA_INTMEM_QCH, 0x3028, IVA),
|
|
SFR(QCH_CON_LHM_AXI_D_DSPSIVA_QCH, 0x3034, IVA),
|
|
SFR(QCH_CON_LHM_AXI_D_IVASC_QCH, 0x3038, IVA),
|
|
SFR(QCH_CON_LHM_AXI_P_DSPMIVA_QCH, 0x303c, IVA),
|
|
SFR(QCH_CON_LHM_AXI_P_IVA_QCH, 0x3040, IVA),
|
|
SFR(QCH_CON_LHS_ACEL_D_IVA_QCH, 0x3044, IVA),
|
|
SFR(QCH_CON_LHS_AXI_D_IVADSPS_QCH, 0x3048, IVA),
|
|
SFR(QCH_CON_LHS_AXI_P_IVADSPM_QCH, 0x304c, IVA),
|
|
SFR(QCH_CON_PGEN_LITE_IVA_QCH, 0x3050, IVA),
|
|
SFR(QCH_CON_PPMU_IVA_QCH, 0x3054, IVA),
|
|
SFR(QCH_CON_SYSMMU_IVA_QCH, 0x3058, IVA),
|
|
SFR(QCH_CON_SYSREG_IVA_QCH, 0x305c, IVA),
|
|
SFR(QCH_CON_TREX_RB_IVA_QCH, 0x3060, IVA),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MFC_BUS_USER, 0x0100, MFC),
|
|
SFR(PLL_CON2_MUX_CLKCMU_MFC_BUS_USER, 0x0108, MFC),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MFC_BUSP, 0x1804, MFC),
|
|
SFR(CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT0, 0x0810, MFC),
|
|
SFR(CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT1, 0x0814, MFC),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MFC_WFD_USER, 0x0120, MFC),
|
|
SFR(PLL_CON2_MUX_CLKCMU_MFC_WFD_USER, 0x0128, MFC),
|
|
SFR(QCH_CON_BTM_MFCD0_QCH, 0x300c, MFC),
|
|
SFR(QCH_CON_BTM_MFCD1_QCH, 0x3010, MFC),
|
|
SFR(QCH_CON_LHM_AXI_P_MFC_QCH, 0x3014, MFC),
|
|
SFR(QCH_CON_LHS_AXI_D0_MFC_QCH, 0x3018, MFC),
|
|
SFR(QCH_CON_LHS_AXI_D1_MFC_QCH, 0x301c, MFC),
|
|
SFR(QCH_CON_LH_ATB_QCH_MI, 0x3020, MFC),
|
|
SFR(QCH_CON_LH_ATB_QCH_SI, 0x3024, MFC),
|
|
SFR(QCH_CON_MFC_QCH, 0x302c, MFC),
|
|
SFR(QCH_CON_MFC_CMU_MFC_QCH, 0x3028, MFC),
|
|
SFR(QCH_CON_PGEN100_LITE_MFC_QCH, 0x3030, MFC),
|
|
SFR(QCH_CON_PPMU_MFCD0_QCH, 0x3034, MFC),
|
|
SFR(QCH_CON_PPMU_MFCD1_QCH, 0x3038, MFC),
|
|
SFR(QCH_CON_PPMU_MFCD2_QCH, 0x303c, MFC),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MI_SW_RESET_QCH, 0x3040, MFC),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_SI_SW_RESET_QCH, 0x3044, MFC),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH, 0x3048, MFC),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH, 0x304c, MFC),
|
|
SFR(QCH_CON_SYSMMU_MFCD0_QCH, 0x3050, MFC),
|
|
SFR(QCH_CON_SYSMMU_MFCD1_QCH, 0x3054, MFC),
|
|
SFR(QCH_CON_SYSREG_MFC_QCH, 0x3058, MFC),
|
|
SFR(QCH_CON_WFD_QCH, 0x305c, MFC),
|
|
SFR(PLL_CON0_PLL_MIF, 0x0120, MIF),
|
|
SFR(PLL_LOCKTIME_PLL_MIF, 0x0000, MIF),
|
|
SFR(CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X, 0x1000, MIF),
|
|
SFR(CLK_CON_DIV_CLK_MIF_BUSD, 0x1800, MIF),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MIF_PRE, 0x1810, MIF),
|
|
SFR(CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT0, 0x0810, MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C, 0x2004, MIF),
|
|
SFR(CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT1, 0x0814, MIF),
|
|
SFR(CLK_CON_MUX_MUX_MIF_CMUREF, 0x1004, MIF),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER, 0x0100, MIF),
|
|
SFR(PLL_CON2_MUX_CLKCMU_MIF_BUSP_USER, 0x0108, MIF),
|
|
SFR(QCH_CON_APBBR_DDRPHY_QCH, 0x3008, MIF),
|
|
SFR(QCH_CON_APBBR_DMC_QCH, 0x3030, MIF),
|
|
SFR(QCH_CON_APBBR_DMCTZ_QCH, 0x300c, MIF),
|
|
SFR(QCH_CON_BUSIF_HPMMIF_QCH, 0x3010, MIF),
|
|
SFR(DMYQCH_CON_CMU_MIF_CMUREF_QCH, 0x3000, MIF),
|
|
SFR(QCH_CON_DMC_QCH, 0x3014, MIF),
|
|
SFR(QCH_CON_LHM_AXI_P_MIF_QCH, 0x301c, MIF),
|
|
SFR(QCH_CON_MIF_CMU_MIF_QCH, 0x3020, MIF),
|
|
SFR(QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG_QCH, 0x3024, MIF),
|
|
SFR(QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS_QCH, 0x3028, MIF),
|
|
SFR(QCH_CON_SYSREG_MIF_QCH, 0x302c, MIF),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 0x0100, PERIC0),
|
|
SFR(PLL_CON2_MUX_CLKCMU_PERIC0_BUS_USER, 0x0108, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, 0x203c, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0, 0x2044, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, 0x2098, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_PCLK, 0x20b0, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_PCLK, 0x20c0, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_PCLK, 0x20d0, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_PCLK, 0x20e0, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P0_IPCLKPORT_ACLK, 0x2034, PERIC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, 0x2000, PERIC0),
|
|
SFR(CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0, 0x0810, PERIC0),
|
|
SFR(CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT1, 0x0814, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, 0x2048, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK, 0x20f0, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P1_IPCLKPORT_ACLK, 0x2038, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_PCLK, 0x2100, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_PCLK, 0x20a8, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_PCLK, 0x20b8, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_PCLK, 0x20c8, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_PCLK, 0x20d8, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK, 0x20e8, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_PCLK, 0x20f8, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK, 0x2054, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_I2C_IPCLKPORT_CLK, 0x2050, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK, 0x205c, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK, 0x2064, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK, 0x206c, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK, 0x2074, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK, 0x207c, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK, 0x20a0, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK, 0x204c, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_XIU_P_PERIC0_IPCLKPORT_ACLK, 0x2134, PERIC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI, 0x1804, PERIC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI, 0x1808, PERIC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI, 0x180c, PERIC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI, 0x1810, PERIC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI, 0x1814, PERIC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI, 0x1818, PERIC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0x1828, PERIC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG, 0x1800, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_I2C_IPCLKPORT_CLK, 0x2058, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_I2C_IPCLKPORT_CLK, 0x2060, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_I2C_IPCLKPORT_CLK, 0x2068, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_I2C_IPCLKPORT_CLK, 0x2070, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_I2C_IPCLKPORT_CLK, 0x2078, PERIC0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER, 0x0120, PERIC0),
|
|
SFR(PLL_CON2_MUX_CLKCMU_PERIC0_IP_USER, 0x0128, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_IPCLK, 0x209c, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_IPCLK, 0x20ac, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_IPCLK, 0x20b4, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_IPCLK, 0x20bc, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_IPCLK, 0x20c4, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_IPCLK, 0x20cc, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_IPCLK, 0x20d4, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_IPCLK, 0x20dc, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK, 0x20e4, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK, 0x20ec, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_IPCLK, 0x20f4, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_IPCLK, 0x20fc, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, 0x2040, PERIC0),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERIC0_USI00_USI, 0x200c, PERIC0),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERIC0_USI01_USI, 0x2010, PERIC0),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERIC0_USI02_USI, 0x2014, PERIC0),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERIC0_USI03_USI, 0x2018, PERIC0),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERIC0_USI04_USI, 0x201c, PERIC0),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERIC0_USI05_USI, 0x2020, PERIC0),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERIC0_USI_I2C, 0x2030, PERIC0),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERIC0_UART_DBG, 0x2008, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_IPCLK, 0x20a4, PERIC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI12_USI, 0x181c, PERIC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI, 0x1820, PERIC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0x1824, PERIC0),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERIC0_USI12_USI, 0x2024, PERIC0),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERIC0_USI13_USI, 0x2028, PERIC0),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERIC0_USI14_USI, 0x202c, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_USI_IPCLKPORT_CLK, 0x2084, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK, 0x208c, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, 0x2094, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_PCLK, 0x2110, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_IPCLK, 0x210c, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_PCLK, 0x2108, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_IPCLK, 0x2104, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_I2C_IPCLKPORT_CLK, 0x2080, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_I2C_IPCLKPORT_CLK, 0x2088, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_I2C_IPCLKPORT_CLK, 0x2090, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_PCLK, 0x2118, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_IPCLK, 0x2114, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_PCLK, 0x2120, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_IPCLK, 0x211c, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK, 0x2130, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK, 0x212c, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_PCLK, 0x2128, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_IPCLK, 0x2124, PERIC0),
|
|
SFR(QCH_CON_GPIO_PERIC0_QCH, 0x3004, PERIC0),
|
|
SFR(QCH_CON_LHM_AXI_P_PERIC0_QCH, 0x3008, PERIC0),
|
|
SFR(QCH_CON_PERIC0_CMU_PERIC0_QCH, 0x300c, PERIC0),
|
|
SFR(QCH_CON_PWM_QCH, 0x3010, PERIC0),
|
|
SFR(QCH_CON_SYSREG_PERIC0_QCH, 0x3014, PERIC0),
|
|
SFR(QCH_CON_UART_DBG_QCH, 0x3018, PERIC0),
|
|
SFR(QCH_CON_USI00_I2C_QCH, 0x301c, PERIC0),
|
|
SFR(QCH_CON_USI00_USI_QCH, 0x3020, PERIC0),
|
|
SFR(QCH_CON_USI01_I2C_QCH, 0x3024, PERIC0),
|
|
SFR(QCH_CON_USI01_USI_QCH, 0x3028, PERIC0),
|
|
SFR(QCH_CON_USI02_I2C_QCH, 0x302c, PERIC0),
|
|
SFR(QCH_CON_USI02_USI_QCH, 0x3030, PERIC0),
|
|
SFR(QCH_CON_USI03_I2C_QCH, 0x3034, PERIC0),
|
|
SFR(QCH_CON_USI03_USI_QCH, 0x3038, PERIC0),
|
|
SFR(QCH_CON_USI04_I2C_QCH, 0x303c, PERIC0),
|
|
SFR(QCH_CON_USI04_USI_QCH, 0x3040, PERIC0),
|
|
SFR(QCH_CON_USI05_I2C_QCH, 0x3044, PERIC0),
|
|
SFR(QCH_CON_USI05_USI_QCH, 0x3048, PERIC0),
|
|
SFR(QCH_CON_USI12_I2C_QCH, 0x304c, PERIC0),
|
|
SFR(QCH_CON_USI12_USI_QCH, 0x3050, PERIC0),
|
|
SFR(QCH_CON_USI13_I2C_QCH, 0x3054, PERIC0),
|
|
SFR(QCH_CON_USI13_USI_QCH, 0x3058, PERIC0),
|
|
SFR(QCH_CON_USI14_I2C_QCH, 0x305c, PERIC0),
|
|
SFR(QCH_CON_USI14_USI_QCH, 0x3060, PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK, 0x2058, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, 0x205c, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, 0x20c0, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK, 0x20c8, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_PCLK, 0x206c, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_PCLK, 0x2074, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_PCLK, 0x207c, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_PCLK, 0x20d8, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK, 0x20e8, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK, 0x20f8, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_PCLK, 0x2064, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK, 0x212c, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK, 0x2054, PERIC1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 0x0100, PERIC1),
|
|
SFR(PLL_CON2_MUX_CLKCMU_PERIC1_BUS_USER, 0x0108, PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, 0x2000, PERIC1),
|
|
SFR(CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0, 0x0810, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK, 0x20bc, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK, 0x2108, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_PCLK, 0x20d0, PERIC1),
|
|
SFR(CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT1, 0x0814, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK, 0x2084, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK, 0x2118, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_PCLK, 0x20e0, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_PCLK, 0x20f0, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK, 0x2100, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK, 0x2110, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK, 0x208c, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK, 0x2094, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK, 0x209c, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK, 0x20a4, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK, 0x20ac, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_I2C_IPCLKPORT_CLK, 0x2088, PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK, 0x201c, PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPI_CAM0_IPCLKPORT_CLK, 0x2018, PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM0_IPCLKPORT_CLK, 0x2004, PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM1_IPCLKPORT_CLK, 0x2008, PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM2_IPCLKPORT_CLK, 0x200c, PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM3_IPCLKPORT_CLK, 0x2010, PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT, 0x1814, PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0x1830, PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI, 0x1818, PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI, 0x181c, PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI, 0x1820, PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM0, 0x1800, PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM1, 0x1804, PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM2, 0x1808, PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM3, 0x180c, PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_SPI_CAM0, 0x1810, PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI, 0x1824, PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0x1828, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_I2C_IPCLKPORT_CLK, 0x2090, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_I2C_IPCLKPORT_CLK, 0x2098, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_I2C_IPCLKPORT_CLK, 0x20a0, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_I2C_IPCLKPORT_CLK, 0x20a8, PERIC1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER, 0x0120, PERIC1),
|
|
SFR(PLL_CON2_MUX_CLKCMU_PERIC1_IP_USER, 0x0128, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_IPCLK, 0x2060, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_IPCLK, 0x2068, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_IPCLK, 0x2070, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_IPCLK, 0x2078, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, 0x2080, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_IPCLK, 0x20b8, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_IPCLK, 0x20c4, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_IPCLK, 0x20cc, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_IPCLK, 0x20d4, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_IPCLK, 0x20dc, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK, 0x20e4, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_IPCLK, 0x20ec, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK, 0x20f4, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK, 0x20fc, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK, 0x2104, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK, 0x210c, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK, 0x2114, PERIC1),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERIC1_UART_BT, 0x2034, PERIC1),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERIC1_USI_I2C, 0x2050, PERIC1),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERIC1_USI06_USI, 0x2038, PERIC1),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERIC1_USI07_USI, 0x203c, PERIC1),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERIC1_USI08_USI, 0x2040, PERIC1),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM0, 0x2020, PERIC1),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM1, 0x2024, PERIC1),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM2, 0x2028, PERIC1),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM3, 0x202c, PERIC1),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERIC1_SPI_CAM0, 0x2030, PERIC1),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERIC1_USI09_USI, 0x2044, PERIC1),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERIC1_USI10_USI, 0x2048, PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0x182c, PERIC1),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERIC1_USI11_USI, 0x204c, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK, 0x2128, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK, 0x2124, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_PCLK, 0x2120, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_IPCLK, 0x211c, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK, 0x20b4, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_I2C_IPCLKPORT_CLK, 0x20b0, PERIC1),
|
|
SFR(QCH_CON_GPIO_PERIC1_QCH, 0x3004, PERIC1),
|
|
SFR(QCH_CON_I2C_CAM0_QCH, 0x3008, PERIC1),
|
|
SFR(QCH_CON_I2C_CAM1_QCH, 0x300c, PERIC1),
|
|
SFR(QCH_CON_I2C_CAM2_QCH, 0x3010, PERIC1),
|
|
SFR(QCH_CON_I2C_CAM3_QCH, 0x3014, PERIC1),
|
|
SFR(QCH_CON_LHM_AXI_P_PERIC1_QCH, 0x3018, PERIC1),
|
|
SFR(QCH_CON_PERIC1_CMU_PERIC1_QCH, 0x301c, PERIC1),
|
|
SFR(QCH_CON_SPI_CAM0_QCH, 0x3020, PERIC1),
|
|
SFR(QCH_CON_SYSREG_PERIC1_QCH, 0x3024, PERIC1),
|
|
SFR(QCH_CON_UART_BT_QCH, 0x3028, PERIC1),
|
|
SFR(QCH_CON_USI06_I2C_QCH, 0x302c, PERIC1),
|
|
SFR(QCH_CON_USI06_USI_QCH, 0x3030, PERIC1),
|
|
SFR(QCH_CON_USI07_I2C_QCH, 0x3034, PERIC1),
|
|
SFR(QCH_CON_USI07_USI_QCH, 0x3038, PERIC1),
|
|
SFR(QCH_CON_USI08_I2C_QCH, 0x303c, PERIC1),
|
|
SFR(QCH_CON_USI08_USI_QCH, 0x3040, PERIC1),
|
|
SFR(QCH_CON_USI09_I2C_QCH, 0x3044, PERIC1),
|
|
SFR(QCH_CON_USI09_USI_QCH, 0x3048, PERIC1),
|
|
SFR(QCH_CON_USI10_I2C_QCH, 0x304c, PERIC1),
|
|
SFR(QCH_CON_USI10_USI_QCH, 0x3050, PERIC1),
|
|
SFR(QCH_CON_USI11_I2C_QCH, 0x3054, PERIC1),
|
|
SFR(QCH_CON_USI11_USI_QCH, 0x3058, PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP_IPCLKPORT_ACLK, 0x2010, PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK, 0x2040, PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK, 0x2014, PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK, 0x2034, PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, 0x203c, PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, 0x2038, PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK, 0x2000, PERIS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER, 0x0100, PERIS),
|
|
SFR(PLL_CON2_MUX_CLKCMU_PERIS_BUS_USER, 0x0108, PERIS),
|
|
SFR(CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT0, 0x0810, PERIS),
|
|
SFR(CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT1, 0x0814, PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK, 0x202c, PERIS),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIS_GIC, 0x1000, PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK, 0x2030, PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS, 0x200c, PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM, 0x2008, PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, 0x2024, PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK, 0x2018, PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK, 0x201c, PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK, 0x2020, PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK, 0x2028, PERIS),
|
|
SFR(QCH_CON_BUSIF_TMU_QCH, 0x3004, PERIS),
|
|
SFR(QCH_CON_GIC_QCH, 0x3008, PERIS),
|
|
SFR(QCH_CON_LHM_AXI_P_PERIS_QCH, 0x300c, PERIS),
|
|
SFR(QCH_CON_MCT_QCH, 0x3010, PERIS),
|
|
SFR(QCH_CON_OTP_CON_BIRA_QCH, 0x3014, PERIS),
|
|
SFR(QCH_CON_OTP_CON_TOP_QCH, 0x3018, PERIS),
|
|
SFR(QCH_CON_PERIS_CMU_PERIS_QCH, 0x301c, PERIS),
|
|
SFR(QCH_CON_SYSREG_PERIS_QCH, 0x3020, PERIS),
|
|
SFR(QCH_CON_WDT_CLUSTER0_QCH, 0x3024, PERIS),
|
|
SFR(QCH_CON_WDT_CLUSTER1_QCH, 0x3028, PERIS),
|
|
SFR(PLL_CON0_PLL_MIF_S2D, 0x0100, S2D),
|
|
SFR(PLL_LOCKTIME_PLL_MIF_S2D, 0x0000, S2D),
|
|
SFR(CLK_CON_MUX_CLKCMU_MIF_DDRPHY2X_S2D, 0x1000, S2D),
|
|
SFR(CLK_CON_DIV_CLK_MIF_BUSD_S2D, 0x1800, S2D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK, 0x2004, S2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK, 0x200c, S2D),
|
|
SFR(CLK_CON_MUX_MUX_CLK_S2D_CORE, 0x1004, S2D),
|
|
SFR(QCH_CON_S2D_CMU_S2D_QCH, 0x3004, S2D),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF, 0x180c, VTS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VTS_DMIC, 0x1804, VTS),
|
|
SFR(CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT0, 0x0810, VTS),
|
|
SFR(CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT1, 0x0814, VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK, 0x207c, VTS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2, 0x1808, VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_CLK, 0x2038, VTS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_VTS_BUS_USER, 0x0100, VTS),
|
|
SFR(PLL_CON2_MUX_CLKCMU_VTS_BUS_USER, 0x0108, VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_DIV2_CLK, 0x2000, VTS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_VTS_DLL_USER, 0x0120, VTS),
|
|
SFR(PLL_CON2_MUX_CLKCMU_VTS_DLL_USER, 0x0168, VTS),
|
|
SFR(CLK_CON_MUX_MUX_CLK_VTS_BUS, 0x1000, VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IPCLKPORT_CLK, 0x2080, VTS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VTS_BUS, 0x1800, VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_MUX_IPCLKPORT_D0, 0x2008, VTS),
|
|
SFR(QCH_CON_AHB_BUSMATRIX_QCH_SYS, 0x3014, VTS),
|
|
SFR(QCH_CON_ASYNCAHBM_VTS_QCH, 0x3018, VTS),
|
|
SFR(QCH_CON_CORTEXM4INTEGRATION_QCH_CPU, 0x301c, VTS),
|
|
SFR(QCH_CON_DMIC_AHB0_QCH_PCLK, 0x3020, VTS),
|
|
SFR(QCH_CON_DMIC_AHB1_QCH_PCLK, 0x3024, VTS),
|
|
SFR(QCH_CON_DMIC_IF_QCH_PCLK, 0x3028, VTS),
|
|
SFR(DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK, 0x3000, VTS),
|
|
SFR(QCH_CON_GPIO_VTS_QCH, 0x302c, VTS),
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SFR(QCH_CON_HWACG_SYS_DMIC0_QCH, 0x3030, VTS),
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SFR(QCH_CON_HWACG_SYS_DMIC1_QCH, 0x3034, VTS),
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SFR(QCH_CON_MAILBOX_VTS2CHUB_QCH, 0x303c, VTS),
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SFR(QCH_CON_SYSREG_VTS_QCH, 0x3040, VTS),
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SFR(QCH_CON_VTS_CMU_VTS_QCH, 0x3044, VTS),
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SFR(QCH_CON_WDT_VTS_QCH, 0x3048, VTS),
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SFR(DMYQCH_CON_U_DMIC_CLK_MUX_QCH, 0x3008, VTS),
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/*====================The section of controller option SFR instance===================*/
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SFR(APM_CMU_APM_CONTROLLER_OPTION, 0x0800, APM),
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SFR(AUD_CMU_AUD_CONTROLLER_OPTION, 0x0800, AUD),
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SFR(BUS1_CMU_BUS1_CONTROLLER_OPTION, 0x0800, BUS1),
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SFR(BUSC_CMU_BUSC_CONTROLLER_OPTION, 0x0800, BUSC),
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SFR(CHUB_CMU_CHUB_CONTROLLER_OPTION, 0x0800, CHUB),
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SFR(CMGP_CMU_CMGP_CONTROLLER_OPTION, 0x0800, CMGP),
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|
SFR(CMU_CMU_CMU_CONTROLLER_OPTION, 0x0800, CMU),
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|
SFR(CORE_CMU_CORE_CONTROLLER_OPTION, 0x0800, CORE),
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SFR(CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION, 0x0800, CPUCL0),
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|
SFR(CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION, 0x0800, CPUCL1),
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|
SFR(DCF_CMU_DCF_CONTROLLER_OPTION, 0x0800, DCF),
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|
SFR(DCPOST_CMU_DCPOST_CONTROLLER_OPTION, 0x0800, DCPOST),
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|
SFR(DCRD_CMU_DCRD_CONTROLLER_OPTION, 0x0800, DCRD),
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|
SFR(DPU_CMU_DPU_CONTROLLER_OPTION, 0x0800, DPU),
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|
SFR(DSPM_CMU_DSPM_CONTROLLER_OPTION, 0x0800, DSPM),
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|
SFR(DSPS_CMU_DSPS_CONTROLLER_OPTION, 0x0800, DSPS),
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|
SFR(FSYS0_CMU_FSYS0_CONTROLLER_OPTION, 0x0800, FSYS0),
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|
SFR(FSYS1_CMU_FSYS1_CONTROLLER_OPTION, 0x0800, FSYS1),
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|
SFR(G2D_CMU_G2D_CONTROLLER_OPTION, 0x0800, G2D),
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|
SFR(G3D_CMU_G3D_CONTROLLER_OPTION, 0x0800, G3D),
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|
SFR(ISPHQ_CMU_ISPHQ_CONTROLLER_OPTION, 0x0800, ISPHQ),
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|
SFR(ISPLP_CMU_ISPLP_CONTROLLER_OPTION, 0x0800, ISPLP),
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|
SFR(ISPPRE_CMU_ISPPRE_CONTROLLER_OPTION, 0x0800, ISPPRE),
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|
SFR(IVA_CMU_IVA_CONTROLLER_OPTION, 0x0800, IVA),
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|
SFR(MFC_CMU_MFC_CONTROLLER_OPTION, 0x0800, MFC),
|
|
SFR(MIF_CMU_MIF_CONTROLLER_OPTION, 0x0800, MIF),
|
|
SFR(PERIC0_CMU_PERIC0_CONTROLLER_OPTION, 0x0800, PERIC0),
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|
SFR(PERIC1_CMU_PERIC1_CONTROLLER_OPTION, 0x0800, PERIC1),
|
|
SFR(PERIS_CMU_PERIS_CONTROLLER_OPTION, 0x0800, PERIS),
|
|
SFR(S2D_CMU_S2D_CONTROLLER_OPTION, 0x0800, S2D),
|
|
SFR(VTS_CMU_VTS_CONTROLLER_OPTION, 0x0804, VTS),
|
|
};
|
|
|
|
unsigned int cmucal_sfr_size = 1710;
|
|
unsigned int dbg_offset = 0x4000;
|
|
|
|
/*====================The section of SFR Access instance===================*/
|
|
struct sfr_access cmucal_sfr_access_list[] __initdata = {
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|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_APM_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_APM_BUS_USER),
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|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_APM_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_APM_BUS_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_APM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_APM_BUS_USER),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_APM_DLL_CHUB_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_APM_DLL_CHUB),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_APM_DLL_CHUB_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_APM_DLL_CHUB),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_APM_DLL_CHUB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_APM_DLL_CHUB),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_APM_DLL_VTS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_APM_DLL_VTS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_APM_DLL_VTS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_APM_DLL_VTS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_APM_DLL_VTS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_APM_DLL_VTS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_APM_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_APM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_APM_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_APM_DLL_CMGP_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_APM_DLL_CMGP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_APM_DLL_CMGP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_APM_DLL_CMGP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_APM_DLL_CMGP_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_APM_DLL_CMGP),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CHUB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CHUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CHUB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CHUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CHUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_CP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CHUB2CP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CHUB2CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CHUB2CP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CHUB2CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CHUB2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CHUB2CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_GNSS2CP_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_P_APM2CMGP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_P_APM2CMGP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_P_APM2CMGP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_P_APM2CMGP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_P_APM2CMGP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_P_APM2CMGP_IPCLKPORT_I_CLK),
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SFR_ACCESS(PLL_CON0_MUX_DLL_USER_BUSY, 7, 1, PLL_CON0_MUX_DLL_USER),
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SFR_ACCESS(PLL_CON0_MUX_DLL_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_DLL_USER),
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SFR_ACCESS(PLL_CON2_MUX_DLL_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_DLL_USER),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_APM_DLL_CMGP_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_APM_DLL_CMGP),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_APM_DLL_CMGP_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_APM_DLL_CMGP),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_APM_DLL_CMGP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_APM_DLL_CMGP),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_APM_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_APM_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_APM_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_APM_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_APM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_APM_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_CHUB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_CHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_CHUB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_CHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_CHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_APM_DLL_VTS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_APM_DLL_VTS),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_APM_DLL_VTS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_APM_DLL_VTS),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_APM_DLL_VTS_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_APM_DLL_VTS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_APM_BUS),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_APM_BUS),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_APM_BUS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK),
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SFR_ACCESS(QCH_CON_APBIF_GPIO_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_APBIF_GPIO_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_APBIF_GPIO_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_GPIO_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_APBIF_GPIO_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_GPIO_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_APBIF_GPIO_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_GPIO_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_APBIF_PMU_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_PMU_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_PMU_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_PMU_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_APBIF_RTC_QCH_ENABLE, 0, 1, QCH_CON_APBIF_RTC_QCH),
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SFR_ACCESS(QCH_CON_APBIF_RTC_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_RTC_QCH),
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SFR_ACCESS(QCH_CON_APBIF_RTC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_RTC_QCH),
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SFR_ACCESS(QCH_CON_APBIF_RTC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_RTC_QCH),
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SFR_ACCESS(QCH_CON_APBIF_TOP_RTC_QCH_ENABLE, 0, 1, QCH_CON_APBIF_TOP_RTC_QCH),
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SFR_ACCESS(QCH_CON_APBIF_TOP_RTC_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_TOP_RTC_QCH),
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SFR_ACCESS(QCH_CON_APBIF_TOP_RTC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_TOP_RTC_QCH),
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SFR_ACCESS(QCH_CON_APBIF_TOP_RTC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_TOP_RTC_QCH),
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SFR_ACCESS(QCH_CON_APM_CMU_APM_QCH_ENABLE, 0, 1, QCH_CON_APM_CMU_APM_QCH),
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SFR_ACCESS(QCH_CON_APM_CMU_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_APM_CMU_APM_QCH),
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SFR_ACCESS(QCH_CON_APM_CMU_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APM_CMU_APM_QCH),
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SFR_ACCESS(QCH_CON_APM_CMU_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APM_CMU_APM_QCH),
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SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_GREBE_ENABLE, 0, 1, QCH_CON_GREBEINTEGRATION_QCH_GREBE),
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SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_GREBE_CLOCK_REQ, 1, 1, QCH_CON_GREBEINTEGRATION_QCH_GREBE),
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SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_GREBE_EXPIRE_VAL, 16, 10, QCH_CON_GREBEINTEGRATION_QCH_GREBE),
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SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_GREBE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GREBEINTEGRATION_QCH_GREBE),
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SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_DBG_ENABLE, 0, 1, QCH_CON_GREBEINTEGRATION_QCH_DBG),
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SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_DBG_CLOCK_REQ, 1, 1, QCH_CON_GREBEINTEGRATION_QCH_DBG),
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SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_DBG_EXPIRE_VAL, 16, 10, QCH_CON_GREBEINTEGRATION_QCH_DBG),
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SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_DBG_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GREBEINTEGRATION_QCH_DBG),
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SFR_ACCESS(QCH_CON_INTMEM_QCH_ENABLE, 0, 1, QCH_CON_INTMEM_QCH),
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SFR_ACCESS(QCH_CON_INTMEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_INTMEM_QCH),
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SFR_ACCESS(QCH_CON_INTMEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_INTMEM_QCH),
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SFR_ACCESS(QCH_CON_INTMEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_INTMEM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_APM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_APM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_APM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_APM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_CHUB_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_APM_CHUB_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_APM_CHUB_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_APM_CHUB_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_APM_CHUB_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_CP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_APM_CP_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_APM_CP_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_APM_CP_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_APM_CP_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_GNSS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_APM_GNSS_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_APM_GNSS_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_APM_GNSS_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_APM_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_APM_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_LP_CHUB_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_LP_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_LP_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_LP_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_LP_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_LP_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_LP_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_LP_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_APM2CMGP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_APM2CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_APM2CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_APM2CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_APM2CMGP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_APM2CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_APM2CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_APM2CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2CHUB_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2CP_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2CP_S_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP2CP_S_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2CP_S_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP2CP_S_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2CP_S_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP2CP_S_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2CP_S_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP2CP_S_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2GNSS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2VTS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP2VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP2VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP2VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP2VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2AP_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM2AP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2AP_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM2AP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2AP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM2AP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2AP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM2AP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2CHUB_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2CP_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2GNSS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CHUB2CP_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_CHUB2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CHUB2CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_CHUB2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CHUB2CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_CHUB2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CHUB2CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_CHUB2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_GNSS2CHUB_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_GNSS2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_GNSS2CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_GNSS2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_GNSS2CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_GNSS2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_GNSS2CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_GNSS2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_GNSS2CP_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_GNSS2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_GNSS2CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_GNSS2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_GNSS2CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_GNSS2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_GNSS2CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_GNSS2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_PEM_QCH_ENABLE, 0, 1, QCH_CON_PEM_QCH),
|
|
SFR_ACCESS(QCH_CON_PEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_PEM_QCH),
|
|
SFR_ACCESS(QCH_CON_PEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PEM_QCH),
|
|
SFR_ACCESS(QCH_CON_PEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PEM_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_APM_QCH_ENABLE, 0, 1, QCH_CON_PGEN_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_PGEN_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PGEN_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PGEN_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_PMU_INTR_GEN_QCH_ENABLE, 0, 1, QCH_CON_PMU_INTR_GEN_QCH),
|
|
SFR_ACCESS(QCH_CON_PMU_INTR_GEN_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_INTR_GEN_QCH),
|
|
SFR_ACCESS(QCH_CON_PMU_INTR_GEN_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_INTR_GEN_QCH),
|
|
SFR_ACCESS(QCH_CON_PMU_INTR_GEN_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PMU_INTR_GEN_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH),
|
|
SFR_ACCESS(QCH_CON_SPEEDY_APM_QCH_ENABLE, 0, 1, QCH_CON_SPEEDY_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SPEEDY_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPEEDY_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SPEEDY_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPEEDY_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SPEEDY_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPEEDY_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SPEEDY_SUB_APM_QCH_ENABLE, 0, 1, QCH_CON_SPEEDY_SUB_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SPEEDY_SUB_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPEEDY_SUB_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SPEEDY_SUB_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPEEDY_SUB_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SPEEDY_SUB_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPEEDY_SUB_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_APM_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_APM_QCH_ENABLE, 0, 1, QCH_CON_WDT_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_APM_QCH),
|
|
SFR_ACCESS(PLL_CON0_PLL_AUD_DIV_P, 8, 6, PLL_CON0_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON0_PLL_AUD_DIV_M, 16, 10, PLL_CON0_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON0_PLL_AUD_DIV_S, 0, 3, PLL_CON0_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON0_PLL_AUD_ENABLE, 31, 1, PLL_CON0_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON0_PLL_AUD_STABLE, 29, 1, PLL_CON0_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD_DIV_K, 0, 16, PLL_CON3_PLL_AUD),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_AUD_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_AUD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_PLL_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_PLL),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_PLL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_PLL),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_PLL_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_AUD_PLL),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_AUDIF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_AUDIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_AUDIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_AUDIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_AUDIF_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_AUDIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ATCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_ATCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_ATCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ATCLK_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUD_CPU_ATCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_DSIF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_DSIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_DSIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_DSIF_DIVRATIO, 0, 5, CLK_CON_DIV_DIV_CLK_AUD_DSIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF0_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF1_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF1_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF2_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF2_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF3_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF3_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF3_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF3_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF2_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_AUD_CPU_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_AUD_CPU_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_AUD_CPU_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_AUD_CPU_USER),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_ATB_AUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_ATB_AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_ATB_AUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_ATB_AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_ATB_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_ATB_AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_AUD_CMU_AUD_CLKOUT1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ATCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ATCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ATCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ATCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ATCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_BUS),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_BUS),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUD_BUS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUSP_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_AUD_BUSP),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_DMIC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_DMIC),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_DMIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_DMIC),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_DMIC_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_AUD_DMIC),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ATB_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ATB),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ATB_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ATB),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ATB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ATB),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_DAP_IPCLKPORT_DAPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_DAP_IPCLKPORT_DAPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_DAP_IPCLKPORT_DAPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_DAP_IPCLKPORT_DAPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_DAP_IPCLKPORT_DAPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_DAP_IPCLKPORT_DAPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK),
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SFR_ACCESS(CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_BUSY, 16, 1, CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU),
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SFR_ACCESS(CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU),
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SFR_ACCESS(CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_SELECT, 0, 5, CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_XIU_P_AUD_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_XIU_P_AUD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_XIU_P_AUD_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_XIU_P_AUD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_XIU_P_AUD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_XIU_P_AUD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_IPCLKPORT_PCLKS),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI2APB_AUD_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI2APB_AUD_IPCLKPORT_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI2APB_AUD_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI2APB_AUD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI2APB_AUD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI2APB_AUD_IPCLKPORT_ACLK),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_ACLK_ENABLE, 0, 1, QCH_CON_ABOX_QCH_ACLK),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_ACLK_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_ACLK),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_ACLK_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_ACLK),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_ACLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_ACLK),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK_DSIF_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK_DSIF),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK_DSIF_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK_DSIF),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK_DSIF_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_BCLK_DSIF),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK_DSIF_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK_DSIF),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK0_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK0),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK0_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK0),
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SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK0_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_BCLK0),
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SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK0),
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SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK1_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK1),
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SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK1_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK1),
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SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK1_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_BCLK1),
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SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK1),
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SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK2_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK2),
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SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK2_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK2),
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SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK2_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_BCLK2),
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SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK2),
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SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK3_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK3),
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SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK3_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK3),
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SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK3_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_BCLK3),
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SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK3_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK3),
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SFR_ACCESS(DMYQCH_CON_ABOX_QCH_DUMMY_ENABLE, 0, 1, DMYQCH_CON_ABOX_QCH_DUMMY),
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SFR_ACCESS(DMYQCH_CON_ABOX_QCH_DUMMY_CLOCK_REQ, 1, 1, DMYQCH_CON_ABOX_QCH_DUMMY),
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SFR_ACCESS(DMYQCH_CON_ABOX_QCH_DUMMY_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ABOX_QCH_DUMMY),
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SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ASB_ENABLE, 0, 1, QCH_CON_ABOX_QCH_CCLK_ASB),
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SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ASB_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_CCLK_ASB),
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SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ASB_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_CCLK_ASB),
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SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ASB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_CCLK_ASB),
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SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ATB_ENABLE, 0, 1, QCH_CON_ABOX_QCH_CCLK_ATB),
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SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ATB_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_CCLK_ATB),
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SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ATB_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_CCLK_ATB),
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SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ATB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_CCLK_ATB),
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SFR_ACCESS(QCH_CON_AUD_CMU_AUD_QCH_ENABLE, 0, 1, QCH_CON_AUD_CMU_AUD_QCH),
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SFR_ACCESS(QCH_CON_AUD_CMU_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_AUD_CMU_AUD_QCH),
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SFR_ACCESS(QCH_CON_AUD_CMU_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_AUD_CMU_AUD_QCH),
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SFR_ACCESS(QCH_CON_AUD_CMU_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_AUD_CMU_AUD_QCH),
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SFR_ACCESS(QCH_CON_BTM_AUD_QCH_ENABLE, 0, 1, QCH_CON_BTM_AUD_QCH),
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SFR_ACCESS(QCH_CON_BTM_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_AUD_QCH),
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SFR_ACCESS(QCH_CON_BTM_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_AUD_QCH),
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SFR_ACCESS(QCH_CON_BTM_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_AUD_QCH),
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SFR_ACCESS(DMYQCH_CON_DFTMUX_AUD_QCH_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_AUD_QCH),
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SFR_ACCESS(DMYQCH_CON_DFTMUX_AUD_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_AUD_QCH),
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SFR_ACCESS(DMYQCH_CON_DFTMUX_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_AUD_QCH),
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SFR_ACCESS(DMYQCH_CON_DMIC_QCH_ENABLE, 0, 1, DMYQCH_CON_DMIC_QCH),
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SFR_ACCESS(DMYQCH_CON_DMIC_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_DMIC_QCH),
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SFR_ACCESS(DMYQCH_CON_DMIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DMIC_QCH),
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SFR_ACCESS(QCH_CON_GPIO_AUD_QCH_ENABLE, 0, 1, QCH_CON_GPIO_AUD_QCH),
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SFR_ACCESS(QCH_CON_GPIO_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_AUD_QCH),
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SFR_ACCESS(QCH_CON_GPIO_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_AUD_QCH),
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SFR_ACCESS(QCH_CON_GPIO_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_AUD_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_AUD_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_AUD_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_AUD_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_AUD_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_AUD_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_AUD_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_AUD_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_AUD_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_AUD_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_AUD_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_D_AUD_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_AUD_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_AUD_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_AUD_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_AUD_QCH),
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SFR_ACCESS(QCH_CON_PPMU_AUD_QCH_ENABLE, 0, 1, QCH_CON_PPMU_AUD_QCH),
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SFR_ACCESS(QCH_CON_PPMU_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_AUD_QCH),
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SFR_ACCESS(QCH_CON_PPMU_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_AUD_QCH),
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SFR_ACCESS(QCH_CON_PPMU_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_AUD_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_AUD_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_AUD_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_AUD_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_AUD_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_AUD_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_AUD_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_AUD_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_AUD_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_AUD_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_AUD_QCH),
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SFR_ACCESS(QCH_CON_TREX_AUD_QCH_ENABLE, 0, 1, QCH_CON_TREX_AUD_QCH),
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SFR_ACCESS(QCH_CON_TREX_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_AUD_QCH),
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SFR_ACCESS(QCH_CON_TREX_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_AUD_QCH),
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SFR_ACCESS(QCH_CON_TREX_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_AUD_QCH),
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SFR_ACCESS(QCH_CON_WDT_AUD_QCH_ENABLE, 0, 1, QCH_CON_WDT_AUD_QCH),
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SFR_ACCESS(QCH_CON_WDT_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_AUD_QCH),
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SFR_ACCESS(QCH_CON_WDT_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_AUD_QCH),
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SFR_ACCESS(QCH_CON_WDT_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_AUD_QCH),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_BUS1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_BUS1_BUS_USER),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_BUS1_CMU_BUS1_CLKOUT1),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUS_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUS_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_CHUB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_CHUB_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_CHUB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_CHUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_CHUB_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_BUS1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_BUS1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_BUS1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_BUS1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_BUS1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_BUS1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CHUB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CHUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CHUB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CHUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CHUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_CHUB_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_CHUB_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_CHUB_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_CHUB_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_CHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_CHUB_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D_BUS1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D_BUS1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D_BUS1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D_BUS1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D_BUS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D_BUS1_IPCLKPORT_ACLK),
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SFR_ACCESS(QCH_CON_BAAW_P_CHUB_QCH_ENABLE, 0, 1, QCH_CON_BAAW_P_CHUB_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_P_CHUB_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_P_CHUB_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_P_CHUB_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_GNSS_QCH_ENABLE, 0, 1, QCH_CON_BAAW_P_GNSS_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_P_GNSS_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_P_GNSS_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_P_GNSS_QCH),
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SFR_ACCESS(QCH_CON_BUS1_CMU_BUS1_QCH_ENABLE, 0, 1, QCH_CON_BUS1_CMU_BUS1_QCH),
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SFR_ACCESS(QCH_CON_BUS1_CMU_BUS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUS1_CMU_BUS1_QCH),
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SFR_ACCESS(QCH_CON_BUS1_CMU_BUS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUS1_CMU_BUS1_QCH),
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SFR_ACCESS(QCH_CON_BUS1_CMU_BUS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUS1_CMU_BUS1_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_APM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_APM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_APM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_APM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_APM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_CHUB_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_CHUB_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_CHUB_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_CHUB_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_CHUB_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_GNSS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_GNSS_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_GNSS_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_GNSS_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_GNSS_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_G_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_G_CSSYS_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_G_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_G_CSSYS_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_G_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_G_CSSYS_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_G_CSSYS_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_BUS1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_BUS1_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_BUS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_BUS1_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_BUS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_BUS1_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_BUS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_BUS1_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_CHUB_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_CHUB_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_CHUB_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_CHUB_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_CHUB_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_CSSYS_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_CSSYS_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_CSSYS_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_CSSYS_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_GNSS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_GNSS_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_GNSS_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_GNSS_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_GNSS_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_BUS1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_BUS1_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_BUS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_BUS1_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_BUS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_BUS1_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_BUS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_BUS1_QCH),
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SFR_ACCESS(QCH_CON_TREX_P_BUS1_QCH_ENABLE, 0, 1, QCH_CON_TREX_P_BUS1_QCH),
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SFR_ACCESS(QCH_CON_TREX_P_BUS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_P_BUS1_QCH),
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SFR_ACCESS(QCH_CON_TREX_P_BUS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_P_BUS1_QCH),
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SFR_ACCESS(QCH_CON_TREX_P_BUS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_P_BUS1_QCH),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BUSC_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_BUSC_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BUSC_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_BUSC_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BUSC_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_BUSC_BUSP),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_BUSC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_BUSC_BUS_USER),
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SFR_ACCESS(CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_BUSC_CMU_BUSC_CLKOUT1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BUSC_UID_HPM_BUSC_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BUSC_UID_HPM_BUSC_IPCLKPORT_HPM_TARGETCLK_C),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BUSC_UID_HPM_BUSC_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BUSC_UID_HPM_BUSC_IPCLKPORT_HPM_TARGETCLK_C),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BUSC_UID_HPM_BUSC_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BUSC_UID_HPM_BUSC_IPCLKPORT_HPM_TARGETCLK_C),
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SFR_ACCESS(QCH_CON_BUSC_CMU_BUSC_QCH_ENABLE, 0, 1, QCH_CON_BUSC_CMU_BUSC_QCH),
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SFR_ACCESS(QCH_CON_BUSC_CMU_BUSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSC_CMU_BUSC_QCH),
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SFR_ACCESS(QCH_CON_BUSC_CMU_BUSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSC_CMU_BUSC_QCH),
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SFR_ACCESS(QCH_CON_BUSC_CMU_BUSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSC_CMU_BUSC_QCH),
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|
SFR_ACCESS(QCH_CON_BUSIF_CMUTOPC_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_CMUTOPC_QCH),
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|
SFR_ACCESS(QCH_CON_BUSIF_CMUTOPC_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_CMUTOPC_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_CMUTOPC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_CMUTOPC_QCH),
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|
SFR_ACCESS(QCH_CON_BUSIF_CMUTOPC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_CMUTOPC_QCH),
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|
SFR_ACCESS(QCH_CON_BUSIF_HPMBUSC_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPMBUSC_QCH),
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|
SFR_ACCESS(QCH_CON_BUSIF_HPMBUSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPMBUSC_QCH),
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|
SFR_ACCESS(QCH_CON_BUSIF_HPMBUSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPMBUSC_QCH),
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|
SFR_ACCESS(QCH_CON_BUSIF_HPMBUSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_HPMBUSC_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D0_DSPM_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D0_DSPM_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D0_DSPM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D0_DSPM_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D0_DSPM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D0_DSPM_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D0_DSPM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D0_DSPM_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D0_G2D_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D0_G2D_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D0_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D0_G2D_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D0_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D0_G2D_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D0_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D0_G2D_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D1_DSPM_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D1_DSPM_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D1_DSPM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D1_DSPM_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D1_DSPM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D1_DSPM_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D1_DSPM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D1_DSPM_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D1_G2D_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D1_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D1_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D1_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D1_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D1_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D1_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D1_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D2_DSPM_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D2_DSPM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D2_DSPM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D2_DSPM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D2_DSPM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D2_DSPM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D2_DSPM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D2_DSPM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D2_G2D_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D2_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D2_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D2_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D2_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D2_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D2_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D2_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_FSYS0_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_FSYS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_FSYS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_FSYS0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_FSYS1_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_FSYS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_FSYS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D_FSYS1_QCH),
|
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SFR_ACCESS(QCH_CON_LHM_ACEL_D_FSYS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D_FSYS1_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D_IVA_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D_IVA_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D_IVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D_IVA_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_IVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D_IVA_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D_IVA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D_IVA_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D0_DPU_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D0_DPU_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D0_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D0_DPU_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D0_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D0_DPU_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D0_DPU_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D0_ISPLP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D0_ISPLP_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D0_ISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D0_ISPLP_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D0_ISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D0_ISPLP_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D0_ISPLP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D0_ISPLP_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D0_MFC_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D0_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D0_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D0_MFC_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D0_MFC_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D0_MFC_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_DPU_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D1_DPU_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D1_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D1_DPU_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D1_DPU_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D1_DPU_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D1_ISPLP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D1_ISPLP_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_ISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D1_ISPLP_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_ISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D1_ISPLP_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D1_ISPLP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D1_ISPLP_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MFC_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D1_MFC_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D1_MFC_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D1_MFC_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D1_MFC_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D2_DPU_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D2_DPU_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D2_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D2_DPU_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D2_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D2_DPU_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D2_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D2_DPU_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D_AUD_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_AUD_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_AUD_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_AUD_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_BUS1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_BUS1_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D_BUS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_BUS1_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D_BUS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_BUS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_DCF_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_DCF_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D_DCF_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_DCF_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D_DCF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_DCF_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D_DCF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_DCF_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_DCRD_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_DCRD_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D_DCRD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_DCRD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_DCRD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_DCRD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_DCRD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_DCRD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_ISPHQ_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_ISPHQ_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D_ISPHQ_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_ISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_ISPHQ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_ISPHQ_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D_ISPHQ_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_ISPHQ_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D_ISPPRE_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_ISPPRE_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D_ISPPRE_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_ISPPRE_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D_ISPPRE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_ISPPRE_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D_ISPPRE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_ISPPRE_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_D_IVASC_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_IVASC_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_D_IVASC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_IVASC_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_D_IVASC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_IVASC_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_D_IVASC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_IVASC_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_P_AUD_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_AUD_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_P_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_AUD_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_P_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_AUD_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DCF_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_DCF_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DCF_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_DCF_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DCF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_DCF_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DCF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_DCF_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DCRD_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_DCRD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DCRD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_DCRD_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DCRD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_DCRD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DCRD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_DCRD_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DPU_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DSPM_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_DSPM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DSPM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_DSPM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DSPM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_DSPM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DSPM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_DSPM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_FSYS0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_FSYS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_FSYS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_FSYS0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_FSYS1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_FSYS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_FSYS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_FSYS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_G2D_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_ISPHQ_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_ISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_ISPHQ_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_ISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_ISPHQ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_ISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_ISPHQ_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_ISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_ISPLP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_ISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_ISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_ISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_ISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_ISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_ISPLP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_ISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_ISPPRE_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_ISPPRE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_ISPPRE_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_ISPPRE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_ISPPRE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_ISPPRE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_ISPPRE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_ISPPRE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_IVA_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_IVA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_IVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_IVA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_IVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_IVA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_IVA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_IVA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MFC_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MIF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MIF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MIF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_MIF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MIF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MIF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MIF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_MIF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF2_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MIF2_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF2_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MIF2_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MIF2_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_MIF2_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF3_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MIF3_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF3_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MIF3_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MIF3_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_MIF3_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA0_QCH_ENABLE, 0, 1, QCH_CON_PDMA0_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PDMA0_QCH),
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|
SFR_ACCESS(QCH_CON_PDMA0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PDMA0_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PDMA0_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_LITE_BUSC_QCH_ENABLE, 0, 1, QCH_CON_PGEN_LITE_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_LITE_BUSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PGEN_LITE_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_LITE_BUSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PGEN_LITE_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_LITE_BUSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PGEN_LITE_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_PDMA0_QCH_ENABLE, 0, 1, QCH_CON_PGEN_PDMA0_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_PDMA0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PGEN_PDMA0_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_PDMA0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PGEN_PDMA0_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_PDMA0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PGEN_PDMA0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_QCH_ENABLE, 0, 1, QCH_CON_PPFW_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPFW_QCH),
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|
SFR_ACCESS(QCH_CON_PPFW_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPFW_QCH),
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|
SFR_ACCESS(QCH_CON_PPFW_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPFW_QCH),
|
|
SFR_ACCESS(QCH_CON_SBIC_QCH_ENABLE, 0, 1, QCH_CON_SBIC_QCH),
|
|
SFR_ACCESS(QCH_CON_SBIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SBIC_QCH),
|
|
SFR_ACCESS(QCH_CON_SBIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SBIC_QCH),
|
|
SFR_ACCESS(QCH_CON_SBIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SBIC_QCH),
|
|
SFR_ACCESS(QCH_CON_SIREX_QCH_ENABLE, 0, 1, QCH_CON_SIREX_QCH),
|
|
SFR_ACCESS(QCH_CON_SIREX_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIREX_QCH),
|
|
SFR_ACCESS(QCH_CON_SIREX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SIREX_QCH),
|
|
SFR_ACCESS(QCH_CON_SIREX_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIREX_QCH),
|
|
SFR_ACCESS(QCH_CON_SPDMA_QCH_ENABLE, 0, 1, QCH_CON_SPDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_SPDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_SPDMA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_SPDMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_BUSC_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_BUSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_BUSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_BUSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_BUSC_QCH_ENABLE, 0, 1, QCH_CON_TREX_D_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_BUSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_BUSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_D_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_BUSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_D_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_BUSC_QCH_ENABLE, 0, 1, QCH_CON_TREX_P_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_BUSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_P_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_BUSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_P_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_BUSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_P_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_RB_BUSC_QCH_ENABLE, 0, 1, QCH_CON_TREX_RB_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_RB_BUSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_RB_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_RB_BUSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_RB_BUSC_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_RB_BUSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_RB_BUSC_QCH),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CHUB_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CHUB_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CHUB_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CHUB_BUS_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CHUB_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CHUB_BUS_USER),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CHUB_CMU_CHUB_CLKOUT1),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CHUB_DLL_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CHUB_DLL_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CHUB_DLL_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CHUB_DLL_BUS_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CHUB_DLL_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CHUB_DLL_BUS_USER),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI01_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CHUB_USI01),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI01_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CHUB_USI01),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI01_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CHUB_USI01),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_I2C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_I2C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI00_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CHUB_USI00),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI00_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CHUB_USI00),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI00_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CHUB_USI00),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI00_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI00_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI00_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI00_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI00_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI00_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI01_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI01_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI01_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI01_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI01_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI01_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_I2C_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_I2C_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI00_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI00),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI00_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI00),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI00_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI00),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI01_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI01),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI01_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI01),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI01_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI01),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CHUB_I2C_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_CHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CHUB_I2C_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_CHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CHUB_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_CHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CHUB_USI00_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_CHUB_USI00),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CHUB_USI00_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_CHUB_USI00),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CHUB_USI00_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_CHUB_USI00),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CHUB_USI01_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_CHUB_USI01),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CHUB_USI01_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_CHUB_USI01),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CHUB_USI01_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_CHUB_USI01),
|
|
SFR_ACCESS(CLK_CON_MUX_CLK_CHUB_TIMER_FCLK_BUSY, 16, 1, CLK_CON_MUX_CLK_CHUB_TIMER_FCLK),
|
|
SFR_ACCESS(CLK_CON_MUX_CLK_CHUB_TIMER_FCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLK_CHUB_TIMER_FCLK),
|
|
SFR_ACCESS(CLK_CON_MUX_CLK_CHUB_TIMER_FCLK_SELECT, 0, 1, CLK_CON_MUX_CLK_CHUB_TIMER_FCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB00_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB00_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB00_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB00_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB00_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB01_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB01_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB01_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB01_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB01_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB01_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB00_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB00_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB00_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB00_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB00_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB01_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB01_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB01_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB01_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB01_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB01_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(QCH_CON_ASYNCAHBM_CHUB_QCH_ENABLE, 0, 1, QCH_CON_ASYNCAHBM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_ASYNCAHBM_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_ASYNCAHBM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_ASYNCAHBM_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ASYNCAHBM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_ASYNCAHBM_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ASYNCAHBM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_D_CHUB_QCH_ENABLE, 0, 1, QCH_CON_BAAW_D_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_D_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_D_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_D_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_D_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_D_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_D_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_APM_CHUB_QCH_ENABLE, 0, 1, QCH_CON_BAAW_P_APM_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_BAAW_P_APM_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_P_APM_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_BAAW_P_APM_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_P_APM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_APM_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_P_APM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_S_CHUB_QCH_ENABLE, 0, 1, QCH_CON_BAAW_S_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_BAAW_S_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_S_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_BAAW_S_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_S_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_BAAW_S_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_S_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_CHUB_CMU_CHUB_QCH_ENABLE, 0, 1, QCH_CON_CHUB_CMU_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_CHUB_CMU_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_CHUB_CMU_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_CHUB_CMU_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CHUB_CMU_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_CHUB_CMU_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CHUB_CMU_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_CM4_CHUB_QCH_ENABLE, 0, 1, QCH_CON_CM4_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_CM4_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_CM4_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_CM4_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CM4_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_CM4_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CM4_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_GPIO_CHUB_QCH_ENABLE, 0, 1, QCH_CON_GPIO_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_GPIO_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_GPIO_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_GPIO_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CHUB00_QCH_ENABLE, 0, 1, QCH_CON_I2C_CHUB00_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CHUB00_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CHUB00_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CHUB00_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CHUB00_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CHUB00_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CHUB00_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CHUB01_QCH_ENABLE, 0, 1, QCH_CON_I2C_CHUB01_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CHUB01_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CHUB01_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CHUB01_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CHUB01_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CHUB01_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CHUB01_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_LP_CHUB_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_LP_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_LP_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_LP_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_LP_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_LP_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_LP_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_LP_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CHUB_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CHUB_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_APM_CHUB_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_APM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_APM_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_APM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_APM_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_APM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_APM_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_APM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_CHUB_QCH_ENABLE, 0, 1, QCH_CON_PDMA_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_PDMA_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PDMA_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PDMA_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_PWM_CHUB_QCH_ENABLE, 0, 1, QCH_CON_PWM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_PWM_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_PWM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_PWM_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PWM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_PWM_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PWM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_D_CHUB_QCH_ENABLE, 0, 1, QCH_CON_SWEEPER_D_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_D_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SWEEPER_D_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_D_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SWEEPER_D_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_D_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SWEEPER_D_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_P_APM_CHUB_QCH_ENABLE, 0, 1, QCH_CON_SWEEPER_P_APM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_P_APM_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SWEEPER_P_APM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_P_APM_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SWEEPER_P_APM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_P_APM_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SWEEPER_P_APM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CHUB_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER_CHUB_QCH_ENABLE, 0, 1, QCH_CON_TIMER_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_TIMER_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TIMER_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TIMER_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB00_QCH_ENABLE, 0, 1, QCH_CON_USI_CHUB00_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB00_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CHUB00_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB00_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_CHUB00_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB00_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CHUB00_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB01_QCH_ENABLE, 0, 1, QCH_CON_USI_CHUB01_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB01_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CHUB01_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB01_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_CHUB01_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB01_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CHUB01_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CHUB_QCH_ENABLE, 0, 1, QCH_CON_WDT_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_CHUB_QCH),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CMGP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CMGP_BUS_USER),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CMGP_CMU_CMGP_CLKOUT1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_I2C_CMGP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_I2C_CMGP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_I2C_CMGP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_I2C_CMGP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_I2C_CMGP_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_I2C_CMGP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_I2C_CMGP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_I2C_CMGP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_I2C_CMGP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_I2C_CMGP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_I2C_CMGP_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_I2C_CMGP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_USI_CMGP01_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_USI_CMGP01),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_USI_CMGP01_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_USI_CMGP01),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_USI_CMGP01_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_USI_CMGP01),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_USI_CMGP00_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_USI_CMGP00),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_USI_CMGP00_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_USI_CMGP00),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_USI_CMGP00_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_USI_CMGP00),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_USI_CMGP01_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_USI_CMGP01),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_USI_CMGP01_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_USI_CMGP01),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_USI_CMGP01_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_USI_CMGP01),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_USI_CMGP00_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_USI_CMGP00),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_USI_CMGP00_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_USI_CMGP00),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_USI_CMGP00_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_USI_CMGP00),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_USI_CMGP02_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_USI_CMGP02),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_USI_CMGP02_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_USI_CMGP02),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_USI_CMGP02_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_USI_CMGP02),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_USI_CMGP03_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_USI_CMGP03),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_USI_CMGP03_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_USI_CMGP03),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_USI_CMGP03_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_USI_CMGP03),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_USI_CMGP02_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_USI_CMGP02),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_USI_CMGP02_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_USI_CMGP02),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_USI_CMGP02_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_USI_CMGP02),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_USI_CMGP03_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_USI_CMGP03),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_USI_CMGP03_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_USI_CMGP03),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_USI_CMGP03_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_USI_CMGP03),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_AXI2APB_CMGP1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP00_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP00_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP00_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP00_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP00_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP00_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP00_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP00_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP00_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP00_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP00_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP00_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP01_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP01_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP01_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP01_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP01_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP01_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP02_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP02_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP02_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP02_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP02_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP02_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP03_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP03_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP03_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP03_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP03_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI_CMGP03_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP01_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP01_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP01_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP01_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP01_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP01_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP02_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP02_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP02_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP02_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP02_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP02_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP03_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP03_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP03_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP03_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP03_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_CMGP03_IPCLKPORT_CLK),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CMGP_DLL_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CMGP_DLL_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CMGP_DLL_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CMGP_DLL_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CMGP_DLL_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CMGP_DLL_USER),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_BUS),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_BUS),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_BUS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_XIU_P_CMGP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_XIU_P_CMGP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_XIU_P_CMGP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_XIU_P_CMGP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_XIU_P_CMGP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_XIU_P_CMGP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_MUX_CLK_CMGP_ADC_BUSY, 16, 1, CLK_CON_MUX_CLK_CMGP_ADC),
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SFR_ACCESS(CLK_CON_MUX_CLK_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLK_CMGP_ADC),
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SFR_ACCESS(CLK_CON_MUX_CLK_CMGP_ADC_SELECT, 0, 1, CLK_CON_MUX_CLK_CMGP_ADC),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_ADC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_ADC),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_ADC),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_ADC_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_ADC),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_P_APM2CMGP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_P_APM2CMGP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_P_APM2CMGP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_P_APM2CMGP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_P_APM2CMGP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_P_APM2CMGP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_I2C_CMGP_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_I2C_CMGP),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_I2C_CMGP_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_I2C_CMGP),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_I2C_CMGP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_I2C_CMGP),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_USI_CMGP00_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_USI_CMGP00),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_USI_CMGP00_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_USI_CMGP00),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_USI_CMGP00_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_USI_CMGP00),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_USI_CMGP01_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_USI_CMGP01),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_USI_CMGP01_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_USI_CMGP01),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_USI_CMGP01_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_USI_CMGP01),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_USI_CMGP02_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_USI_CMGP02),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_USI_CMGP02_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_USI_CMGP02),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_USI_CMGP02_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_USI_CMGP02),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_USI_CMGP03_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_USI_CMGP03),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_USI_CMGP03_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_USI_CMGP03),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_USI_CMGP03_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_USI_CMGP03),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_CHUB_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(QCH_CON_ADC_CMGP_QCH_S0_ENABLE, 0, 1, QCH_CON_ADC_CMGP_QCH_S0),
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SFR_ACCESS(QCH_CON_ADC_CMGP_QCH_S0_CLOCK_REQ, 1, 1, QCH_CON_ADC_CMGP_QCH_S0),
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SFR_ACCESS(QCH_CON_ADC_CMGP_QCH_S0_EXPIRE_VAL, 16, 10, QCH_CON_ADC_CMGP_QCH_S0),
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|
SFR_ACCESS(QCH_CON_ADC_CMGP_QCH_S0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ADC_CMGP_QCH_S0),
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|
SFR_ACCESS(QCH_CON_ADC_CMGP_QCH_S1_ENABLE, 0, 1, QCH_CON_ADC_CMGP_QCH_S1),
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|
SFR_ACCESS(QCH_CON_ADC_CMGP_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_ADC_CMGP_QCH_S1),
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|
SFR_ACCESS(QCH_CON_ADC_CMGP_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_ADC_CMGP_QCH_S1),
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|
SFR_ACCESS(QCH_CON_ADC_CMGP_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ADC_CMGP_QCH_S1),
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|
SFR_ACCESS(DMYQCH_CON_ADC_CMGP_QCH_ADC_ENABLE, 0, 1, DMYQCH_CON_ADC_CMGP_QCH_ADC),
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SFR_ACCESS(DMYQCH_CON_ADC_CMGP_QCH_ADC_CLOCK_REQ, 1, 1, DMYQCH_CON_ADC_CMGP_QCH_ADC),
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SFR_ACCESS(DMYQCH_CON_ADC_CMGP_QCH_ADC_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADC_CMGP_QCH_ADC),
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SFR_ACCESS(QCH_CON_CMGP_CMU_CMGP_QCH_ENABLE, 0, 1, QCH_CON_CMGP_CMU_CMGP_QCH),
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SFR_ACCESS(QCH_CON_CMGP_CMU_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_CMGP_CMU_CMGP_QCH),
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SFR_ACCESS(QCH_CON_CMGP_CMU_CMGP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CMGP_CMU_CMGP_QCH),
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SFR_ACCESS(QCH_CON_CMGP_CMU_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CMGP_CMU_CMGP_QCH),
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SFR_ACCESS(QCH_CON_GPIO_CMGP_QCH_ENABLE, 0, 1, QCH_CON_GPIO_CMGP_QCH),
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SFR_ACCESS(QCH_CON_GPIO_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_CMGP_QCH),
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SFR_ACCESS(QCH_CON_GPIO_CMGP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_CMGP_QCH),
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SFR_ACCESS(QCH_CON_GPIO_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_CMGP_QCH),
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SFR_ACCESS(QCH_CON_I2C_CMGP00_QCH_ENABLE, 0, 1, QCH_CON_I2C_CMGP00_QCH),
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SFR_ACCESS(QCH_CON_I2C_CMGP00_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CMGP00_QCH),
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SFR_ACCESS(QCH_CON_I2C_CMGP00_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CMGP00_QCH),
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SFR_ACCESS(QCH_CON_I2C_CMGP00_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CMGP00_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CMGP01_QCH_ENABLE, 0, 1, QCH_CON_I2C_CMGP01_QCH),
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SFR_ACCESS(QCH_CON_I2C_CMGP01_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CMGP01_QCH),
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SFR_ACCESS(QCH_CON_I2C_CMGP01_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CMGP01_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CMGP01_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CMGP01_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CMGP02_QCH_ENABLE, 0, 1, QCH_CON_I2C_CMGP02_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CMGP02_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CMGP02_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CMGP02_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CMGP02_QCH),
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SFR_ACCESS(QCH_CON_I2C_CMGP02_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CMGP02_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CMGP03_QCH_ENABLE, 0, 1, QCH_CON_I2C_CMGP03_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CMGP03_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CMGP03_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CMGP03_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CMGP03_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CMGP03_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CMGP03_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM2CMGP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_APM2CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM2CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_APM2CMGP_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM2CMGP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_APM2CMGP_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_APM2CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_APM2CMGP_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CMGP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CMGP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CMGP_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CHUB_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CMGP2CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2CP_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2CP_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CMGP2CP_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2CP_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2GNSS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2GNSS_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CMGP2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_AP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2PMU_AP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_AP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2PMU_AP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_AP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CMGP2PMU_AP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_AP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2PMU_AP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_CHUB_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2PMU_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2PMU_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CMGP2PMU_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2PMU_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP00_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP00_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP00_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP00_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP00_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_CMGP00_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP00_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP00_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP01_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP01_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP01_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP01_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP01_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_CMGP01_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP01_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP01_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP02_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP02_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP02_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP02_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP02_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_CMGP02_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP02_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP02_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP03_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP03_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP03_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP03_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP03_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_CMGP03_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP03_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP03_QCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_APM_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_APM_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_APM_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_APM_BUS_DIVRATIO, 0, 2, CLK_CON_DIV_CLKCMU_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED0_DIV2_BUSY, 16, 1, CLK_CON_DIV_DIV_PLL_SHARED0_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED0_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_PLL_SHARED0_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED0_DIV2_DIVRATIO, 0, 1, CLK_CON_DIV_DIV_PLL_SHARED0_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIS_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIS_BUS),
|
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIS_BUS),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIS_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIS_BUS),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_FSYS0_BUS),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS0_BUS),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_FSYS0_BUS),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPU_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_DPU_BUS),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_DPU_BUS),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPU_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_DPU_BUS),
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SFR_ACCESS(PLL_CON0_PLL_SHARED1_DIV_P, 8, 6, PLL_CON0_PLL_SHARED1),
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SFR_ACCESS(PLL_CON0_PLL_SHARED1_DIV_M, 16, 10, PLL_CON0_PLL_SHARED1),
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SFR_ACCESS(PLL_CON0_PLL_SHARED1_DIV_S, 0, 3, PLL_CON0_PLL_SHARED1),
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SFR_ACCESS(PLL_CON0_PLL_SHARED1_ENABLE, 31, 1, PLL_CON0_PLL_SHARED1),
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SFR_ACCESS(PLL_CON0_PLL_SHARED1_STABLE, 29, 1, PLL_CON0_PLL_SHARED1),
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SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED1_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED1),
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SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED1_DIV2_BUSY, 16, 1, CLK_CON_DIV_DIV_PLL_SHARED1_DIV2),
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SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED1_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_PLL_SHARED1_DIV2),
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SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED1_DIV2_DIVRATIO, 0, 1, CLK_CON_DIV_DIV_PLL_SHARED1_DIV2),
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SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_MIF_SWITCH),
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SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_MIF_SWITCH),
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SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_MIF_SWITCH),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUS1_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_BUS1_BUS),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_BUS1_BUS),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUS1_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_BUS1_BUS),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS),
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SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED2_DIV2_BUSY, 16, 1, CLK_CON_DIV_DIV_PLL_SHARED2_DIV2),
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SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED2_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_PLL_SHARED2_DIV2),
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SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED2_DIV2_DIVRATIO, 0, 1, CLK_CON_DIV_DIV_PLL_SHARED2_DIV2),
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SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED3_DIV2_BUSY, 16, 1, CLK_CON_DIV_DIV_PLL_SHARED3_DIV2),
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SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED3_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_PLL_SHARED3_DIV2),
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SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED3_DIV2_DIVRATIO, 0, 1, CLK_CON_DIV_DIV_PLL_SHARED3_DIV2),
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SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED4_DIV2_BUSY, 16, 1, CLK_CON_DIV_DIV_PLL_SHARED4_DIV2),
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SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED4_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_PLL_SHARED4_DIV2),
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SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED4_DIV2_DIVRATIO, 0, 1, CLK_CON_DIV_DIV_PLL_SHARED4_DIV2),
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|
SFR_ACCESS(PLL_CON0_PLL_SHARED4_DIV_P, 8, 6, PLL_CON0_PLL_SHARED4),
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SFR_ACCESS(PLL_CON0_PLL_SHARED4_DIV_M, 16, 10, PLL_CON0_PLL_SHARED4),
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|
SFR_ACCESS(PLL_CON0_PLL_SHARED4_DIV_S, 0, 3, PLL_CON0_PLL_SHARED4),
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|
SFR_ACCESS(PLL_CON0_PLL_SHARED4_ENABLE, 31, 1, PLL_CON0_PLL_SHARED4),
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|
SFR_ACCESS(PLL_CON0_PLL_SHARED4_STABLE, 29, 1, PLL_CON0_PLL_SHARED4),
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|
SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED4_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED4),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED0_DIV4_BUSY, 16, 1, CLK_CON_DIV_DIV_PLL_SHARED0_DIV4),
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SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED0_DIV4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_PLL_SHARED0_DIV4),
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SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED0_DIV4_DIVRATIO, 0, 1, CLK_CON_DIV_DIV_PLL_SHARED0_DIV4),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MFC_BUS),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MFC_BUS),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC_BUS_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_MFC_BUS),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MFC_BUS),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MFC_BUS),
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|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MFC_BUS),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MFC_BUS),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MFC_BUS),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MFC_BUS),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_G2D_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_G2D_G2D),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_G2D_G2D),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_G2D_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_G2D_G2D),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_USB30DRD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS0_USB30DRD),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_USB30DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS0_USB30DRD),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_USB30DRD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_FSYS0_USB30DRD),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_USB30DRD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_USB30DRD),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_USB30DRD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_USB30DRD),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_USB30DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_USB30DRD),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_USB30DRD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_FSYS0_USB30DRD),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_USB30DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS0_USB30DRD),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_USB30DRD_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_FSYS0_USB30DRD),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD_DIVRATIO, 0, 9, CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS1_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_FSYS1_BUS),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS1_BUS),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS1_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_FSYS1_BUS),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS),
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|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMGP_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CMGP_BUS),
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|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CMGP_BUS),
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|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMGP_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CMGP_BUS),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSPM_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DSPM_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSPM_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DSPM_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSPM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DSPM_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DSPM_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_DSPM_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DSPM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_DSPM_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DSPM_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_DSPM_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED3_DIV_P, 8, 6, PLL_CON0_PLL_SHARED3),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED3_DIV_M, 16, 10, PLL_CON0_PLL_SHARED3),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED3_DIV_S, 0, 3, PLL_CON0_PLL_SHARED3),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED3_ENABLE, 31, 1, PLL_CON0_PLL_SHARED3),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED3_STABLE, 29, 1, PLL_CON0_PLL_SHARED3),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED3_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED3),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUSC_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_BUSC_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_BUSC_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUSC_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_BUSC_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED2_DIV_P, 8, 6, PLL_CON0_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED2_DIV_M, 16, 10, PLL_CON0_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED2_DIV_S, 0, 3, PLL_CON0_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED2_ENABLE, 31, 1, PLL_CON0_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED2_STABLE, 29, 1, PLL_CON0_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED2_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED0_DIV_P, 8, 6, PLL_CON0_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED0_DIV_M, 16, 10, PLL_CON0_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED0_DIV_S, 0, 3, PLL_CON0_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED0_ENABLE, 31, 1, PLL_CON0_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED0_STABLE, 29, 1, PLL_CON0_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED0_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DSPM_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DSPM_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DSPM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DSPM_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DSPM_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_DSPM_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISPPRE_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_ISPPRE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISPPRE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_ISPPRE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISPPRE_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_ISPPRE_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISPPRE_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_ISPPRE_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISPPRE_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_ISPPRE_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISPPRE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_ISPPRE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISPPRE_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_ISPPRE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISPPRE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_ISPPRE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISPPRE_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_ISPPRE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISPLP_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_ISPLP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISPLP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_ISPLP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISPLP_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_ISPLP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISPHQ_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_ISPHQ_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISPHQ_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_ISPHQ_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISPHQ_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_ISPHQ_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUD_CPU_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUD_CPU_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_MSCL_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_G2D_MSCL),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_G2D_MSCL),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_MSCL_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_G2D_MSCL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HPM_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HPM_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HPM_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HPM_DIVRATIO, 0, 2, CLK_CON_DIV_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HPM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HPM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS1_PCIE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS1_PCIE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CMU_CMU_CMU_CLKOUT1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK0_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK0_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK1_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK2_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK2_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK3_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK3_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_OTP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_OTP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IVA_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_IVA_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IVA_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_IVA_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IVA_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_IVA_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_IVA_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_IVA_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_IVA_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_IVA_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_IVA_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_IVA_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_IVA_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_IVA_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_IVA_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_IVA_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_IVA_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_IVA_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED1_DIV4_BUSY, 16, 1, CLK_CON_DIV_DIV_PLL_SHARED1_DIV4),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED1_DIV4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_PLL_SHARED1_DIV4),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED1_DIV4_DIVRATIO, 0, 1, CLK_CON_DIV_DIV_PLL_SHARED1_DIV4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_DPGTC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_FSYS0_DPGTC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_DPGTC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS0_DPGTC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_DPGTC_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_FSYS0_DPGTC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MODEM_SHARED0_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MODEM_SHARED0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MODEM_SHARED0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MODEM_SHARED0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MODEM_SHARED0_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_MODEM_SHARED0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MODEM_SHARED1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MODEM_SHARED1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MODEM_SHARED1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MODEM_SHARED1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MODEM_SHARED1_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_MODEM_SHARED1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DCRD_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_DCRD_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DCRD_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_DCRD_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DCRD_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_DCRD_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DCRD_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DCRD_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DCRD_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DCRD_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DCRD_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DCRD_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DCRD_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DCRD_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DCRD_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DCRD_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DCRD_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_DCRD_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMU_CMUREF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMU_CMUREF_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CHUB_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CHUB_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DCF_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_DCF_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DCF_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_DCF_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DCF_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_DCF_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DCF_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DCF_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DCF_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DCF_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DCF_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DCF_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DCF_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DCF_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DCF_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DCF_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DCF_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_DCF_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_APM_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_APM_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMU_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMU_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_VTS_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_VTS_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_VTS_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_VTS_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_VTS_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_VTS_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISPLP_VRA_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_ISPLP_VRA),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISPLP_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_ISPLP_VRA),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISPLP_VRA_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_ISPLP_VRA),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISPLP_VRA_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_ISPLP_VRA),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISPLP_VRA_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_ISPLP_VRA),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISPLP_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_ISPLP_VRA),
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|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISPLP_VRA_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_ISPLP_VRA),
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|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISPLP_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_ISPLP_VRA),
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|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISPLP_VRA_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_ISPLP_VRA),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC_WFD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC_WFD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC_WFD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MFC_WFD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC_WFD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MFC_WFD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MFC_WFD),
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|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC_WFD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MFC_WFD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MFC_WFD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC_WFD_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MFC_WFD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_BUSP_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_BUSP_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_IP_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC0_IP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_IP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC0_IP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_IP_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC0_IP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_IP_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_IP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_IP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_IP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_IP_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_IP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DCPOST_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DCPOST_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DCPOST_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DCPOST_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DCPOST_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_DCPOST_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DCPOST_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DCPOST_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DCPOST_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DCPOST_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DCPOST_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DCPOST_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DCPOST_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_DCPOST_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DCPOST_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_DCPOST_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DCPOST_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_DCPOST_BUS),
|
|
SFR_ACCESS(PLL_CON0_PLL_MMC_DIV_P, 8, 6, PLL_CON0_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON0_PLL_MMC_DIV_M, 16, 10, PLL_CON0_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON0_PLL_MMC_DIV_S, 0, 3, PLL_CON0_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON0_PLL_MMC_ENABLE, 31, 1, PLL_CON0_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON0_PLL_MMC_STABLE, 29, 1, PLL_CON0_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON3_PLL_MMC_DIV_K, 0, 16, PLL_CON3_PLL_MMC),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_MMC_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MMC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDP_DEBUG_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDP_DEBUG),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDP_DEBUG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDP_DEBUG),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDP_DEBUG_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDP_DEBUG),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDP_DEBUG_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDP_DEBUG),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDP_DEBUG_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDP_DEBUG),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDP_DEBUG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDP_DEBUG),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_USBDP_DEBUG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS0_USBDP_DEBUG),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISPLP_GDC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_ISPLP_GDC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISPLP_GDC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_ISPLP_GDC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISPLP_GDC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_ISPLP_GDC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISPLP_GDC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_ISPLP_GDC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISPLP_GDC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_ISPLP_GDC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISPLP_GDC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_ISPLP_GDC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISPLP_GDC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_ISPLP_GDC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISPLP_GDC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_ISPLP_GDC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISPLP_GDC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_ISPLP_GDC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DSPS_AUD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DSPS_AUD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DSPS_AUD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DSPS_AUD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DSPS_AUD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_DSPS_AUD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DSPS_AUD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_DSPS_AUD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DSPS_AUD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_DSPS_AUD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DSPS_AUD_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_DSPS_AUD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSPS_AUD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DSPS_AUD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSPS_AUD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DSPS_AUD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSPS_AUD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DSPS_AUD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED1_DIV3_BUSY, 16, 1, CLK_CON_DIV_DIV_PLL_SHARED1_DIV3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED1_DIV3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_PLL_SHARED1_DIV3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED1_DIV3_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_PLL_SHARED1_DIV3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED0_DIV3_BUSY, 16, 1, CLK_CON_DIV_DIV_PLL_SHARED0_DIV3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED0_DIV3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_PLL_SHARED0_DIV3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED0_DIV3_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_PLL_SHARED0_DIV3),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DPU_BUS_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_DPU_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_DPU_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DPU_BUS_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_DPU_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPU_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_DPU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_DPU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPU_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLKCMU_DPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPU_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPU_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CMU_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_CMU_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CMU_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_CMU_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CMU_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_CMU_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3),
|
|
SFR_ACCESS(DMYQCH_CON_OTP_QCH_ENABLE, 0, 1, DMYQCH_CON_OTP_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_OTP_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_OTP_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_OTP_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_OTP_QCH),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CORE_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CORE_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CORE_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CORE_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CORE_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CORE_BUSP),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMUPPC_CCI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMUPPC_CCI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMUPPC_CCI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMUPPC_CCI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMUPPC_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMUPPC_CCI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CORE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CORE_BUS_USER),
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SFR_ACCESS(CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CORE_CMU_CORE_CLKOUT1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_G3D_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_G3D_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_G3D_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_G3D_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_G3D_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_G3D_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_IO_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_IO_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_IO_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_IO_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_IO_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_IO_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_DP_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_DP_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_DP_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_DP_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_DP_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_DP_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BPS_P_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BPS_P_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BPS_P_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BPS_P_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BPS_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BPS_P_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(QCH_CON_ACE_SLICE_G3D0_QCH_ENABLE, 0, 1, QCH_CON_ACE_SLICE_G3D0_QCH),
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SFR_ACCESS(QCH_CON_ACE_SLICE_G3D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_ACE_SLICE_G3D0_QCH),
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SFR_ACCESS(QCH_CON_ACE_SLICE_G3D0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ACE_SLICE_G3D0_QCH),
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SFR_ACCESS(QCH_CON_ACE_SLICE_G3D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ACE_SLICE_G3D0_QCH),
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|
SFR_ACCESS(QCH_CON_ACE_SLICE_G3D1_QCH_ENABLE, 0, 1, QCH_CON_ACE_SLICE_G3D1_QCH),
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SFR_ACCESS(QCH_CON_ACE_SLICE_G3D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_ACE_SLICE_G3D1_QCH),
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SFR_ACCESS(QCH_CON_ACE_SLICE_G3D1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ACE_SLICE_G3D1_QCH),
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|
SFR_ACCESS(QCH_CON_ACE_SLICE_G3D1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ACE_SLICE_G3D1_QCH),
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|
SFR_ACCESS(QCH_CON_ACE_SLICE_G3D2_QCH_ENABLE, 0, 1, QCH_CON_ACE_SLICE_G3D2_QCH),
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SFR_ACCESS(QCH_CON_ACE_SLICE_G3D2_QCH_CLOCK_REQ, 1, 1, QCH_CON_ACE_SLICE_G3D2_QCH),
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SFR_ACCESS(QCH_CON_ACE_SLICE_G3D2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ACE_SLICE_G3D2_QCH),
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SFR_ACCESS(QCH_CON_ACE_SLICE_G3D2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ACE_SLICE_G3D2_QCH),
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|
SFR_ACCESS(QCH_CON_ACE_SLICE_G3D3_QCH_ENABLE, 0, 1, QCH_CON_ACE_SLICE_G3D3_QCH),
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SFR_ACCESS(QCH_CON_ACE_SLICE_G3D3_QCH_CLOCK_REQ, 1, 1, QCH_CON_ACE_SLICE_G3D3_QCH),
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SFR_ACCESS(QCH_CON_ACE_SLICE_G3D3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ACE_SLICE_G3D3_QCH),
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SFR_ACCESS(QCH_CON_ACE_SLICE_G3D3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ACE_SLICE_G3D3_QCH),
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|
SFR_ACCESS(QCH_CON_BAAW_CP_QCH_ENABLE, 0, 1, QCH_CON_BAAW_CP_QCH),
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SFR_ACCESS(QCH_CON_BAAW_CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_CP_QCH),
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|
SFR_ACCESS(QCH_CON_BAAW_CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_CP_QCH),
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SFR_ACCESS(QCH_CON_BAAW_CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_CP_QCH),
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SFR_ACCESS(QCH_CON_BDU_QCH_ENABLE, 0, 1, QCH_CON_BDU_QCH),
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|
SFR_ACCESS(QCH_CON_BDU_QCH_CLOCK_REQ, 1, 1, QCH_CON_BDU_QCH),
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SFR_ACCESS(QCH_CON_BDU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BDU_QCH),
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|
SFR_ACCESS(QCH_CON_BDU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BDU_QCH),
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|
SFR_ACCESS(QCH_CON_BUSIF_HPMCORE_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPMCORE_QCH),
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|
SFR_ACCESS(QCH_CON_BUSIF_HPMCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPMCORE_QCH),
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|
SFR_ACCESS(QCH_CON_BUSIF_HPMCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPMCORE_QCH),
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|
SFR_ACCESS(QCH_CON_BUSIF_HPMCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_HPMCORE_QCH),
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|
SFR_ACCESS(DMYQCH_CON_CCI_QCH_ENABLE, 0, 1, DMYQCH_CON_CCI_QCH),
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|
SFR_ACCESS(DMYQCH_CON_CCI_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CCI_QCH),
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|
SFR_ACCESS(DMYQCH_CON_CCI_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CCI_QCH),
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|
SFR_ACCESS(QCH_CON_CORE_CMU_CORE_QCH_ENABLE, 0, 1, QCH_CON_CORE_CMU_CORE_QCH),
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|
SFR_ACCESS(QCH_CON_CORE_CMU_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_CORE_CMU_CORE_QCH),
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|
SFR_ACCESS(QCH_CON_CORE_CMU_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CORE_CMU_CORE_QCH),
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|
SFR_ACCESS(QCH_CON_CORE_CMU_CORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CORE_CMU_CORE_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACE_D0_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACE_D0_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACE_D0_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACE_D0_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACE_D0_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACE_D0_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACE_D0_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACE_D0_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACE_D1_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACE_D1_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACE_D1_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACE_D1_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACE_D1_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACE_D1_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACE_D1_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACE_D1_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACE_D2_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACE_D2_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACE_D2_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACE_D2_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACE_D2_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACE_D2_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACE_D2_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACE_D2_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACE_D3_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACE_D3_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACE_D3_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACE_D3_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACE_D3_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACE_D3_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACE_D3_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACE_D3_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACE_D_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACE_D_CPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACE_D_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACE_D_CPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACE_D_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACE_D_CPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACE_D_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACE_D_CPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_CP_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_CP_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_CP_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_CP_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_CLUSTER0_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ATB_T_BDU_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_T_BDU_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ATB_T_BDU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_T_BDU_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ATB_T_BDU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_T_BDU_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ATB_T_BDU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_T_BDU_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_P_APM_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_APM_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_P_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_APM_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_CP_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_CP_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_CPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_CPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_PPCFW_G3D_QCH_ENABLE, 0, 1, QCH_CON_PPCFW_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_PPCFW_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPCFW_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_PPCFW_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPCFW_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_PPCFW_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPCFW_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_DP_QCH_ENABLE, 0, 1, QCH_CON_PPFW_DP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_DP_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPFW_DP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_DP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPFW_DP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_DP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPFW_DP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_G3D_QCH_ENABLE, 0, 1, QCH_CON_PPFW_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPFW_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPFW_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPFW_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_IO_QCH_ENABLE, 0, 1, QCH_CON_PPFW_IO_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_IO_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPFW_IO_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_IO_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPFW_IO_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_IO_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPFW_IO_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_G3D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_G3D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_G3D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_G3D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_G3D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_G3D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_G3D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_G3D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D2_QCH_ENABLE, 0, 1, QCH_CON_PPMU_G3D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D2_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_G3D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_G3D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_G3D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D3_QCH_ENABLE, 0, 1, QCH_CON_PPMU_G3D3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D3_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_G3D3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_G3D3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_G3D3_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CORE_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CORE_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CORE_QCH),
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SFR_ACCESS(QCH_CON_TREX_D_CORE_QCH_ENABLE, 0, 1, QCH_CON_TREX_D_CORE_QCH),
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SFR_ACCESS(QCH_CON_TREX_D_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D_CORE_QCH),
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SFR_ACCESS(QCH_CON_TREX_D_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_D_CORE_QCH),
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SFR_ACCESS(QCH_CON_TREX_D_CORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_D_CORE_QCH),
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SFR_ACCESS(QCH_CON_TREX_P0_CORE_QCH_ENABLE, 0, 1, QCH_CON_TREX_P0_CORE_QCH),
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SFR_ACCESS(QCH_CON_TREX_P0_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_P0_CORE_QCH),
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SFR_ACCESS(QCH_CON_TREX_P0_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_P0_CORE_QCH),
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SFR_ACCESS(QCH_CON_TREX_P0_CORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_P0_CORE_QCH),
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SFR_ACCESS(QCH_CON_TREX_P1_CORE_QCH_ENABLE, 0, 1, QCH_CON_TREX_P1_CORE_QCH),
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SFR_ACCESS(QCH_CON_TREX_P1_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_P1_CORE_QCH),
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SFR_ACCESS(QCH_CON_TREX_P1_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_P1_CORE_QCH),
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SFR_ACCESS(QCH_CON_TREX_P1_CORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_P1_CORE_QCH),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF),
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SFR_ACCESS(PLL_CON0_PLL_CPUCL0_DIV_P, 8, 6, PLL_CON0_PLL_CPUCL0),
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SFR_ACCESS(PLL_CON0_PLL_CPUCL0_DIV_M, 16, 10, PLL_CON0_PLL_CPUCL0),
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SFR_ACCESS(PLL_CON0_PLL_CPUCL0_DIV_S, 0, 3, PLL_CON0_PLL_CPUCL0),
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SFR_ACCESS(PLL_CON0_PLL_CPUCL0_ENABLE, 31, 1, PLL_CON0_PLL_CPUCL0),
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SFR_ACCESS(PLL_CON0_PLL_CPUCL0_STABLE, 29, 1, PLL_CON0_PLL_CPUCL0),
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SFR_ACCESS(PLL_LOCKTIME_PLL_CPUCL0_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_CPUCL0),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C),
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|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT1),
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|
SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT1),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CPUCL0_CPU_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_CPUCL0_CPU),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CPUCL0_CPU_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_CPUCL0_CPU),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CPUCL0_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_CPUCL0_CPU),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_DIVRATIO, 0, 12, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU),
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SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT1),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK),
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|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CPUCL0_DBG_BUS_USER),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_BDU_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_BDU_IPCLKPORT_PCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_BDU_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_BDU_IPCLKPORT_PCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_BDU_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_BDU_IPCLKPORT_PCLKS),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER0_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER0_IPCLKPORT_I_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER0_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER0_IPCLKPORT_I_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER0_IPCLKPORT_I_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER1_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER1_IPCLKPORT_I_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER1_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER1_IPCLKPORT_I_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMPPC_CLUSTER1_IPCLKPORT_I_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER0_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER0_IPCLKPORT_PCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER0_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER0_IPCLKPORT_PCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER0_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER1_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER1_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CLUSTER1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_SSS_IPCLKPORT_HCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_DSPM_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_DSPM_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_DSPM_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_DSPM_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_DSPM_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_DSPM_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CSSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CSSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CSSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_P_CSSYS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_P_CSSYS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_P_CSSYS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_P_CSSYS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_P_CSSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_P_CSSYS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ACE_D_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI_DS_64TO32_G_CSSYS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI_DS_64TO32_G_CSSYS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI_DS_64TO32_G_CSSYS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI_DS_64TO32_G_CSSYS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI_DS_64TO32_G_CSSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI_DS_64TO32_G_CSSYS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CLUSTER0_SCLK_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CLUSTER0_SCLK),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CLUSTER0_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CLUSTER0_SCLK),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CLUSTER0_SCLK_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CLUSTER0_SCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLK_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLK),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLK),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLK_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLK),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLKP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLKP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLKP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLKP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLKP_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLKP),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLKP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLKP),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLKP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLKP),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLKP_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CLUSTER0_ACLKP),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_P_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_P_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_P_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_P_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_P_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_P_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLKP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLKP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLKP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLKP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLKP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLKP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_SCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER0_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ASB_APB_P_DUMPPC_CLUSTER1_IPCLKPORT_PCLKS),
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SFR_ACCESS(DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH_ENABLE, 0, 1, DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH),
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SFR_ACCESS(DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH),
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SFR_ACCESS(DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_HPMCPUCL0_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPMCPUCL0_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_HPMCPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPMCPUCL0_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_HPMCPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPMCPUCL0_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_HPMCPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_HPMCPUCL0_QCH),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_SCLK_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_SCLK),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_SCLK_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_SCLK),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_SCLK_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_SCLK),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_SCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_SCLK),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_ATCLK_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_ATCLK),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_ATCLK_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_ATCLK),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_ATCLK_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_ATCLK),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_ATCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_ATCLK),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PDBGCLK_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_PDBGCLK),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PDBGCLK_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_PDBGCLK),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PDBGCLK_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_PDBGCLK),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PDBGCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_PDBGCLK),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_GIC_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_GIC),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_GIC_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_GIC),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_GIC_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_GIC),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_GIC_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_GIC),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_DBG_PD_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_DBG_PD),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_DBG_PD_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_DBG_PD),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_DBG_PD_EXPIRE_VAL, 16, 4, QCH_CON_CLUSTER0_QCH_DBG_PD),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_DBG_PD_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_DBG_PD),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PCLK_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_PCLK),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_PCLK),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_PCLK),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_PCLK),
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SFR_ACCESS(DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_ENABLE, 0, 1, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK),
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SFR_ACCESS(DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_CLOCK_REQ, 1, 1, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK),
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SFR_ACCESS(DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK),
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SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_ENABLE, 0, 1, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH),
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SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH),
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SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH),
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SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH),
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SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_CPUCL0_CMU_CPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_CPUCL0_CMU_CPUCL0_QCH),
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SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CPUCL0_CMU_CPUCL0_QCH),
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SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL0_CMU_CPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_CSSYS_QCH),
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|
SFR_ACCESS(QCH_CON_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_CSSYS_QCH),
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|
SFR_ACCESS(QCH_CON_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CSSYS_QCH),
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|
SFR_ACCESS(QCH_CON_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSSYS_QCH),
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|
SFR_ACCESS(QCH_CON_DUMPPC_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_DUMPPC_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_DUMPPC_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_DUMPPC_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_DUMPPC_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DUMPPC_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_DUMPPC_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DUMPPC_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_DUMPPC_CLUSTER1_QCH_ENABLE, 0, 1, QCH_CON_DUMPPC_CLUSTER1_QCH),
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|
SFR_ACCESS(QCH_CON_DUMPPC_CLUSTER1_QCH_CLOCK_REQ, 1, 1, QCH_CON_DUMPPC_CLUSTER1_QCH),
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|
SFR_ACCESS(QCH_CON_DUMPPC_CLUSTER1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DUMPPC_CLUSTER1_QCH),
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|
SFR_ACCESS(QCH_CON_DUMPPC_CLUSTER1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DUMPPC_CLUSTER1_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ATB_T0_CLUSTER1_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T0_CLUSTER1_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ATB_T0_CLUSTER1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T0_CLUSTER1_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ATB_T0_CLUSTER1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T0_CLUSTER1_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ATB_T0_CLUSTER1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_T0_CLUSTER1_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T1_CLUSTER1_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T1_CLUSTER1_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T1_CLUSTER1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T1_CLUSTER1_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T1_CLUSTER1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T1_CLUSTER1_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T1_CLUSTER1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_T1_CLUSTER1_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T2_CLUSTER1_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T2_CLUSTER1_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T2_CLUSTER1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T2_CLUSTER1_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T2_CLUSTER1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T2_CLUSTER1_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T2_CLUSTER1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_T2_CLUSTER1_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T3_CLUSTER1_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T3_CLUSTER1_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T3_CLUSTER1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T3_CLUSTER1_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T3_CLUSTER1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T3_CLUSTER1_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T3_CLUSTER1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_T3_CLUSTER1_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T_AUD_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T_AUD_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T_AUD_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T_AUD_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_T_AUD_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T_BDU_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T_BDU_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T_BDU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T_BDU_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T_BDU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T_BDU_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_T_BDU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_T_BDU_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_CPUCL0_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_CPUCL0_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_CPUCL0_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_CPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_CSSYS_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_CSSYS_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_CSSYS_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_CSSYS_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ACE_D_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACE_D_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ACE_D_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACE_D_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ACE_D_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACE_D_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ACE_D_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACE_D_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_T0_CLUSTER0_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_T0_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_T0_CLUSTER0_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_T0_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_T1_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_T1_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_T1_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_T1_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_T2_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_T2_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_T2_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_T2_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_T3_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_T3_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_T3_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_T3_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_G_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_G_CSSYS_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_G_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_G_CSSYS_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_G_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_G_CSSYS_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_G_CSSYS_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_G_ETR_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_G_ETR_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_G_ETR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_G_ETR_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_G_ETR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_G_ETR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_ETR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_G_ETR_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_SECJTAG_QCH_ENABLE, 0, 1, QCH_CON_SECJTAG_QCH),
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|
SFR_ACCESS(QCH_CON_SECJTAG_QCH_CLOCK_REQ, 1, 1, QCH_CON_SECJTAG_QCH),
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|
SFR_ACCESS(QCH_CON_SECJTAG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SECJTAG_QCH),
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|
SFR_ACCESS(QCH_CON_SECJTAG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SECJTAG_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CPUCL0_QCH),
|
|
SFR_ACCESS(PLL_CON0_PLL_CPUCL1_DIV_P, 8, 6, PLL_CON0_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON0_PLL_CPUCL1_DIV_M, 16, 10, PLL_CON0_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON0_PLL_CPUCL1_DIV_S, 0, 3, PLL_CON0_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON0_PLL_CPUCL1_ENABLE, 31, 1, PLL_CON0_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON0_PLL_CPUCL1_STABLE, 29, 1, PLL_CON0_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_CPUCL1_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT0),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_0_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_0_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_0_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_0_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_0_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_0_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CPUCL1_CPU_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_CPUCL1_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CPUCL1_CPU_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_CPUCL1_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CPUCL1_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_CPUCL1_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_DIVRATIO, 0, 12, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU),
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SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CPUCL1_CLKOUT1),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CLUSTER1_IPCLKPORT_PCLKDBG_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CLUSTER1_IPCLKPORT_PCLKDBG),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CLUSTER1_IPCLKPORT_PCLKDBG_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CLUSTER1_IPCLKPORT_PCLKDBG),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CLUSTER1_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CLUSTER1_IPCLKPORT_PCLKDBG),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_1_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_1_IPCLKPORT_HPM_TARGETCLK_C),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_1_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_1_IPCLKPORT_HPM_TARGETCLK_C),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_1_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_1_IPCLKPORT_HPM_TARGETCLK_C),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_2_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_2_IPCLKPORT_HPM_TARGETCLK_C),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_2_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_2_IPCLKPORT_HPM_TARGETCLK_C),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_2_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_2_IPCLKPORT_HPM_TARGETCLK_C),
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SFR_ACCESS(QCH_CON_BUSIF_HPMCPUCL1_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPMCPUCL1_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_HPMCPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPMCPUCL1_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_HPMCPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPMCPUCL1_QCH),
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|
SFR_ACCESS(QCH_CON_BUSIF_HPMCPUCL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_HPMCPUCL1_QCH),
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SFR_ACCESS(DMYQCH_CON_CLUSTER1_QCH_CPU_ENABLE, 0, 1, DMYQCH_CON_CLUSTER1_QCH_CPU),
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SFR_ACCESS(DMYQCH_CON_CLUSTER1_QCH_CPU_CLOCK_REQ, 1, 1, DMYQCH_CON_CLUSTER1_QCH_CPU),
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SFR_ACCESS(DMYQCH_CON_CLUSTER1_QCH_CPU_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CLUSTER1_QCH_CPU),
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SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1_ENABLE, 0, 1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1),
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SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1),
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SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1),
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SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1),
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SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1_ENABLE, 0, 1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1),
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SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1),
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SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1),
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SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1),
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SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1_ENABLE, 0, 1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1),
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SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1),
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SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1),
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SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1),
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SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1_ENABLE, 0, 1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1),
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SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1),
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SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1),
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SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1),
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SFR_ACCESS(DMYQCH_CON_CLUSTER1_QCH_PCLKDBG_ENABLE, 0, 1, DMYQCH_CON_CLUSTER1_QCH_PCLKDBG),
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SFR_ACCESS(DMYQCH_CON_CLUSTER1_QCH_PCLKDBG_CLOCK_REQ, 1, 1, DMYQCH_CON_CLUSTER1_QCH_PCLKDBG),
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SFR_ACCESS(DMYQCH_CON_CLUSTER1_QCH_PCLKDBG_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CLUSTER1_QCH_PCLKDBG),
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SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_ENABLE, 0, 1, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH),
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SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH),
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SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH),
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SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH),
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SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_CPUCL1_CMU_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_CPUCL1_CMU_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CPUCL1_CMU_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL1_CMU_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CPUCL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CPUCL1_QCH),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DCF_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DCF_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DCF_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DCF_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DCF_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DCF_BUSP),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DCF_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_DCF_BUS_USER),
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|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DCF_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DCF_BUS_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_DCF_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_DCF_BUS_USER),
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SFR_ACCESS(CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_DCF_CMU_DCF_CLKOUT1),
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SFR_ACCESS(QCH_CON_BTM_DCF_QCH_ENABLE, 0, 1, QCH_CON_BTM_DCF_QCH),
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|
SFR_ACCESS(QCH_CON_BTM_DCF_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_DCF_QCH),
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|
SFR_ACCESS(QCH_CON_BTM_DCF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_DCF_QCH),
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|
SFR_ACCESS(QCH_CON_BTM_DCF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_DCF_QCH),
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|
SFR_ACCESS(QCH_CON_DCF_CMU_DCF_QCH_ENABLE, 0, 1, QCH_CON_DCF_CMU_DCF_QCH),
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|
SFR_ACCESS(QCH_CON_DCF_CMU_DCF_QCH_CLOCK_REQ, 1, 1, QCH_CON_DCF_CMU_DCF_QCH),
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|
SFR_ACCESS(QCH_CON_DCF_CMU_DCF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DCF_CMU_DCF_QCH),
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|
SFR_ACCESS(QCH_CON_DCF_CMU_DCF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DCF_CMU_DCF_QCH),
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|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_CIP_ENABLE, 0, 1, QCH_CON_IS_DCF_QCH_CIP),
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|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_CIP_CLOCK_REQ, 1, 1, QCH_CON_IS_DCF_QCH_CIP),
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|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_CIP_EXPIRE_VAL, 16, 10, QCH_CON_IS_DCF_QCH_CIP),
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|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_CIP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_DCF_QCH_CIP),
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|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_QE_ENABLE, 0, 1, QCH_CON_IS_DCF_QCH_QE),
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|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_QE_CLOCK_REQ, 1, 1, QCH_CON_IS_DCF_QCH_QE),
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|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_QE_EXPIRE_VAL, 16, 10, QCH_CON_IS_DCF_QCH_QE),
|
|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_QE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_DCF_QCH_QE),
|
|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_SYSREG_ENABLE, 0, 1, QCH_CON_IS_DCF_QCH_SYSREG),
|
|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_SYSREG_CLOCK_REQ, 1, 1, QCH_CON_IS_DCF_QCH_SYSREG),
|
|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_SYSREG_EXPIRE_VAL, 16, 10, QCH_CON_IS_DCF_QCH_SYSREG),
|
|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_SYSREG_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_DCF_QCH_SYSREG),
|
|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_PPMU_ENABLE, 0, 1, QCH_CON_IS_DCF_QCH_PPMU),
|
|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_PPMU_CLOCK_REQ, 1, 1, QCH_CON_IS_DCF_QCH_PPMU),
|
|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_PPMU_EXPIRE_VAL, 16, 10, QCH_CON_IS_DCF_QCH_PPMU),
|
|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_PPMU_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_DCF_QCH_PPMU),
|
|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_SYSMMU_ENABLE, 0, 1, QCH_CON_IS_DCF_QCH_SYSMMU),
|
|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_SYSMMU_CLOCK_REQ, 1, 1, QCH_CON_IS_DCF_QCH_SYSMMU),
|
|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_SYSMMU_EXPIRE_VAL, 16, 10, QCH_CON_IS_DCF_QCH_SYSMMU),
|
|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_SYSMMU_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_DCF_QCH_SYSMMU),
|
|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_C2SYNC_2SLV_ENABLE, 0, 1, QCH_CON_IS_DCF_QCH_C2SYNC_2SLV),
|
|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_C2SYNC_2SLV_CLOCK_REQ, 1, 1, QCH_CON_IS_DCF_QCH_C2SYNC_2SLV),
|
|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_C2SYNC_2SLV_EXPIRE_VAL, 16, 10, QCH_CON_IS_DCF_QCH_C2SYNC_2SLV),
|
|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_C2SYNC_2SLV_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_DCF_QCH_C2SYNC_2SLV),
|
|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_PGEN_LITE_ENABLE, 0, 1, QCH_CON_IS_DCF_QCH_PGEN_LITE),
|
|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_PGEN_LITE_CLOCK_REQ, 1, 1, QCH_CON_IS_DCF_QCH_PGEN_LITE),
|
|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_PGEN_LITE_EXPIRE_VAL, 16, 10, QCH_CON_IS_DCF_QCH_PGEN_LITE),
|
|
SFR_ACCESS(QCH_CON_IS_DCF_QCH_PGEN_LITE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_DCF_QCH_PGEN_LITE),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_DCPOSTDCF_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_DCPOSTDCF_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_DCPOSTDCF_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_DCPOSTDCF_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_DCPOSTDCF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_DCPOSTDCF_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_DCPOSTDCF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_DCPOSTDCF_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_ISPHQDCF_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_ISPHQDCF_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_ISPHQDCF_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_ISPHQDCF_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_ISPHQDCF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_ISPHQDCF_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_ISPHQDCF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_ISPHQDCF_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_DCPOSTDCF_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_DCPOSTDCF_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_DCPOSTDCF_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_DCPOSTDCF_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_DCPOSTDCF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_DCPOSTDCF_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_DCPOSTDCF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_DCPOSTDCF_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_DCF_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_DCF_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_DCF_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_DCF_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_DCF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_DCF_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_DCF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_DCF_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_DCFDCPOST_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_DCFDCPOST_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_DCFDCPOST_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_DCFDCPOST_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_DCFDCPOST_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_DCFDCPOST_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_DCFDCPOST_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_DCFDCPOST_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_DCFISPLP_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_DCFISPLP_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_DCFISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_DCFISPLP_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_DCFISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_DCFISPLP_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_DCFISPLP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_DCFISPLP_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_DCF_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_DCF_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_DCF_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_DCF_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_DCF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_DCF_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_DCF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_DCF_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_DCFDCPOST_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_DCFDCPOST_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_DCFDCPOST_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_DCFDCPOST_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_DCFDCPOST_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_DCFDCPOST_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_DCFDCPOST_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_DCFDCPOST_QCH),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DCPOST_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_DCPOST_BUS_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DCPOST_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DCPOST_BUS_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_DCPOST_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_DCPOST_BUS_USER),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DCPOST_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DCPOST_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DCPOST_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DCPOST_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DCPOST_BUSP_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_DCPOST_BUSP),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_AXI_D_DCPOSTDCF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_AXI_D_DCPOSTDCF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_AXI_D_DCPOSTDCF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_AXI_D_DCPOSTDCF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_AXI_D_DCPOSTDCF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_AXI_D_DCPOSTDCF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCRDDCPOST_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCRDDCPOST_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCRDDCPOST_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCRDDCPOST_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCRDDCPOST_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCRDDCPOST_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_SYSREG_DCPOST_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_SYSREG_DCPOST_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_SYSREG_DCPOST_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_SYSREG_DCPOST_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_SYSREG_DCPOST_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_SYSREG_DCPOST_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_CIP2_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_CIP2_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_CIP2_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_CIP2_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_CIP2_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_CIP2_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_CIP2_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_CIP2_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_CIP2_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_CIP2_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_CIP2_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_CIP2_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_QE_DCPOST_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_AXI_P_DCFDCPOST_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_AXI_P_DCFDCPOST_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_AXI_P_DCFDCPOST_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_AXI_P_DCFDCPOST_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_AXI_P_DCFDCPOST_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_AXI_P_DCFDCPOST_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_RSTNSYNC_CLK_DCPOST_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_DCPOST_CMU_DCPOST_CLKOUT1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DCPOST_UID_DCPOST_CMU_DCPOST_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DCPOST_UID_DCPOST_CMU_DCPOST_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DCPOST_UID_DCPOST_CMU_DCPOST_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DCPOST_UID_DCPOST_CMU_DCPOST_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DCPOST_UID_DCPOST_CMU_DCPOST_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DCPOST_UID_DCPOST_CMU_DCPOST_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_C2SYNC_1SLV_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_C2SYNC_1SLV_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_C2SYNC_1SLV_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_C2SYNC_1SLV_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_C2SYNC_1SLV_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_M_C2SYNC_1SLV_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_C2SYNC_1SLV_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_C2SYNC_1SLV_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_C2SYNC_1SLV_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_C2SYNC_1SLV_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_C2SYNC_1SLV_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AD_APB_DCPOST_S_C2SYNC_1SLV_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCFDCPOST_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCFDCPOST_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCFDCPOST_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCFDCPOST_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCFDCPOST_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHM_ATB_DCFDCPOST_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCRD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCRD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCRD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCRD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCRD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_LHS_ATB_DCPOSTDCRD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_CIP2_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_CIP2_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_CIP2_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_CIP2_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_CIP2_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_CIP2_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_C2SYNC_1SLV_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_C2SYNC_1SLV_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_C2SYNC_1SLV_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_C2SYNC_1SLV_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_C2SYNC_1SLV_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_C2SYNC_1SLV_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AXI2APB_DCPOST_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AXI2APB_DCPOST_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AXI2APB_DCPOST_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AXI2APB_DCPOST_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AXI2APB_DCPOST_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCPOST_UID_IS_DCPOST_IPCLKPORT_AXI2APB_DCPOST_ACLK),
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SFR_ACCESS(QCH_CON_DCPOST_CMU_DCPOST_QCH_ENABLE, 0, 1, QCH_CON_DCPOST_CMU_DCPOST_QCH),
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SFR_ACCESS(QCH_CON_DCPOST_CMU_DCPOST_QCH_CLOCK_REQ, 1, 1, QCH_CON_DCPOST_CMU_DCPOST_QCH),
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SFR_ACCESS(QCH_CON_DCPOST_CMU_DCPOST_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DCPOST_CMU_DCPOST_QCH),
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SFR_ACCESS(QCH_CON_DCPOST_CMU_DCPOST_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DCPOST_CMU_DCPOST_QCH),
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SFR_ACCESS(QCH_CON_IS_DCPOST_QCH_SYSREG_ENABLE, 0, 1, QCH_CON_IS_DCPOST_QCH_SYSREG),
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SFR_ACCESS(QCH_CON_IS_DCPOST_QCH_SYSREG_CLOCK_REQ, 1, 1, QCH_CON_IS_DCPOST_QCH_SYSREG),
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SFR_ACCESS(QCH_CON_IS_DCPOST_QCH_SYSREG_EXPIRE_VAL, 16, 10, QCH_CON_IS_DCPOST_QCH_SYSREG),
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SFR_ACCESS(QCH_CON_IS_DCPOST_QCH_SYSREG_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_DCPOST_QCH_SYSREG),
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SFR_ACCESS(QCH_CON_IS_DCPOST_QCH_CIP2_ENABLE, 0, 1, QCH_CON_IS_DCPOST_QCH_CIP2),
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SFR_ACCESS(QCH_CON_IS_DCPOST_QCH_CIP2_CLOCK_REQ, 1, 1, QCH_CON_IS_DCPOST_QCH_CIP2),
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SFR_ACCESS(QCH_CON_IS_DCPOST_QCH_CIP2_EXPIRE_VAL, 16, 10, QCH_CON_IS_DCPOST_QCH_CIP2),
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SFR_ACCESS(QCH_CON_IS_DCPOST_QCH_CIP2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_DCPOST_QCH_CIP2),
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SFR_ACCESS(QCH_CON_IS_DCPOST_QCH_QE_ENABLE, 0, 1, QCH_CON_IS_DCPOST_QCH_QE),
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SFR_ACCESS(QCH_CON_IS_DCPOST_QCH_QE_CLOCK_REQ, 1, 1, QCH_CON_IS_DCPOST_QCH_QE),
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SFR_ACCESS(QCH_CON_IS_DCPOST_QCH_QE_EXPIRE_VAL, 16, 10, QCH_CON_IS_DCPOST_QCH_QE),
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SFR_ACCESS(QCH_CON_IS_DCPOST_QCH_QE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_DCPOST_QCH_QE),
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SFR_ACCESS(QCH_CON_IS_DCPOST_QCH_C2SYNC_1SLV_CLK_ENABLE, 0, 1, QCH_CON_IS_DCPOST_QCH_C2SYNC_1SLV_CLK),
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SFR_ACCESS(QCH_CON_IS_DCPOST_QCH_C2SYNC_1SLV_CLK_CLOCK_REQ, 1, 1, QCH_CON_IS_DCPOST_QCH_C2SYNC_1SLV_CLK),
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SFR_ACCESS(QCH_CON_IS_DCPOST_QCH_C2SYNC_1SLV_CLK_EXPIRE_VAL, 16, 10, QCH_CON_IS_DCPOST_QCH_C2SYNC_1SLV_CLK),
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SFR_ACCESS(QCH_CON_IS_DCPOST_QCH_C2SYNC_1SLV_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_DCPOST_QCH_C2SYNC_1SLV_CLK),
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SFR_ACCESS(QCH_CON_LHM_ATB_DCFDCPOST_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_DCFDCPOST_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_DCFDCPOST_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_DCFDCPOST_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_DCFDCPOST_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_DCFDCPOST_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_DCFDCPOST_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_DCFDCPOST_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_DCRDDCPOST_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_DCRDDCPOST_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_DCRDDCPOST_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_DCRDDCPOST_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_DCRDDCPOST_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_DCRDDCPOST_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_DCRDDCPOST_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_DCRDDCPOST_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_DCFDCPOST_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_DCFDCPOST_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_DCFDCPOST_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_DCFDCPOST_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_DCFDCPOST_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_DCFDCPOST_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_DCFDCPOST_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_DCFDCPOST_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_DCPOSTDCF_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_DCPOSTDCF_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_DCPOSTDCF_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_DCPOSTDCF_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_DCPOSTDCF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_DCPOSTDCF_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_DCPOSTDCF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_DCPOSTDCF_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_DCPOSTDCRD_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_DCPOSTDCRD_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_DCPOSTDCRD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_DCPOSTDCRD_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_DCPOSTDCRD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_DCPOSTDCRD_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_DCPOSTDCRD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_DCPOSTDCRD_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_DCPOSTDCF_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_DCPOSTDCF_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_DCPOSTDCF_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_DCPOSTDCF_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_DCPOSTDCF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_DCPOSTDCF_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_DCPOSTDCF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_DCPOSTDCF_QCH),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DCRD_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DCRD_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DCRD_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DCRD_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DCRD_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DCRD_BUSP),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DCRD_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_DCRD_BUS_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DCRD_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DCRD_BUS_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_DCRD_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_DCRD_BUS_USER),
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SFR_ACCESS(CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_DCRD_CMU_DCRD_CLKOUT1),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DCRD_BUSD_HALF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DCRD_BUSD_HALF),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DCRD_BUSD_HALF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DCRD_BUSD_HALF),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DCRD_BUSD_HALF_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DCRD_BUSD_HALF),
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SFR_ACCESS(QCH_CON_BTM_DCRD_QCH_ENABLE, 0, 1, QCH_CON_BTM_DCRD_QCH),
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SFR_ACCESS(QCH_CON_BTM_DCRD_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_DCRD_QCH),
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SFR_ACCESS(QCH_CON_BTM_DCRD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_DCRD_QCH),
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SFR_ACCESS(QCH_CON_BTM_DCRD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_DCRD_QCH),
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SFR_ACCESS(QCH_CON_DCRD_CMU_DCRD_QCH_ENABLE, 0, 1, QCH_CON_DCRD_CMU_DCRD_QCH),
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SFR_ACCESS(QCH_CON_DCRD_CMU_DCRD_QCH_CLOCK_REQ, 1, 1, QCH_CON_DCRD_CMU_DCRD_QCH),
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SFR_ACCESS(QCH_CON_DCRD_CMU_DCRD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DCRD_CMU_DCRD_QCH),
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SFR_ACCESS(QCH_CON_DCRD_CMU_DCRD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DCRD_CMU_DCRD_QCH),
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SFR_ACCESS(QCH_CON_IS_DCRD_QCH_DCP_ENABLE, 0, 1, QCH_CON_IS_DCRD_QCH_DCP),
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SFR_ACCESS(QCH_CON_IS_DCRD_QCH_DCP_CLOCK_REQ, 1, 1, QCH_CON_IS_DCRD_QCH_DCP),
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SFR_ACCESS(QCH_CON_IS_DCRD_QCH_DCP_EXPIRE_VAL, 16, 10, QCH_CON_IS_DCRD_QCH_DCP),
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SFR_ACCESS(QCH_CON_IS_DCRD_QCH_DCP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_DCRD_QCH_DCP),
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SFR_ACCESS(QCH_CON_IS_DCRD_QCH_PPMU_ENABLE, 0, 1, QCH_CON_IS_DCRD_QCH_PPMU),
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SFR_ACCESS(QCH_CON_IS_DCRD_QCH_PPMU_CLOCK_REQ, 1, 1, QCH_CON_IS_DCRD_QCH_PPMU),
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SFR_ACCESS(QCH_CON_IS_DCRD_QCH_PPMU_EXPIRE_VAL, 16, 10, QCH_CON_IS_DCRD_QCH_PPMU),
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SFR_ACCESS(QCH_CON_IS_DCRD_QCH_PPMU_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_DCRD_QCH_PPMU),
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SFR_ACCESS(QCH_CON_IS_DCRD_QCH_SYSMMU_ENABLE, 0, 1, QCH_CON_IS_DCRD_QCH_SYSMMU),
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SFR_ACCESS(QCH_CON_IS_DCRD_QCH_SYSMMU_CLOCK_REQ, 1, 1, QCH_CON_IS_DCRD_QCH_SYSMMU),
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SFR_ACCESS(QCH_CON_IS_DCRD_QCH_SYSMMU_EXPIRE_VAL, 16, 10, QCH_CON_IS_DCRD_QCH_SYSMMU),
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SFR_ACCESS(QCH_CON_IS_DCRD_QCH_SYSMMU_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_DCRD_QCH_SYSMMU),
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|
SFR_ACCESS(QCH_CON_IS_DCRD_QCH_SYSREG_ENABLE, 0, 1, QCH_CON_IS_DCRD_QCH_SYSREG),
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SFR_ACCESS(QCH_CON_IS_DCRD_QCH_SYSREG_CLOCK_REQ, 1, 1, QCH_CON_IS_DCRD_QCH_SYSREG),
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SFR_ACCESS(QCH_CON_IS_DCRD_QCH_SYSREG_EXPIRE_VAL, 16, 10, QCH_CON_IS_DCRD_QCH_SYSREG),
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SFR_ACCESS(QCH_CON_IS_DCRD_QCH_SYSREG_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_DCRD_QCH_SYSREG),
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|
SFR_ACCESS(QCH_CON_IS_DCRD_QCH_PGEN_LITE_ENABLE, 0, 1, QCH_CON_IS_DCRD_QCH_PGEN_LITE),
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SFR_ACCESS(QCH_CON_IS_DCRD_QCH_PGEN_LITE_CLOCK_REQ, 1, 1, QCH_CON_IS_DCRD_QCH_PGEN_LITE),
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|
SFR_ACCESS(QCH_CON_IS_DCRD_QCH_PGEN_LITE_EXPIRE_VAL, 16, 10, QCH_CON_IS_DCRD_QCH_PGEN_LITE),
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SFR_ACCESS(QCH_CON_IS_DCRD_QCH_PGEN_LITE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_DCRD_QCH_PGEN_LITE),
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|
SFR_ACCESS(QCH_CON_IS_DCRD_QCH_DCP_C2C_ENABLE, 0, 1, QCH_CON_IS_DCRD_QCH_DCP_C2C),
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|
SFR_ACCESS(QCH_CON_IS_DCRD_QCH_DCP_C2C_CLOCK_REQ, 1, 1, QCH_CON_IS_DCRD_QCH_DCP_C2C),
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|
SFR_ACCESS(QCH_CON_IS_DCRD_QCH_DCP_C2C_EXPIRE_VAL, 16, 10, QCH_CON_IS_DCRD_QCH_DCP_C2C),
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SFR_ACCESS(QCH_CON_IS_DCRD_QCH_DCP_C2C_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_DCRD_QCH_DCP_C2C),
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|
SFR_ACCESS(QCH_CON_IS_DCRD_QCH_DCP_DIV2_ENABLE, 0, 1, QCH_CON_IS_DCRD_QCH_DCP_DIV2),
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|
SFR_ACCESS(QCH_CON_IS_DCRD_QCH_DCP_DIV2_CLOCK_REQ, 1, 1, QCH_CON_IS_DCRD_QCH_DCP_DIV2),
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|
SFR_ACCESS(QCH_CON_IS_DCRD_QCH_DCP_DIV2_EXPIRE_VAL, 16, 10, QCH_CON_IS_DCRD_QCH_DCP_DIV2),
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|
SFR_ACCESS(QCH_CON_IS_DCRD_QCH_DCP_DIV2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_DCRD_QCH_DCP_DIV2),
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|
SFR_ACCESS(QCH_CON_LHM_ATB_DCPOSTDCRD_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_DCPOSTDCRD_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ATB_DCPOSTDCRD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_DCPOSTDCRD_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ATB_DCPOSTDCRD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_DCPOSTDCRD_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ATB_DCPOSTDCRD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_DCPOSTDCRD_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_DCRD_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_DCRD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_DCRD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_DCRD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_DCRD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_DCRD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_DCRD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_DCRD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_DCRDDCPOST_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_DCRDDCPOST_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_DCRDDCPOST_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_DCRDDCPOST_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_DCRDDCPOST_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_DCRDDCPOST_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_DCRDDCPOST_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_DCRDDCPOST_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_DCRDISPLP_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_DCRDISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_DCRDISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_DCRDISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_DCRDISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_DCRDISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_DCRDISPLP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_DCRDISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_DCRD_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_DCRD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_DCRD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_DCRD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_DCRD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_DCRD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_DCRD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_DCRD_QCH),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPU_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_DPU_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPU_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DPU_BUS_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_DPU_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_DPU_BUS_USER),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPU_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DPU_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPU_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DPU_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPU_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DPU_BUSP),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD0_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD0_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD0_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD0_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD0_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD1_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD1_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AXI2APB_DPUP0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_XIU_P_DPU_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_XIU_P_DPU_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_XIU_P_DPU_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_XIU_P_DPU_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_XIU_P_DPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_XIU_P_DPU_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON1_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON1_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPP_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPP_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPP_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPP_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPP_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPP_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD2_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD2_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD2_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD2_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_BTM_DPUD2_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON2_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON2_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON2_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON2_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON2_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON2_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_S_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_S_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_S_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_S_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_S_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_S_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_S_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_S_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_S_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_S_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_S_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_S_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_S_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_S_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_S_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_S_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_S_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_S_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_WRAPPER_FOR_S5I6211_HSI_DCPHY_COMBO_TOP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_WRAPPER_FOR_S5I6211_HSI_DCPHY_COMBO_TOP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_WRAPPER_FOR_S5I6211_HSI_DCPHY_COMBO_TOP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_WRAPPER_FOR_S5I6211_HSI_DCPHY_COMBO_TOP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_WRAPPER_FOR_S5I6211_HSI_DCPHY_COMBO_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_WRAPPER_FOR_S5I6211_HSI_DCPHY_COMBO_TOP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_PGEN_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_PGEN_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_PGEN_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_PGEN_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_PGEN_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_PGEN_IPCLKPORT_PCLKS),
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SFR_ACCESS(QCH_CON_BTM_DPUD0_QCH_ENABLE, 0, 1, QCH_CON_BTM_DPUD0_QCH),
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SFR_ACCESS(QCH_CON_BTM_DPUD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_DPUD0_QCH),
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SFR_ACCESS(QCH_CON_BTM_DPUD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_DPUD0_QCH),
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SFR_ACCESS(QCH_CON_BTM_DPUD0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_DPUD0_QCH),
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SFR_ACCESS(QCH_CON_BTM_DPUD1_QCH_ENABLE, 0, 1, QCH_CON_BTM_DPUD1_QCH),
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SFR_ACCESS(QCH_CON_BTM_DPUD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_DPUD1_QCH),
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SFR_ACCESS(QCH_CON_BTM_DPUD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_DPUD1_QCH),
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SFR_ACCESS(QCH_CON_BTM_DPUD1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_DPUD1_QCH),
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SFR_ACCESS(QCH_CON_BTM_DPUD2_QCH_ENABLE, 0, 1, QCH_CON_BTM_DPUD2_QCH),
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SFR_ACCESS(QCH_CON_BTM_DPUD2_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_DPUD2_QCH),
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SFR_ACCESS(QCH_CON_BTM_DPUD2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_DPUD2_QCH),
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SFR_ACCESS(QCH_CON_BTM_DPUD2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_DPUD2_QCH),
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SFR_ACCESS(QCH_CON_DPU_QCH_DPU_ENABLE, 0, 1, QCH_CON_DPU_QCH_DPU),
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SFR_ACCESS(QCH_CON_DPU_QCH_DPU_CLOCK_REQ, 1, 1, QCH_CON_DPU_QCH_DPU),
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SFR_ACCESS(QCH_CON_DPU_QCH_DPU_EXPIRE_VAL, 16, 10, QCH_CON_DPU_QCH_DPU),
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SFR_ACCESS(QCH_CON_DPU_QCH_DPU_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPU_QCH_DPU),
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SFR_ACCESS(QCH_CON_DPU_QCH_DPU_DMA_ENABLE, 0, 1, QCH_CON_DPU_QCH_DPU_DMA),
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SFR_ACCESS(QCH_CON_DPU_QCH_DPU_DMA_CLOCK_REQ, 1, 1, QCH_CON_DPU_QCH_DPU_DMA),
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SFR_ACCESS(QCH_CON_DPU_QCH_DPU_DMA_EXPIRE_VAL, 16, 10, QCH_CON_DPU_QCH_DPU_DMA),
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SFR_ACCESS(QCH_CON_DPU_QCH_DPU_DMA_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPU_QCH_DPU_DMA),
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SFR_ACCESS(QCH_CON_DPU_QCH_DPU_DPP_ENABLE, 0, 1, QCH_CON_DPU_QCH_DPU_DPP),
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SFR_ACCESS(QCH_CON_DPU_QCH_DPU_DPP_CLOCK_REQ, 1, 1, QCH_CON_DPU_QCH_DPU_DPP),
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SFR_ACCESS(QCH_CON_DPU_QCH_DPU_DPP_EXPIRE_VAL, 16, 10, QCH_CON_DPU_QCH_DPU_DPP),
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SFR_ACCESS(QCH_CON_DPU_QCH_DPU_DPP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPU_QCH_DPU_DPP),
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SFR_ACCESS(QCH_CON_DPU_QCH_DPU_WB_MUX_ENABLE, 0, 1, QCH_CON_DPU_QCH_DPU_WB_MUX),
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SFR_ACCESS(QCH_CON_DPU_QCH_DPU_WB_MUX_CLOCK_REQ, 1, 1, QCH_CON_DPU_QCH_DPU_WB_MUX),
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SFR_ACCESS(QCH_CON_DPU_QCH_DPU_WB_MUX_EXPIRE_VAL, 16, 10, QCH_CON_DPU_QCH_DPU_WB_MUX),
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SFR_ACCESS(QCH_CON_DPU_QCH_DPU_WB_MUX_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPU_QCH_DPU_WB_MUX),
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SFR_ACCESS(QCH_CON_DPU_CMU_DPU_QCH_ENABLE, 0, 1, QCH_CON_DPU_CMU_DPU_QCH),
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SFR_ACCESS(QCH_CON_DPU_CMU_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_DPU_CMU_DPU_QCH),
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SFR_ACCESS(QCH_CON_DPU_CMU_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DPU_CMU_DPU_QCH),
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SFR_ACCESS(QCH_CON_DPU_CMU_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPU_CMU_DPU_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_DPU_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_DPU_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_DPU_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_DPU_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_DPU_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D0_DPU_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D0_DPU_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D0_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D0_DPU_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D0_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D0_DPU_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D0_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D0_DPU_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D1_DPU_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D1_DPU_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D1_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D1_DPU_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D1_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D1_DPU_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D1_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D1_DPU_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D2_DPU_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D2_DPU_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D2_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D2_DPU_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D2_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D2_DPU_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D2_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D2_DPU_QCH),
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SFR_ACCESS(QCH_CON_PPMU_DPUD0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_DPUD0_QCH),
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SFR_ACCESS(QCH_CON_PPMU_DPUD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_DPUD0_QCH),
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SFR_ACCESS(QCH_CON_PPMU_DPUD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_DPUD0_QCH),
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SFR_ACCESS(QCH_CON_PPMU_DPUD0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_DPUD0_QCH),
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SFR_ACCESS(QCH_CON_PPMU_DPUD1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_DPUD1_QCH),
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SFR_ACCESS(QCH_CON_PPMU_DPUD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_DPUD1_QCH),
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SFR_ACCESS(QCH_CON_PPMU_DPUD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_DPUD1_QCH),
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SFR_ACCESS(QCH_CON_PPMU_DPUD1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_DPUD1_QCH),
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SFR_ACCESS(QCH_CON_PPMU_DPUD2_QCH_ENABLE, 0, 1, QCH_CON_PPMU_DPUD2_QCH),
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SFR_ACCESS(QCH_CON_PPMU_DPUD2_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_DPUD2_QCH),
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SFR_ACCESS(QCH_CON_PPMU_DPUD2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_DPUD2_QCH),
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SFR_ACCESS(QCH_CON_PPMU_DPUD2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_DPUD2_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_DPUD0_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_DPUD0_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_DPUD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DPUD0_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_DPUD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_DPUD0_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_DPUD0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DPUD0_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_DPUD1_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_DPUD1_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_DPUD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DPUD1_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_DPUD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_DPUD1_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_DPUD1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DPUD1_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_DPUD2_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_DPUD2_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_DPUD2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DPUD2_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_DPUD2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_DPUD2_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_DPUD2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DPUD2_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_DPU_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DPU_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DPU_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_DPU_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_DPU_QCH),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSPM_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DSPM_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSPM_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DSPM_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSPM_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DSPM_BUSP),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DSPM_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_DSPM_BUS_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DSPM_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DSPM_BUS_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_DSPM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_DSPM_BUS_USER),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSPM_UID_DSPM_CMU_DSPM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSPM_UID_DSPM_CMU_DSPM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSPM_UID_DSPM_CMU_DSPM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSPM_UID_DSPM_CMU_DSPM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSPM_UID_DSPM_CMU_DSPM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSPM_UID_DSPM_CMU_DSPM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSREG_DSPM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSREG_DSPM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSREG_DSPM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSREG_DSPM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSREG_DSPM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSREG_DSPM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AXI2APB_DSPM_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AXI2APB_DSPM_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AXI2APB_DSPM_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AXI2APB_DSPM_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AXI2APB_DSPM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AXI2APB_DSPM_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM0_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM0_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_DSPM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_DSPM_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_DSPM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_DSPM_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_DSPM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_DSPM_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_PCLK),
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|
SFR_ACCESS(CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT0),
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|
SFR_ACCESS(CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT0),
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|
SFR_ACCESS(CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT0),
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|
SFR_ACCESS(CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT1),
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|
SFR_ACCESS(CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_DSPM_CMU_DSPM_CLKOUT1),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D0_DSPM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D0_DSPM_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D0_DSPM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D0_DSPM_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D0_DSPM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D0_DSPM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_IVADSPM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_IVADSPM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_IVADSPM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_IVADSPM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_IVADSPM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_P_IVADSPM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMIVA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMIVA_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMIVA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMIVA_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMIVA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMIVA_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_WRAP2_CONV_DSPM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_WRAP2_CONV_DSPM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_WRAP2_CONV_DSPM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_WRAP2_CONV_DSPM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_WRAP2_CONV_DSPM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_WRAP2_CONV_DSPM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D1_DSPM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D1_DSPM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D1_DSPM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D1_DSPM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D1_DSPM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D1_DSPM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SYSMMU_DSPM1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLKCMU_DSPS_BUS_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_DSPS_BUS),
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SFR_ACCESS(CLK_CON_GAT_CLKCMU_DSPS_BUS_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_DSPS_BUS),
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SFR_ACCESS(CLK_CON_GAT_CLKCMU_DSPS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_DSPS_BUS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_ADM_APB_DSPM_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_ADM_APB_DSPM_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_ADM_APB_DSPM_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_ADM_APB_DSPM_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_ADM_APB_DSPM_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_ADM_APB_DSPM_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D0_DSPSDSPM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D0_DSPSDSPM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D0_DSPSDSPM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D0_DSPSDSPM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D0_DSPSDSPM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D0_DSPSDSPM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D1_DSPSDSPM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D1_DSPSDSPM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D1_DSPSDSPM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D1_DSPSDSPM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D1_DSPSDSPM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHM_AXI_D1_DSPSDSPM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_XIU_P_DSPM_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_XIU_P_DSPM_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_XIU_P_DSPM_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_XIU_P_DSPM_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_XIU_P_DSPM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_XIU_P_DSPM_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_PGEN_LITE_DSPM_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PGEN_LITE_DSPM_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_PGEN_LITE_DSPM_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PGEN_LITE_DSPM_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_PGEN_LITE_DSPM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_PGEN_LITE_DSPM_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D2_DSPM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D2_DSPM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D2_DSPM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D2_DSPM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D2_DSPM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_LHS_ACEL_D2_DSPM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_AD_APB_DSPM4_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_SCORE_MASTER_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SCORE_MASTER_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_SCORE_MASTER_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SCORE_MASTER_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPM_UID_SCORE_MASTER_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPM_UID_SCORE_MASTER_IPCLKPORT_I_CLK),
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SFR_ACCESS(DMYQCH_CON_ADM_APB_DSPM_QCH_ENABLE, 0, 1, DMYQCH_CON_ADM_APB_DSPM_QCH),
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SFR_ACCESS(DMYQCH_CON_ADM_APB_DSPM_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADM_APB_DSPM_QCH),
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SFR_ACCESS(DMYQCH_CON_ADM_APB_DSPM_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADM_APB_DSPM_QCH),
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SFR_ACCESS(QCH_CON_BTM_DSPM0_QCH_ENABLE, 0, 1, QCH_CON_BTM_DSPM0_QCH),
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SFR_ACCESS(QCH_CON_BTM_DSPM0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_DSPM0_QCH),
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SFR_ACCESS(QCH_CON_BTM_DSPM0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_DSPM0_QCH),
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SFR_ACCESS(QCH_CON_BTM_DSPM0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_DSPM0_QCH),
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SFR_ACCESS(QCH_CON_BTM_DSPM1_QCH_ENABLE, 0, 1, QCH_CON_BTM_DSPM1_QCH),
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SFR_ACCESS(QCH_CON_BTM_DSPM1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_DSPM1_QCH),
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SFR_ACCESS(QCH_CON_BTM_DSPM1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_DSPM1_QCH),
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SFR_ACCESS(QCH_CON_BTM_DSPM1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_DSPM1_QCH),
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SFR_ACCESS(QCH_CON_DSPM_CMU_DSPM_QCH_ENABLE, 0, 1, QCH_CON_DSPM_CMU_DSPM_QCH),
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SFR_ACCESS(QCH_CON_DSPM_CMU_DSPM_QCH_CLOCK_REQ, 1, 1, QCH_CON_DSPM_CMU_DSPM_QCH),
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SFR_ACCESS(QCH_CON_DSPM_CMU_DSPM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DSPM_CMU_DSPM_QCH),
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SFR_ACCESS(QCH_CON_DSPM_CMU_DSPM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DSPM_CMU_DSPM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D0_DSPSDSPM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D0_DSPSDSPM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D0_DSPSDSPM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D0_DSPSDSPM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D0_DSPSDSPM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D0_DSPSDSPM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D0_DSPSDSPM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D0_DSPSDSPM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D1_DSPSDSPM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D1_DSPSDSPM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D1_DSPSDSPM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D1_DSPSDSPM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D1_DSPSDSPM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D1_DSPSDSPM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D1_DSPSDSPM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D1_DSPSDSPM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_DSPM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_DSPM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_DSPM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_DSPM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_DSPM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_DSPM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_DSPM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_DSPM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_IVADSPM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_IVADSPM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_IVADSPM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_IVADSPM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_IVADSPM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_IVADSPM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_IVADSPM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_IVADSPM_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D0_DSPM_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D0_DSPM_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D0_DSPM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D0_DSPM_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D0_DSPM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D0_DSPM_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D0_DSPM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D0_DSPM_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D1_DSPM_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D1_DSPM_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D1_DSPM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D1_DSPM_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D1_DSPM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D1_DSPM_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D1_DSPM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D1_DSPM_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D2_DSPM_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D2_DSPM_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ACEL_D2_DSPM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D2_DSPM_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D2_DSPM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D2_DSPM_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D2_DSPM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D2_DSPM_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_DSPMDSPS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_DSPMDSPS_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_DSPMDSPS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_DSPMDSPS_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_DSPMDSPS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_DSPMDSPS_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_DSPMDSPS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_DSPMDSPS_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_DSPMIVA_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_DSPMIVA_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_DSPMIVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_DSPMIVA_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_DSPMIVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_DSPMIVA_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_DSPMIVA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_DSPMIVA_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_DSPM_QCH_ENABLE, 0, 1, QCH_CON_PGEN_LITE_DSPM_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_DSPM_QCH_CLOCK_REQ, 1, 1, QCH_CON_PGEN_LITE_DSPM_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_DSPM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PGEN_LITE_DSPM_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_DSPM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PGEN_LITE_DSPM_QCH),
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SFR_ACCESS(QCH_CON_PPMU_DSPM0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_DSPM0_QCH),
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SFR_ACCESS(QCH_CON_PPMU_DSPM0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_DSPM0_QCH),
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SFR_ACCESS(QCH_CON_PPMU_DSPM0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_DSPM0_QCH),
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SFR_ACCESS(QCH_CON_PPMU_DSPM0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_DSPM0_QCH),
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SFR_ACCESS(QCH_CON_PPMU_DSPM1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_DSPM1_QCH),
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SFR_ACCESS(QCH_CON_PPMU_DSPM1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_DSPM1_QCH),
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SFR_ACCESS(QCH_CON_PPMU_DSPM1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_DSPM1_QCH),
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SFR_ACCESS(QCH_CON_PPMU_DSPM1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_DSPM1_QCH),
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|
SFR_ACCESS(QCH_CON_SCORE_MASTER_QCH_ENABLE, 0, 1, QCH_CON_SCORE_MASTER_QCH),
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SFR_ACCESS(QCH_CON_SCORE_MASTER_QCH_CLOCK_REQ, 1, 1, QCH_CON_SCORE_MASTER_QCH),
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SFR_ACCESS(QCH_CON_SCORE_MASTER_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SCORE_MASTER_QCH),
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SFR_ACCESS(QCH_CON_SCORE_MASTER_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SCORE_MASTER_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_DSPM0_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_DSPM0_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_DSPM0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DSPM0_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_DSPM0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_DSPM0_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_DSPM0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DSPM0_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_DSPM1_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_DSPM1_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_DSPM1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DSPM1_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_DSPM1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_DSPM1_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_DSPM1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DSPM1_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_DSPM_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DSPM_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_DSPM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DSPM_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_DSPM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_DSPM_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_DSPM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_DSPM_QCH),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSPS_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DSPS_BUSP),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSPS_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DSPS_BUSP),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSPS_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DSPS_BUSP),
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|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DSPS_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_DSPS_BUS_USER),
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|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DSPS_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DSPS_BUS_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_DSPS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_DSPS_BUS_USER),
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|
SFR_ACCESS(CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT0),
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|
SFR_ACCESS(CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT0),
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|
SFR_ACCESS(CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT1),
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|
SFR_ACCESS(CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT1),
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|
SFR_ACCESS(CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_DSPS_CMU_DSPS_CLKOUT1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSPS_UID_DSPS_CMU_DSPS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSPS_UID_DSPS_CMU_DSPS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSPS_UID_DSPS_CMU_DSPS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSPS_UID_DSPS_CMU_DSPS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSPS_UID_DSPS_CMU_DSPS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSPS_UID_DSPS_CMU_DSPS_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPS_UID_AXI2APB_DSPS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPS_UID_AXI2APB_DSPS_IPCLKPORT_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPS_UID_AXI2APB_DSPS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPS_UID_AXI2APB_DSPS_IPCLKPORT_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPS_UID_AXI2APB_DSPS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPS_UID_AXI2APB_DSPS_IPCLKPORT_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPS_UID_LHM_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPS_UID_LHM_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPS_UID_LHM_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPS_UID_LHM_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPS_UID_LHM_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPS_UID_LHM_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPS_UID_SYSREG_DSPS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPS_UID_SYSREG_DSPS_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPS_UID_SYSREG_DSPS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPS_UID_SYSREG_DSPS_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPS_UID_SYSREG_DSPS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPS_UID_SYSREG_DSPS_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPS_UID_RSTNSYNC_CLK_DSPS_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSPS_UID_RSTNSYNC_CLK_DSPS_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPS_UID_RSTNSYNC_CLK_DSPS_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSPS_UID_RSTNSYNC_CLK_DSPS_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSPS_UID_RSTNSYNC_CLK_DSPS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSPS_UID_RSTNSYNC_CLK_DSPS_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DSPS_AUD_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_DSPS_AUD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DSPS_AUD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DSPS_AUD_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_DSPS_AUD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_DSPS_AUD_USER),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSPS_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_DSPS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSPS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_DSPS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSPS_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_DSPS_BUS),
|
|
SFR_ACCESS(QCH_CON_DSPS_CMU_DSPS_QCH_ENABLE, 0, 1, QCH_CON_DSPS_CMU_DSPS_QCH),
|
|
SFR_ACCESS(QCH_CON_DSPS_CMU_DSPS_QCH_CLOCK_REQ, 1, 1, QCH_CON_DSPS_CMU_DSPS_QCH),
|
|
SFR_ACCESS(QCH_CON_DSPS_CMU_DSPS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DSPS_CMU_DSPS_QCH),
|
|
SFR_ACCESS(QCH_CON_DSPS_CMU_DSPS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DSPS_CMU_DSPS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_IVADSPS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_IVADSPS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_IVADSPS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_IVADSPS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_IVADSPS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_IVADSPS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_IVADSPS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_IVADSPS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_DSPMDSPS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_DSPMDSPS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_DSPMDSPS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_DSPMDSPS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_DSPMDSPS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_DSPMDSPS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_DSPMDSPS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_DSPMDSPS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_DSPSDSPM_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D0_DSPSDSPM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_DSPSDSPM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D0_DSPSDSPM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_DSPSDSPM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D0_DSPSDSPM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_DSPSDSPM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D0_DSPSDSPM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_DSPSDSPM_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D1_DSPSDSPM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_DSPSDSPM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D1_DSPSDSPM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_DSPSDSPM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D1_DSPSDSPM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_DSPSDSPM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D1_DSPSDSPM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_DSPSIVA_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_DSPSIVA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_DSPSIVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_DSPSIVA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_DSPSIVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_DSPSIVA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_DSPSIVA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_DSPSIVA_QCH),
|
|
SFR_ACCESS(QCH_CON_SCORE_KNIGHT_QCH_ENABLE, 0, 1, QCH_CON_SCORE_KNIGHT_QCH),
|
|
SFR_ACCESS(QCH_CON_SCORE_KNIGHT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SCORE_KNIGHT_QCH),
|
|
SFR_ACCESS(QCH_CON_SCORE_KNIGHT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SCORE_KNIGHT_QCH),
|
|
SFR_ACCESS(QCH_CON_SCORE_KNIGHT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SCORE_KNIGHT_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DSPS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DSPS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DSPS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DSPS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DSPS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_DSPS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DSPS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_DSPS_QCH),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS0_UFS_EMBD_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS0_UFS_EMBD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS0_UFS_EMBD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS0_UFS_EMBD_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS0_UFS_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS0_UFS_EMBD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS0_BUS_USER),
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|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS0_USB30DRD_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS0_USB30DRD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS0_USB30DRD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS0_USB30DRD_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS0_USB30DRD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS0_USB30DRD_USER),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USB30DRD_REF_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USB30DRD_REF_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USB30DRD_REF_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USB30DRD_REF_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USB30DRD_REF_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USB30DRD_REF_CLK),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_FSYS0_CMU_FSYS0_CLKOUT1),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS0_DPGTC_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS0_DPGTC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS0_DPGTC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS0_DPGTC_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS0_DPGTC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS0_DPGTC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS0_USBDP_DEBUG_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS0_USBDP_DEBUG_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS0_USBDP_DEBUG_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS0_USBDP_DEBUG_USER),
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|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS0_USBDP_DEBUG_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS0_USBDP_DEBUG_USER),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_FSYS0_UID_USB30DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK),
|
|
SFR_ACCESS(QCH_CON_BTM_FSYS0_QCH_ENABLE, 0, 1, QCH_CON_BTM_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_FSYS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_FSYS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_FSYS0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_ENABLE, 0, 1, QCH_CON_DP_LINK_QCH),
|
|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_CLOCK_REQ, 1, 1, QCH_CON_DP_LINK_QCH),
|
|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DP_LINK_QCH),
|
|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DP_LINK_QCH),
|
|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_GTC_ENABLE, 0, 1, QCH_CON_DP_LINK_QCH_GTC),
|
|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_GTC_CLOCK_REQ, 1, 1, QCH_CON_DP_LINK_QCH_GTC),
|
|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_GTC_EXPIRE_VAL, 16, 10, QCH_CON_DP_LINK_QCH_GTC),
|
|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_GTC_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DP_LINK_QCH_GTC),
|
|
SFR_ACCESS(QCH_CON_ETR_MIU_QCH_PCLK_ENABLE, 0, 1, QCH_CON_ETR_MIU_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_ETR_MIU_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_ETR_MIU_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_ETR_MIU_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_ETR_MIU_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_ETR_MIU_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ETR_MIU_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_ETR_MIU_QCH_ACLK_ENABLE, 0, 1, QCH_CON_ETR_MIU_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_ETR_MIU_QCH_ACLK_CLOCK_REQ, 1, 1, QCH_CON_ETR_MIU_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_ETR_MIU_QCH_ACLK_EXPIRE_VAL, 16, 10, QCH_CON_ETR_MIU_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_ETR_MIU_QCH_ACLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ETR_MIU_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_FSYS0_CMU_FSYS0_QCH_ENABLE, 0, 1, QCH_CON_FSYS0_CMU_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_FSYS0_CMU_FSYS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_FSYS0_CMU_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_FSYS0_CMU_FSYS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_FSYS0_CMU_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_FSYS0_CMU_FSYS0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_FSYS0_CMU_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_FSYS0_QCH_ENABLE, 0, 1, QCH_CON_GPIO_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_FSYS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_FSYS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_FSYS0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_ETR_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_G_ETR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_ETR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_G_ETR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_ETR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_G_ETR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_ETR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_G_ETR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_FSYS0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_FSYS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_FSYS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_FSYS0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_FSYS0_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_FSYS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_FSYS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_FSYS0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_LITE_FSYS0_QCH_ENABLE, 0, 1, QCH_CON_PGEN_LITE_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_LITE_FSYS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PGEN_LITE_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_LITE_FSYS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PGEN_LITE_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_LITE_FSYS0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PGEN_LITE_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_FSYS0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_FSYS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_FSYS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_FSYS0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_FSYS0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_FSYS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_FSYS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_FSYS0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_FSYS0_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_ENABLE, 0, 1, QCH_CON_UFS_EMBD_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_CLOCK_REQ, 1, 1, QCH_CON_UFS_EMBD_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UFS_EMBD_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UFS_EMBD_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_ENABLE, 0, 1, QCH_CON_UFS_EMBD_QCH_FMP),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_CLOCK_REQ, 1, 1, QCH_CON_UFS_EMBD_QCH_FMP),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_EXPIRE_VAL, 16, 10, QCH_CON_UFS_EMBD_QCH_FMP),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UFS_EMBD_QCH_FMP),
|
|
SFR_ACCESS(QCH_CON_USB30DRD_QCH_USB30DRD_LINK_ENABLE, 0, 1, QCH_CON_USB30DRD_QCH_USB30DRD_LINK),
|
|
SFR_ACCESS(QCH_CON_USB30DRD_QCH_USB30DRD_LINK_CLOCK_REQ, 1, 1, QCH_CON_USB30DRD_QCH_USB30DRD_LINK),
|
|
SFR_ACCESS(QCH_CON_USB30DRD_QCH_USB30DRD_LINK_EXPIRE_VAL, 16, 10, QCH_CON_USB30DRD_QCH_USB30DRD_LINK),
|
|
SFR_ACCESS(QCH_CON_USB30DRD_QCH_USB30DRD_LINK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB30DRD_QCH_USB30DRD_LINK),
|
|
SFR_ACCESS(QCH_CON_USB30DRD_QCH_USBPCS_ENABLE, 0, 1, QCH_CON_USB30DRD_QCH_USBPCS),
|
|
SFR_ACCESS(QCH_CON_USB30DRD_QCH_USBPCS_CLOCK_REQ, 1, 1, QCH_CON_USB30DRD_QCH_USBPCS),
|
|
SFR_ACCESS(QCH_CON_USB30DRD_QCH_USBPCS_EXPIRE_VAL, 16, 10, QCH_CON_USB30DRD_QCH_USBPCS),
|
|
SFR_ACCESS(QCH_CON_USB30DRD_QCH_USBPCS_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB30DRD_QCH_USBPCS),
|
|
SFR_ACCESS(QCH_CON_USB30DRD_QCH_USB30DRD_CTRL_ENABLE, 0, 1, QCH_CON_USB30DRD_QCH_USB30DRD_CTRL),
|
|
SFR_ACCESS(QCH_CON_USB30DRD_QCH_USB30DRD_CTRL_CLOCK_REQ, 1, 1, QCH_CON_USB30DRD_QCH_USB30DRD_CTRL),
|
|
SFR_ACCESS(QCH_CON_USB30DRD_QCH_USB30DRD_CTRL_EXPIRE_VAL, 16, 10, QCH_CON_USB30DRD_QCH_USB30DRD_CTRL),
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SFR_ACCESS(QCH_CON_USB30DRD_QCH_USB30DRD_CTRL_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB30DRD_QCH_USB30DRD_CTRL),
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SFR_ACCESS(QCH_CON_USB30DRD_QCH_USBDPPHY_ENABLE, 0, 1, QCH_CON_USB30DRD_QCH_USBDPPHY),
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SFR_ACCESS(QCH_CON_USB30DRD_QCH_USBDPPHY_CLOCK_REQ, 1, 1, QCH_CON_USB30DRD_QCH_USBDPPHY),
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SFR_ACCESS(QCH_CON_USB30DRD_QCH_USBDPPHY_EXPIRE_VAL, 16, 10, QCH_CON_USB30DRD_QCH_USBDPPHY),
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SFR_ACCESS(QCH_CON_USB30DRD_QCH_USBDPPHY_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB30DRD_QCH_USBDPPHY),
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SFR_ACCESS(DMYQCH_CON_USB30DRD_QCH_SOC_PLL_ENABLE, 0, 1, DMYQCH_CON_USB30DRD_QCH_SOC_PLL),
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SFR_ACCESS(DMYQCH_CON_USB30DRD_QCH_SOC_PLL_CLOCK_REQ, 1, 1, DMYQCH_CON_USB30DRD_QCH_SOC_PLL),
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SFR_ACCESS(DMYQCH_CON_USB30DRD_QCH_SOC_PLL_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_USB30DRD_QCH_SOC_PLL),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS1_BUS_USER),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS1_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS1_MMC_CARD_USER),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL),
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SFR_ACCESS(CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_FSYS1_CMU_FSYS1_CLKOUT1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS1_PCIE_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS1_PCIE_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS1_PCIE_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS1_PCIE_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS1_PCIE_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS1_PCIE_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS1_UFS_CARD_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS1_UFS_CARD_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS1_UFS_CARD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS1_UFS_CARD_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS1_UFS_CARD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS1_UFS_CARD_USER),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSMMU_FSYS1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSMMU_FSYS1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSMMU_FSYS1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSMMU_FSYS1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSMMU_FSYS1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSMMU_FSYS1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PGEN_LITE_FSYS1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PGEN_LITE_FSYS1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PGEN_LITE_FSYS1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PGEN_LITE_FSYS1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PGEN_LITE_FSYS1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PGEN_LITE_FSYS1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_DBI_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_DBI_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_DBI_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_DBI_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_DBI_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_DBI_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_IEEE1500_WRAPPER_FOR_QCHANNEL_WRAPPER_FOR_PCIEG3_PHY_X1_TOP_INST_0_I_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_IEEE1500_WRAPPER_FOR_QCHANNEL_WRAPPER_FOR_PCIEG3_PHY_X1_TOP_INST_0_I_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_IEEE1500_WRAPPER_FOR_QCHANNEL_WRAPPER_FOR_PCIEG3_PHY_X1_TOP_INST_0_I_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_IEEE1500_WRAPPER_FOR_QCHANNEL_WRAPPER_FOR_PCIEG3_PHY_X1_TOP_INST_0_I_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_IEEE1500_WRAPPER_FOR_QCHANNEL_WRAPPER_FOR_PCIEG3_PHY_X1_TOP_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_IEEE1500_WRAPPER_FOR_QCHANNEL_WRAPPER_FOR_PCIEG3_PHY_X1_TOP_INST_0_I_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_LT_PCIE3_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_LT_PCIE3_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_LT_PCIE3_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_LT_PCIE3_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_LT_PCIE3_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_LT_PCIE3_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PHY_REFCLK_IN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PHY_REFCLK_IN),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PHY_REFCLK_IN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PHY_REFCLK_IN),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PHY_REFCLK_IN),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PIPE42_PCIE_PCS_X1_WRAP_INST_0_I_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PIPE42_PCIE_PCS_X1_WRAP_INST_0_I_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PIPE42_PCIE_PCS_X1_WRAP_INST_0_I_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PIPE42_PCIE_PCS_X1_WRAP_INST_0_I_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PIPE42_PCIE_PCS_X1_WRAP_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_PIPE42_PCIE_PCS_X1_WRAP_INST_0_I_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_SLV_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_SLV_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_SLV_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_SLV_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_SLV_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_SLV_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_DBI_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_DBI_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_DBI_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_DBI_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_DBI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_DBI_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_SLV_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_SLV_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_SLV_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_SLV_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_SLV_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_SLV_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_SLV_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_SLV_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_SLV_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_SLV_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_SLV_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN2_SLV_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_DBI_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_DBI_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_DBI_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_DBI_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_DBI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_PCIE_GEN3_DBI_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_MSTR_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_MSTR_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_MSTR_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_MSTR_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_MSTR_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_GEN3_IPCLKPORT_MSTR_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK),
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SFR_ACCESS(QCH_CON_ADM_AHB_SSS_QCH_ENABLE, 0, 1, QCH_CON_ADM_AHB_SSS_QCH),
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SFR_ACCESS(QCH_CON_ADM_AHB_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_ADM_AHB_SSS_QCH),
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SFR_ACCESS(QCH_CON_ADM_AHB_SSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ADM_AHB_SSS_QCH),
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SFR_ACCESS(QCH_CON_ADM_AHB_SSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ADM_AHB_SSS_QCH),
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SFR_ACCESS(QCH_CON_BTM_FSYS1_QCH_ENABLE, 0, 1, QCH_CON_BTM_FSYS1_QCH),
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SFR_ACCESS(QCH_CON_BTM_FSYS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_FSYS1_QCH),
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SFR_ACCESS(QCH_CON_BTM_FSYS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_FSYS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_FSYS1_CMU_FSYS1_QCH_ENABLE, 0, 1, QCH_CON_FSYS1_CMU_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_FSYS1_CMU_FSYS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_FSYS1_CMU_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_FSYS1_CMU_FSYS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_FSYS1_CMU_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_FSYS1_CMU_FSYS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_FSYS1_CMU_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_FSYS1_QCH_ENABLE, 0, 1, QCH_CON_GPIO_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_FSYS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_FSYS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_FSYS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_FSYS1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_FSYS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_FSYS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_FSYS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_FSYS1_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_FSYS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_FSYS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_FSYS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_MMC_CARD_QCH_ENABLE, 0, 1, QCH_CON_MMC_CARD_QCH),
|
|
SFR_ACCESS(QCH_CON_MMC_CARD_QCH_CLOCK_REQ, 1, 1, QCH_CON_MMC_CARD_QCH),
|
|
SFR_ACCESS(QCH_CON_MMC_CARD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MMC_CARD_QCH),
|
|
SFR_ACCESS(QCH_CON_MMC_CARD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MMC_CARD_QCH),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_MSTR_ENABLE, 0, 1, QCH_CON_PCIE_GEN2_QCH_MSTR),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_MSTR_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN2_QCH_MSTR),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_MSTR_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN2_QCH_MSTR),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_MSTR_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN2_QCH_MSTR),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_PCS_ENABLE, 0, 1, QCH_CON_PCIE_GEN2_QCH_PCS),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_PCS_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN2_QCH_PCS),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_PCS_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN2_QCH_PCS),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_PCS_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN2_QCH_PCS),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_PHY_ENABLE, 0, 1, QCH_CON_PCIE_GEN2_QCH_PHY),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_PHY_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN2_QCH_PHY),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_PHY_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN2_QCH_PHY),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_PHY_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN2_QCH_PHY),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_DBI_ENABLE, 0, 1, QCH_CON_PCIE_GEN2_QCH_DBI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_DBI_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN2_QCH_DBI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_DBI_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN2_QCH_DBI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_DBI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN2_QCH_DBI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_APB_ENABLE, 0, 1, QCH_CON_PCIE_GEN2_QCH_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_APB_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN2_QCH_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_APB_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN2_QCH_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_APB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN2_QCH_APB),
|
|
SFR_ACCESS(DMYQCH_CON_PCIE_GEN2_QCH_SOCPLL_ENABLE, 0, 1, DMYQCH_CON_PCIE_GEN2_QCH_SOCPLL),
|
|
SFR_ACCESS(DMYQCH_CON_PCIE_GEN2_QCH_SOCPLL_CLOCK_REQ, 1, 1, DMYQCH_CON_PCIE_GEN2_QCH_SOCPLL),
|
|
SFR_ACCESS(DMYQCH_CON_PCIE_GEN2_QCH_SOCPLL_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_PCIE_GEN2_QCH_SOCPLL),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_MSTR_ENABLE, 0, 1, QCH_CON_PCIE_GEN3_QCH_MSTR),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_MSTR_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN3_QCH_MSTR),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_MSTR_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN3_QCH_MSTR),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_MSTR_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN3_QCH_MSTR),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_PCS_ENABLE, 0, 1, QCH_CON_PCIE_GEN3_QCH_PCS),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_PCS_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN3_QCH_PCS),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_PCS_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN3_QCH_PCS),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_PCS_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN3_QCH_PCS),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_DBI_ENABLE, 0, 1, QCH_CON_PCIE_GEN3_QCH_DBI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_DBI_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN3_QCH_DBI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_DBI_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN3_QCH_DBI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_DBI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN3_QCH_DBI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_APB_ENABLE, 0, 1, QCH_CON_PCIE_GEN3_QCH_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_APB_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN3_QCH_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_APB_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN3_QCH_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_APB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN3_QCH_APB),
|
|
SFR_ACCESS(DMYQCH_CON_PCIE_GEN3_QCH_SOCPLL_ENABLE, 0, 1, DMYQCH_CON_PCIE_GEN3_QCH_SOCPLL),
|
|
SFR_ACCESS(DMYQCH_CON_PCIE_GEN3_QCH_SOCPLL_CLOCK_REQ, 1, 1, DMYQCH_CON_PCIE_GEN3_QCH_SOCPLL),
|
|
SFR_ACCESS(DMYQCH_CON_PCIE_GEN3_QCH_SOCPLL_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_PCIE_GEN3_QCH_SOCPLL),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_PHY_ENABLE, 0, 1, QCH_CON_PCIE_GEN3_QCH_PHY),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_PHY_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN3_QCH_PHY),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_PHY_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN3_QCH_PHY),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_PHY_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN3_QCH_PHY),
|
|
SFR_ACCESS(QCH_CON_PCIE_IA_GEN2_QCH_ENABLE, 0, 1, QCH_CON_PCIE_IA_GEN2_QCH),
|
|
SFR_ACCESS(QCH_CON_PCIE_IA_GEN2_QCH_CLOCK_REQ, 1, 1, QCH_CON_PCIE_IA_GEN2_QCH),
|
|
SFR_ACCESS(QCH_CON_PCIE_IA_GEN2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_IA_GEN2_QCH),
|
|
SFR_ACCESS(QCH_CON_PCIE_IA_GEN2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_IA_GEN2_QCH),
|
|
SFR_ACCESS(QCH_CON_PCIE_IA_GEN3_QCH_ENABLE, 0, 1, QCH_CON_PCIE_IA_GEN3_QCH),
|
|
SFR_ACCESS(QCH_CON_PCIE_IA_GEN3_QCH_CLOCK_REQ, 1, 1, QCH_CON_PCIE_IA_GEN3_QCH),
|
|
SFR_ACCESS(QCH_CON_PCIE_IA_GEN3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_IA_GEN3_QCH),
|
|
SFR_ACCESS(QCH_CON_PCIE_IA_GEN3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_IA_GEN3_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_LITE_FSYS1_QCH_ENABLE, 0, 1, QCH_CON_PGEN_LITE_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_LITE_FSYS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PGEN_LITE_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_LITE_FSYS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PGEN_LITE_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_LITE_FSYS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PGEN_LITE_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_FSYS1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_FSYS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_FSYS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_FSYS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_RTIC_QCH_ENABLE, 0, 1, QCH_CON_RTIC_QCH),
|
|
SFR_ACCESS(QCH_CON_RTIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_RTIC_QCH),
|
|
SFR_ACCESS(QCH_CON_RTIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RTIC_QCH),
|
|
SFR_ACCESS(QCH_CON_RTIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RTIC_QCH),
|
|
SFR_ACCESS(QCH_CON_SSS_QCH_ENABLE, 0, 1, QCH_CON_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_FSYS1_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_FSYS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_FSYS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_FSYS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_FSYS1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_FSYS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_FSYS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_FSYS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_FSYS1_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_CARD_QCH_ENABLE, 0, 1, QCH_CON_UFS_CARD_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_CARD_QCH_CLOCK_REQ, 1, 1, QCH_CON_UFS_CARD_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_CARD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UFS_CARD_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_CARD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UFS_CARD_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_CARD_QCH_FMP_ENABLE, 0, 1, QCH_CON_UFS_CARD_QCH_FMP),
|
|
SFR_ACCESS(QCH_CON_UFS_CARD_QCH_FMP_CLOCK_REQ, 1, 1, QCH_CON_UFS_CARD_QCH_FMP),
|
|
SFR_ACCESS(QCH_CON_UFS_CARD_QCH_FMP_EXPIRE_VAL, 16, 10, QCH_CON_UFS_CARD_QCH_FMP),
|
|
SFR_ACCESS(QCH_CON_UFS_CARD_QCH_FMP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UFS_CARD_QCH_FMP),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_G2D_G2D_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_G2D_G2D_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_G2D_G2D_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_G2D_G2D_USER),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G2D_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_G2D_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G2D_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_G2D_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G2D_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_G2D_BUSP),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_G2D_MSCL_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_G2D_MSCL_USER),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_G2D_CMU_G2D_CLKOUT1),
|
|
SFR_ACCESS(QCH_CON_ASTC_QCH_ENABLE, 0, 1, QCH_CON_ASTC_QCH),
|
|
SFR_ACCESS(QCH_CON_ASTC_QCH_CLOCK_REQ, 1, 1, QCH_CON_ASTC_QCH),
|
|
SFR_ACCESS(QCH_CON_ASTC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ASTC_QCH),
|
|
SFR_ACCESS(QCH_CON_ASTC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ASTC_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_G2DD0_QCH_ENABLE, 0, 1, QCH_CON_BTM_G2DD0_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_G2DD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_G2DD0_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_G2DD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_G2DD0_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_G2DD0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_G2DD0_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_G2DD1_QCH_ENABLE, 0, 1, QCH_CON_BTM_G2DD1_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_G2DD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_G2DD1_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_G2DD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_G2DD1_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_G2DD1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_G2DD1_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_G2DD2_QCH_ENABLE, 0, 1, QCH_CON_BTM_G2DD2_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_G2DD2_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_G2DD2_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_G2DD2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_G2DD2_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_G2DD2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_G2DD2_QCH),
|
|
SFR_ACCESS(QCH_CON_G2D_QCH_ENABLE, 0, 1, QCH_CON_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_G2D_CMU_G2D_QCH_ENABLE, 0, 1, QCH_CON_G2D_CMU_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_G2D_CMU_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_G2D_CMU_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_G2D_CMU_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_G2D_CMU_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_G2D_CMU_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_G2D_CMU_G2D_QCH),
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|
SFR_ACCESS(QCH_CON_JPEG_QCH_ENABLE, 0, 1, QCH_CON_JPEG_QCH),
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|
SFR_ACCESS(QCH_CON_JPEG_QCH_CLOCK_REQ, 1, 1, QCH_CON_JPEG_QCH),
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|
SFR_ACCESS(QCH_CON_JPEG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_JPEG_QCH),
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|
SFR_ACCESS(QCH_CON_JPEG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_JPEG_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_G2D_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_G2D_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_G2D_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_G2D_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ACEL_D0_G2D_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D0_G2D_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ACEL_D0_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D0_G2D_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ACEL_D0_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D0_G2D_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D0_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D0_G2D_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ACEL_D1_G2D_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D1_G2D_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ACEL_D1_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D1_G2D_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ACEL_D1_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D1_G2D_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ACEL_D1_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D1_G2D_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ACEL_D2_G2D_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D2_G2D_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ACEL_D2_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D2_G2D_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ACEL_D2_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D2_G2D_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_ACEL_D2_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D2_G2D_QCH),
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|
SFR_ACCESS(QCH_CON_MSCL_QCH_ENABLE, 0, 1, QCH_CON_MSCL_QCH),
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|
SFR_ACCESS(QCH_CON_MSCL_QCH_CLOCK_REQ, 1, 1, QCH_CON_MSCL_QCH),
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|
SFR_ACCESS(QCH_CON_MSCL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MSCL_QCH),
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|
SFR_ACCESS(QCH_CON_MSCL_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MSCL_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN100_LITE_G2D_QCH_ENABLE, 0, 1, QCH_CON_PGEN100_LITE_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN100_LITE_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_PGEN100_LITE_G2D_QCH),
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|
SFR_ACCESS(QCH_CON_PGEN100_LITE_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PGEN100_LITE_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN100_LITE_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PGEN100_LITE_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G2DD0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_G2DD0_QCH),
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|
SFR_ACCESS(QCH_CON_PPMU_G2DD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_G2DD0_QCH),
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|
SFR_ACCESS(QCH_CON_PPMU_G2DD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_G2DD0_QCH),
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|
SFR_ACCESS(QCH_CON_PPMU_G2DD0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_G2DD0_QCH),
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|
SFR_ACCESS(QCH_CON_PPMU_G2DD1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_G2DD1_QCH),
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|
SFR_ACCESS(QCH_CON_PPMU_G2DD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_G2DD1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G2DD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_G2DD1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G2DD1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_G2DD1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G2DD2_QCH_ENABLE, 0, 1, QCH_CON_PPMU_G2DD2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G2DD2_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_G2DD2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G2DD2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_G2DD2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G2DD2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_G2DD2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ASTC_QCH_ENABLE, 0, 1, QCH_CON_QE_ASTC_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ASTC_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_ASTC_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ASTC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_ASTC_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ASTC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_ASTC_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_JPEG_QCH_ENABLE, 0, 1, QCH_CON_QE_JPEG_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_JPEG_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_JPEG_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_JPEG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_JPEG_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_JPEG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_JPEG_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_MSCL_QCH_ENABLE, 0, 1, QCH_CON_QE_MSCL_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_MSCL_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_MSCL_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_MSCL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_MSCL_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_MSCL_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_MSCL_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G2DD0_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_G2DD0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G2DD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_G2DD0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G2DD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_G2DD0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G2DD0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_G2DD0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G2DD1_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_G2DD1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G2DD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_G2DD1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G2DD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_G2DD1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G2DD1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_G2DD1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G2DD2_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_G2DD2_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G2DD2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_G2DD2_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G2DD2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_G2DD2_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G2DD2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_G2DD2_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_G2D_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_G2D_QCH),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_G3D_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_G3D_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_G3D_BUSP),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D0_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D0_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D0_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D0_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D0_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D0_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_BUSD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_G3D_BUSD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_G3D_BUSD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_BUSD_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_G3D_BUSD),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_G3D_CMU_G3D_CLKOUT1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(PLL_CON0_PLL_G3D_DIV_P, 8, 6, PLL_CON0_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON0_PLL_G3D_DIV_M, 16, 10, PLL_CON0_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON0_PLL_G3D_DIV_S, 0, 3, PLL_CON0_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON0_PLL_G3D_ENABLE, 31, 1, PLL_CON0_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON0_PLL_G3D_STABLE, 29, 1, PLL_CON0_PLL_G3D),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_G3D_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_G3D),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_G3D_CLKOUT1),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_EMBEDDED_G3D_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_EMBEDDED_G3D_USER),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSD_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_G3D_BUSD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_G3D_BUSD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSD_DIVRATIO, 0, 12, CLK_CON_DIV_DIV_CLK_G3D_BUSD),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(QCH_CON_BUSIF_HPMG3D_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPMG3D_QCH),
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|
SFR_ACCESS(QCH_CON_BUSIF_HPMG3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPMG3D_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_HPMG3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPMG3D_QCH),
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|
SFR_ACCESS(QCH_CON_BUSIF_HPMG3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_HPMG3D_QCH),
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|
SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_ENABLE, 0, 1, QCH_CON_G3D_CMU_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_G3D_CMU_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_G3D_CMU_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_G3D_CMU_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_GPU_QCH_ENABLE, 0, 1, QCH_CON_GPU_QCH),
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|
SFR_ACCESS(QCH_CON_GPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPU_QCH),
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|
SFR_ACCESS(QCH_CON_GPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPU_QCH),
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|
SFR_ACCESS(QCH_CON_GPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPU_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_G3DSFR_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_G3DSFR_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_G3DSFR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_G3DSFR_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_G3DSFR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_G3DSFR_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_G3DSFR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_G3DSFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACE_D0_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACE_D0_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACE_D0_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACE_D0_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACE_D0_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACE_D0_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACE_D0_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACE_D0_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACE_D1_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACE_D1_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACE_D1_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACE_D1_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACE_D1_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACE_D1_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACE_D1_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACE_D1_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACE_D2_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACE_D2_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACE_D2_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACE_D2_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACE_D2_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACE_D2_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACE_D2_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACE_D2_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACE_D3_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACE_D3_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACE_D3_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACE_D3_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACE_D3_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACE_D3_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACE_D3_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACE_D3_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G3DSFR_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_G3DSFR_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_G3DSFR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_G3DSFR_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_G3DSFR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_G3DSFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G3DSFR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_G3DSFR_QCH),
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|
SFR_ACCESS(QCH_CON_PGEN_LITE_G3D_QCH_ENABLE, 0, 1, QCH_CON_PGEN_LITE_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_PGEN_LITE_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_PGEN_LITE_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_PGEN_LITE_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PGEN_LITE_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_LITE_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PGEN_LITE_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_G3D_QCH),
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|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ISPHQ_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_ISPHQ_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ISPHQ_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_ISPHQ_BUS_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_ISPHQ_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_ISPHQ_BUS_USER),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP),
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|
SFR_ACCESS(CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT0),
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|
SFR_ACCESS(CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT0),
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|
SFR_ACCESS(CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT1),
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|
SFR_ACCESS(CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_ISPHQ_CMU_ISPHQ_CLKOUT1),
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|
SFR_ACCESS(QCH_CON_BTM_ISPHQ_QCH_ENABLE, 0, 1, QCH_CON_BTM_ISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_ISPHQ_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_ISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_ISPHQ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_ISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_ISPHQ_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_ISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_ISPHQ_CMU_ISPHQ_QCH_ENABLE, 0, 1, QCH_CON_ISPHQ_CMU_ISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_ISPHQ_CMU_ISPHQ_QCH_CLOCK_REQ, 1, 1, QCH_CON_ISPHQ_CMU_ISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_ISPHQ_CMU_ISPHQ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ISPHQ_CMU_ISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_ISPHQ_CMU_ISPHQ_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ISPHQ_CMU_ISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_ISPHQ_ENABLE, 0, 1, QCH_CON_IS_ISPHQ_QCH_ISPHQ),
|
|
SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_ISPHQ_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPHQ_QCH_ISPHQ),
|
|
SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_ISPHQ_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPHQ_QCH_ISPHQ),
|
|
SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_ISPHQ_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPHQ_QCH_ISPHQ),
|
|
SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_SYSMMU_ISPHQ_ENABLE, 0, 1, QCH_CON_IS_ISPHQ_QCH_SYSMMU_ISPHQ),
|
|
SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_SYSMMU_ISPHQ_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPHQ_QCH_SYSMMU_ISPHQ),
|
|
SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_SYSMMU_ISPHQ_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPHQ_QCH_SYSMMU_ISPHQ),
|
|
SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_SYSMMU_ISPHQ_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPHQ_QCH_SYSMMU_ISPHQ),
|
|
SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_PPMU_ISPHQ_ENABLE, 0, 1, QCH_CON_IS_ISPHQ_QCH_PPMU_ISPHQ),
|
|
SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_PPMU_ISPHQ_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPHQ_QCH_PPMU_ISPHQ),
|
|
SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_PPMU_ISPHQ_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPHQ_QCH_PPMU_ISPHQ),
|
|
SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_PPMU_ISPHQ_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPHQ_QCH_PPMU_ISPHQ),
|
|
SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_PGEN_LITE_ISPHQ_ENABLE, 0, 1, QCH_CON_IS_ISPHQ_QCH_PGEN_LITE_ISPHQ),
|
|
SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_PGEN_LITE_ISPHQ_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPHQ_QCH_PGEN_LITE_ISPHQ),
|
|
SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_PGEN_LITE_ISPHQ_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPHQ_QCH_PGEN_LITE_ISPHQ),
|
|
SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_PGEN_LITE_ISPHQ_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPHQ_QCH_PGEN_LITE_ISPHQ),
|
|
SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_ISPHQ_C2COM_ENABLE, 0, 1, QCH_CON_IS_ISPHQ_QCH_ISPHQ_C2COM),
|
|
SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_ISPHQ_C2COM_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPHQ_QCH_ISPHQ_C2COM),
|
|
SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_ISPHQ_C2COM_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPHQ_QCH_ISPHQ_C2COM),
|
|
SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_ISPHQ_C2COM_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPHQ_QCH_ISPHQ_C2COM),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_ISPLPISPHQ_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_ISPLPISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_ISPLPISPHQ_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_ISPLPISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_ISPLPISPHQ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_ISPLPISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_ISPLPISPHQ_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_ISPLPISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_ISPPREISPHQ_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_ISPPREISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_ISPPREISPHQ_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_ISPPREISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_ISPPREISPHQ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_ISPPREISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_ISPPREISPHQ_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_ISPPREISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_ISPHQ_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_ISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_ISPHQ_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_ISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_ISPHQ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_ISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_ISPHQ_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_ISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_ISPHQDCF_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_ISPHQDCF_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_ISPHQDCF_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_ISPHQDCF_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_ISPHQDCF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_ISPHQDCF_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_ISPHQDCF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_ISPHQDCF_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_ISPHQISPLP_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_ISPHQISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_ISPHQISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_ISPHQISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_ISPHQISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_ISPHQISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_ISPHQISPLP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_ISPHQISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_ISPHQ_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_ISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_ISPHQ_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_ISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_ISPHQ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_ISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_ISPHQ_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_ISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ISPHQ_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_ISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ISPHQ_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_ISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ISPHQ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_ISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ISPHQ_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_ISPHQ_QCH),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ISPLP_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_ISPLP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ISPLP_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_ISPLP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_ISPLP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_ISPLP_BUS_USER),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ISPLP_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ISPLP_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ISPLP_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ISPLP_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ISPLP_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_ISPLP_BUSP),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_ISPLP_CMU_ISPLP_CLKOUT1),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ISPLP_VRA_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_ISPLP_VRA_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ISPLP_VRA_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_ISPLP_VRA_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_ISPLP_VRA_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_ISPLP_VRA_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ISPLP_GDC_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_ISPLP_GDC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ISPLP_GDC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_ISPLP_GDC_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_ISPLP_GDC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_ISPLP_GDC_USER),
|
|
SFR_ACCESS(QCH_CON_BTM_ISPLP0_QCH_ENABLE, 0, 1, QCH_CON_BTM_ISPLP0_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_ISPLP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_ISPLP0_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_ISPLP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_ISPLP0_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_ISPLP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_ISPLP0_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_ISPLP1_QCH_ENABLE, 0, 1, QCH_CON_BTM_ISPLP1_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_ISPLP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_ISPLP1_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_ISPLP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_ISPLP1_QCH),
|
|
SFR_ACCESS(QCH_CON_BTM_ISPLP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_ISPLP1_QCH),
|
|
SFR_ACCESS(QCH_CON_ISPLP_CMU_ISPLP_QCH_ENABLE, 0, 1, QCH_CON_ISPLP_CMU_ISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_ISPLP_CMU_ISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_ISPLP_CMU_ISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_ISPLP_CMU_ISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ISPLP_CMU_ISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_ISPLP_CMU_ISPLP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ISPLP_CMU_ISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_MC_SCALER_ENABLE, 0, 1, QCH_CON_IS_ISPLP_QCH_MC_SCALER),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_MC_SCALER_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPLP_QCH_MC_SCALER),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_MC_SCALER_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPLP_QCH_MC_SCALER),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_MC_SCALER_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPLP_QCH_MC_SCALER),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_ISPLP_ENABLE, 0, 1, QCH_CON_IS_ISPLP_QCH_ISPLP),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_ISPLP_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPLP_QCH_ISPLP),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_ISPLP_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPLP_QCH_ISPLP),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_ISPLP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPLP_QCH_ISPLP),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_QE_ISPLP_ENABLE, 0, 1, QCH_CON_IS_ISPLP_QCH_QE_ISPLP),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_QE_ISPLP_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPLP_QCH_QE_ISPLP),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_QE_ISPLP_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPLP_QCH_QE_ISPLP),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_QE_ISPLP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPLP_QCH_QE_ISPLP),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP0_ENABLE, 0, 1, QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP0),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP0_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP0),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP0_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP0),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP0),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP0_ENABLE, 0, 1, QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP0),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP0_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP0),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP0_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP0),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP0),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP1_ENABLE, 0, 1, QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP1),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP1_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP1),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP1_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP1),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP1),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP1_ENABLE, 0, 1, QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP1),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP1_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP1),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP1_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP1),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP1),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_QE_VRA_ENABLE, 0, 1, QCH_CON_IS_ISPLP_QCH_QE_VRA),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_QE_VRA_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPLP_QCH_QE_VRA),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_QE_VRA_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPLP_QCH_QE_VRA),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_QE_VRA_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPLP_QCH_QE_VRA),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_VRA_ENABLE, 0, 1, QCH_CON_IS_ISPLP_QCH_VRA),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_VRA_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPLP_QCH_VRA),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_VRA_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPLP_QCH_VRA),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_VRA_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPLP_QCH_VRA),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_GDC_ENABLE, 0, 1, QCH_CON_IS_ISPLP_QCH_GDC),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_GDC_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPLP_QCH_GDC),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_GDC_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPLP_QCH_GDC),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_GDC_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPLP_QCH_GDC),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_PGEN_LITE_ENABLE, 0, 1, QCH_CON_IS_ISPLP_QCH_PGEN_LITE),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_PGEN_LITE_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPLP_QCH_PGEN_LITE),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_PGEN_LITE_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPLP_QCH_PGEN_LITE),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_PGEN_LITE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPLP_QCH_PGEN_LITE),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_QE_GDC_ENABLE, 0, 1, QCH_CON_IS_ISPLP_QCH_QE_GDC),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_QE_GDC_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPLP_QCH_QE_GDC),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_QE_GDC_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPLP_QCH_QE_GDC),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_QE_GDC_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPLP_QCH_QE_GDC),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_ISPLP_C2_ENABLE, 0, 1, QCH_CON_IS_ISPLP_QCH_ISPLP_C2),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_ISPLP_C2_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPLP_QCH_ISPLP_C2),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_ISPLP_C2_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPLP_QCH_ISPLP_C2),
|
|
SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_ISPLP_C2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPLP_QCH_ISPLP_C2),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_DCFISPLP_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_DCFISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_DCFISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_DCFISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_DCFISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_DCFISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_DCFISPLP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_DCFISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_DCRDISPLP_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_DCRDISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_DCRDISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_DCRDISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_DCRDISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_DCRDISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_DCRDISPLP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_DCRDISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_ISPHQISPLP_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_ISPHQISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_ISPHQISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_ISPHQISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_ISPHQISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_ISPHQISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_ISPHQISPLP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_ISPHQISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_ISPPREISPLP_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_ISPPREISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_ISPPREISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_ISPPREISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_ISPPREISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_ISPPREISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_ISPPREISPLP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_ISPPREISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_ISPLP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_ISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_ISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_ISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_ISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_ISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_ISPLP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_ISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_ISPLPISPHQ_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_ISPLPISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_ISPLPISPHQ_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_ISPLPISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_ISPLPISPHQ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_ISPLPISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_ISPLPISPHQ_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_ISPLPISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_ISPLP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D0_ISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_ISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D0_ISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_ISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D0_ISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_ISPLP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D0_ISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_ISPLP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D1_ISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_ISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D1_ISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_ISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D1_ISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_ISPLP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D1_ISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ISPLP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_ISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_ISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_ISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ISPLP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_ISPLP_QCH),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ISPPRE_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_ISPPRE_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ISPPRE_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_ISPPRE_BUS_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_ISPPRE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_ISPPRE_BUS_USER),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ISPPRE_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ISPPRE_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ISPPRE_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ISPPRE_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ISPPRE_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_ISPPRE_BUSP),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_ISPPRE_CMU_ISPPRE_CLKOUT1),
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SFR_ACCESS(QCH_CON_BTM_ISPPRE_QCH_ENABLE, 0, 1, QCH_CON_BTM_ISPPRE_QCH),
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SFR_ACCESS(QCH_CON_BTM_ISPPRE_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_ISPPRE_QCH),
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SFR_ACCESS(QCH_CON_BTM_ISPPRE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_ISPPRE_QCH),
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SFR_ACCESS(QCH_CON_BTM_ISPPRE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_ISPPRE_QCH),
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SFR_ACCESS(QCH_CON_ISPPRE_CMU_ISPPRE_QCH_ENABLE, 0, 1, QCH_CON_ISPPRE_CMU_ISPPRE_QCH),
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SFR_ACCESS(QCH_CON_ISPPRE_CMU_ISPPRE_QCH_CLOCK_REQ, 1, 1, QCH_CON_ISPPRE_CMU_ISPPRE_QCH),
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SFR_ACCESS(QCH_CON_ISPPRE_CMU_ISPPRE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ISPPRE_CMU_ISPPRE_QCH),
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SFR_ACCESS(QCH_CON_ISPPRE_CMU_ISPPRE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ISPPRE_CMU_ISPPRE_QCH),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_CSIS0_ENABLE, 0, 1, QCH_CON_IS_ISPPRE_QCH_CSIS0),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_CSIS0_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPPRE_QCH_CSIS0),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_CSIS0_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPPRE_QCH_CSIS0),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_CSIS0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPPRE_QCH_CSIS0),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_CSIS1_ENABLE, 0, 1, QCH_CON_IS_ISPPRE_QCH_CSIS1),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_CSIS1_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPPRE_QCH_CSIS1),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_CSIS1_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPPRE_QCH_CSIS1),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_CSIS1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPPRE_QCH_CSIS1),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_CSIS2_ENABLE, 0, 1, QCH_CON_IS_ISPPRE_QCH_CSIS2),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_CSIS2_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPPRE_QCH_CSIS2),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_CSIS2_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPPRE_QCH_CSIS2),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_CSIS2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPPRE_QCH_CSIS2),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_CSIS3_ENABLE, 0, 1, QCH_CON_IS_ISPPRE_QCH_CSIS3),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_CSIS3_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPPRE_QCH_CSIS3),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_CSIS3_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPPRE_QCH_CSIS3),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_CSIS3_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPPRE_QCH_CSIS3),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_PPMU_ISPPRE_ENABLE, 0, 1, QCH_CON_IS_ISPPRE_QCH_PPMU_ISPPRE),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_PPMU_ISPPRE_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPPRE_QCH_PPMU_ISPPRE),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_PPMU_ISPPRE_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPPRE_QCH_PPMU_ISPPRE),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_PPMU_ISPPRE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPPRE_QCH_PPMU_ISPPRE),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_PDP_DMA_ENABLE, 0, 1, QCH_CON_IS_ISPPRE_QCH_PDP_DMA),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_PDP_DMA_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPPRE_QCH_PDP_DMA),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_PDP_DMA_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPPRE_QCH_PDP_DMA),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_PDP_DMA_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPPRE_QCH_PDP_DMA),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_SYSMMU_ISPPRE_ENABLE, 0, 1, QCH_CON_IS_ISPPRE_QCH_SYSMMU_ISPPRE),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_SYSMMU_ISPPRE_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPPRE_QCH_SYSMMU_ISPPRE),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_SYSMMU_ISPPRE_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPPRE_QCH_SYSMMU_ISPPRE),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_SYSMMU_ISPPRE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPPRE_QCH_SYSMMU_ISPPRE),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_QE_PDP_ENABLE, 0, 1, QCH_CON_IS_ISPPRE_QCH_QE_PDP),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_QE_PDP_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPPRE_QCH_QE_PDP),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_QE_PDP_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPPRE_QCH_QE_PDP),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_QE_PDP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPPRE_QCH_QE_PDP),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_QE_3AA_ENABLE, 0, 1, QCH_CON_IS_ISPPRE_QCH_QE_3AA),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_QE_3AA_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPPRE_QCH_QE_3AA),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_QE_3AA_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPPRE_QCH_QE_3AA),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_QE_3AA_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPPRE_QCH_QE_3AA),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_QE_3AAM_ENABLE, 0, 1, QCH_CON_IS_ISPPRE_QCH_QE_3AAM),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_QE_3AAM_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPPRE_QCH_QE_3AAM),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_QE_3AAM_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPPRE_QCH_QE_3AAM),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_QE_3AAM_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPPRE_QCH_QE_3AAM),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_3AA_ENABLE, 0, 1, QCH_CON_IS_ISPPRE_QCH_3AA),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_3AA_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPPRE_QCH_3AA),
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|
SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_3AA_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPPRE_QCH_3AA),
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|
SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_3AA_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPPRE_QCH_3AA),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_3AAM_ENABLE, 0, 1, QCH_CON_IS_ISPPRE_QCH_3AAM),
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|
SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_3AAM_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPPRE_QCH_3AAM),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_3AAM_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPPRE_QCH_3AAM),
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|
SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_3AAM_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPPRE_QCH_3AAM),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_PDP_CORE0_ENABLE, 0, 1, QCH_CON_IS_ISPPRE_QCH_PDP_CORE0),
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|
SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_PDP_CORE0_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPPRE_QCH_PDP_CORE0),
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|
SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_PDP_CORE0_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPPRE_QCH_PDP_CORE0),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_PDP_CORE0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPPRE_QCH_PDP_CORE0),
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SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_PDP_CORE1_ENABLE, 0, 1, QCH_CON_IS_ISPPRE_QCH_PDP_CORE1),
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|
SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_PDP_CORE1_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPPRE_QCH_PDP_CORE1),
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|
SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_PDP_CORE1_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPPRE_QCH_PDP_CORE1),
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|
SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_PDP_CORE1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPPRE_QCH_PDP_CORE1),
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|
SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_PGEN_LITE_ENABLE, 0, 1, QCH_CON_IS_ISPPRE_QCH_PGEN_LITE),
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|
SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_PGEN_LITE_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPPRE_QCH_PGEN_LITE),
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|
SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_PGEN_LITE_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPPRE_QCH_PGEN_LITE),
|
|
SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_PGEN_LITE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPPRE_QCH_PGEN_LITE),
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|
SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_QE_PDP_STAT_ENABLE, 0, 1, QCH_CON_IS_ISPPRE_QCH_QE_PDP_STAT),
|
|
SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_QE_PDP_STAT_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPPRE_QCH_QE_PDP_STAT),
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|
SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_QE_PDP_STAT_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPPRE_QCH_QE_PDP_STAT),
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|
SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_QE_PDP_STAT_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPPRE_QCH_QE_PDP_STAT),
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|
SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_PGEN_LITE1_ENABLE, 0, 1, QCH_CON_IS_ISPPRE_QCH_PGEN_LITE1),
|
|
SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_PGEN_LITE1_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPPRE_QCH_PGEN_LITE1),
|
|
SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_PGEN_LITE1_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPPRE_QCH_PGEN_LITE1),
|
|
SFR_ACCESS(QCH_CON_IS_ISPPRE_QCH_PGEN_LITE1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS_ISPPRE_QCH_PGEN_LITE1),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_ISPPRE_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_ISPPRE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_ISPPRE_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_ISPPRE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_ISPPRE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_ISPPRE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_ISPPRE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_ISPPRE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_ISPPREISPHQ_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_ISPPREISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_ISPPREISPHQ_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_ISPPREISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_ISPPREISPHQ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_ISPPREISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_ISPPREISPHQ_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_ISPPREISPHQ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_ISPPREISPLP_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_ISPPREISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_ISPPREISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_ISPPREISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_ISPPREISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_ISPPREISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_ISPPREISPLP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_ISPPREISPLP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_ISPPRE_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_ISPPRE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_ISPPRE_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_ISPPRE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_ISPPRE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_ISPPRE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_ISPPRE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_ISPPRE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ISPPRE_QCH_SYSREG_ENABLE, 0, 1, QCH_CON_SYSREG_ISPPRE_QCH_SYSREG),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ISPPRE_QCH_SYSREG_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_ISPPRE_QCH_SYSREG),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ISPPRE_QCH_SYSREG_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_ISPPRE_QCH_SYSREG),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ISPPRE_QCH_SYSREG_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_ISPPRE_QCH_SYSREG),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_IVA_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_IVA_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_IVA_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_IVA_BUS_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_IVA_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_IVA_BUS_USER),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_IVA_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_IVA_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_IVA_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_IVA_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_IVA_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_IVA_BUSP),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_IVA_CMU_IVA_CLKOUT1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_PPMU_IVA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_PPMU_IVA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_PPMU_IVA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_PPMU_IVA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_PPMU_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_PPMU_IVA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA0_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA0_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA0_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA0_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA0_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_IVA_DEBUG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_IVA_DEBUG),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_IVA_DEBUG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_IVA_DEBUG),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_IVA_DEBUG_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_IVA_DEBUG),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_ADM_DAP_IVA_IPCLKPORT_DAPCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_ADM_DAP_IVA_IPCLKPORT_DAPCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_ADM_DAP_IVA_IPCLKPORT_DAPCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_ADM_DAP_IVA_IPCLKPORT_DAPCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_ADM_DAP_IVA_IPCLKPORT_DAPCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_ADM_DAP_IVA_IPCLKPORT_DAPCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_DEBUG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_DEBUG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_DEBUG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_DEBUG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_DEBUG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_DEBUG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA1_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA1_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA2_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA2_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA2_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA2_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA2_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA2_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_PGEN_LITE_IVA_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_PGEN_LITE_IVA_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_PGEN_LITE_IVA_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_PGEN_LITE_IVA_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_PGEN_LITE_IVA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_PGEN_LITE_IVA_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_TREX_RB_IVA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_TREX_RB_IVA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_TREX_RB_IVA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_TREX_RB_IVA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_TREX_RB_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_TREX_RB_IVA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_DAP_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_DAP_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_DAP_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_DAP_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_DAP_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_DAP_CLK),
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SFR_ACCESS(DMYQCH_CON_ADM_DAP_IVA_QCH_ENABLE, 0, 1, DMYQCH_CON_ADM_DAP_IVA_QCH),
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SFR_ACCESS(DMYQCH_CON_ADM_DAP_IVA_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADM_DAP_IVA_QCH),
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SFR_ACCESS(DMYQCH_CON_ADM_DAP_IVA_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADM_DAP_IVA_QCH),
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SFR_ACCESS(QCH_CON_BTM_IVA_QCH_ENABLE, 0, 1, QCH_CON_BTM_IVA_QCH),
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SFR_ACCESS(QCH_CON_BTM_IVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_IVA_QCH),
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SFR_ACCESS(QCH_CON_BTM_IVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_IVA_QCH),
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SFR_ACCESS(QCH_CON_BTM_IVA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_IVA_QCH),
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SFR_ACCESS(QCH_CON_IVA_QCH_IVA_ENABLE, 0, 1, QCH_CON_IVA_QCH_IVA),
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SFR_ACCESS(QCH_CON_IVA_QCH_IVA_CLOCK_REQ, 1, 1, QCH_CON_IVA_QCH_IVA),
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SFR_ACCESS(QCH_CON_IVA_QCH_IVA_EXPIRE_VAL, 16, 10, QCH_CON_IVA_QCH_IVA),
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SFR_ACCESS(QCH_CON_IVA_QCH_IVA_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IVA_QCH_IVA),
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SFR_ACCESS(QCH_CON_IVA_QCH_IVA_DEBUG_ENABLE, 0, 1, QCH_CON_IVA_QCH_IVA_DEBUG),
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SFR_ACCESS(QCH_CON_IVA_QCH_IVA_DEBUG_CLOCK_REQ, 1, 1, QCH_CON_IVA_QCH_IVA_DEBUG),
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SFR_ACCESS(QCH_CON_IVA_QCH_IVA_DEBUG_EXPIRE_VAL, 16, 10, QCH_CON_IVA_QCH_IVA_DEBUG),
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SFR_ACCESS(QCH_CON_IVA_QCH_IVA_DEBUG_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IVA_QCH_IVA_DEBUG),
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SFR_ACCESS(QCH_CON_IVA_CMU_IVA_QCH_ENABLE, 0, 1, QCH_CON_IVA_CMU_IVA_QCH),
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SFR_ACCESS(QCH_CON_IVA_CMU_IVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_IVA_CMU_IVA_QCH),
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SFR_ACCESS(QCH_CON_IVA_CMU_IVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_IVA_CMU_IVA_QCH),
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SFR_ACCESS(QCH_CON_IVA_CMU_IVA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IVA_CMU_IVA_QCH),
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SFR_ACCESS(QCH_CON_IVA_INTMEM_QCH_ENABLE, 0, 1, QCH_CON_IVA_INTMEM_QCH),
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SFR_ACCESS(QCH_CON_IVA_INTMEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_IVA_INTMEM_QCH),
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SFR_ACCESS(QCH_CON_IVA_INTMEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_IVA_INTMEM_QCH),
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SFR_ACCESS(QCH_CON_IVA_INTMEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IVA_INTMEM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_DSPSIVA_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_DSPSIVA_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_DSPSIVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_DSPSIVA_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_DSPSIVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_DSPSIVA_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_DSPSIVA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_DSPSIVA_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_IVASC_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_IVASC_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_IVASC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_IVASC_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_IVASC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_IVASC_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_IVASC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_IVASC_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_DSPMIVA_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_DSPMIVA_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_DSPMIVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_DSPMIVA_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_DSPMIVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_DSPMIVA_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_DSPMIVA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_DSPMIVA_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_IVA_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_IVA_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_IVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_IVA_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_IVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_IVA_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_IVA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_IVA_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_IVA_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D_IVA_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_IVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D_IVA_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_IVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D_IVA_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_IVA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D_IVA_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_IVADSPS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_IVADSPS_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_IVADSPS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_IVADSPS_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_IVADSPS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_IVADSPS_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_IVADSPS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_IVADSPS_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_IVADSPM_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_IVADSPM_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_IVADSPM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_IVADSPM_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_IVADSPM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_IVADSPM_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_IVADSPM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_IVADSPM_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_IVA_QCH_ENABLE, 0, 1, QCH_CON_PGEN_LITE_IVA_QCH),
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|
SFR_ACCESS(QCH_CON_PGEN_LITE_IVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_PGEN_LITE_IVA_QCH),
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|
SFR_ACCESS(QCH_CON_PGEN_LITE_IVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PGEN_LITE_IVA_QCH),
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|
SFR_ACCESS(QCH_CON_PGEN_LITE_IVA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PGEN_LITE_IVA_QCH),
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|
SFR_ACCESS(QCH_CON_PPMU_IVA_QCH_ENABLE, 0, 1, QCH_CON_PPMU_IVA_QCH),
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|
SFR_ACCESS(QCH_CON_PPMU_IVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_IVA_QCH),
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|
SFR_ACCESS(QCH_CON_PPMU_IVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_IVA_QCH),
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|
SFR_ACCESS(QCH_CON_PPMU_IVA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_IVA_QCH),
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|
SFR_ACCESS(QCH_CON_SYSMMU_IVA_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_IVA_QCH),
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|
SFR_ACCESS(QCH_CON_SYSMMU_IVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_IVA_QCH),
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|
SFR_ACCESS(QCH_CON_SYSMMU_IVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_IVA_QCH),
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|
SFR_ACCESS(QCH_CON_SYSMMU_IVA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_IVA_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_IVA_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_IVA_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_IVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_IVA_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_IVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_IVA_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_IVA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_IVA_QCH),
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|
SFR_ACCESS(QCH_CON_TREX_RB_IVA_QCH_ENABLE, 0, 1, QCH_CON_TREX_RB_IVA_QCH),
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|
SFR_ACCESS(QCH_CON_TREX_RB_IVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_RB_IVA_QCH),
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|
SFR_ACCESS(QCH_CON_TREX_RB_IVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_RB_IVA_QCH),
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|
SFR_ACCESS(QCH_CON_TREX_RB_IVA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_RB_IVA_QCH),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_MFC_BUS_USER),
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|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MFC_BUS_USER),
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|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_MFC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_MFC_BUS_USER),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MFC_BUSP),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MFC_BUSP),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MFC_BUSP),
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|
SFR_ACCESS(CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT0),
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|
SFR_ACCESS(CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT1),
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|
SFR_ACCESS(CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT1),
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|
SFR_ACCESS(CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_MFC_CMU_MFC_CLKOUT1),
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|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC_WFD_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_MFC_WFD_USER),
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|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC_WFD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MFC_WFD_USER),
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|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_MFC_WFD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_MFC_WFD_USER),
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|
SFR_ACCESS(QCH_CON_BTM_MFCD0_QCH_ENABLE, 0, 1, QCH_CON_BTM_MFCD0_QCH),
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|
SFR_ACCESS(QCH_CON_BTM_MFCD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_MFCD0_QCH),
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|
SFR_ACCESS(QCH_CON_BTM_MFCD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_MFCD0_QCH),
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|
SFR_ACCESS(QCH_CON_BTM_MFCD0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_MFCD0_QCH),
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SFR_ACCESS(QCH_CON_BTM_MFCD1_QCH_ENABLE, 0, 1, QCH_CON_BTM_MFCD1_QCH),
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|
SFR_ACCESS(QCH_CON_BTM_MFCD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_MFCD1_QCH),
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|
SFR_ACCESS(QCH_CON_BTM_MFCD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_MFCD1_QCH),
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|
SFR_ACCESS(QCH_CON_BTM_MFCD1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_MFCD1_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MFC_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_MFC_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_MFC_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MFC_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D0_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D0_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D0_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D0_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D0_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D0_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D0_MFC_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MFC_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D1_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D1_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D1_MFC_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D1_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D1_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D1_MFC_QCH),
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|
SFR_ACCESS(QCH_CON_LH_ATB_QCH_MI_ENABLE, 0, 1, QCH_CON_LH_ATB_QCH_MI),
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SFR_ACCESS(QCH_CON_LH_ATB_QCH_MI_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_QCH_MI),
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|
SFR_ACCESS(QCH_CON_LH_ATB_QCH_MI_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_QCH_MI),
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|
SFR_ACCESS(QCH_CON_LH_ATB_QCH_MI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_QCH_MI),
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|
SFR_ACCESS(QCH_CON_LH_ATB_QCH_SI_ENABLE, 0, 1, QCH_CON_LH_ATB_QCH_SI),
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|
SFR_ACCESS(QCH_CON_LH_ATB_QCH_SI_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_QCH_SI),
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|
SFR_ACCESS(QCH_CON_LH_ATB_QCH_SI_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_QCH_SI),
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|
SFR_ACCESS(QCH_CON_LH_ATB_QCH_SI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_QCH_SI),
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|
SFR_ACCESS(QCH_CON_MFC_QCH_ENABLE, 0, 1, QCH_CON_MFC_QCH),
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|
SFR_ACCESS(QCH_CON_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC_CMU_MFC_QCH_ENABLE, 0, 1, QCH_CON_MFC_CMU_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC_CMU_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_MFC_CMU_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC_CMU_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MFC_CMU_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC_CMU_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MFC_CMU_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN100_LITE_MFC_QCH_ENABLE, 0, 1, QCH_CON_PGEN100_LITE_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN100_LITE_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PGEN100_LITE_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN100_LITE_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PGEN100_LITE_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN100_LITE_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PGEN100_LITE_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFCD0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_MFCD0_QCH),
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|
SFR_ACCESS(QCH_CON_PPMU_MFCD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_MFCD0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFCD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_MFCD0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFCD0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_MFCD0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFCD1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_MFCD1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFCD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_MFCD1_QCH),
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|
SFR_ACCESS(QCH_CON_PPMU_MFCD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_MFCD1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFCD1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_MFCD1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFCD2_QCH_ENABLE, 0, 1, QCH_CON_PPMU_MFCD2_QCH),
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|
SFR_ACCESS(QCH_CON_PPMU_MFCD2_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_MFCD2_QCH),
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|
SFR_ACCESS(QCH_CON_PPMU_MFCD2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_MFCD2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFCD2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_MFCD2_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MI_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MI_SW_RESET_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MI_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MI_SW_RESET_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MI_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MI_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MI_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MI_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_SI_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_SI_SW_RESET_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_SI_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_SI_SW_RESET_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_SI_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_SI_SW_RESET_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_SI_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_SI_SW_RESET_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFCD0_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_MFCD0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFCD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MFCD0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFCD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_MFCD0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFCD0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MFCD0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFCD1_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_MFCD1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFCD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MFCD1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFCD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_MFCD1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFCD1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MFCD1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MFC_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_WFD_QCH_ENABLE, 0, 1, QCH_CON_WFD_QCH),
|
|
SFR_ACCESS(QCH_CON_WFD_QCH_CLOCK_REQ, 1, 1, QCH_CON_WFD_QCH),
|
|
SFR_ACCESS(QCH_CON_WFD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WFD_QCH),
|
|
SFR_ACCESS(QCH_CON_WFD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WFD_QCH),
|
|
SFR_ACCESS(PLL_CON0_PLL_MIF_DIV_P, 8, 6, PLL_CON0_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON0_PLL_MIF_DIV_M, 16, 10, PLL_CON0_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON0_PLL_MIF_DIV_S, 0, 3, PLL_CON0_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON0_PLL_MIF_ENABLE, 31, 1, PLL_CON0_PLL_MIF),
|
|
SFR_ACCESS(PLL_CON0_PLL_MIF_STABLE, 29, 1, PLL_CON0_PLL_MIF),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_MIF_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MIF),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X_BUSY, 16, 1, CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X_SELECT, 0, 1, CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_MIF_BUSD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_MIF_BUSD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_PRE_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MIF_PRE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_PRE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MIF_PRE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_PRE_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MIF_PRE),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT0),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_MIF_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_MIF_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_MIF_CMUREF),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_MIF_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_MIF_BUSP_USER),
|
|
SFR_ACCESS(QCH_CON_APBBR_DDRPHY_QCH_ENABLE, 0, 1, QCH_CON_APBBR_DDRPHY_QCH),
|
|
SFR_ACCESS(QCH_CON_APBBR_DDRPHY_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBBR_DDRPHY_QCH),
|
|
SFR_ACCESS(QCH_CON_APBBR_DDRPHY_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBBR_DDRPHY_QCH),
|
|
SFR_ACCESS(QCH_CON_APBBR_DDRPHY_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBBR_DDRPHY_QCH),
|
|
SFR_ACCESS(QCH_CON_APBBR_DMC_QCH_ENABLE, 0, 1, QCH_CON_APBBR_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBBR_DMC_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBBR_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBBR_DMC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBBR_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBBR_DMC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBBR_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBBR_DMCTZ_QCH_ENABLE, 0, 1, QCH_CON_APBBR_DMCTZ_QCH),
|
|
SFR_ACCESS(QCH_CON_APBBR_DMCTZ_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBBR_DMCTZ_QCH),
|
|
SFR_ACCESS(QCH_CON_APBBR_DMCTZ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBBR_DMCTZ_QCH),
|
|
SFR_ACCESS(QCH_CON_APBBR_DMCTZ_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBBR_DMCTZ_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPMMIF_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPMMIF_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPMMIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPMMIF_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPMMIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPMMIF_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPMMIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_HPMMIF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_MIF_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_MIF_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_MIF_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_MIF_CMUREF_QCH),
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SFR_ACCESS(DMYQCH_CON_CMU_MIF_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_MIF_CMUREF_QCH),
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SFR_ACCESS(QCH_CON_DMC_QCH_ENABLE, 0, 1, QCH_CON_DMC_QCH),
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SFR_ACCESS(QCH_CON_DMC_QCH_CLOCK_REQ, 1, 1, QCH_CON_DMC_QCH),
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SFR_ACCESS(QCH_CON_DMC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DMC_QCH),
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SFR_ACCESS(QCH_CON_DMC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMC_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_MIF_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_MIF_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_MIF_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_MIF_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_MIF_QCH),
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SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_ENABLE, 0, 1, QCH_CON_MIF_CMU_MIF_QCH),
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SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_MIF_CMU_MIF_QCH),
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SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MIF_CMU_MIF_QCH),
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SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIF_CMU_MIF_QCH),
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SFR_ACCESS(QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG_QCH_ENABLE, 0, 1, QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG_QCH),
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SFR_ACCESS(QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG_QCH_CLOCK_REQ, 1, 1, QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG_QCH),
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SFR_ACCESS(QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG_QCH),
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SFR_ACCESS(QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG_QCH),
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SFR_ACCESS(QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS_QCH_ENABLE, 0, 1, QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS_QCH),
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SFR_ACCESS(QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS_QCH_CLOCK_REQ, 1, 1, QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS_QCH),
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SFR_ACCESS(QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS_QCH),
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SFR_ACCESS(QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MIF_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MIF_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_MIF_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_MIF_QCH),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC0_BUS_USER),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_XIU_P_PERIC0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_XIU_P_PERIC0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_XIU_P_PERIC0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_XIU_P_PERIC0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_XIU_P_PERIC0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_XIU_P_PERIC0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC0_IP_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC0_IP_USER),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI00_USI_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI00_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI00_USI_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI00_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI00_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI00_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI01_USI_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI01_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI01_USI_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI01_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI01_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI01_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI02_USI_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI02_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI02_USI_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI02_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI02_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI02_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI03_USI_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI03_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI03_USI_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI03_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI03_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI03_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI04_USI_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI04_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI04_USI_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI04_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI04_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI04_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI05_USI_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI05_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI05_USI_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI05_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI05_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI05_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI_I2C_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI_I2C),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI_I2C_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI_I2C),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI_I2C),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_UART_DBG_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERIC0_UART_DBG),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_UART_DBG_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERIC0_UART_DBG),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_UART_DBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERIC0_UART_DBG),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI12_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI12_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI12_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI12_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI12_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC0_USI12_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI12_USI_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI12_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI12_USI_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI12_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI12_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI12_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI13_USI_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI13_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI13_USI_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI13_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI13_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI13_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI14_USI_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI14_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI14_USI_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI14_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC0_USI14_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERIC0_USI14_USI),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(QCH_CON_GPIO_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_GPIO_PERIC0_QCH),
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SFR_ACCESS(QCH_CON_GPIO_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_PERIC0_QCH),
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SFR_ACCESS(QCH_CON_GPIO_PERIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_PERIC0_QCH),
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SFR_ACCESS(QCH_CON_GPIO_PERIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_PERIC0_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_PERIC0_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_PERIC0_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_PERIC0_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_PERIC0_QCH),
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SFR_ACCESS(QCH_CON_PERIC0_CMU_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_PERIC0_CMU_PERIC0_QCH),
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SFR_ACCESS(QCH_CON_PERIC0_CMU_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_CMU_PERIC0_QCH),
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SFR_ACCESS(QCH_CON_PERIC0_CMU_PERIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PERIC0_CMU_PERIC0_QCH),
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SFR_ACCESS(QCH_CON_PERIC0_CMU_PERIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC0_CMU_PERIC0_QCH),
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SFR_ACCESS(QCH_CON_PWM_QCH_ENABLE, 0, 1, QCH_CON_PWM_QCH),
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SFR_ACCESS(QCH_CON_PWM_QCH_CLOCK_REQ, 1, 1, QCH_CON_PWM_QCH),
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SFR_ACCESS(QCH_CON_PWM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PWM_QCH),
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SFR_ACCESS(QCH_CON_PWM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PWM_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_PERIC0_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_PERIC0_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_PERIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_PERIC0_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_PERIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_PERIC0_QCH),
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SFR_ACCESS(QCH_CON_UART_DBG_QCH_ENABLE, 0, 1, QCH_CON_UART_DBG_QCH),
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SFR_ACCESS(QCH_CON_UART_DBG_QCH_CLOCK_REQ, 1, 1, QCH_CON_UART_DBG_QCH),
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SFR_ACCESS(QCH_CON_UART_DBG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UART_DBG_QCH),
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SFR_ACCESS(QCH_CON_UART_DBG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UART_DBG_QCH),
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|
SFR_ACCESS(QCH_CON_USI00_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI00_I2C_QCH),
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SFR_ACCESS(QCH_CON_USI00_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI00_I2C_QCH),
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SFR_ACCESS(QCH_CON_USI00_I2C_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI00_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI00_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI00_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI00_USI_QCH_ENABLE, 0, 1, QCH_CON_USI00_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI00_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI00_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI00_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI00_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI00_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI00_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI01_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI01_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI01_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI01_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI01_I2C_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI01_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI01_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI01_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI01_USI_QCH_ENABLE, 0, 1, QCH_CON_USI01_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI01_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI01_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI01_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI01_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI01_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI01_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI02_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI02_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI02_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI02_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI02_I2C_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI02_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI02_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI02_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI02_USI_QCH_ENABLE, 0, 1, QCH_CON_USI02_USI_QCH),
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SFR_ACCESS(QCH_CON_USI02_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI02_USI_QCH),
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SFR_ACCESS(QCH_CON_USI02_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI02_USI_QCH),
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SFR_ACCESS(QCH_CON_USI02_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI02_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI03_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI03_I2C_QCH),
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SFR_ACCESS(QCH_CON_USI03_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI03_I2C_QCH),
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SFR_ACCESS(QCH_CON_USI03_I2C_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI03_I2C_QCH),
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SFR_ACCESS(QCH_CON_USI03_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI03_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI03_USI_QCH_ENABLE, 0, 1, QCH_CON_USI03_USI_QCH),
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SFR_ACCESS(QCH_CON_USI03_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI03_USI_QCH),
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SFR_ACCESS(QCH_CON_USI03_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI03_USI_QCH),
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SFR_ACCESS(QCH_CON_USI03_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI03_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI04_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI04_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI04_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI04_I2C_QCH),
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SFR_ACCESS(QCH_CON_USI04_I2C_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI04_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI04_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI04_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI04_USI_QCH_ENABLE, 0, 1, QCH_CON_USI04_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI04_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI04_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI04_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI04_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI04_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI04_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI05_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI05_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI05_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI05_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI05_I2C_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI05_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI05_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI05_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI05_USI_QCH_ENABLE, 0, 1, QCH_CON_USI05_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI05_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI05_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI05_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI05_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI05_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI05_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI12_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI12_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI12_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI12_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI12_I2C_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI12_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI12_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI12_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI12_USI_QCH_ENABLE, 0, 1, QCH_CON_USI12_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI12_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI12_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI12_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI12_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI12_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI12_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI13_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI13_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI13_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI13_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI13_I2C_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI13_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI13_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI13_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI13_USI_QCH_ENABLE, 0, 1, QCH_CON_USI13_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI13_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI13_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI13_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI13_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI13_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI13_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI14_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI14_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI14_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI14_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI14_I2C_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI14_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI14_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI14_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI14_USI_QCH_ENABLE, 0, 1, QCH_CON_USI14_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI14_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI14_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI14_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI14_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI14_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI14_USI_QCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC1_BUS_USER),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPI_CAM0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPI_CAM0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPI_CAM0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPI_CAM0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPI_CAM0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPI_CAM0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM3_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM3_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM3_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM3_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM3_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM0),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM0),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM0_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM0),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM1_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM1),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM1),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM1_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM1),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM2_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM2),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM2),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM2_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM2),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM3_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM3),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM3),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM3_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_CAM3),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_SPI_CAM0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_SPI_CAM0),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_SPI_CAM0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_SPI_CAM0),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_SPI_CAM0_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_SPI_CAM0),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC1_IP_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC1_IP_USER),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_UART_BT_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERIC1_UART_BT),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_UART_BT_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERIC1_UART_BT),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERIC1_UART_BT),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_USI_I2C_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERIC1_USI_I2C),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_USI_I2C_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERIC1_USI_I2C),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_USI_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERIC1_USI_I2C),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_USI06_USI_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERIC1_USI06_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_USI06_USI_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERIC1_USI06_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_USI06_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERIC1_USI06_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_USI07_USI_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERIC1_USI07_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_USI07_USI_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERIC1_USI07_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_USI07_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERIC1_USI07_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_USI08_USI_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERIC1_USI08_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_USI08_USI_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERIC1_USI08_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_USI08_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERIC1_USI08_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM1),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM1),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM1),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM2_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM2),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM2_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM2),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM2),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM3_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM3),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM3_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM3),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERIC1_I2C_CAM3),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_SPI_CAM0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERIC1_SPI_CAM0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_SPI_CAM0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERIC1_SPI_CAM0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_SPI_CAM0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERIC1_SPI_CAM0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_USI09_USI_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERIC1_USI09_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_USI09_USI_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERIC1_USI09_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_USI09_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERIC1_USI09_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_USI10_USI_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERIC1_USI10_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_USI10_USI_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERIC1_USI10_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_USI10_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERIC1_USI10_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_USI11_USI_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERIC1_USI11_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_USI11_USI_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERIC1_USI11_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERIC1_USI11_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERIC1_USI11_USI),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(QCH_CON_GPIO_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_GPIO_PERIC1_QCH),
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SFR_ACCESS(QCH_CON_GPIO_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_PERIC1_QCH),
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SFR_ACCESS(QCH_CON_GPIO_PERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_PERIC1_QCH),
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SFR_ACCESS(QCH_CON_GPIO_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_PERIC1_QCH),
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SFR_ACCESS(QCH_CON_I2C_CAM0_QCH_ENABLE, 0, 1, QCH_CON_I2C_CAM0_QCH),
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SFR_ACCESS(QCH_CON_I2C_CAM0_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CAM0_QCH),
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SFR_ACCESS(QCH_CON_I2C_CAM0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CAM0_QCH),
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SFR_ACCESS(QCH_CON_I2C_CAM0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CAM0_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CAM1_QCH_ENABLE, 0, 1, QCH_CON_I2C_CAM1_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CAM1_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CAM1_QCH),
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SFR_ACCESS(QCH_CON_I2C_CAM1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CAM1_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CAM1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CAM1_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CAM2_QCH_ENABLE, 0, 1, QCH_CON_I2C_CAM2_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CAM2_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CAM2_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CAM2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CAM2_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CAM2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CAM2_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CAM3_QCH_ENABLE, 0, 1, QCH_CON_I2C_CAM3_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CAM3_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CAM3_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CAM3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CAM3_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CAM3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CAM3_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_PERIC1_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_PERIC1_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC1_CMU_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_PERIC1_CMU_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC1_CMU_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PERIC1_CMU_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC1_CMU_PERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PERIC1_CMU_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC1_CMU_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC1_CMU_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_CAM0_QCH_ENABLE, 0, 1, QCH_CON_SPI_CAM0_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_CAM0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPI_CAM0_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_CAM0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPI_CAM0_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_CAM0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPI_CAM0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_UART_BT_QCH_ENABLE, 0, 1, QCH_CON_UART_BT_QCH),
|
|
SFR_ACCESS(QCH_CON_UART_BT_QCH_CLOCK_REQ, 1, 1, QCH_CON_UART_BT_QCH),
|
|
SFR_ACCESS(QCH_CON_UART_BT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UART_BT_QCH),
|
|
SFR_ACCESS(QCH_CON_UART_BT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UART_BT_QCH),
|
|
SFR_ACCESS(QCH_CON_USI06_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI06_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI06_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI06_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI06_I2C_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI06_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI06_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI06_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI06_USI_QCH_ENABLE, 0, 1, QCH_CON_USI06_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI06_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI06_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI06_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI06_USI_QCH),
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SFR_ACCESS(QCH_CON_USI06_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI06_USI_QCH),
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SFR_ACCESS(QCH_CON_USI07_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI07_I2C_QCH),
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SFR_ACCESS(QCH_CON_USI07_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI07_I2C_QCH),
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SFR_ACCESS(QCH_CON_USI07_I2C_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI07_I2C_QCH),
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SFR_ACCESS(QCH_CON_USI07_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI07_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI07_USI_QCH_ENABLE, 0, 1, QCH_CON_USI07_USI_QCH),
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SFR_ACCESS(QCH_CON_USI07_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI07_USI_QCH),
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SFR_ACCESS(QCH_CON_USI07_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI07_USI_QCH),
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SFR_ACCESS(QCH_CON_USI07_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI07_USI_QCH),
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SFR_ACCESS(QCH_CON_USI08_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI08_I2C_QCH),
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SFR_ACCESS(QCH_CON_USI08_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI08_I2C_QCH),
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SFR_ACCESS(QCH_CON_USI08_I2C_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI08_I2C_QCH),
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SFR_ACCESS(QCH_CON_USI08_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI08_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI08_USI_QCH_ENABLE, 0, 1, QCH_CON_USI08_USI_QCH),
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SFR_ACCESS(QCH_CON_USI08_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI08_USI_QCH),
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SFR_ACCESS(QCH_CON_USI08_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI08_USI_QCH),
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SFR_ACCESS(QCH_CON_USI08_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI08_USI_QCH),
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SFR_ACCESS(QCH_CON_USI09_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI09_I2C_QCH),
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SFR_ACCESS(QCH_CON_USI09_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI09_I2C_QCH),
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SFR_ACCESS(QCH_CON_USI09_I2C_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI09_I2C_QCH),
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SFR_ACCESS(QCH_CON_USI09_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI09_I2C_QCH),
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SFR_ACCESS(QCH_CON_USI09_USI_QCH_ENABLE, 0, 1, QCH_CON_USI09_USI_QCH),
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SFR_ACCESS(QCH_CON_USI09_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI09_USI_QCH),
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SFR_ACCESS(QCH_CON_USI09_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI09_USI_QCH),
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SFR_ACCESS(QCH_CON_USI09_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI09_USI_QCH),
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SFR_ACCESS(QCH_CON_USI10_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI10_I2C_QCH),
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SFR_ACCESS(QCH_CON_USI10_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI10_I2C_QCH),
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SFR_ACCESS(QCH_CON_USI10_I2C_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI10_I2C_QCH),
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SFR_ACCESS(QCH_CON_USI10_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI10_I2C_QCH),
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SFR_ACCESS(QCH_CON_USI10_USI_QCH_ENABLE, 0, 1, QCH_CON_USI10_USI_QCH),
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SFR_ACCESS(QCH_CON_USI10_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI10_USI_QCH),
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SFR_ACCESS(QCH_CON_USI10_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI10_USI_QCH),
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SFR_ACCESS(QCH_CON_USI10_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI10_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI11_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI11_I2C_QCH),
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SFR_ACCESS(QCH_CON_USI11_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI11_I2C_QCH),
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SFR_ACCESS(QCH_CON_USI11_I2C_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI11_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI11_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI11_I2C_QCH),
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|
SFR_ACCESS(QCH_CON_USI11_USI_QCH_ENABLE, 0, 1, QCH_CON_USI11_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI11_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI11_USI_QCH),
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|
SFR_ACCESS(QCH_CON_USI11_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI11_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI11_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI11_USI_QCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP_IPCLKPORT_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIS_BUS_USER),
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|
SFR_ACCESS(CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT0),
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|
SFR_ACCESS(CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT0),
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SFR_ACCESS(CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT1),
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SFR_ACCESS(CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT1),
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|
SFR_ACCESS(CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_PERIS_CMU_PERIS_CLKOUT1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIS_GIC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIS_GIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIS_GIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIS_GIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIS_GIC_SELECT, 0, 5, CLK_CON_MUX_MUX_CLK_PERIS_GIC),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(QCH_CON_BUSIF_TMU_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_TMU_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_TMU_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_TMU_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_TMU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_TMU_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_TMU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_TMU_QCH),
|
|
SFR_ACCESS(QCH_CON_GIC_QCH_ENABLE, 0, 1, QCH_CON_GIC_QCH),
|
|
SFR_ACCESS(QCH_CON_GIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_GIC_QCH),
|
|
SFR_ACCESS(QCH_CON_GIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GIC_QCH),
|
|
SFR_ACCESS(QCH_CON_GIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GIC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_MCT_QCH_ENABLE, 0, 1, QCH_CON_MCT_QCH),
|
|
SFR_ACCESS(QCH_CON_MCT_QCH_CLOCK_REQ, 1, 1, QCH_CON_MCT_QCH),
|
|
SFR_ACCESS(QCH_CON_MCT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MCT_QCH),
|
|
SFR_ACCESS(QCH_CON_MCT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCT_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_BIRA_QCH_ENABLE, 0, 1, QCH_CON_OTP_CON_BIRA_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_BIRA_QCH_CLOCK_REQ, 1, 1, QCH_CON_OTP_CON_BIRA_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_BIRA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_OTP_CON_BIRA_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_BIRA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_OTP_CON_BIRA_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_ENABLE, 0, 1, QCH_CON_OTP_CON_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_OTP_CON_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_OTP_CON_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_OTP_CON_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIS_CMU_PERIS_QCH_ENABLE, 0, 1, QCH_CON_PERIS_CMU_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIS_CMU_PERIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_PERIS_CMU_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIS_CMU_PERIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PERIS_CMU_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIS_CMU_PERIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIS_CMU_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_WDT_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CLUSTER1_QCH_ENABLE, 0, 1, QCH_CON_WDT_CLUSTER1_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CLUSTER1_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_CLUSTER1_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CLUSTER1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_CLUSTER1_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CLUSTER1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_CLUSTER1_QCH),
|
|
SFR_ACCESS(PLL_CON0_PLL_MIF_S2D_DIV_P, 8, 6, PLL_CON0_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON0_PLL_MIF_S2D_DIV_M, 16, 10, PLL_CON0_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON0_PLL_MIF_S2D_DIV_S, 0, 3, PLL_CON0_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON0_PLL_MIF_S2D_ENABLE, 31, 1, PLL_CON0_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON0_PLL_MIF_S2D_STABLE, 29, 1, PLL_CON0_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_MIF_S2D_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MIF_S2D),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_MIF_DDRPHY2X_S2D_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_MIF_DDRPHY2X_S2D),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_MIF_DDRPHY2X_S2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_MIF_DDRPHY2X_S2D),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_MIF_DDRPHY2X_S2D_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_MIF_DDRPHY2X_S2D),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_MIF_BUSD_S2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_MIF_BUSD_S2D),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_S2D_CORE_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_S2D_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_S2D_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_S2D_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_S2D_CORE_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_S2D_CORE),
|
|
SFR_ACCESS(QCH_CON_S2D_CMU_S2D_QCH_ENABLE, 0, 1, QCH_CON_S2D_CMU_S2D_QCH),
|
|
SFR_ACCESS(QCH_CON_S2D_CMU_S2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_S2D_CMU_S2D_QCH),
|
|
SFR_ACCESS(QCH_CON_S2D_CMU_S2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_S2D_CMU_S2D_QCH),
|
|
SFR_ACCESS(QCH_CON_S2D_CMU_S2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_S2D_CMU_S2D_QCH),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIVRATIO, 0, 6, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIVRATIO, 0, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT0),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT1),
|
|
SFR_ACCESS(CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_VTS_CMU_VTS_CLKOUT1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2_DIVRATIO, 0, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_CLK),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_VTS_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_VTS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_VTS_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_VTS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_VTS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_VTS_BUS_USER),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_DIV2_CLK),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_VTS_DLL_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_VTS_DLL_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_VTS_DLL_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_VTS_DLL_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_VTS_DLL_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_VTS_DLL_USER),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_MUX_IPCLKPORT_D0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_MUX_IPCLKPORT_D0),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_MUX_IPCLKPORT_D0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_MUX_IPCLKPORT_D0),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_MUX_IPCLKPORT_D0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_MUX_IPCLKPORT_D0),
|
|
SFR_ACCESS(QCH_CON_AHB_BUSMATRIX_QCH_SYS_ENABLE, 0, 1, QCH_CON_AHB_BUSMATRIX_QCH_SYS),
|
|
SFR_ACCESS(QCH_CON_AHB_BUSMATRIX_QCH_SYS_CLOCK_REQ, 1, 1, QCH_CON_AHB_BUSMATRIX_QCH_SYS),
|
|
SFR_ACCESS(QCH_CON_AHB_BUSMATRIX_QCH_SYS_EXPIRE_VAL, 16, 10, QCH_CON_AHB_BUSMATRIX_QCH_SYS),
|
|
SFR_ACCESS(QCH_CON_AHB_BUSMATRIX_QCH_SYS_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_AHB_BUSMATRIX_QCH_SYS),
|
|
SFR_ACCESS(QCH_CON_ASYNCAHBM_VTS_QCH_ENABLE, 0, 1, QCH_CON_ASYNCAHBM_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_ASYNCAHBM_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_ASYNCAHBM_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_ASYNCAHBM_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ASYNCAHBM_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_ASYNCAHBM_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ASYNCAHBM_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_ENABLE, 0, 1, QCH_CON_CORTEXM4INTEGRATION_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_CLOCK_REQ, 1, 1, QCH_CON_CORTEXM4INTEGRATION_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_EXPIRE_VAL, 16, 10, QCH_CON_CORTEXM4INTEGRATION_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CORTEXM4INTEGRATION_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB0_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_AHB0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB0_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_AHB0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB0_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DMIC_AHB0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB0_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_AHB0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB1_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_AHB1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB1_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_AHB1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB1_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DMIC_AHB1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB1_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_AHB1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_IF_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_IF_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DMIC_IF_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_IF_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK_ENABLE, 0, 1, DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK_CLOCK_REQ, 1, 1, DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK),
|
|
SFR_ACCESS(QCH_CON_GPIO_VTS_QCH_ENABLE, 0, 1, QCH_CON_GPIO_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC0_QCH_ENABLE, 0, 1, QCH_CON_HWACG_SYS_DMIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_HWACG_SYS_DMIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HWACG_SYS_DMIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HWACG_SYS_DMIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC1_QCH_ENABLE, 0, 1, QCH_CON_HWACG_SYS_DMIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_HWACG_SYS_DMIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HWACG_SYS_DMIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HWACG_SYS_DMIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_VTS2CHUB_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_VTS2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_VTS2CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_VTS2CHUB_QCH),
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SFR_ACCESS(QCH_CON_MAILBOX_VTS2CHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_VTS2CHUB_QCH),
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SFR_ACCESS(QCH_CON_MAILBOX_VTS2CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_VTS2CHUB_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_VTS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_VTS_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_VTS_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_VTS_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_VTS_QCH),
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SFR_ACCESS(QCH_CON_VTS_CMU_VTS_QCH_ENABLE, 0, 1, QCH_CON_VTS_CMU_VTS_QCH),
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SFR_ACCESS(QCH_CON_VTS_CMU_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_VTS_CMU_VTS_QCH),
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SFR_ACCESS(QCH_CON_VTS_CMU_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VTS_CMU_VTS_QCH),
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SFR_ACCESS(QCH_CON_VTS_CMU_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VTS_CMU_VTS_QCH),
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SFR_ACCESS(QCH_CON_WDT_VTS_QCH_ENABLE, 0, 1, QCH_CON_WDT_VTS_QCH),
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SFR_ACCESS(QCH_CON_WDT_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_VTS_QCH),
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SFR_ACCESS(QCH_CON_WDT_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_VTS_QCH),
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SFR_ACCESS(QCH_CON_WDT_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_VTS_QCH),
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SFR_ACCESS(DMYQCH_CON_U_DMIC_CLK_MUX_QCH_ENABLE, 0, 1, DMYQCH_CON_U_DMIC_CLK_MUX_QCH),
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SFR_ACCESS(DMYQCH_CON_U_DMIC_CLK_MUX_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_U_DMIC_CLK_MUX_QCH),
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SFR_ACCESS(DMYQCH_CON_U_DMIC_CLK_MUX_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_U_DMIC_CLK_MUX_QCH),
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/*====================The section of controller option SFR ACCESS instance===================*/
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SFR_ACCESS(APM_ENABLE_POWER_MANAGEMENT, 29, 1, APM_CMU_APM_CONTROLLER_OPTION),
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SFR_ACCESS(APM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, APM_CMU_APM_CONTROLLER_OPTION),
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SFR_ACCESS(AUD_ENABLE_POWER_MANAGEMENT, 29, 1, AUD_CMU_AUD_CONTROLLER_OPTION),
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SFR_ACCESS(AUD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, AUD_CMU_AUD_CONTROLLER_OPTION),
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SFR_ACCESS(BUS1_ENABLE_POWER_MANAGEMENT, 29, 1, BUS1_CMU_BUS1_CONTROLLER_OPTION),
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SFR_ACCESS(BUS1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, BUS1_CMU_BUS1_CONTROLLER_OPTION),
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SFR_ACCESS(BUSC_ENABLE_POWER_MANAGEMENT, 29, 1, BUSC_CMU_BUSC_CONTROLLER_OPTION),
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SFR_ACCESS(BUSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, BUSC_CMU_BUSC_CONTROLLER_OPTION),
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SFR_ACCESS(CHUB_ENABLE_POWER_MANAGEMENT, 29, 1, CHUB_CMU_CHUB_CONTROLLER_OPTION),
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SFR_ACCESS(CHUB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CHUB_CMU_CHUB_CONTROLLER_OPTION),
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SFR_ACCESS(CMGP_ENABLE_POWER_MANAGEMENT, 29, 1, CMGP_CMU_CMGP_CONTROLLER_OPTION),
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SFR_ACCESS(CMGP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CMGP_CMU_CMGP_CONTROLLER_OPTION),
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SFR_ACCESS(CMU_ENABLE_POWER_MANAGEMENT, 29, 1, CMU_CMU_CMU_CONTROLLER_OPTION),
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SFR_ACCESS(CMU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CMU_CMU_CMU_CONTROLLER_OPTION),
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SFR_ACCESS(CORE_ENABLE_POWER_MANAGEMENT, 29, 1, CORE_CMU_CORE_CONTROLLER_OPTION),
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SFR_ACCESS(CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CORE_CMU_CORE_CONTROLLER_OPTION),
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SFR_ACCESS(CPUCL0_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION),
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SFR_ACCESS(CPUCL0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION),
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SFR_ACCESS(CPUCL1_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION),
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SFR_ACCESS(CPUCL1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION),
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SFR_ACCESS(DCF_ENABLE_POWER_MANAGEMENT, 29, 1, DCF_CMU_DCF_CONTROLLER_OPTION),
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SFR_ACCESS(DCF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DCF_CMU_DCF_CONTROLLER_OPTION),
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SFR_ACCESS(DCPOST_ENABLE_POWER_MANAGEMENT, 29, 1, DCPOST_CMU_DCPOST_CONTROLLER_OPTION),
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SFR_ACCESS(DCPOST_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DCPOST_CMU_DCPOST_CONTROLLER_OPTION),
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SFR_ACCESS(DCRD_ENABLE_POWER_MANAGEMENT, 29, 1, DCRD_CMU_DCRD_CONTROLLER_OPTION),
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SFR_ACCESS(DCRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DCRD_CMU_DCRD_CONTROLLER_OPTION),
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SFR_ACCESS(DPU_ENABLE_POWER_MANAGEMENT, 29, 1, DPU_CMU_DPU_CONTROLLER_OPTION),
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SFR_ACCESS(DPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DPU_CMU_DPU_CONTROLLER_OPTION),
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SFR_ACCESS(DSPM_ENABLE_POWER_MANAGEMENT, 29, 1, DSPM_CMU_DSPM_CONTROLLER_OPTION),
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SFR_ACCESS(DSPM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DSPM_CMU_DSPM_CONTROLLER_OPTION),
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SFR_ACCESS(DSPS_ENABLE_POWER_MANAGEMENT, 29, 1, DSPS_CMU_DSPS_CONTROLLER_OPTION),
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SFR_ACCESS(DSPS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DSPS_CMU_DSPS_CONTROLLER_OPTION),
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SFR_ACCESS(FSYS0_ENABLE_POWER_MANAGEMENT, 29, 1, FSYS0_CMU_FSYS0_CONTROLLER_OPTION),
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SFR_ACCESS(FSYS0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, FSYS0_CMU_FSYS0_CONTROLLER_OPTION),
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SFR_ACCESS(FSYS1_ENABLE_POWER_MANAGEMENT, 29, 1, FSYS1_CMU_FSYS1_CONTROLLER_OPTION),
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SFR_ACCESS(FSYS1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, FSYS1_CMU_FSYS1_CONTROLLER_OPTION),
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SFR_ACCESS(G2D_ENABLE_POWER_MANAGEMENT, 29, 1, G2D_CMU_G2D_CONTROLLER_OPTION),
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SFR_ACCESS(G2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, G2D_CMU_G2D_CONTROLLER_OPTION),
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SFR_ACCESS(G3D_ENABLE_POWER_MANAGEMENT, 29, 1, G3D_CMU_G3D_CONTROLLER_OPTION),
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SFR_ACCESS(G3D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, G3D_CMU_G3D_CONTROLLER_OPTION),
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SFR_ACCESS(ISPHQ_ENABLE_POWER_MANAGEMENT, 29, 1, ISPHQ_CMU_ISPHQ_CONTROLLER_OPTION),
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SFR_ACCESS(ISPHQ_ENABLE_AUTOMATIC_CLKGATING, 28, 1, ISPHQ_CMU_ISPHQ_CONTROLLER_OPTION),
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SFR_ACCESS(ISPLP_ENABLE_POWER_MANAGEMENT, 29, 1, ISPLP_CMU_ISPLP_CONTROLLER_OPTION),
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SFR_ACCESS(ISPLP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, ISPLP_CMU_ISPLP_CONTROLLER_OPTION),
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SFR_ACCESS(ISPPRE_ENABLE_POWER_MANAGEMENT, 29, 1, ISPPRE_CMU_ISPPRE_CONTROLLER_OPTION),
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SFR_ACCESS(ISPPRE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, ISPPRE_CMU_ISPPRE_CONTROLLER_OPTION),
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SFR_ACCESS(IVA_ENABLE_POWER_MANAGEMENT, 29, 1, IVA_CMU_IVA_CONTROLLER_OPTION),
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SFR_ACCESS(IVA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, IVA_CMU_IVA_CONTROLLER_OPTION),
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SFR_ACCESS(MFC_ENABLE_POWER_MANAGEMENT, 29, 1, MFC_CMU_MFC_CONTROLLER_OPTION),
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SFR_ACCESS(MFC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MFC_CMU_MFC_CONTROLLER_OPTION),
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SFR_ACCESS(MIF_ENABLE_POWER_MANAGEMENT, 29, 1, MIF_CMU_MIF_CONTROLLER_OPTION),
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SFR_ACCESS(MIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MIF_CMU_MIF_CONTROLLER_OPTION),
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SFR_ACCESS(PERIC0_ENABLE_POWER_MANAGEMENT, 29, 1, PERIC0_CMU_PERIC0_CONTROLLER_OPTION),
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SFR_ACCESS(PERIC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PERIC0_CMU_PERIC0_CONTROLLER_OPTION),
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SFR_ACCESS(PERIC1_ENABLE_POWER_MANAGEMENT, 29, 1, PERIC1_CMU_PERIC1_CONTROLLER_OPTION),
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SFR_ACCESS(PERIC1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PERIC1_CMU_PERIC1_CONTROLLER_OPTION),
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SFR_ACCESS(PERIS_ENABLE_POWER_MANAGEMENT, 29, 1, PERIS_CMU_PERIS_CONTROLLER_OPTION),
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SFR_ACCESS(PERIS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PERIS_CMU_PERIS_CONTROLLER_OPTION),
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SFR_ACCESS(S2D_ENABLE_POWER_MANAGEMENT, 29, 1, S2D_CMU_S2D_CONTROLLER_OPTION),
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SFR_ACCESS(S2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, S2D_CMU_S2D_CONTROLLER_OPTION),
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SFR_ACCESS(VTS_ENABLE_POWER_MANAGEMENT, 29, 1, VTS_CMU_VTS_CONTROLLER_OPTION),
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SFR_ACCESS(VTS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, VTS_CMU_VTS_CONTROLLER_OPTION),
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};
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unsigned int cmucal_sfr_access_size = 5532;
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