669 lines
115 KiB
C
Executable File
669 lines
115 KiB
C
Executable File
#include "../cmucal.h"
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#include "cmucal-sfr.h"
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#include "cmucal-qch.h"
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/*=================CMUCAL version: S5E9810================================*/
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/*====================The section of QCH nodes===================*/
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unsigned int cmucal_qch_size = 617;
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struct cmucal_qch cmucal_qch_list[] = {
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CLK_QCH(APBIF_GPIO_ALIVE_QCH, QCH_CON_APBIF_GPIO_ALIVE_QCH_ENABLE, QCH_CON_APBIF_GPIO_ALIVE_QCH_CLOCK_REQ, QCH_CON_APBIF_GPIO_ALIVE_QCH_EXPIRE_VAL, QCH_CON_APBIF_GPIO_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_PMU_ALIVE_QCH, QCH_CON_APBIF_PMU_ALIVE_QCH_ENABLE, QCH_CON_APBIF_PMU_ALIVE_QCH_CLOCK_REQ, QCH_CON_APBIF_PMU_ALIVE_QCH_EXPIRE_VAL, QCH_CON_APBIF_PMU_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_RTC_QCH, QCH_CON_APBIF_RTC_QCH_ENABLE, QCH_CON_APBIF_RTC_QCH_CLOCK_REQ, QCH_CON_APBIF_RTC_QCH_EXPIRE_VAL, QCH_CON_APBIF_RTC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_TOP_RTC_QCH, QCH_CON_APBIF_TOP_RTC_QCH_ENABLE, QCH_CON_APBIF_TOP_RTC_QCH_CLOCK_REQ, QCH_CON_APBIF_TOP_RTC_QCH_EXPIRE_VAL, QCH_CON_APBIF_TOP_RTC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APM_CMU_APM_QCH, QCH_CON_APM_CMU_APM_QCH_ENABLE, QCH_CON_APM_CMU_APM_QCH_CLOCK_REQ, QCH_CON_APM_CMU_APM_QCH_EXPIRE_VAL, QCH_CON_APM_CMU_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GREBEINTEGRATION_QCH_GREBE, QCH_CON_GREBEINTEGRATION_QCH_GREBE_ENABLE, QCH_CON_GREBEINTEGRATION_QCH_GREBE_CLOCK_REQ, QCH_CON_GREBEINTEGRATION_QCH_GREBE_EXPIRE_VAL, QCH_CON_GREBEINTEGRATION_QCH_GREBE_IGNORE_FORCE_PM_EN),
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CLK_QCH(GREBEINTEGRATION_QCH_DBG, QCH_CON_GREBEINTEGRATION_QCH_DBG_ENABLE, QCH_CON_GREBEINTEGRATION_QCH_DBG_CLOCK_REQ, QCH_CON_GREBEINTEGRATION_QCH_DBG_EXPIRE_VAL, QCH_CON_GREBEINTEGRATION_QCH_DBG_IGNORE_FORCE_PM_EN),
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CLK_QCH(INTMEM_QCH, QCH_CON_INTMEM_QCH_ENABLE, QCH_CON_INTMEM_QCH_CLOCK_REQ, QCH_CON_INTMEM_QCH_EXPIRE_VAL, QCH_CON_INTMEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_APM_QCH, QCH_CON_LHM_AXI_P_APM_QCH_ENABLE, QCH_CON_LHM_AXI_P_APM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_APM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_APM_CHUB_QCH, QCH_CON_LHM_AXI_P_APM_CHUB_QCH_ENABLE, QCH_CON_LHM_AXI_P_APM_CHUB_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_APM_CHUB_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_APM_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_APM_CP_QCH, QCH_CON_LHM_AXI_P_APM_CP_QCH_ENABLE, QCH_CON_LHM_AXI_P_APM_CP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_APM_CP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_APM_CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_APM_GNSS_QCH, QCH_CON_LHM_AXI_P_APM_GNSS_QCH_ENABLE, QCH_CON_LHM_AXI_P_APM_GNSS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_APM_GNSS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_APM_GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_APM_QCH, QCH_CON_LHS_AXI_D_APM_QCH_ENABLE, QCH_CON_LHS_AXI_D_APM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_APM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_G_SCAN2DRAM_QCH, QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_ENABLE, QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_LP_CHUB_QCH, QCH_CON_LHS_AXI_LP_CHUB_QCH_ENABLE, QCH_CON_LHS_AXI_LP_CHUB_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_LP_CHUB_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_LP_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_APM2CMGP_QCH, QCH_CON_LHS_AXI_P_APM2CMGP_QCH_ENABLE, QCH_CON_LHS_AXI_P_APM2CMGP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_APM2CMGP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_APM2CMGP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP2CHUB_QCH, QCH_CON_MAILBOX_AP2CHUB_QCH_ENABLE, QCH_CON_MAILBOX_AP2CHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP2CHUB_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP2CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP2CP_QCH, QCH_CON_MAILBOX_AP2CP_QCH_ENABLE, QCH_CON_MAILBOX_AP2CP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP2CP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP2CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP2CP_S_QCH, QCH_CON_MAILBOX_AP2CP_S_QCH_ENABLE, QCH_CON_MAILBOX_AP2CP_S_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP2CP_S_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP2CP_S_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP2GNSS_QCH, QCH_CON_MAILBOX_AP2GNSS_QCH_ENABLE, QCH_CON_MAILBOX_AP2GNSS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP2GNSS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP2GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP2VTS_QCH, QCH_CON_MAILBOX_AP2VTS_QCH_ENABLE, QCH_CON_MAILBOX_AP2VTS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP2VTS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP2VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM2AP_QCH, QCH_CON_MAILBOX_APM2AP_QCH_ENABLE, QCH_CON_MAILBOX_APM2AP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM2AP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM2AP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM2CHUB_QCH, QCH_CON_MAILBOX_APM2CHUB_QCH_ENABLE, QCH_CON_MAILBOX_APM2CHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM2CHUB_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM2CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM2CP_QCH, QCH_CON_MAILBOX_APM2CP_QCH_ENABLE, QCH_CON_MAILBOX_APM2CP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM2CP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM2CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM2GNSS_QCH, QCH_CON_MAILBOX_APM2GNSS_QCH_ENABLE, QCH_CON_MAILBOX_APM2GNSS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM2GNSS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM2GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_CHUB2CP_QCH, QCH_CON_MAILBOX_CHUB2CP_QCH_ENABLE, QCH_CON_MAILBOX_CHUB2CP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_CHUB2CP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_CHUB2CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_GNSS2CHUB_QCH, QCH_CON_MAILBOX_GNSS2CHUB_QCH_ENABLE, QCH_CON_MAILBOX_GNSS2CHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_GNSS2CHUB_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_GNSS2CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_GNSS2CP_QCH, QCH_CON_MAILBOX_GNSS2CP_QCH_ENABLE, QCH_CON_MAILBOX_GNSS2CP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_GNSS2CP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_GNSS2CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PEM_QCH, QCH_CON_PEM_QCH_ENABLE, QCH_CON_PEM_QCH_CLOCK_REQ, QCH_CON_PEM_QCH_EXPIRE_VAL, QCH_CON_PEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PGEN_APM_QCH, QCH_CON_PGEN_APM_QCH_ENABLE, QCH_CON_PGEN_APM_QCH_CLOCK_REQ, QCH_CON_PGEN_APM_QCH_EXPIRE_VAL, QCH_CON_PGEN_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PMU_INTR_GEN_QCH, QCH_CON_PMU_INTR_GEN_QCH_ENABLE, QCH_CON_PMU_INTR_GEN_QCH_CLOCK_REQ, QCH_CON_PMU_INTR_GEN_QCH_EXPIRE_VAL, QCH_CON_PMU_INTR_GEN_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_APM_BUS_QCH, QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SPEEDY_APM_QCH, QCH_CON_SPEEDY_APM_QCH_ENABLE, QCH_CON_SPEEDY_APM_QCH_CLOCK_REQ, QCH_CON_SPEEDY_APM_QCH_EXPIRE_VAL, QCH_CON_SPEEDY_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SPEEDY_SUB_APM_QCH, QCH_CON_SPEEDY_SUB_APM_QCH_ENABLE, QCH_CON_SPEEDY_SUB_APM_QCH_CLOCK_REQ, QCH_CON_SPEEDY_SUB_APM_QCH_EXPIRE_VAL, QCH_CON_SPEEDY_SUB_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_APM_QCH, QCH_CON_SYSREG_APM_QCH_ENABLE, QCH_CON_SYSREG_APM_QCH_CLOCK_REQ, QCH_CON_SYSREG_APM_QCH_EXPIRE_VAL, QCH_CON_SYSREG_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WDT_APM_QCH, QCH_CON_WDT_APM_QCH_ENABLE, QCH_CON_WDT_APM_QCH_CLOCK_REQ, QCH_CON_WDT_APM_QCH_EXPIRE_VAL, QCH_CON_WDT_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_ACLK, QCH_CON_ABOX_QCH_ACLK_ENABLE, QCH_CON_ABOX_QCH_ACLK_CLOCK_REQ, QCH_CON_ABOX_QCH_ACLK_EXPIRE_VAL, QCH_CON_ABOX_QCH_ACLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_BCLK_DSIF, QCH_CON_ABOX_QCH_BCLK_DSIF_ENABLE, QCH_CON_ABOX_QCH_BCLK_DSIF_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK_DSIF_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK_DSIF_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_BCLK0, QCH_CON_ABOX_QCH_BCLK0_ENABLE, QCH_CON_ABOX_QCH_BCLK0_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK0_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK0_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_BCLK1, QCH_CON_ABOX_QCH_BCLK1_ENABLE, QCH_CON_ABOX_QCH_BCLK1_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK1_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK1_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_BCLK2, QCH_CON_ABOX_QCH_BCLK2_ENABLE, QCH_CON_ABOX_QCH_BCLK2_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK2_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK2_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_BCLK3, QCH_CON_ABOX_QCH_BCLK3_ENABLE, QCH_CON_ABOX_QCH_BCLK3_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK3_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK3_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_DUMMY, DMYQCH_CON_ABOX_QCH_DUMMY_ENABLE, DMYQCH_CON_ABOX_QCH_DUMMY_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ABOX_QCH_DUMMY_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_CCLK_ASB, QCH_CON_ABOX_QCH_CCLK_ASB_ENABLE, QCH_CON_ABOX_QCH_CCLK_ASB_CLOCK_REQ, QCH_CON_ABOX_QCH_CCLK_ASB_EXPIRE_VAL, QCH_CON_ABOX_QCH_CCLK_ASB_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_CCLK_ATB, QCH_CON_ABOX_QCH_CCLK_ATB_ENABLE, QCH_CON_ABOX_QCH_CCLK_ATB_CLOCK_REQ, QCH_CON_ABOX_QCH_CCLK_ATB_EXPIRE_VAL, QCH_CON_ABOX_QCH_CCLK_ATB_IGNORE_FORCE_PM_EN),
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CLK_QCH(AUD_CMU_AUD_QCH, QCH_CON_AUD_CMU_AUD_QCH_ENABLE, QCH_CON_AUD_CMU_AUD_QCH_CLOCK_REQ, QCH_CON_AUD_CMU_AUD_QCH_EXPIRE_VAL, QCH_CON_AUD_CMU_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_AUD_QCH, QCH_CON_BTM_AUD_QCH_ENABLE, QCH_CON_BTM_AUD_QCH_CLOCK_REQ, QCH_CON_BTM_AUD_QCH_EXPIRE_VAL, QCH_CON_BTM_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DFTMUX_AUD_QCH, DMYQCH_CON_DFTMUX_AUD_QCH_ENABLE, DMYQCH_CON_DFTMUX_AUD_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_QCH, DMYQCH_CON_DMIC_QCH_ENABLE, DMYQCH_CON_DMIC_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DMIC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPIO_AUD_QCH, QCH_CON_GPIO_AUD_QCH_ENABLE, QCH_CON_GPIO_AUD_QCH_CLOCK_REQ, QCH_CON_GPIO_AUD_QCH_EXPIRE_VAL, QCH_CON_GPIO_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_AUD_QCH, QCH_CON_LHM_AXI_P_AUD_QCH_ENABLE, QCH_CON_LHM_AXI_P_AUD_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_AUD_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_AUD_QCH, QCH_CON_LHS_ATB_AUD_QCH_ENABLE, QCH_CON_LHS_ATB_AUD_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_AUD_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_AUD_QCH, QCH_CON_LHS_AXI_D_AUD_QCH_ENABLE, QCH_CON_LHS_AXI_D_AUD_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_AUD_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_AUD_QCH, QCH_CON_PPMU_AUD_QCH_ENABLE, QCH_CON_PPMU_AUD_QCH_CLOCK_REQ, QCH_CON_PPMU_AUD_QCH_EXPIRE_VAL, QCH_CON_PPMU_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_AUD_QCH, QCH_CON_SYSMMU_AUD_QCH_ENABLE, QCH_CON_SYSMMU_AUD_QCH_CLOCK_REQ, QCH_CON_SYSMMU_AUD_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_AUD_QCH, QCH_CON_SYSREG_AUD_QCH_ENABLE, QCH_CON_SYSREG_AUD_QCH_CLOCK_REQ, QCH_CON_SYSREG_AUD_QCH_EXPIRE_VAL, QCH_CON_SYSREG_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_AUD_QCH, QCH_CON_TREX_AUD_QCH_ENABLE, QCH_CON_TREX_AUD_QCH_CLOCK_REQ, QCH_CON_TREX_AUD_QCH_EXPIRE_VAL, QCH_CON_TREX_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WDT_AUD_QCH, QCH_CON_WDT_AUD_QCH_ENABLE, QCH_CON_WDT_AUD_QCH_CLOCK_REQ, QCH_CON_WDT_AUD_QCH_EXPIRE_VAL, QCH_CON_WDT_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_P_CHUB_QCH, QCH_CON_BAAW_P_CHUB_QCH_ENABLE, QCH_CON_BAAW_P_CHUB_QCH_CLOCK_REQ, QCH_CON_BAAW_P_CHUB_QCH_EXPIRE_VAL, QCH_CON_BAAW_P_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_P_GNSS_QCH, QCH_CON_BAAW_P_GNSS_QCH_ENABLE, QCH_CON_BAAW_P_GNSS_QCH_CLOCK_REQ, QCH_CON_BAAW_P_GNSS_QCH_EXPIRE_VAL, QCH_CON_BAAW_P_GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUS1_CMU_BUS1_QCH, QCH_CON_BUS1_CMU_BUS1_QCH_ENABLE, QCH_CON_BUS1_CMU_BUS1_QCH_CLOCK_REQ, QCH_CON_BUS1_CMU_BUS1_QCH_EXPIRE_VAL, QCH_CON_BUS1_CMU_BUS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_APM_QCH, QCH_CON_LHM_AXI_D_APM_QCH_ENABLE, QCH_CON_LHM_AXI_D_APM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_APM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_CHUB_QCH, QCH_CON_LHM_AXI_D_CHUB_QCH_ENABLE, QCH_CON_LHM_AXI_D_CHUB_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_CHUB_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_GNSS_QCH, QCH_CON_LHM_AXI_D_GNSS_QCH_ENABLE, QCH_CON_LHM_AXI_D_GNSS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_GNSS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_G_CSSYS_QCH, QCH_CON_LHM_AXI_G_CSSYS_QCH_ENABLE, QCH_CON_LHM_AXI_G_CSSYS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_G_CSSYS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_BUS1_QCH, QCH_CON_LHS_AXI_D_BUS1_QCH_ENABLE, QCH_CON_LHS_AXI_D_BUS1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_BUS1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_BUS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_CHUB_QCH, QCH_CON_LHS_AXI_P_CHUB_QCH_ENABLE, QCH_CON_LHS_AXI_P_CHUB_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_CHUB_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_CSSYS_QCH, QCH_CON_LHS_AXI_P_CSSYS_QCH_ENABLE, QCH_CON_LHS_AXI_P_CSSYS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_CSSYS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_CSSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_GNSS_QCH, QCH_CON_LHS_AXI_P_GNSS_QCH_ENABLE, QCH_CON_LHS_AXI_P_GNSS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_GNSS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_BUS1_QCH, QCH_CON_SYSREG_BUS1_QCH_ENABLE, QCH_CON_SYSREG_BUS1_QCH_CLOCK_REQ, QCH_CON_SYSREG_BUS1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_BUS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_P_BUS1_QCH, QCH_CON_TREX_P_BUS1_QCH_ENABLE, QCH_CON_TREX_P_BUS1_QCH_CLOCK_REQ, QCH_CON_TREX_P_BUS1_QCH_EXPIRE_VAL, QCH_CON_TREX_P_BUS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSC_CMU_BUSC_QCH, QCH_CON_BUSC_CMU_BUSC_QCH_ENABLE, QCH_CON_BUSC_CMU_BUSC_QCH_CLOCK_REQ, QCH_CON_BUSC_CMU_BUSC_QCH_EXPIRE_VAL, QCH_CON_BUSC_CMU_BUSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_CMUTOPC_QCH, QCH_CON_BUSIF_CMUTOPC_QCH_ENABLE, QCH_CON_BUSIF_CMUTOPC_QCH_CLOCK_REQ, QCH_CON_BUSIF_CMUTOPC_QCH_EXPIRE_VAL, QCH_CON_BUSIF_CMUTOPC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_HPMBUSC_QCH, QCH_CON_BUSIF_HPMBUSC_QCH_ENABLE, QCH_CON_BUSIF_HPMBUSC_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMBUSC_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMBUSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D0_DSPM_QCH, QCH_CON_LHM_ACEL_D0_DSPM_QCH_ENABLE, QCH_CON_LHM_ACEL_D0_DSPM_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D0_DSPM_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D0_DSPM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D0_G2D_QCH, QCH_CON_LHM_ACEL_D0_G2D_QCH_ENABLE, QCH_CON_LHM_ACEL_D0_G2D_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D0_G2D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D0_G2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D1_DSPM_QCH, QCH_CON_LHM_ACEL_D1_DSPM_QCH_ENABLE, QCH_CON_LHM_ACEL_D1_DSPM_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D1_DSPM_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D1_DSPM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D1_G2D_QCH, QCH_CON_LHM_ACEL_D1_G2D_QCH_ENABLE, QCH_CON_LHM_ACEL_D1_G2D_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D1_G2D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D1_G2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D2_DSPM_QCH, QCH_CON_LHM_ACEL_D2_DSPM_QCH_ENABLE, QCH_CON_LHM_ACEL_D2_DSPM_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D2_DSPM_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D2_DSPM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D2_G2D_QCH, QCH_CON_LHM_ACEL_D2_G2D_QCH_ENABLE, QCH_CON_LHM_ACEL_D2_G2D_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D2_G2D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D2_G2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D_FSYS0_QCH, QCH_CON_LHM_ACEL_D_FSYS0_QCH_ENABLE, QCH_CON_LHM_ACEL_D_FSYS0_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_FSYS0_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_FSYS0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D_FSYS1_QCH, QCH_CON_LHM_ACEL_D_FSYS1_QCH_ENABLE, QCH_CON_LHM_ACEL_D_FSYS1_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_FSYS1_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_FSYS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D_IVA_QCH, QCH_CON_LHM_ACEL_D_IVA_QCH_ENABLE, QCH_CON_LHM_ACEL_D_IVA_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_IVA_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_IVA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D0_DPU_QCH, QCH_CON_LHM_AXI_D0_DPU_QCH_ENABLE, QCH_CON_LHM_AXI_D0_DPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_DPU_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D0_ISPLP_QCH, QCH_CON_LHM_AXI_D0_ISPLP_QCH_ENABLE, QCH_CON_LHM_AXI_D0_ISPLP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_ISPLP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_ISPLP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D0_MFC_QCH, QCH_CON_LHM_AXI_D0_MFC_QCH_ENABLE, QCH_CON_LHM_AXI_D0_MFC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_MFC_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D1_DPU_QCH, QCH_CON_LHM_AXI_D1_DPU_QCH_ENABLE, QCH_CON_LHM_AXI_D1_DPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_DPU_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D1_ISPLP_QCH, QCH_CON_LHM_AXI_D1_ISPLP_QCH_ENABLE, QCH_CON_LHM_AXI_D1_ISPLP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_ISPLP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_ISPLP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D1_MFC_QCH, QCH_CON_LHM_AXI_D1_MFC_QCH_ENABLE, QCH_CON_LHM_AXI_D1_MFC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_MFC_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D2_DPU_QCH, QCH_CON_LHM_AXI_D2_DPU_QCH_ENABLE, QCH_CON_LHM_AXI_D2_DPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D2_DPU_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D2_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_AUD_QCH, QCH_CON_LHM_AXI_D_AUD_QCH_ENABLE, QCH_CON_LHM_AXI_D_AUD_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_AUD_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_BUS1_QCH, QCH_CON_LHM_AXI_D_BUS1_QCH_ENABLE, QCH_CON_LHM_AXI_D_BUS1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_BUS1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_BUS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_DCF_QCH, QCH_CON_LHM_AXI_D_DCF_QCH_ENABLE, QCH_CON_LHM_AXI_D_DCF_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_DCF_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_DCF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_DCRD_QCH, QCH_CON_LHM_AXI_D_DCRD_QCH_ENABLE, QCH_CON_LHM_AXI_D_DCRD_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_DCRD_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_DCRD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_ISPHQ_QCH, QCH_CON_LHM_AXI_D_ISPHQ_QCH_ENABLE, QCH_CON_LHM_AXI_D_ISPHQ_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_ISPHQ_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_ISPHQ_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_ISPPRE_QCH, QCH_CON_LHM_AXI_D_ISPPRE_QCH_ENABLE, QCH_CON_LHM_AXI_D_ISPPRE_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_ISPPRE_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_ISPPRE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_IVASC_QCH, QCH_CON_LHS_AXI_D_IVASC_QCH_ENABLE, QCH_CON_LHS_AXI_D_IVASC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_IVASC_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_IVASC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_AUD_QCH, QCH_CON_LHS_AXI_P_AUD_QCH_ENABLE, QCH_CON_LHS_AXI_P_AUD_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_AUD_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_DCF_QCH, QCH_CON_LHS_AXI_P_DCF_QCH_ENABLE, QCH_CON_LHS_AXI_P_DCF_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_DCF_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_DCF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_DCRD_QCH, QCH_CON_LHS_AXI_P_DCRD_QCH_ENABLE, QCH_CON_LHS_AXI_P_DCRD_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_DCRD_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_DCRD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_DPU_QCH, QCH_CON_LHS_AXI_P_DPU_QCH_ENABLE, QCH_CON_LHS_AXI_P_DPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_DPU_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_DSPM_QCH, QCH_CON_LHS_AXI_P_DSPM_QCH_ENABLE, QCH_CON_LHS_AXI_P_DSPM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_DSPM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_DSPM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_FSYS0_QCH, QCH_CON_LHS_AXI_P_FSYS0_QCH_ENABLE, QCH_CON_LHS_AXI_P_FSYS0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_FSYS0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_FSYS0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_FSYS1_QCH, QCH_CON_LHS_AXI_P_FSYS1_QCH_ENABLE, QCH_CON_LHS_AXI_P_FSYS1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_FSYS1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_FSYS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_G2D_QCH, QCH_CON_LHS_AXI_P_G2D_QCH_ENABLE, QCH_CON_LHS_AXI_P_G2D_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_G2D_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_G2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_ISPHQ_QCH, QCH_CON_LHS_AXI_P_ISPHQ_QCH_ENABLE, QCH_CON_LHS_AXI_P_ISPHQ_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_ISPHQ_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_ISPHQ_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_ISPLP_QCH, QCH_CON_LHS_AXI_P_ISPLP_QCH_ENABLE, QCH_CON_LHS_AXI_P_ISPLP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_ISPLP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_ISPLP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_ISPPRE_QCH, QCH_CON_LHS_AXI_P_ISPPRE_QCH_ENABLE, QCH_CON_LHS_AXI_P_ISPPRE_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_ISPPRE_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_ISPPRE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_IVA_QCH, QCH_CON_LHS_AXI_P_IVA_QCH_ENABLE, QCH_CON_LHS_AXI_P_IVA_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_IVA_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_IVA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_MFC_QCH, QCH_CON_LHS_AXI_P_MFC_QCH_ENABLE, QCH_CON_LHS_AXI_P_MFC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MFC_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_MIF0_QCH, QCH_CON_LHS_AXI_P_MIF0_QCH_ENABLE, QCH_CON_LHS_AXI_P_MIF0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MIF0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MIF0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_MIF1_QCH, QCH_CON_LHS_AXI_P_MIF1_QCH_ENABLE, QCH_CON_LHS_AXI_P_MIF1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MIF1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MIF1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_MIF2_QCH, QCH_CON_LHS_AXI_P_MIF2_QCH_ENABLE, QCH_CON_LHS_AXI_P_MIF2_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MIF2_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MIF2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_MIF3_QCH, QCH_CON_LHS_AXI_P_MIF3_QCH_ENABLE, QCH_CON_LHS_AXI_P_MIF3_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MIF3_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MIF3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_PERIC0_QCH, QCH_CON_LHS_AXI_P_PERIC0_QCH_ENABLE, QCH_CON_LHS_AXI_P_PERIC0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_PERIC0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_PERIC1_QCH, QCH_CON_LHS_AXI_P_PERIC1_QCH_ENABLE, QCH_CON_LHS_AXI_P_PERIC1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_PERIC1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_PERIS_QCH, QCH_CON_LHS_AXI_P_PERIS_QCH_ENABLE, QCH_CON_LHS_AXI_P_PERIS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_PERIS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_PERIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PDMA0_QCH, QCH_CON_PDMA0_QCH_ENABLE, QCH_CON_PDMA0_QCH_CLOCK_REQ, QCH_CON_PDMA0_QCH_EXPIRE_VAL, QCH_CON_PDMA0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PGEN_LITE_BUSC_QCH, QCH_CON_PGEN_LITE_BUSC_QCH_ENABLE, QCH_CON_PGEN_LITE_BUSC_QCH_CLOCK_REQ, QCH_CON_PGEN_LITE_BUSC_QCH_EXPIRE_VAL, QCH_CON_PGEN_LITE_BUSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PGEN_PDMA0_QCH, QCH_CON_PGEN_PDMA0_QCH_ENABLE, QCH_CON_PGEN_PDMA0_QCH_CLOCK_REQ, QCH_CON_PGEN_PDMA0_QCH_EXPIRE_VAL, QCH_CON_PGEN_PDMA0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPFW_QCH, QCH_CON_PPFW_QCH_ENABLE, QCH_CON_PPFW_QCH_CLOCK_REQ, QCH_CON_PPFW_QCH_EXPIRE_VAL, QCH_CON_PPFW_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SBIC_QCH, QCH_CON_SBIC_QCH_ENABLE, QCH_CON_SBIC_QCH_CLOCK_REQ, QCH_CON_SBIC_QCH_EXPIRE_VAL, QCH_CON_SBIC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SIREX_QCH, QCH_CON_SIREX_QCH_ENABLE, QCH_CON_SIREX_QCH_CLOCK_REQ, QCH_CON_SIREX_QCH_EXPIRE_VAL, QCH_CON_SIREX_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SPDMA_QCH, QCH_CON_SPDMA_QCH_ENABLE, QCH_CON_SPDMA_QCH_CLOCK_REQ, QCH_CON_SPDMA_QCH_EXPIRE_VAL, QCH_CON_SPDMA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_BUSC_QCH, QCH_CON_SYSREG_BUSC_QCH_ENABLE, QCH_CON_SYSREG_BUSC_QCH_CLOCK_REQ, QCH_CON_SYSREG_BUSC_QCH_EXPIRE_VAL, QCH_CON_SYSREG_BUSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_D_BUSC_QCH, QCH_CON_TREX_D_BUSC_QCH_ENABLE, QCH_CON_TREX_D_BUSC_QCH_CLOCK_REQ, QCH_CON_TREX_D_BUSC_QCH_EXPIRE_VAL, QCH_CON_TREX_D_BUSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_P_BUSC_QCH, QCH_CON_TREX_P_BUSC_QCH_ENABLE, QCH_CON_TREX_P_BUSC_QCH_CLOCK_REQ, QCH_CON_TREX_P_BUSC_QCH_EXPIRE_VAL, QCH_CON_TREX_P_BUSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_RB_BUSC_QCH, QCH_CON_TREX_RB_BUSC_QCH_ENABLE, QCH_CON_TREX_RB_BUSC_QCH_CLOCK_REQ, QCH_CON_TREX_RB_BUSC_QCH_EXPIRE_VAL, QCH_CON_TREX_RB_BUSC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ASYNCAHBM_CHUB_QCH, QCH_CON_ASYNCAHBM_CHUB_QCH_ENABLE, QCH_CON_ASYNCAHBM_CHUB_QCH_CLOCK_REQ, QCH_CON_ASYNCAHBM_CHUB_QCH_EXPIRE_VAL, QCH_CON_ASYNCAHBM_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_D_CHUB_QCH, QCH_CON_BAAW_D_CHUB_QCH_ENABLE, QCH_CON_BAAW_D_CHUB_QCH_CLOCK_REQ, QCH_CON_BAAW_D_CHUB_QCH_EXPIRE_VAL, QCH_CON_BAAW_D_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_P_APM_CHUB_QCH, QCH_CON_BAAW_P_APM_CHUB_QCH_ENABLE, QCH_CON_BAAW_P_APM_CHUB_QCH_CLOCK_REQ, QCH_CON_BAAW_P_APM_CHUB_QCH_EXPIRE_VAL, QCH_CON_BAAW_P_APM_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_S_CHUB_QCH, QCH_CON_BAAW_S_CHUB_QCH_ENABLE, QCH_CON_BAAW_S_CHUB_QCH_CLOCK_REQ, QCH_CON_BAAW_S_CHUB_QCH_EXPIRE_VAL, QCH_CON_BAAW_S_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CHUB_CMU_CHUB_QCH, QCH_CON_CHUB_CMU_CHUB_QCH_ENABLE, QCH_CON_CHUB_CMU_CHUB_QCH_CLOCK_REQ, QCH_CON_CHUB_CMU_CHUB_QCH_EXPIRE_VAL, QCH_CON_CHUB_CMU_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CM4_CHUB_QCH, QCH_CON_CM4_CHUB_QCH_ENABLE, QCH_CON_CM4_CHUB_QCH_CLOCK_REQ, QCH_CON_CM4_CHUB_QCH_EXPIRE_VAL, QCH_CON_CM4_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPIO_CHUB_QCH, QCH_CON_GPIO_CHUB_QCH_ENABLE, QCH_CON_GPIO_CHUB_QCH_CLOCK_REQ, QCH_CON_GPIO_CHUB_QCH_EXPIRE_VAL, QCH_CON_GPIO_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_CHUB00_QCH, QCH_CON_I2C_CHUB00_QCH_ENABLE, QCH_CON_I2C_CHUB00_QCH_CLOCK_REQ, QCH_CON_I2C_CHUB00_QCH_EXPIRE_VAL, QCH_CON_I2C_CHUB00_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_CHUB01_QCH, QCH_CON_I2C_CHUB01_QCH_ENABLE, QCH_CON_I2C_CHUB01_QCH_CLOCK_REQ, QCH_CON_I2C_CHUB01_QCH_EXPIRE_VAL, QCH_CON_I2C_CHUB01_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_LP_CHUB_QCH, QCH_CON_LHM_AXI_LP_CHUB_QCH_ENABLE, QCH_CON_LHM_AXI_LP_CHUB_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_LP_CHUB_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_LP_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_CHUB_QCH, QCH_CON_LHM_AXI_P_CHUB_QCH_ENABLE, QCH_CON_LHM_AXI_P_CHUB_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_CHUB_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_CHUB_QCH, QCH_CON_LHS_AXI_D_CHUB_QCH_ENABLE, QCH_CON_LHS_AXI_D_CHUB_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_CHUB_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_APM_CHUB_QCH, QCH_CON_LHS_AXI_P_APM_CHUB_QCH_ENABLE, QCH_CON_LHS_AXI_P_APM_CHUB_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_APM_CHUB_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_APM_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PDMA_CHUB_QCH, QCH_CON_PDMA_CHUB_QCH_ENABLE, QCH_CON_PDMA_CHUB_QCH_CLOCK_REQ, QCH_CON_PDMA_CHUB_QCH_EXPIRE_VAL, QCH_CON_PDMA_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PWM_CHUB_QCH, QCH_CON_PWM_CHUB_QCH_ENABLE, QCH_CON_PWM_CHUB_QCH_CLOCK_REQ, QCH_CON_PWM_CHUB_QCH_EXPIRE_VAL, QCH_CON_PWM_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SWEEPER_D_CHUB_QCH, QCH_CON_SWEEPER_D_CHUB_QCH_ENABLE, QCH_CON_SWEEPER_D_CHUB_QCH_CLOCK_REQ, QCH_CON_SWEEPER_D_CHUB_QCH_EXPIRE_VAL, QCH_CON_SWEEPER_D_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SWEEPER_P_APM_CHUB_QCH, QCH_CON_SWEEPER_P_APM_CHUB_QCH_ENABLE, QCH_CON_SWEEPER_P_APM_CHUB_QCH_CLOCK_REQ, QCH_CON_SWEEPER_P_APM_CHUB_QCH_EXPIRE_VAL, QCH_CON_SWEEPER_P_APM_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CHUB_QCH, QCH_CON_SYSREG_CHUB_QCH_ENABLE, QCH_CON_SYSREG_CHUB_QCH_CLOCK_REQ, QCH_CON_SYSREG_CHUB_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TIMER_CHUB_QCH, QCH_CON_TIMER_CHUB_QCH_ENABLE, QCH_CON_TIMER_CHUB_QCH_CLOCK_REQ, QCH_CON_TIMER_CHUB_QCH_EXPIRE_VAL, QCH_CON_TIMER_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_CHUB00_QCH, QCH_CON_USI_CHUB00_QCH_ENABLE, QCH_CON_USI_CHUB00_QCH_CLOCK_REQ, QCH_CON_USI_CHUB00_QCH_EXPIRE_VAL, QCH_CON_USI_CHUB00_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_CHUB01_QCH, QCH_CON_USI_CHUB01_QCH_ENABLE, QCH_CON_USI_CHUB01_QCH_CLOCK_REQ, QCH_CON_USI_CHUB01_QCH_EXPIRE_VAL, QCH_CON_USI_CHUB01_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WDT_CHUB_QCH, QCH_CON_WDT_CHUB_QCH_ENABLE, QCH_CON_WDT_CHUB_QCH_CLOCK_REQ, QCH_CON_WDT_CHUB_QCH_EXPIRE_VAL, QCH_CON_WDT_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADC_CMGP_QCH_S0, QCH_CON_ADC_CMGP_QCH_S0_ENABLE, QCH_CON_ADC_CMGP_QCH_S0_CLOCK_REQ, QCH_CON_ADC_CMGP_QCH_S0_EXPIRE_VAL, QCH_CON_ADC_CMGP_QCH_S0_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADC_CMGP_QCH_S1, QCH_CON_ADC_CMGP_QCH_S1_ENABLE, QCH_CON_ADC_CMGP_QCH_S1_CLOCK_REQ, QCH_CON_ADC_CMGP_QCH_S1_EXPIRE_VAL, QCH_CON_ADC_CMGP_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADC_CMGP_QCH_ADC, DMYQCH_CON_ADC_CMGP_QCH_ADC_ENABLE, DMYQCH_CON_ADC_CMGP_QCH_ADC_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADC_CMGP_QCH_ADC_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMGP_CMU_CMGP_QCH, QCH_CON_CMGP_CMU_CMGP_QCH_ENABLE, QCH_CON_CMGP_CMU_CMGP_QCH_CLOCK_REQ, QCH_CON_CMGP_CMU_CMGP_QCH_EXPIRE_VAL, QCH_CON_CMGP_CMU_CMGP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPIO_CMGP_QCH, QCH_CON_GPIO_CMGP_QCH_ENABLE, QCH_CON_GPIO_CMGP_QCH_CLOCK_REQ, QCH_CON_GPIO_CMGP_QCH_EXPIRE_VAL, QCH_CON_GPIO_CMGP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_CMGP00_QCH, QCH_CON_I2C_CMGP00_QCH_ENABLE, QCH_CON_I2C_CMGP00_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP00_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP00_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_CMGP01_QCH, QCH_CON_I2C_CMGP01_QCH_ENABLE, QCH_CON_I2C_CMGP01_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP01_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP01_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_CMGP02_QCH, QCH_CON_I2C_CMGP02_QCH_ENABLE, QCH_CON_I2C_CMGP02_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP02_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP02_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_CMGP03_QCH, QCH_CON_I2C_CMGP03_QCH_ENABLE, QCH_CON_I2C_CMGP03_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP03_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP03_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_APM2CMGP_QCH, QCH_CON_LHM_AXI_P_APM2CMGP_QCH_ENABLE, QCH_CON_LHM_AXI_P_APM2CMGP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_APM2CMGP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_APM2CMGP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CMGP_QCH, QCH_CON_SYSREG_CMGP_QCH_ENABLE, QCH_CON_SYSREG_CMGP_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CMGP2CHUB_QCH, QCH_CON_SYSREG_CMGP2CHUB_QCH_ENABLE, QCH_CON_SYSREG_CMGP2CHUB_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2CHUB_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CMGP2CP_QCH, QCH_CON_SYSREG_CMGP2CP_QCH_ENABLE, QCH_CON_SYSREG_CMGP2CP_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2CP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CMGP2GNSS_QCH, QCH_CON_SYSREG_CMGP2GNSS_QCH_ENABLE, QCH_CON_SYSREG_CMGP2GNSS_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2GNSS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CMGP2PMU_AP_QCH, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_ENABLE, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CMGP2PMU_CHUB_QCH, QCH_CON_SYSREG_CMGP2PMU_CHUB_QCH_ENABLE, QCH_CON_SYSREG_CMGP2PMU_CHUB_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2PMU_CHUB_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2PMU_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_CMGP00_QCH, QCH_CON_USI_CMGP00_QCH_ENABLE, QCH_CON_USI_CMGP00_QCH_CLOCK_REQ, QCH_CON_USI_CMGP00_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP00_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_CMGP01_QCH, QCH_CON_USI_CMGP01_QCH_ENABLE, QCH_CON_USI_CMGP01_QCH_CLOCK_REQ, QCH_CON_USI_CMGP01_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP01_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_CMGP02_QCH, QCH_CON_USI_CMGP02_QCH_ENABLE, QCH_CON_USI_CMGP02_QCH_CLOCK_REQ, QCH_CON_USI_CMGP02_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP02_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_CMGP03_QCH, QCH_CON_USI_CMGP03_QCH_ENABLE, QCH_CON_USI_CMGP03_QCH_CLOCK_REQ, QCH_CON_USI_CMGP03_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP03_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_CMU_CMUREF_QCH, DMYQCH_CON_CMU_CMU_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CMU_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_CMU_CMUREF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DFTMUX_TOP_QCH_CIS_CLK0, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_IGNORE_FORCE_PM_EN),
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CLK_QCH(DFTMUX_TOP_QCH_CIS_CLK1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_IGNORE_FORCE_PM_EN),
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CLK_QCH(DFTMUX_TOP_QCH_CIS_CLK2, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_IGNORE_FORCE_PM_EN),
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CLK_QCH(DFTMUX_TOP_QCH_CIS_CLK3, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_IGNORE_FORCE_PM_EN),
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CLK_QCH(OTP_QCH, DMYQCH_CON_OTP_QCH_ENABLE, DMYQCH_CON_OTP_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_OTP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ACE_SLICE_G3D0_QCH, QCH_CON_ACE_SLICE_G3D0_QCH_ENABLE, QCH_CON_ACE_SLICE_G3D0_QCH_CLOCK_REQ, QCH_CON_ACE_SLICE_G3D0_QCH_EXPIRE_VAL, QCH_CON_ACE_SLICE_G3D0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ACE_SLICE_G3D1_QCH, QCH_CON_ACE_SLICE_G3D1_QCH_ENABLE, QCH_CON_ACE_SLICE_G3D1_QCH_CLOCK_REQ, QCH_CON_ACE_SLICE_G3D1_QCH_EXPIRE_VAL, QCH_CON_ACE_SLICE_G3D1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ACE_SLICE_G3D2_QCH, QCH_CON_ACE_SLICE_G3D2_QCH_ENABLE, QCH_CON_ACE_SLICE_G3D2_QCH_CLOCK_REQ, QCH_CON_ACE_SLICE_G3D2_QCH_EXPIRE_VAL, QCH_CON_ACE_SLICE_G3D2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ACE_SLICE_G3D3_QCH, QCH_CON_ACE_SLICE_G3D3_QCH_ENABLE, QCH_CON_ACE_SLICE_G3D3_QCH_CLOCK_REQ, QCH_CON_ACE_SLICE_G3D3_QCH_EXPIRE_VAL, QCH_CON_ACE_SLICE_G3D3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_CP_QCH, QCH_CON_BAAW_CP_QCH_ENABLE, QCH_CON_BAAW_CP_QCH_CLOCK_REQ, QCH_CON_BAAW_CP_QCH_EXPIRE_VAL, QCH_CON_BAAW_CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BDU_QCH, QCH_CON_BDU_QCH_ENABLE, QCH_CON_BDU_QCH_CLOCK_REQ, QCH_CON_BDU_QCH_EXPIRE_VAL, QCH_CON_BDU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_HPMCORE_QCH, QCH_CON_BUSIF_HPMCORE_QCH_ENABLE, QCH_CON_BUSIF_HPMCORE_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMCORE_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMCORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CCI_QCH, DMYQCH_CON_CCI_QCH_ENABLE, DMYQCH_CON_CCI_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CCI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CORE_CMU_CORE_QCH, QCH_CON_CORE_CMU_CORE_QCH_ENABLE, QCH_CON_CORE_CMU_CORE_QCH_CLOCK_REQ, QCH_CON_CORE_CMU_CORE_QCH_EXPIRE_VAL, QCH_CON_CORE_CMU_CORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACE_D0_G3D_QCH, QCH_CON_LHM_ACE_D0_G3D_QCH_ENABLE, QCH_CON_LHM_ACE_D0_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D0_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D0_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACE_D1_G3D_QCH, QCH_CON_LHM_ACE_D1_G3D_QCH_ENABLE, QCH_CON_LHM_ACE_D1_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D1_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D1_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACE_D2_G3D_QCH, QCH_CON_LHM_ACE_D2_G3D_QCH_ENABLE, QCH_CON_LHM_ACE_D2_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D2_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D2_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACE_D3_G3D_QCH, QCH_CON_LHM_ACE_D3_G3D_QCH_ENABLE, QCH_CON_LHM_ACE_D3_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D3_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D3_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACE_D_CPUCL0_QCH, QCH_CON_LHM_ACE_D_CPUCL0_QCH_ENABLE, QCH_CON_LHM_ACE_D_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_CP_QCH, QCH_CON_LHM_AXI_D_CP_QCH_ENABLE, QCH_CON_LHM_AXI_D_CP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_CP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_CLUSTER0_QCH, QCH_CON_LHM_AXI_P_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_AXI_P_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_T_BDU_QCH, QCH_CON_LHS_ATB_T_BDU_QCH_ENABLE, QCH_CON_LHS_ATB_T_BDU_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T_BDU_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_T_BDU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_APM_QCH, QCH_CON_LHS_AXI_P_APM_QCH_ENABLE, QCH_CON_LHS_AXI_P_APM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_APM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_CP_QCH, QCH_CON_LHS_AXI_P_CP_QCH_ENABLE, QCH_CON_LHS_AXI_P_CP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_CP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_CPUCL0_QCH, QCH_CON_LHS_AXI_P_CPUCL0_QCH_ENABLE, QCH_CON_LHS_AXI_P_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_CPUCL1_QCH, QCH_CON_LHS_AXI_P_CPUCL1_QCH_ENABLE, QCH_CON_LHS_AXI_P_CPUCL1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_CPUCL1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_G3D_QCH, QCH_CON_LHS_AXI_P_G3D_QCH_ENABLE, QCH_CON_LHS_AXI_P_G3D_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_G3D_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPCFW_G3D_QCH, QCH_CON_PPCFW_G3D_QCH_ENABLE, QCH_CON_PPCFW_G3D_QCH_CLOCK_REQ, QCH_CON_PPCFW_G3D_QCH_EXPIRE_VAL, QCH_CON_PPCFW_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPFW_DP_QCH, QCH_CON_PPFW_DP_QCH_ENABLE, QCH_CON_PPFW_DP_QCH_CLOCK_REQ, QCH_CON_PPFW_DP_QCH_EXPIRE_VAL, QCH_CON_PPFW_DP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPFW_G3D_QCH, QCH_CON_PPFW_G3D_QCH_ENABLE, QCH_CON_PPFW_G3D_QCH_CLOCK_REQ, QCH_CON_PPFW_G3D_QCH_EXPIRE_VAL, QCH_CON_PPFW_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPFW_IO_QCH, QCH_CON_PPFW_IO_QCH_ENABLE, QCH_CON_PPFW_IO_QCH_CLOCK_REQ, QCH_CON_PPFW_IO_QCH_EXPIRE_VAL, QCH_CON_PPFW_IO_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_CPUCL0_QCH, QCH_CON_PPMU_CPUCL0_QCH_ENABLE, QCH_CON_PPMU_CPUCL0_QCH_CLOCK_REQ, QCH_CON_PPMU_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_PPMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_CPUCL1_QCH, QCH_CON_PPMU_CPUCL1_QCH_ENABLE, QCH_CON_PPMU_CPUCL1_QCH_CLOCK_REQ, QCH_CON_PPMU_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_PPMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_G3D0_QCH, QCH_CON_PPMU_G3D0_QCH_ENABLE, QCH_CON_PPMU_G3D0_QCH_CLOCK_REQ, QCH_CON_PPMU_G3D0_QCH_EXPIRE_VAL, QCH_CON_PPMU_G3D0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_G3D1_QCH, QCH_CON_PPMU_G3D1_QCH_ENABLE, QCH_CON_PPMU_G3D1_QCH_CLOCK_REQ, QCH_CON_PPMU_G3D1_QCH_EXPIRE_VAL, QCH_CON_PPMU_G3D1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_G3D2_QCH, QCH_CON_PPMU_G3D2_QCH_ENABLE, QCH_CON_PPMU_G3D2_QCH_CLOCK_REQ, QCH_CON_PPMU_G3D2_QCH_EXPIRE_VAL, QCH_CON_PPMU_G3D2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_G3D3_QCH, QCH_CON_PPMU_G3D3_QCH_ENABLE, QCH_CON_PPMU_G3D3_QCH_CLOCK_REQ, QCH_CON_PPMU_G3D3_QCH_EXPIRE_VAL, QCH_CON_PPMU_G3D3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CORE_QCH, QCH_CON_SYSREG_CORE_QCH_ENABLE, QCH_CON_SYSREG_CORE_QCH_CLOCK_REQ, QCH_CON_SYSREG_CORE_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_D_CORE_QCH, QCH_CON_TREX_D_CORE_QCH_ENABLE, QCH_CON_TREX_D_CORE_QCH_CLOCK_REQ, QCH_CON_TREX_D_CORE_QCH_EXPIRE_VAL, QCH_CON_TREX_D_CORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_P0_CORE_QCH, QCH_CON_TREX_P0_CORE_QCH_ENABLE, QCH_CON_TREX_P0_CORE_QCH_CLOCK_REQ, QCH_CON_TREX_P0_CORE_QCH_EXPIRE_VAL, QCH_CON_TREX_P0_CORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_P1_CORE_QCH, QCH_CON_TREX_P1_CORE_QCH_ENABLE, QCH_CON_TREX_P1_CORE_QCH_CLOCK_REQ, QCH_CON_TREX_P1_CORE_QCH_EXPIRE_VAL, QCH_CON_TREX_P1_CORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADM_APB_G_CLUSTER0_QCH, DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH_ENABLE, DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_HPMCPUCL0_QCH, QCH_CON_BUSIF_HPMCPUCL0_QCH_ENABLE, QCH_CON_BUSIF_HPMCPUCL0_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMCPUCL0_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMCPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER0_QCH_SCLK, QCH_CON_CLUSTER0_QCH_SCLK_ENABLE, QCH_CON_CLUSTER0_QCH_SCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_SCLK_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_SCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER0_QCH_ATCLK, QCH_CON_CLUSTER0_QCH_ATCLK_ENABLE, QCH_CON_CLUSTER0_QCH_ATCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_ATCLK_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_ATCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER0_QCH_PDBGCLK, QCH_CON_CLUSTER0_QCH_PDBGCLK_ENABLE, QCH_CON_CLUSTER0_QCH_PDBGCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_PDBGCLK_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_PDBGCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER0_QCH_GIC, QCH_CON_CLUSTER0_QCH_GIC_ENABLE, QCH_CON_CLUSTER0_QCH_GIC_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_GIC_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_GIC_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER0_QCH_DBG_PD, QCH_CON_CLUSTER0_QCH_DBG_PD_ENABLE, QCH_CON_CLUSTER0_QCH_DBG_PD_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_DBG_PD_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_DBG_PD_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER0_QCH_PCLK, QCH_CON_CLUSTER0_QCH_PCLK_ENABLE, QCH_CON_CLUSTER0_QCH_PCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_PCLK_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER0_QCH_PERIPHCLK, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_ENABLE, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_CPUCL0_SHORTSTOP_QCH, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_EXPIRE_VAL, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CPUCL0_CMU_CPUCL0_QCH, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_ENABLE, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_CLOCK_REQ, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CSSYS_QCH, QCH_CON_CSSYS_QCH_ENABLE, QCH_CON_CSSYS_QCH_CLOCK_REQ, QCH_CON_CSSYS_QCH_EXPIRE_VAL, QCH_CON_CSSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DUMPPC_CLUSTER0_QCH, QCH_CON_DUMPPC_CLUSTER0_QCH_ENABLE, QCH_CON_DUMPPC_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_DUMPPC_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_DUMPPC_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DUMPPC_CLUSTER1_QCH, QCH_CON_DUMPPC_CLUSTER1_QCH_ENABLE, QCH_CON_DUMPPC_CLUSTER1_QCH_CLOCK_REQ, QCH_CON_DUMPPC_CLUSTER1_QCH_EXPIRE_VAL, QCH_CON_DUMPPC_CLUSTER1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_T0_CLUSTER0_QCH, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_T0_CLUSTER1_QCH, QCH_CON_LHM_ATB_T0_CLUSTER1_QCH_ENABLE, QCH_CON_LHM_ATB_T0_CLUSTER1_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T0_CLUSTER1_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T0_CLUSTER1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_T1_CLUSTER0_QCH, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_T1_CLUSTER1_QCH, QCH_CON_LHM_ATB_T1_CLUSTER1_QCH_ENABLE, QCH_CON_LHM_ATB_T1_CLUSTER1_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T1_CLUSTER1_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T1_CLUSTER1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_T2_CLUSTER0_QCH, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_T2_CLUSTER1_QCH, QCH_CON_LHM_ATB_T2_CLUSTER1_QCH_ENABLE, QCH_CON_LHM_ATB_T2_CLUSTER1_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T2_CLUSTER1_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T2_CLUSTER1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_T3_CLUSTER0_QCH, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_T3_CLUSTER1_QCH, QCH_CON_LHM_ATB_T3_CLUSTER1_QCH_ENABLE, QCH_CON_LHM_ATB_T3_CLUSTER1_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T3_CLUSTER1_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T3_CLUSTER1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_T_AUD_QCH, QCH_CON_LHM_ATB_T_AUD_QCH_ENABLE, QCH_CON_LHM_ATB_T_AUD_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T_AUD_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_T_BDU_QCH, QCH_CON_LHM_ATB_T_BDU_QCH_ENABLE, QCH_CON_LHM_ATB_T_BDU_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T_BDU_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T_BDU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_CPUCL0_QCH, QCH_CON_LHM_AXI_P_CPUCL0_QCH_ENABLE, QCH_CON_LHM_AXI_P_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_CSSYS_QCH, QCH_CON_LHM_AXI_P_CSSYS_QCH_ENABLE, QCH_CON_LHM_AXI_P_CSSYS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_CSSYS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_CSSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACE_D_CLUSTER0_QCH, QCH_CON_LHS_ACE_D_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_ACE_D_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_ACE_D_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_ACE_D_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_T0_CLUSTER0_QCH, QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_T1_CLUSTER0_QCH, QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_T2_CLUSTER0_QCH, QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_T3_CLUSTER0_QCH, QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_G_CSSYS_QCH, QCH_CON_LHS_AXI_G_CSSYS_QCH_ENABLE, QCH_CON_LHS_AXI_G_CSSYS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G_CSSYS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_G_ETR_QCH, QCH_CON_LHS_AXI_G_ETR_QCH_ENABLE, QCH_CON_LHS_AXI_G_ETR_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G_ETR_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_G_ETR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_CLUSTER0_QCH, QCH_CON_LHS_AXI_P_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_AXI_P_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SECJTAG_QCH, QCH_CON_SECJTAG_QCH_ENABLE, QCH_CON_SECJTAG_QCH_CLOCK_REQ, QCH_CON_SECJTAG_QCH_EXPIRE_VAL, QCH_CON_SECJTAG_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CPUCL0_QCH, QCH_CON_SYSREG_CPUCL0_QCH_ENABLE, QCH_CON_SYSREG_CPUCL0_QCH_CLOCK_REQ, QCH_CON_SYSREG_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_HPMCPUCL1_QCH, QCH_CON_BUSIF_HPMCPUCL1_QCH_ENABLE, QCH_CON_BUSIF_HPMCPUCL1_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMCPUCL1_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMCPUCL1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER1_QCH_CPU, DMYQCH_CON_CLUSTER1_QCH_CPU_ENABLE, DMYQCH_CON_CLUSTER1_QCH_CPU_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CLUSTER1_QCH_CPU_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1_ENABLE, QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1_CLOCK_REQ, QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1_EXPIRE_VAL, QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1_ENABLE, QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1_CLOCK_REQ, QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1_EXPIRE_VAL, QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1_ENABLE, QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1_CLOCK_REQ, QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1_EXPIRE_VAL, QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1_ENABLE, QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1_CLOCK_REQ, QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1_EXPIRE_VAL, QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER1_QCH_PCLKDBG, DMYQCH_CON_CLUSTER1_QCH_PCLKDBG_ENABLE, DMYQCH_CON_CLUSTER1_QCH_PCLKDBG_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CLUSTER1_QCH_PCLKDBG_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_CPUCL1_SHORTSTOP_QCH, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_EXPIRE_VAL, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CPUCL1_CMU_CPUCL1_QCH, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_ENABLE, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_CLOCK_REQ, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_CPUCL1_QCH, QCH_CON_LHM_AXI_P_CPUCL1_QCH_ENABLE, QCH_CON_LHM_AXI_P_CPUCL1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_CPUCL1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CPUCL1_QCH, QCH_CON_SYSREG_CPUCL1_QCH_ENABLE, QCH_CON_SYSREG_CPUCL1_QCH_CLOCK_REQ, QCH_CON_SYSREG_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CPUCL1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_DCF_QCH, QCH_CON_BTM_DCF_QCH_ENABLE, QCH_CON_BTM_DCF_QCH_CLOCK_REQ, QCH_CON_BTM_DCF_QCH_EXPIRE_VAL, QCH_CON_BTM_DCF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DCF_CMU_DCF_QCH, QCH_CON_DCF_CMU_DCF_QCH_ENABLE, QCH_CON_DCF_CMU_DCF_QCH_CLOCK_REQ, QCH_CON_DCF_CMU_DCF_QCH_EXPIRE_VAL, QCH_CON_DCF_CMU_DCF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_DCF_QCH_CIP, QCH_CON_IS_DCF_QCH_CIP_ENABLE, QCH_CON_IS_DCF_QCH_CIP_CLOCK_REQ, QCH_CON_IS_DCF_QCH_CIP_EXPIRE_VAL, QCH_CON_IS_DCF_QCH_CIP_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_DCF_QCH_QE, QCH_CON_IS_DCF_QCH_QE_ENABLE, QCH_CON_IS_DCF_QCH_QE_CLOCK_REQ, QCH_CON_IS_DCF_QCH_QE_EXPIRE_VAL, QCH_CON_IS_DCF_QCH_QE_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_DCF_QCH_SYSREG, QCH_CON_IS_DCF_QCH_SYSREG_ENABLE, QCH_CON_IS_DCF_QCH_SYSREG_CLOCK_REQ, QCH_CON_IS_DCF_QCH_SYSREG_EXPIRE_VAL, QCH_CON_IS_DCF_QCH_SYSREG_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_DCF_QCH_PPMU, QCH_CON_IS_DCF_QCH_PPMU_ENABLE, QCH_CON_IS_DCF_QCH_PPMU_CLOCK_REQ, QCH_CON_IS_DCF_QCH_PPMU_EXPIRE_VAL, QCH_CON_IS_DCF_QCH_PPMU_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_DCF_QCH_SYSMMU, QCH_CON_IS_DCF_QCH_SYSMMU_ENABLE, QCH_CON_IS_DCF_QCH_SYSMMU_CLOCK_REQ, QCH_CON_IS_DCF_QCH_SYSMMU_EXPIRE_VAL, QCH_CON_IS_DCF_QCH_SYSMMU_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_DCF_QCH_C2SYNC_2SLV, QCH_CON_IS_DCF_QCH_C2SYNC_2SLV_ENABLE, QCH_CON_IS_DCF_QCH_C2SYNC_2SLV_CLOCK_REQ, QCH_CON_IS_DCF_QCH_C2SYNC_2SLV_EXPIRE_VAL, QCH_CON_IS_DCF_QCH_C2SYNC_2SLV_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_DCF_QCH_PGEN_LITE, QCH_CON_IS_DCF_QCH_PGEN_LITE_ENABLE, QCH_CON_IS_DCF_QCH_PGEN_LITE_CLOCK_REQ, QCH_CON_IS_DCF_QCH_PGEN_LITE_EXPIRE_VAL, QCH_CON_IS_DCF_QCH_PGEN_LITE_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_DCPOSTDCF_QCH, QCH_CON_LHM_ATB_DCPOSTDCF_QCH_ENABLE, QCH_CON_LHM_ATB_DCPOSTDCF_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_DCPOSTDCF_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_DCPOSTDCF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_ISPHQDCF_QCH, QCH_CON_LHM_ATB_ISPHQDCF_QCH_ENABLE, QCH_CON_LHM_ATB_ISPHQDCF_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_ISPHQDCF_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_ISPHQDCF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_DCPOSTDCF_QCH, QCH_CON_LHM_AXI_D_DCPOSTDCF_QCH_ENABLE, QCH_CON_LHM_AXI_D_DCPOSTDCF_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_DCPOSTDCF_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_DCPOSTDCF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_DCF_QCH, QCH_CON_LHM_AXI_P_DCF_QCH_ENABLE, QCH_CON_LHM_AXI_P_DCF_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DCF_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_DCF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_DCFDCPOST_QCH, QCH_CON_LHS_ATB_DCFDCPOST_QCH_ENABLE, QCH_CON_LHS_ATB_DCFDCPOST_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_DCFDCPOST_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_DCFDCPOST_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_DCFISPLP_QCH, QCH_CON_LHS_ATB_DCFISPLP_QCH_ENABLE, QCH_CON_LHS_ATB_DCFISPLP_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_DCFISPLP_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_DCFISPLP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_DCF_QCH, QCH_CON_LHS_AXI_D_DCF_QCH_ENABLE, QCH_CON_LHS_AXI_D_DCF_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_DCF_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_DCF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_DCFDCPOST_QCH, QCH_CON_LHS_AXI_P_DCFDCPOST_QCH_ENABLE, QCH_CON_LHS_AXI_P_DCFDCPOST_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_DCFDCPOST_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_DCFDCPOST_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DCPOST_CMU_DCPOST_QCH, QCH_CON_DCPOST_CMU_DCPOST_QCH_ENABLE, QCH_CON_DCPOST_CMU_DCPOST_QCH_CLOCK_REQ, QCH_CON_DCPOST_CMU_DCPOST_QCH_EXPIRE_VAL, QCH_CON_DCPOST_CMU_DCPOST_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_DCPOST_QCH_SYSREG, QCH_CON_IS_DCPOST_QCH_SYSREG_ENABLE, QCH_CON_IS_DCPOST_QCH_SYSREG_CLOCK_REQ, QCH_CON_IS_DCPOST_QCH_SYSREG_EXPIRE_VAL, QCH_CON_IS_DCPOST_QCH_SYSREG_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_DCPOST_QCH_CIP2, QCH_CON_IS_DCPOST_QCH_CIP2_ENABLE, QCH_CON_IS_DCPOST_QCH_CIP2_CLOCK_REQ, QCH_CON_IS_DCPOST_QCH_CIP2_EXPIRE_VAL, QCH_CON_IS_DCPOST_QCH_CIP2_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_DCPOST_QCH_QE, QCH_CON_IS_DCPOST_QCH_QE_ENABLE, QCH_CON_IS_DCPOST_QCH_QE_CLOCK_REQ, QCH_CON_IS_DCPOST_QCH_QE_EXPIRE_VAL, QCH_CON_IS_DCPOST_QCH_QE_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_DCPOST_QCH_C2SYNC_1SLV_CLK, QCH_CON_IS_DCPOST_QCH_C2SYNC_1SLV_CLK_ENABLE, QCH_CON_IS_DCPOST_QCH_C2SYNC_1SLV_CLK_CLOCK_REQ, QCH_CON_IS_DCPOST_QCH_C2SYNC_1SLV_CLK_EXPIRE_VAL, QCH_CON_IS_DCPOST_QCH_C2SYNC_1SLV_CLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_DCFDCPOST_QCH, QCH_CON_LHM_ATB_DCFDCPOST_QCH_ENABLE, QCH_CON_LHM_ATB_DCFDCPOST_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_DCFDCPOST_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_DCFDCPOST_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_DCRDDCPOST_QCH, QCH_CON_LHM_ATB_DCRDDCPOST_QCH_ENABLE, QCH_CON_LHM_ATB_DCRDDCPOST_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_DCRDDCPOST_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_DCRDDCPOST_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_DCFDCPOST_QCH, QCH_CON_LHM_AXI_P_DCFDCPOST_QCH_ENABLE, QCH_CON_LHM_AXI_P_DCFDCPOST_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DCFDCPOST_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_DCFDCPOST_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_DCPOSTDCF_QCH, QCH_CON_LHS_ATB_DCPOSTDCF_QCH_ENABLE, QCH_CON_LHS_ATB_DCPOSTDCF_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_DCPOSTDCF_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_DCPOSTDCF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_DCPOSTDCRD_QCH, QCH_CON_LHS_ATB_DCPOSTDCRD_QCH_ENABLE, QCH_CON_LHS_ATB_DCPOSTDCRD_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_DCPOSTDCRD_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_DCPOSTDCRD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_DCPOSTDCF_QCH, QCH_CON_LHS_AXI_D_DCPOSTDCF_QCH_ENABLE, QCH_CON_LHS_AXI_D_DCPOSTDCF_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_DCPOSTDCF_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_DCPOSTDCF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_DCRD_QCH, QCH_CON_BTM_DCRD_QCH_ENABLE, QCH_CON_BTM_DCRD_QCH_CLOCK_REQ, QCH_CON_BTM_DCRD_QCH_EXPIRE_VAL, QCH_CON_BTM_DCRD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DCRD_CMU_DCRD_QCH, QCH_CON_DCRD_CMU_DCRD_QCH_ENABLE, QCH_CON_DCRD_CMU_DCRD_QCH_CLOCK_REQ, QCH_CON_DCRD_CMU_DCRD_QCH_EXPIRE_VAL, QCH_CON_DCRD_CMU_DCRD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_DCRD_QCH_DCP, QCH_CON_IS_DCRD_QCH_DCP_ENABLE, QCH_CON_IS_DCRD_QCH_DCP_CLOCK_REQ, QCH_CON_IS_DCRD_QCH_DCP_EXPIRE_VAL, QCH_CON_IS_DCRD_QCH_DCP_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_DCRD_QCH_PPMU, QCH_CON_IS_DCRD_QCH_PPMU_ENABLE, QCH_CON_IS_DCRD_QCH_PPMU_CLOCK_REQ, QCH_CON_IS_DCRD_QCH_PPMU_EXPIRE_VAL, QCH_CON_IS_DCRD_QCH_PPMU_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_DCRD_QCH_SYSMMU, QCH_CON_IS_DCRD_QCH_SYSMMU_ENABLE, QCH_CON_IS_DCRD_QCH_SYSMMU_CLOCK_REQ, QCH_CON_IS_DCRD_QCH_SYSMMU_EXPIRE_VAL, QCH_CON_IS_DCRD_QCH_SYSMMU_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_DCRD_QCH_SYSREG, QCH_CON_IS_DCRD_QCH_SYSREG_ENABLE, QCH_CON_IS_DCRD_QCH_SYSREG_CLOCK_REQ, QCH_CON_IS_DCRD_QCH_SYSREG_EXPIRE_VAL, QCH_CON_IS_DCRD_QCH_SYSREG_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_DCRD_QCH_PGEN_LITE, QCH_CON_IS_DCRD_QCH_PGEN_LITE_ENABLE, QCH_CON_IS_DCRD_QCH_PGEN_LITE_CLOCK_REQ, QCH_CON_IS_DCRD_QCH_PGEN_LITE_EXPIRE_VAL, QCH_CON_IS_DCRD_QCH_PGEN_LITE_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_DCRD_QCH_DCP_C2C, QCH_CON_IS_DCRD_QCH_DCP_C2C_ENABLE, QCH_CON_IS_DCRD_QCH_DCP_C2C_CLOCK_REQ, QCH_CON_IS_DCRD_QCH_DCP_C2C_EXPIRE_VAL, QCH_CON_IS_DCRD_QCH_DCP_C2C_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_DCRD_QCH_DCP_DIV2, QCH_CON_IS_DCRD_QCH_DCP_DIV2_ENABLE, QCH_CON_IS_DCRD_QCH_DCP_DIV2_CLOCK_REQ, QCH_CON_IS_DCRD_QCH_DCP_DIV2_EXPIRE_VAL, QCH_CON_IS_DCRD_QCH_DCP_DIV2_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_DCPOSTDCRD_QCH, QCH_CON_LHM_ATB_DCPOSTDCRD_QCH_ENABLE, QCH_CON_LHM_ATB_DCPOSTDCRD_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_DCPOSTDCRD_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_DCPOSTDCRD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_DCRD_QCH, QCH_CON_LHM_AXI_P_DCRD_QCH_ENABLE, QCH_CON_LHM_AXI_P_DCRD_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DCRD_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_DCRD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_DCRDDCPOST_QCH, QCH_CON_LHS_ATB_DCRDDCPOST_QCH_ENABLE, QCH_CON_LHS_ATB_DCRDDCPOST_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_DCRDDCPOST_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_DCRDDCPOST_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_DCRDISPLP_QCH, QCH_CON_LHS_ATB_DCRDISPLP_QCH_ENABLE, QCH_CON_LHS_ATB_DCRDISPLP_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_DCRDISPLP_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_DCRDISPLP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_DCRD_QCH, QCH_CON_LHS_AXI_D_DCRD_QCH_ENABLE, QCH_CON_LHS_AXI_D_DCRD_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_DCRD_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_DCRD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_DPUD0_QCH, QCH_CON_BTM_DPUD0_QCH_ENABLE, QCH_CON_BTM_DPUD0_QCH_CLOCK_REQ, QCH_CON_BTM_DPUD0_QCH_EXPIRE_VAL, QCH_CON_BTM_DPUD0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_DPUD1_QCH, QCH_CON_BTM_DPUD1_QCH_ENABLE, QCH_CON_BTM_DPUD1_QCH_CLOCK_REQ, QCH_CON_BTM_DPUD1_QCH_EXPIRE_VAL, QCH_CON_BTM_DPUD1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_DPUD2_QCH, QCH_CON_BTM_DPUD2_QCH_ENABLE, QCH_CON_BTM_DPUD2_QCH_CLOCK_REQ, QCH_CON_BTM_DPUD2_QCH_EXPIRE_VAL, QCH_CON_BTM_DPUD2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DPU_QCH_DPU, QCH_CON_DPU_QCH_DPU_ENABLE, QCH_CON_DPU_QCH_DPU_CLOCK_REQ, QCH_CON_DPU_QCH_DPU_EXPIRE_VAL, QCH_CON_DPU_QCH_DPU_IGNORE_FORCE_PM_EN),
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CLK_QCH(DPU_QCH_DPU_DMA, QCH_CON_DPU_QCH_DPU_DMA_ENABLE, QCH_CON_DPU_QCH_DPU_DMA_CLOCK_REQ, QCH_CON_DPU_QCH_DPU_DMA_EXPIRE_VAL, QCH_CON_DPU_QCH_DPU_DMA_IGNORE_FORCE_PM_EN),
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CLK_QCH(DPU_QCH_DPU_DPP, QCH_CON_DPU_QCH_DPU_DPP_ENABLE, QCH_CON_DPU_QCH_DPU_DPP_CLOCK_REQ, QCH_CON_DPU_QCH_DPU_DPP_EXPIRE_VAL, QCH_CON_DPU_QCH_DPU_DPP_IGNORE_FORCE_PM_EN),
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CLK_QCH(DPU_QCH_DPU_WB_MUX, QCH_CON_DPU_QCH_DPU_WB_MUX_ENABLE, QCH_CON_DPU_QCH_DPU_WB_MUX_CLOCK_REQ, QCH_CON_DPU_QCH_DPU_WB_MUX_EXPIRE_VAL, QCH_CON_DPU_QCH_DPU_WB_MUX_IGNORE_FORCE_PM_EN),
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CLK_QCH(DPU_CMU_DPU_QCH, QCH_CON_DPU_CMU_DPU_QCH_ENABLE, QCH_CON_DPU_CMU_DPU_QCH_CLOCK_REQ, QCH_CON_DPU_CMU_DPU_QCH_EXPIRE_VAL, QCH_CON_DPU_CMU_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_DPU_QCH, QCH_CON_LHM_AXI_P_DPU_QCH_ENABLE, QCH_CON_LHM_AXI_P_DPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DPU_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D0_DPU_QCH, QCH_CON_LHS_AXI_D0_DPU_QCH_ENABLE, QCH_CON_LHS_AXI_D0_DPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_DPU_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D1_DPU_QCH, QCH_CON_LHS_AXI_D1_DPU_QCH_ENABLE, QCH_CON_LHS_AXI_D1_DPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_DPU_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D2_DPU_QCH, QCH_CON_LHS_AXI_D2_DPU_QCH_ENABLE, QCH_CON_LHS_AXI_D2_DPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D2_DPU_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D2_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_DPUD0_QCH, QCH_CON_PPMU_DPUD0_QCH_ENABLE, QCH_CON_PPMU_DPUD0_QCH_CLOCK_REQ, QCH_CON_PPMU_DPUD0_QCH_EXPIRE_VAL, QCH_CON_PPMU_DPUD0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_DPUD1_QCH, QCH_CON_PPMU_DPUD1_QCH_ENABLE, QCH_CON_PPMU_DPUD1_QCH_CLOCK_REQ, QCH_CON_PPMU_DPUD1_QCH_EXPIRE_VAL, QCH_CON_PPMU_DPUD1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_DPUD2_QCH, QCH_CON_PPMU_DPUD2_QCH_ENABLE, QCH_CON_PPMU_DPUD2_QCH_CLOCK_REQ, QCH_CON_PPMU_DPUD2_QCH_EXPIRE_VAL, QCH_CON_PPMU_DPUD2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_DPUD0_QCH, QCH_CON_SYSMMU_DPUD0_QCH_ENABLE, QCH_CON_SYSMMU_DPUD0_QCH_CLOCK_REQ, QCH_CON_SYSMMU_DPUD0_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_DPUD0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_DPUD1_QCH, QCH_CON_SYSMMU_DPUD1_QCH_ENABLE, QCH_CON_SYSMMU_DPUD1_QCH_CLOCK_REQ, QCH_CON_SYSMMU_DPUD1_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_DPUD1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_DPUD2_QCH, QCH_CON_SYSMMU_DPUD2_QCH_ENABLE, QCH_CON_SYSMMU_DPUD2_QCH_CLOCK_REQ, QCH_CON_SYSMMU_DPUD2_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_DPUD2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_DPU_QCH, QCH_CON_SYSREG_DPU_QCH_ENABLE, QCH_CON_SYSREG_DPU_QCH_CLOCK_REQ, QCH_CON_SYSREG_DPU_QCH_EXPIRE_VAL, QCH_CON_SYSREG_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADM_APB_DSPM_QCH, DMYQCH_CON_ADM_APB_DSPM_QCH_ENABLE, DMYQCH_CON_ADM_APB_DSPM_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADM_APB_DSPM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_DSPM0_QCH, QCH_CON_BTM_DSPM0_QCH_ENABLE, QCH_CON_BTM_DSPM0_QCH_CLOCK_REQ, QCH_CON_BTM_DSPM0_QCH_EXPIRE_VAL, QCH_CON_BTM_DSPM0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_DSPM1_QCH, QCH_CON_BTM_DSPM1_QCH_ENABLE, QCH_CON_BTM_DSPM1_QCH_CLOCK_REQ, QCH_CON_BTM_DSPM1_QCH_EXPIRE_VAL, QCH_CON_BTM_DSPM1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DSPM_CMU_DSPM_QCH, QCH_CON_DSPM_CMU_DSPM_QCH_ENABLE, QCH_CON_DSPM_CMU_DSPM_QCH_CLOCK_REQ, QCH_CON_DSPM_CMU_DSPM_QCH_EXPIRE_VAL, QCH_CON_DSPM_CMU_DSPM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D0_DSPSDSPM_QCH, QCH_CON_LHM_AXI_D0_DSPSDSPM_QCH_ENABLE, QCH_CON_LHM_AXI_D0_DSPSDSPM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_DSPSDSPM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_DSPSDSPM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D1_DSPSDSPM_QCH, QCH_CON_LHM_AXI_D1_DSPSDSPM_QCH_ENABLE, QCH_CON_LHM_AXI_D1_DSPSDSPM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_DSPSDSPM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_DSPSDSPM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_DSPM_QCH, QCH_CON_LHM_AXI_P_DSPM_QCH_ENABLE, QCH_CON_LHM_AXI_P_DSPM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DSPM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_DSPM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_IVADSPM_QCH, QCH_CON_LHM_AXI_P_IVADSPM_QCH_ENABLE, QCH_CON_LHM_AXI_P_IVADSPM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_IVADSPM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_IVADSPM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D0_DSPM_QCH, QCH_CON_LHS_ACEL_D0_DSPM_QCH_ENABLE, QCH_CON_LHS_ACEL_D0_DSPM_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D0_DSPM_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D0_DSPM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D1_DSPM_QCH, QCH_CON_LHS_ACEL_D1_DSPM_QCH_ENABLE, QCH_CON_LHS_ACEL_D1_DSPM_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D1_DSPM_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D1_DSPM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D2_DSPM_QCH, QCH_CON_LHS_ACEL_D2_DSPM_QCH_ENABLE, QCH_CON_LHS_ACEL_D2_DSPM_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D2_DSPM_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D2_DSPM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_DSPMDSPS_QCH, QCH_CON_LHS_AXI_P_DSPMDSPS_QCH_ENABLE, QCH_CON_LHS_AXI_P_DSPMDSPS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_DSPMDSPS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_DSPMDSPS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_DSPMIVA_QCH, QCH_CON_LHS_AXI_P_DSPMIVA_QCH_ENABLE, QCH_CON_LHS_AXI_P_DSPMIVA_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_DSPMIVA_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_DSPMIVA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PGEN_LITE_DSPM_QCH, QCH_CON_PGEN_LITE_DSPM_QCH_ENABLE, QCH_CON_PGEN_LITE_DSPM_QCH_CLOCK_REQ, QCH_CON_PGEN_LITE_DSPM_QCH_EXPIRE_VAL, QCH_CON_PGEN_LITE_DSPM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_DSPM0_QCH, QCH_CON_PPMU_DSPM0_QCH_ENABLE, QCH_CON_PPMU_DSPM0_QCH_CLOCK_REQ, QCH_CON_PPMU_DSPM0_QCH_EXPIRE_VAL, QCH_CON_PPMU_DSPM0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_DSPM1_QCH, QCH_CON_PPMU_DSPM1_QCH_ENABLE, QCH_CON_PPMU_DSPM1_QCH_CLOCK_REQ, QCH_CON_PPMU_DSPM1_QCH_EXPIRE_VAL, QCH_CON_PPMU_DSPM1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SCORE_MASTER_QCH, QCH_CON_SCORE_MASTER_QCH_ENABLE, QCH_CON_SCORE_MASTER_QCH_CLOCK_REQ, QCH_CON_SCORE_MASTER_QCH_EXPIRE_VAL, QCH_CON_SCORE_MASTER_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_DSPM0_QCH, QCH_CON_SYSMMU_DSPM0_QCH_ENABLE, QCH_CON_SYSMMU_DSPM0_QCH_CLOCK_REQ, QCH_CON_SYSMMU_DSPM0_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_DSPM0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_DSPM1_QCH, QCH_CON_SYSMMU_DSPM1_QCH_ENABLE, QCH_CON_SYSMMU_DSPM1_QCH_CLOCK_REQ, QCH_CON_SYSMMU_DSPM1_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_DSPM1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_DSPM_QCH, QCH_CON_SYSREG_DSPM_QCH_ENABLE, QCH_CON_SYSREG_DSPM_QCH_CLOCK_REQ, QCH_CON_SYSREG_DSPM_QCH_EXPIRE_VAL, QCH_CON_SYSREG_DSPM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DSPS_CMU_DSPS_QCH, QCH_CON_DSPS_CMU_DSPS_QCH_ENABLE, QCH_CON_DSPS_CMU_DSPS_QCH_CLOCK_REQ, QCH_CON_DSPS_CMU_DSPS_QCH_EXPIRE_VAL, QCH_CON_DSPS_CMU_DSPS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_IVADSPS_QCH, QCH_CON_LHM_AXI_D_IVADSPS_QCH_ENABLE, QCH_CON_LHM_AXI_D_IVADSPS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_IVADSPS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_IVADSPS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_DSPMDSPS_QCH, QCH_CON_LHM_AXI_P_DSPMDSPS_QCH_ENABLE, QCH_CON_LHM_AXI_P_DSPMDSPS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DSPMDSPS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_DSPMDSPS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D0_DSPSDSPM_QCH, QCH_CON_LHS_AXI_D0_DSPSDSPM_QCH_ENABLE, QCH_CON_LHS_AXI_D0_DSPSDSPM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_DSPSDSPM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_DSPSDSPM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D1_DSPSDSPM_QCH, QCH_CON_LHS_AXI_D1_DSPSDSPM_QCH_ENABLE, QCH_CON_LHS_AXI_D1_DSPSDSPM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_DSPSDSPM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_DSPSDSPM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_DSPSIVA_QCH, QCH_CON_LHS_AXI_D_DSPSIVA_QCH_ENABLE, QCH_CON_LHS_AXI_D_DSPSIVA_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_DSPSIVA_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_DSPSIVA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SCORE_KNIGHT_QCH, QCH_CON_SCORE_KNIGHT_QCH_ENABLE, QCH_CON_SCORE_KNIGHT_QCH_CLOCK_REQ, QCH_CON_SCORE_KNIGHT_QCH_EXPIRE_VAL, QCH_CON_SCORE_KNIGHT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_DSPS_QCH, QCH_CON_SYSREG_DSPS_QCH_ENABLE, QCH_CON_SYSREG_DSPS_QCH_CLOCK_REQ, QCH_CON_SYSREG_DSPS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_DSPS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_FSYS0_QCH, QCH_CON_BTM_FSYS0_QCH_ENABLE, QCH_CON_BTM_FSYS0_QCH_CLOCK_REQ, QCH_CON_BTM_FSYS0_QCH_EXPIRE_VAL, QCH_CON_BTM_FSYS0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DP_LINK_QCH, QCH_CON_DP_LINK_QCH_ENABLE, QCH_CON_DP_LINK_QCH_CLOCK_REQ, QCH_CON_DP_LINK_QCH_EXPIRE_VAL, QCH_CON_DP_LINK_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DP_LINK_QCH_GTC, QCH_CON_DP_LINK_QCH_GTC_ENABLE, QCH_CON_DP_LINK_QCH_GTC_CLOCK_REQ, QCH_CON_DP_LINK_QCH_GTC_EXPIRE_VAL, QCH_CON_DP_LINK_QCH_GTC_IGNORE_FORCE_PM_EN),
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CLK_QCH(ETR_MIU_QCH_PCLK, QCH_CON_ETR_MIU_QCH_PCLK_ENABLE, QCH_CON_ETR_MIU_QCH_PCLK_CLOCK_REQ, QCH_CON_ETR_MIU_QCH_PCLK_EXPIRE_VAL, QCH_CON_ETR_MIU_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(ETR_MIU_QCH_ACLK, QCH_CON_ETR_MIU_QCH_ACLK_ENABLE, QCH_CON_ETR_MIU_QCH_ACLK_CLOCK_REQ, QCH_CON_ETR_MIU_QCH_ACLK_EXPIRE_VAL, QCH_CON_ETR_MIU_QCH_ACLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(FSYS0_CMU_FSYS0_QCH, QCH_CON_FSYS0_CMU_FSYS0_QCH_ENABLE, QCH_CON_FSYS0_CMU_FSYS0_QCH_CLOCK_REQ, QCH_CON_FSYS0_CMU_FSYS0_QCH_EXPIRE_VAL, QCH_CON_FSYS0_CMU_FSYS0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPIO_FSYS0_QCH, QCH_CON_GPIO_FSYS0_QCH_ENABLE, QCH_CON_GPIO_FSYS0_QCH_CLOCK_REQ, QCH_CON_GPIO_FSYS0_QCH_EXPIRE_VAL, QCH_CON_GPIO_FSYS0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_G_ETR_QCH, QCH_CON_LHM_AXI_G_ETR_QCH_ENABLE, QCH_CON_LHM_AXI_G_ETR_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_G_ETR_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_G_ETR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_FSYS0_QCH, QCH_CON_LHM_AXI_P_FSYS0_QCH_ENABLE, QCH_CON_LHM_AXI_P_FSYS0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_FSYS0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_FSYS0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D_FSYS0_QCH, QCH_CON_LHS_ACEL_D_FSYS0_QCH_ENABLE, QCH_CON_LHS_ACEL_D_FSYS0_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_FSYS0_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_FSYS0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PGEN_LITE_FSYS0_QCH, QCH_CON_PGEN_LITE_FSYS0_QCH_ENABLE, QCH_CON_PGEN_LITE_FSYS0_QCH_CLOCK_REQ, QCH_CON_PGEN_LITE_FSYS0_QCH_EXPIRE_VAL, QCH_CON_PGEN_LITE_FSYS0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_FSYS0_QCH, QCH_CON_PPMU_FSYS0_QCH_ENABLE, QCH_CON_PPMU_FSYS0_QCH_CLOCK_REQ, QCH_CON_PPMU_FSYS0_QCH_EXPIRE_VAL, QCH_CON_PPMU_FSYS0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_FSYS0_QCH, QCH_CON_SYSREG_FSYS0_QCH_ENABLE, QCH_CON_SYSREG_FSYS0_QCH_CLOCK_REQ, QCH_CON_SYSREG_FSYS0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_FSYS0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(UFS_EMBD_QCH, QCH_CON_UFS_EMBD_QCH_ENABLE, QCH_CON_UFS_EMBD_QCH_CLOCK_REQ, QCH_CON_UFS_EMBD_QCH_EXPIRE_VAL, QCH_CON_UFS_EMBD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(UFS_EMBD_QCH_FMP, QCH_CON_UFS_EMBD_QCH_FMP_ENABLE, QCH_CON_UFS_EMBD_QCH_FMP_CLOCK_REQ, QCH_CON_UFS_EMBD_QCH_FMP_EXPIRE_VAL, QCH_CON_UFS_EMBD_QCH_FMP_IGNORE_FORCE_PM_EN),
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CLK_QCH(USB30DRD_QCH_USB30DRD_LINK, QCH_CON_USB30DRD_QCH_USB30DRD_LINK_ENABLE, QCH_CON_USB30DRD_QCH_USB30DRD_LINK_CLOCK_REQ, QCH_CON_USB30DRD_QCH_USB30DRD_LINK_EXPIRE_VAL, QCH_CON_USB30DRD_QCH_USB30DRD_LINK_IGNORE_FORCE_PM_EN),
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CLK_QCH(USB30DRD_QCH_USBPCS, QCH_CON_USB30DRD_QCH_USBPCS_ENABLE, QCH_CON_USB30DRD_QCH_USBPCS_CLOCK_REQ, QCH_CON_USB30DRD_QCH_USBPCS_EXPIRE_VAL, QCH_CON_USB30DRD_QCH_USBPCS_IGNORE_FORCE_PM_EN),
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CLK_QCH(USB30DRD_QCH_USB30DRD_CTRL, QCH_CON_USB30DRD_QCH_USB30DRD_CTRL_ENABLE, QCH_CON_USB30DRD_QCH_USB30DRD_CTRL_CLOCK_REQ, QCH_CON_USB30DRD_QCH_USB30DRD_CTRL_EXPIRE_VAL, QCH_CON_USB30DRD_QCH_USB30DRD_CTRL_IGNORE_FORCE_PM_EN),
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CLK_QCH(USB30DRD_QCH_USBDPPHY, QCH_CON_USB30DRD_QCH_USBDPPHY_ENABLE, QCH_CON_USB30DRD_QCH_USBDPPHY_CLOCK_REQ, QCH_CON_USB30DRD_QCH_USBDPPHY_EXPIRE_VAL, QCH_CON_USB30DRD_QCH_USBDPPHY_IGNORE_FORCE_PM_EN),
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CLK_QCH(USB30DRD_QCH_SOC_PLL, DMYQCH_CON_USB30DRD_QCH_SOC_PLL_ENABLE, DMYQCH_CON_USB30DRD_QCH_SOC_PLL_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_USB30DRD_QCH_SOC_PLL_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADM_AHB_SSS_QCH, QCH_CON_ADM_AHB_SSS_QCH_ENABLE, QCH_CON_ADM_AHB_SSS_QCH_CLOCK_REQ, QCH_CON_ADM_AHB_SSS_QCH_EXPIRE_VAL, QCH_CON_ADM_AHB_SSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_FSYS1_QCH, QCH_CON_BTM_FSYS1_QCH_ENABLE, QCH_CON_BTM_FSYS1_QCH_CLOCK_REQ, QCH_CON_BTM_FSYS1_QCH_EXPIRE_VAL, QCH_CON_BTM_FSYS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(FSYS1_CMU_FSYS1_QCH, QCH_CON_FSYS1_CMU_FSYS1_QCH_ENABLE, QCH_CON_FSYS1_CMU_FSYS1_QCH_CLOCK_REQ, QCH_CON_FSYS1_CMU_FSYS1_QCH_EXPIRE_VAL, QCH_CON_FSYS1_CMU_FSYS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPIO_FSYS1_QCH, QCH_CON_GPIO_FSYS1_QCH_ENABLE, QCH_CON_GPIO_FSYS1_QCH_CLOCK_REQ, QCH_CON_GPIO_FSYS1_QCH_EXPIRE_VAL, QCH_CON_GPIO_FSYS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_FSYS1_QCH, QCH_CON_LHM_AXI_P_FSYS1_QCH_ENABLE, QCH_CON_LHM_AXI_P_FSYS1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_FSYS1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_FSYS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D_FSYS1_QCH, QCH_CON_LHS_ACEL_D_FSYS1_QCH_ENABLE, QCH_CON_LHS_ACEL_D_FSYS1_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_FSYS1_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_FSYS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MMC_CARD_QCH, QCH_CON_MMC_CARD_QCH_ENABLE, QCH_CON_MMC_CARD_QCH_CLOCK_REQ, QCH_CON_MMC_CARD_QCH_EXPIRE_VAL, QCH_CON_MMC_CARD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN2_QCH_MSTR, QCH_CON_PCIE_GEN2_QCH_MSTR_ENABLE, QCH_CON_PCIE_GEN2_QCH_MSTR_CLOCK_REQ, QCH_CON_PCIE_GEN2_QCH_MSTR_EXPIRE_VAL, QCH_CON_PCIE_GEN2_QCH_MSTR_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN2_QCH_PCS, QCH_CON_PCIE_GEN2_QCH_PCS_ENABLE, QCH_CON_PCIE_GEN2_QCH_PCS_CLOCK_REQ, QCH_CON_PCIE_GEN2_QCH_PCS_EXPIRE_VAL, QCH_CON_PCIE_GEN2_QCH_PCS_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN2_QCH_PHY, QCH_CON_PCIE_GEN2_QCH_PHY_ENABLE, QCH_CON_PCIE_GEN2_QCH_PHY_CLOCK_REQ, QCH_CON_PCIE_GEN2_QCH_PHY_EXPIRE_VAL, QCH_CON_PCIE_GEN2_QCH_PHY_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN2_QCH_DBI, QCH_CON_PCIE_GEN2_QCH_DBI_ENABLE, QCH_CON_PCIE_GEN2_QCH_DBI_CLOCK_REQ, QCH_CON_PCIE_GEN2_QCH_DBI_EXPIRE_VAL, QCH_CON_PCIE_GEN2_QCH_DBI_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN2_QCH_APB, QCH_CON_PCIE_GEN2_QCH_APB_ENABLE, QCH_CON_PCIE_GEN2_QCH_APB_CLOCK_REQ, QCH_CON_PCIE_GEN2_QCH_APB_EXPIRE_VAL, QCH_CON_PCIE_GEN2_QCH_APB_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN2_QCH_SOCPLL, DMYQCH_CON_PCIE_GEN2_QCH_SOCPLL_ENABLE, DMYQCH_CON_PCIE_GEN2_QCH_SOCPLL_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_PCIE_GEN2_QCH_SOCPLL_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN3_QCH_MSTR, QCH_CON_PCIE_GEN3_QCH_MSTR_ENABLE, QCH_CON_PCIE_GEN3_QCH_MSTR_CLOCK_REQ, QCH_CON_PCIE_GEN3_QCH_MSTR_EXPIRE_VAL, QCH_CON_PCIE_GEN3_QCH_MSTR_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN3_QCH_PCS, QCH_CON_PCIE_GEN3_QCH_PCS_ENABLE, QCH_CON_PCIE_GEN3_QCH_PCS_CLOCK_REQ, QCH_CON_PCIE_GEN3_QCH_PCS_EXPIRE_VAL, QCH_CON_PCIE_GEN3_QCH_PCS_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN3_QCH_DBI, QCH_CON_PCIE_GEN3_QCH_DBI_ENABLE, QCH_CON_PCIE_GEN3_QCH_DBI_CLOCK_REQ, QCH_CON_PCIE_GEN3_QCH_DBI_EXPIRE_VAL, QCH_CON_PCIE_GEN3_QCH_DBI_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN3_QCH_APB, QCH_CON_PCIE_GEN3_QCH_APB_ENABLE, QCH_CON_PCIE_GEN3_QCH_APB_CLOCK_REQ, QCH_CON_PCIE_GEN3_QCH_APB_EXPIRE_VAL, QCH_CON_PCIE_GEN3_QCH_APB_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN3_QCH_SOCPLL, DMYQCH_CON_PCIE_GEN3_QCH_SOCPLL_ENABLE, DMYQCH_CON_PCIE_GEN3_QCH_SOCPLL_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_PCIE_GEN3_QCH_SOCPLL_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_GEN3_QCH_PHY, QCH_CON_PCIE_GEN3_QCH_PHY_ENABLE, QCH_CON_PCIE_GEN3_QCH_PHY_CLOCK_REQ, QCH_CON_PCIE_GEN3_QCH_PHY_EXPIRE_VAL, QCH_CON_PCIE_GEN3_QCH_PHY_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_IA_GEN2_QCH, QCH_CON_PCIE_IA_GEN2_QCH_ENABLE, QCH_CON_PCIE_IA_GEN2_QCH_CLOCK_REQ, QCH_CON_PCIE_IA_GEN2_QCH_EXPIRE_VAL, QCH_CON_PCIE_IA_GEN2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PCIE_IA_GEN3_QCH, QCH_CON_PCIE_IA_GEN3_QCH_ENABLE, QCH_CON_PCIE_IA_GEN3_QCH_CLOCK_REQ, QCH_CON_PCIE_IA_GEN3_QCH_EXPIRE_VAL, QCH_CON_PCIE_IA_GEN3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PGEN_LITE_FSYS1_QCH, QCH_CON_PGEN_LITE_FSYS1_QCH_ENABLE, QCH_CON_PGEN_LITE_FSYS1_QCH_CLOCK_REQ, QCH_CON_PGEN_LITE_FSYS1_QCH_EXPIRE_VAL, QCH_CON_PGEN_LITE_FSYS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_FSYS1_QCH, QCH_CON_PPMU_FSYS1_QCH_ENABLE, QCH_CON_PPMU_FSYS1_QCH_CLOCK_REQ, QCH_CON_PPMU_FSYS1_QCH_EXPIRE_VAL, QCH_CON_PPMU_FSYS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RTIC_QCH, QCH_CON_RTIC_QCH_ENABLE, QCH_CON_RTIC_QCH_CLOCK_REQ, QCH_CON_RTIC_QCH_EXPIRE_VAL, QCH_CON_RTIC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SSS_QCH, QCH_CON_SSS_QCH_ENABLE, QCH_CON_SSS_QCH_CLOCK_REQ, QCH_CON_SSS_QCH_EXPIRE_VAL, QCH_CON_SSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_FSYS1_QCH, QCH_CON_SYSMMU_FSYS1_QCH_ENABLE, QCH_CON_SYSMMU_FSYS1_QCH_CLOCK_REQ, QCH_CON_SYSMMU_FSYS1_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_FSYS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_FSYS1_QCH, QCH_CON_SYSREG_FSYS1_QCH_ENABLE, QCH_CON_SYSREG_FSYS1_QCH_CLOCK_REQ, QCH_CON_SYSREG_FSYS1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_FSYS1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(UFS_CARD_QCH, QCH_CON_UFS_CARD_QCH_ENABLE, QCH_CON_UFS_CARD_QCH_CLOCK_REQ, QCH_CON_UFS_CARD_QCH_EXPIRE_VAL, QCH_CON_UFS_CARD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(UFS_CARD_QCH_FMP, QCH_CON_UFS_CARD_QCH_FMP_ENABLE, QCH_CON_UFS_CARD_QCH_FMP_CLOCK_REQ, QCH_CON_UFS_CARD_QCH_FMP_EXPIRE_VAL, QCH_CON_UFS_CARD_QCH_FMP_IGNORE_FORCE_PM_EN),
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CLK_QCH(ASTC_QCH, QCH_CON_ASTC_QCH_ENABLE, QCH_CON_ASTC_QCH_CLOCK_REQ, QCH_CON_ASTC_QCH_EXPIRE_VAL, QCH_CON_ASTC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_G2DD0_QCH, QCH_CON_BTM_G2DD0_QCH_ENABLE, QCH_CON_BTM_G2DD0_QCH_CLOCK_REQ, QCH_CON_BTM_G2DD0_QCH_EXPIRE_VAL, QCH_CON_BTM_G2DD0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_G2DD1_QCH, QCH_CON_BTM_G2DD1_QCH_ENABLE, QCH_CON_BTM_G2DD1_QCH_CLOCK_REQ, QCH_CON_BTM_G2DD1_QCH_EXPIRE_VAL, QCH_CON_BTM_G2DD1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_G2DD2_QCH, QCH_CON_BTM_G2DD2_QCH_ENABLE, QCH_CON_BTM_G2DD2_QCH_CLOCK_REQ, QCH_CON_BTM_G2DD2_QCH_EXPIRE_VAL, QCH_CON_BTM_G2DD2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(G2D_QCH, QCH_CON_G2D_QCH_ENABLE, QCH_CON_G2D_QCH_CLOCK_REQ, QCH_CON_G2D_QCH_EXPIRE_VAL, QCH_CON_G2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(G2D_CMU_G2D_QCH, QCH_CON_G2D_CMU_G2D_QCH_ENABLE, QCH_CON_G2D_CMU_G2D_QCH_CLOCK_REQ, QCH_CON_G2D_CMU_G2D_QCH_EXPIRE_VAL, QCH_CON_G2D_CMU_G2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(JPEG_QCH, QCH_CON_JPEG_QCH_ENABLE, QCH_CON_JPEG_QCH_CLOCK_REQ, QCH_CON_JPEG_QCH_EXPIRE_VAL, QCH_CON_JPEG_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_G2D_QCH, QCH_CON_LHM_AXI_P_G2D_QCH_ENABLE, QCH_CON_LHM_AXI_P_G2D_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_G2D_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_G2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D0_G2D_QCH, QCH_CON_LHS_ACEL_D0_G2D_QCH_ENABLE, QCH_CON_LHS_ACEL_D0_G2D_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D0_G2D_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D0_G2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D1_G2D_QCH, QCH_CON_LHS_ACEL_D1_G2D_QCH_ENABLE, QCH_CON_LHS_ACEL_D1_G2D_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D1_G2D_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D1_G2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D2_G2D_QCH, QCH_CON_LHS_ACEL_D2_G2D_QCH_ENABLE, QCH_CON_LHS_ACEL_D2_G2D_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D2_G2D_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D2_G2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MSCL_QCH, QCH_CON_MSCL_QCH_ENABLE, QCH_CON_MSCL_QCH_CLOCK_REQ, QCH_CON_MSCL_QCH_EXPIRE_VAL, QCH_CON_MSCL_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PGEN100_LITE_G2D_QCH, QCH_CON_PGEN100_LITE_G2D_QCH_ENABLE, QCH_CON_PGEN100_LITE_G2D_QCH_CLOCK_REQ, QCH_CON_PGEN100_LITE_G2D_QCH_EXPIRE_VAL, QCH_CON_PGEN100_LITE_G2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_G2DD0_QCH, QCH_CON_PPMU_G2DD0_QCH_ENABLE, QCH_CON_PPMU_G2DD0_QCH_CLOCK_REQ, QCH_CON_PPMU_G2DD0_QCH_EXPIRE_VAL, QCH_CON_PPMU_G2DD0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_G2DD1_QCH, QCH_CON_PPMU_G2DD1_QCH_ENABLE, QCH_CON_PPMU_G2DD1_QCH_CLOCK_REQ, QCH_CON_PPMU_G2DD1_QCH_EXPIRE_VAL, QCH_CON_PPMU_G2DD1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_G2DD2_QCH, QCH_CON_PPMU_G2DD2_QCH_ENABLE, QCH_CON_PPMU_G2DD2_QCH_CLOCK_REQ, QCH_CON_PPMU_G2DD2_QCH_EXPIRE_VAL, QCH_CON_PPMU_G2DD2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_ASTC_QCH, QCH_CON_QE_ASTC_QCH_ENABLE, QCH_CON_QE_ASTC_QCH_CLOCK_REQ, QCH_CON_QE_ASTC_QCH_EXPIRE_VAL, QCH_CON_QE_ASTC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_JPEG_QCH, QCH_CON_QE_JPEG_QCH_ENABLE, QCH_CON_QE_JPEG_QCH_CLOCK_REQ, QCH_CON_QE_JPEG_QCH_EXPIRE_VAL, QCH_CON_QE_JPEG_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_MSCL_QCH, QCH_CON_QE_MSCL_QCH_ENABLE, QCH_CON_QE_MSCL_QCH_CLOCK_REQ, QCH_CON_QE_MSCL_QCH_EXPIRE_VAL, QCH_CON_QE_MSCL_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_G2DD0_QCH, QCH_CON_SYSMMU_G2DD0_QCH_ENABLE, QCH_CON_SYSMMU_G2DD0_QCH_CLOCK_REQ, QCH_CON_SYSMMU_G2DD0_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_G2DD0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_G2DD1_QCH, QCH_CON_SYSMMU_G2DD1_QCH_ENABLE, QCH_CON_SYSMMU_G2DD1_QCH_CLOCK_REQ, QCH_CON_SYSMMU_G2DD1_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_G2DD1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_G2DD2_QCH, QCH_CON_SYSMMU_G2DD2_QCH_ENABLE, QCH_CON_SYSMMU_G2DD2_QCH_CLOCK_REQ, QCH_CON_SYSMMU_G2DD2_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_G2DD2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_G2D_QCH, QCH_CON_SYSREG_G2D_QCH_ENABLE, QCH_CON_SYSREG_G2D_QCH_CLOCK_REQ, QCH_CON_SYSREG_G2D_QCH_EXPIRE_VAL, QCH_CON_SYSREG_G2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_HPMG3D_QCH, QCH_CON_BUSIF_HPMG3D_QCH_ENABLE, QCH_CON_BUSIF_HPMG3D_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMG3D_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMG3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(G3D_CMU_G3D_QCH, QCH_CON_G3D_CMU_G3D_QCH_ENABLE, QCH_CON_G3D_CMU_G3D_QCH_CLOCK_REQ, QCH_CON_G3D_CMU_G3D_QCH_EXPIRE_VAL, QCH_CON_G3D_CMU_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPU_QCH, QCH_CON_GPU_QCH_ENABLE, QCH_CON_GPU_QCH_CLOCK_REQ, QCH_CON_GPU_QCH_EXPIRE_VAL, QCH_CON_GPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_G3DSFR_QCH, QCH_CON_LHM_AXI_G3DSFR_QCH_ENABLE, QCH_CON_LHM_AXI_G3DSFR_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_G3DSFR_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_G3DSFR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_G3D_QCH, QCH_CON_LHM_AXI_P_G3D_QCH_ENABLE, QCH_CON_LHM_AXI_P_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACE_D0_G3D_QCH, QCH_CON_LHS_ACE_D0_G3D_QCH_ENABLE, QCH_CON_LHS_ACE_D0_G3D_QCH_CLOCK_REQ, QCH_CON_LHS_ACE_D0_G3D_QCH_EXPIRE_VAL, QCH_CON_LHS_ACE_D0_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACE_D1_G3D_QCH, QCH_CON_LHS_ACE_D1_G3D_QCH_ENABLE, QCH_CON_LHS_ACE_D1_G3D_QCH_CLOCK_REQ, QCH_CON_LHS_ACE_D1_G3D_QCH_EXPIRE_VAL, QCH_CON_LHS_ACE_D1_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACE_D2_G3D_QCH, QCH_CON_LHS_ACE_D2_G3D_QCH_ENABLE, QCH_CON_LHS_ACE_D2_G3D_QCH_CLOCK_REQ, QCH_CON_LHS_ACE_D2_G3D_QCH_EXPIRE_VAL, QCH_CON_LHS_ACE_D2_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACE_D3_G3D_QCH, QCH_CON_LHS_ACE_D3_G3D_QCH_ENABLE, QCH_CON_LHS_ACE_D3_G3D_QCH_CLOCK_REQ, QCH_CON_LHS_ACE_D3_G3D_QCH_EXPIRE_VAL, QCH_CON_LHS_ACE_D3_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_G3DSFR_QCH, QCH_CON_LHS_AXI_G3DSFR_QCH_ENABLE, QCH_CON_LHS_AXI_G3DSFR_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G3DSFR_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_G3DSFR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PGEN_LITE_G3D_QCH, QCH_CON_PGEN_LITE_G3D_QCH_ENABLE, QCH_CON_PGEN_LITE_G3D_QCH_CLOCK_REQ, QCH_CON_PGEN_LITE_G3D_QCH_EXPIRE_VAL, QCH_CON_PGEN_LITE_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_G3D_QCH, QCH_CON_SYSREG_G3D_QCH_ENABLE, QCH_CON_SYSREG_G3D_QCH_CLOCK_REQ, QCH_CON_SYSREG_G3D_QCH_EXPIRE_VAL, QCH_CON_SYSREG_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_ISPHQ_QCH, QCH_CON_BTM_ISPHQ_QCH_ENABLE, QCH_CON_BTM_ISPHQ_QCH_CLOCK_REQ, QCH_CON_BTM_ISPHQ_QCH_EXPIRE_VAL, QCH_CON_BTM_ISPHQ_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ISPHQ_CMU_ISPHQ_QCH, QCH_CON_ISPHQ_CMU_ISPHQ_QCH_ENABLE, QCH_CON_ISPHQ_CMU_ISPHQ_QCH_CLOCK_REQ, QCH_CON_ISPHQ_CMU_ISPHQ_QCH_EXPIRE_VAL, QCH_CON_ISPHQ_CMU_ISPHQ_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPHQ_QCH_ISPHQ, QCH_CON_IS_ISPHQ_QCH_ISPHQ_ENABLE, QCH_CON_IS_ISPHQ_QCH_ISPHQ_CLOCK_REQ, QCH_CON_IS_ISPHQ_QCH_ISPHQ_EXPIRE_VAL, QCH_CON_IS_ISPHQ_QCH_ISPHQ_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPHQ_QCH_SYSMMU_ISPHQ, QCH_CON_IS_ISPHQ_QCH_SYSMMU_ISPHQ_ENABLE, QCH_CON_IS_ISPHQ_QCH_SYSMMU_ISPHQ_CLOCK_REQ, QCH_CON_IS_ISPHQ_QCH_SYSMMU_ISPHQ_EXPIRE_VAL, QCH_CON_IS_ISPHQ_QCH_SYSMMU_ISPHQ_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPHQ_QCH_PPMU_ISPHQ, QCH_CON_IS_ISPHQ_QCH_PPMU_ISPHQ_ENABLE, QCH_CON_IS_ISPHQ_QCH_PPMU_ISPHQ_CLOCK_REQ, QCH_CON_IS_ISPHQ_QCH_PPMU_ISPHQ_EXPIRE_VAL, QCH_CON_IS_ISPHQ_QCH_PPMU_ISPHQ_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPHQ_QCH_PGEN_LITE_ISPHQ, QCH_CON_IS_ISPHQ_QCH_PGEN_LITE_ISPHQ_ENABLE, QCH_CON_IS_ISPHQ_QCH_PGEN_LITE_ISPHQ_CLOCK_REQ, QCH_CON_IS_ISPHQ_QCH_PGEN_LITE_ISPHQ_EXPIRE_VAL, QCH_CON_IS_ISPHQ_QCH_PGEN_LITE_ISPHQ_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPHQ_QCH_ISPHQ_C2COM, QCH_CON_IS_ISPHQ_QCH_ISPHQ_C2COM_ENABLE, QCH_CON_IS_ISPHQ_QCH_ISPHQ_C2COM_CLOCK_REQ, QCH_CON_IS_ISPHQ_QCH_ISPHQ_C2COM_EXPIRE_VAL, QCH_CON_IS_ISPHQ_QCH_ISPHQ_C2COM_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_ISPLPISPHQ_QCH, QCH_CON_LHM_ATB_ISPLPISPHQ_QCH_ENABLE, QCH_CON_LHM_ATB_ISPLPISPHQ_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_ISPLPISPHQ_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_ISPLPISPHQ_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_ISPPREISPHQ_QCH, QCH_CON_LHM_ATB_ISPPREISPHQ_QCH_ENABLE, QCH_CON_LHM_ATB_ISPPREISPHQ_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_ISPPREISPHQ_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_ISPPREISPHQ_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_ISPHQ_QCH, QCH_CON_LHM_AXI_P_ISPHQ_QCH_ENABLE, QCH_CON_LHM_AXI_P_ISPHQ_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_ISPHQ_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_ISPHQ_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_ISPHQDCF_QCH, QCH_CON_LHS_ATB_ISPHQDCF_QCH_ENABLE, QCH_CON_LHS_ATB_ISPHQDCF_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_ISPHQDCF_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_ISPHQDCF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_ISPHQISPLP_QCH, QCH_CON_LHS_ATB_ISPHQISPLP_QCH_ENABLE, QCH_CON_LHS_ATB_ISPHQISPLP_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_ISPHQISPLP_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_ISPHQISPLP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_ISPHQ_QCH, QCH_CON_LHS_AXI_D_ISPHQ_QCH_ENABLE, QCH_CON_LHS_AXI_D_ISPHQ_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_ISPHQ_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_ISPHQ_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_ISPHQ_QCH, QCH_CON_SYSREG_ISPHQ_QCH_ENABLE, QCH_CON_SYSREG_ISPHQ_QCH_CLOCK_REQ, QCH_CON_SYSREG_ISPHQ_QCH_EXPIRE_VAL, QCH_CON_SYSREG_ISPHQ_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_ISPLP0_QCH, QCH_CON_BTM_ISPLP0_QCH_ENABLE, QCH_CON_BTM_ISPLP0_QCH_CLOCK_REQ, QCH_CON_BTM_ISPLP0_QCH_EXPIRE_VAL, QCH_CON_BTM_ISPLP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_ISPLP1_QCH, QCH_CON_BTM_ISPLP1_QCH_ENABLE, QCH_CON_BTM_ISPLP1_QCH_CLOCK_REQ, QCH_CON_BTM_ISPLP1_QCH_EXPIRE_VAL, QCH_CON_BTM_ISPLP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ISPLP_CMU_ISPLP_QCH, QCH_CON_ISPLP_CMU_ISPLP_QCH_ENABLE, QCH_CON_ISPLP_CMU_ISPLP_QCH_CLOCK_REQ, QCH_CON_ISPLP_CMU_ISPLP_QCH_EXPIRE_VAL, QCH_CON_ISPLP_CMU_ISPLP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPLP_QCH_MC_SCALER, QCH_CON_IS_ISPLP_QCH_MC_SCALER_ENABLE, QCH_CON_IS_ISPLP_QCH_MC_SCALER_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_MC_SCALER_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_MC_SCALER_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPLP_QCH_ISPLP, QCH_CON_IS_ISPLP_QCH_ISPLP_ENABLE, QCH_CON_IS_ISPLP_QCH_ISPLP_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_ISPLP_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_ISPLP_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPLP_QCH_QE_ISPLP, QCH_CON_IS_ISPLP_QCH_QE_ISPLP_ENABLE, QCH_CON_IS_ISPLP_QCH_QE_ISPLP_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_QE_ISPLP_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_QE_ISPLP_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPLP_QCH_SYSMMU_ISPLP0, QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP0_ENABLE, QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP0_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP0_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP0_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPLP_QCH_PPMU_ISPLP0, QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP0_ENABLE, QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP0_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP0_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP0_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPLP_QCH_SYSMMU_ISPLP1, QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP1_ENABLE, QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP1_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP1_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP1_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPLP_QCH_PPMU_ISPLP1, QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP1_ENABLE, QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP1_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP1_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP1_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPLP_QCH_QE_VRA, QCH_CON_IS_ISPLP_QCH_QE_VRA_ENABLE, QCH_CON_IS_ISPLP_QCH_QE_VRA_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_QE_VRA_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_QE_VRA_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPLP_QCH_VRA, QCH_CON_IS_ISPLP_QCH_VRA_ENABLE, QCH_CON_IS_ISPLP_QCH_VRA_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_VRA_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_VRA_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPLP_QCH_GDC, QCH_CON_IS_ISPLP_QCH_GDC_ENABLE, QCH_CON_IS_ISPLP_QCH_GDC_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_GDC_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_GDC_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPLP_QCH_PGEN_LITE, QCH_CON_IS_ISPLP_QCH_PGEN_LITE_ENABLE, QCH_CON_IS_ISPLP_QCH_PGEN_LITE_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_PGEN_LITE_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_PGEN_LITE_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPLP_QCH_QE_GDC, QCH_CON_IS_ISPLP_QCH_QE_GDC_ENABLE, QCH_CON_IS_ISPLP_QCH_QE_GDC_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_QE_GDC_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_QE_GDC_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPLP_QCH_ISPLP_C2, QCH_CON_IS_ISPLP_QCH_ISPLP_C2_ENABLE, QCH_CON_IS_ISPLP_QCH_ISPLP_C2_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_ISPLP_C2_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_ISPLP_C2_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_DCFISPLP_QCH, QCH_CON_LHM_ATB_DCFISPLP_QCH_ENABLE, QCH_CON_LHM_ATB_DCFISPLP_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_DCFISPLP_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_DCFISPLP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_DCRDISPLP_QCH, QCH_CON_LHM_ATB_DCRDISPLP_QCH_ENABLE, QCH_CON_LHM_ATB_DCRDISPLP_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_DCRDISPLP_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_DCRDISPLP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_ISPHQISPLP_QCH, QCH_CON_LHM_ATB_ISPHQISPLP_QCH_ENABLE, QCH_CON_LHM_ATB_ISPHQISPLP_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_ISPHQISPLP_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_ISPHQISPLP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_ISPPREISPLP_QCH, QCH_CON_LHM_ATB_ISPPREISPLP_QCH_ENABLE, QCH_CON_LHM_ATB_ISPPREISPLP_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_ISPPREISPLP_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_ISPPREISPLP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_ISPLP_QCH, QCH_CON_LHM_AXI_P_ISPLP_QCH_ENABLE, QCH_CON_LHM_AXI_P_ISPLP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_ISPLP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_ISPLP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_ISPLPISPHQ_QCH, QCH_CON_LHS_ATB_ISPLPISPHQ_QCH_ENABLE, QCH_CON_LHS_ATB_ISPLPISPHQ_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_ISPLPISPHQ_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_ISPLPISPHQ_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D0_ISPLP_QCH, QCH_CON_LHS_AXI_D0_ISPLP_QCH_ENABLE, QCH_CON_LHS_AXI_D0_ISPLP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_ISPLP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_ISPLP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D1_ISPLP_QCH, QCH_CON_LHS_AXI_D1_ISPLP_QCH_ENABLE, QCH_CON_LHS_AXI_D1_ISPLP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_ISPLP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_ISPLP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_ISPLP_QCH, QCH_CON_SYSREG_ISPLP_QCH_ENABLE, QCH_CON_SYSREG_ISPLP_QCH_CLOCK_REQ, QCH_CON_SYSREG_ISPLP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_ISPLP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_ISPPRE_QCH, QCH_CON_BTM_ISPPRE_QCH_ENABLE, QCH_CON_BTM_ISPPRE_QCH_CLOCK_REQ, QCH_CON_BTM_ISPPRE_QCH_EXPIRE_VAL, QCH_CON_BTM_ISPPRE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ISPPRE_CMU_ISPPRE_QCH, QCH_CON_ISPPRE_CMU_ISPPRE_QCH_ENABLE, QCH_CON_ISPPRE_CMU_ISPPRE_QCH_CLOCK_REQ, QCH_CON_ISPPRE_CMU_ISPPRE_QCH_EXPIRE_VAL, QCH_CON_ISPPRE_CMU_ISPPRE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPPRE_QCH_CSIS0, QCH_CON_IS_ISPPRE_QCH_CSIS0_ENABLE, QCH_CON_IS_ISPPRE_QCH_CSIS0_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_CSIS0_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_CSIS0_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPPRE_QCH_CSIS1, QCH_CON_IS_ISPPRE_QCH_CSIS1_ENABLE, QCH_CON_IS_ISPPRE_QCH_CSIS1_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_CSIS1_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_CSIS1_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPPRE_QCH_CSIS2, QCH_CON_IS_ISPPRE_QCH_CSIS2_ENABLE, QCH_CON_IS_ISPPRE_QCH_CSIS2_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_CSIS2_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_CSIS2_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPPRE_QCH_CSIS3, QCH_CON_IS_ISPPRE_QCH_CSIS3_ENABLE, QCH_CON_IS_ISPPRE_QCH_CSIS3_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_CSIS3_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_CSIS3_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPPRE_QCH_PPMU_ISPPRE, QCH_CON_IS_ISPPRE_QCH_PPMU_ISPPRE_ENABLE, QCH_CON_IS_ISPPRE_QCH_PPMU_ISPPRE_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_PPMU_ISPPRE_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_PPMU_ISPPRE_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPPRE_QCH_PDP_DMA, QCH_CON_IS_ISPPRE_QCH_PDP_DMA_ENABLE, QCH_CON_IS_ISPPRE_QCH_PDP_DMA_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_PDP_DMA_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_PDP_DMA_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPPRE_QCH_SYSMMU_ISPPRE, QCH_CON_IS_ISPPRE_QCH_SYSMMU_ISPPRE_ENABLE, QCH_CON_IS_ISPPRE_QCH_SYSMMU_ISPPRE_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_SYSMMU_ISPPRE_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_SYSMMU_ISPPRE_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPPRE_QCH_QE_PDP, QCH_CON_IS_ISPPRE_QCH_QE_PDP_ENABLE, QCH_CON_IS_ISPPRE_QCH_QE_PDP_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_QE_PDP_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_QE_PDP_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPPRE_QCH_QE_3AA, QCH_CON_IS_ISPPRE_QCH_QE_3AA_ENABLE, QCH_CON_IS_ISPPRE_QCH_QE_3AA_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_QE_3AA_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_QE_3AA_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPPRE_QCH_QE_3AAM, QCH_CON_IS_ISPPRE_QCH_QE_3AAM_ENABLE, QCH_CON_IS_ISPPRE_QCH_QE_3AAM_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_QE_3AAM_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_QE_3AAM_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPPRE_QCH_3AA, QCH_CON_IS_ISPPRE_QCH_3AA_ENABLE, QCH_CON_IS_ISPPRE_QCH_3AA_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_3AA_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_3AA_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPPRE_QCH_3AAM, QCH_CON_IS_ISPPRE_QCH_3AAM_ENABLE, QCH_CON_IS_ISPPRE_QCH_3AAM_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_3AAM_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_3AAM_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPPRE_QCH_PDP_CORE0, QCH_CON_IS_ISPPRE_QCH_PDP_CORE0_ENABLE, QCH_CON_IS_ISPPRE_QCH_PDP_CORE0_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_PDP_CORE0_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_PDP_CORE0_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPPRE_QCH_PDP_CORE1, QCH_CON_IS_ISPPRE_QCH_PDP_CORE1_ENABLE, QCH_CON_IS_ISPPRE_QCH_PDP_CORE1_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_PDP_CORE1_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_PDP_CORE1_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPPRE_QCH_PGEN_LITE, QCH_CON_IS_ISPPRE_QCH_PGEN_LITE_ENABLE, QCH_CON_IS_ISPPRE_QCH_PGEN_LITE_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_PGEN_LITE_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_PGEN_LITE_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPPRE_QCH_QE_PDP_STAT, QCH_CON_IS_ISPPRE_QCH_QE_PDP_STAT_ENABLE, QCH_CON_IS_ISPPRE_QCH_QE_PDP_STAT_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_QE_PDP_STAT_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_QE_PDP_STAT_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS_ISPPRE_QCH_PGEN_LITE1, QCH_CON_IS_ISPPRE_QCH_PGEN_LITE1_ENABLE, QCH_CON_IS_ISPPRE_QCH_PGEN_LITE1_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_PGEN_LITE1_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_PGEN_LITE1_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_ISPPRE_QCH, QCH_CON_LHM_AXI_P_ISPPRE_QCH_ENABLE, QCH_CON_LHM_AXI_P_ISPPRE_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_ISPPRE_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_ISPPRE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_ISPPREISPHQ_QCH, QCH_CON_LHS_ATB_ISPPREISPHQ_QCH_ENABLE, QCH_CON_LHS_ATB_ISPPREISPHQ_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_ISPPREISPHQ_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_ISPPREISPHQ_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_ISPPREISPLP_QCH, QCH_CON_LHS_ATB_ISPPREISPLP_QCH_ENABLE, QCH_CON_LHS_ATB_ISPPREISPLP_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_ISPPREISPLP_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_ISPPREISPLP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_ISPPRE_QCH, QCH_CON_LHS_AXI_D_ISPPRE_QCH_ENABLE, QCH_CON_LHS_AXI_D_ISPPRE_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_ISPPRE_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_ISPPRE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_ISPPRE_QCH_SYSREG, QCH_CON_SYSREG_ISPPRE_QCH_SYSREG_ENABLE, QCH_CON_SYSREG_ISPPRE_QCH_SYSREG_CLOCK_REQ, QCH_CON_SYSREG_ISPPRE_QCH_SYSREG_EXPIRE_VAL, QCH_CON_SYSREG_ISPPRE_QCH_SYSREG_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADM_DAP_IVA_QCH, DMYQCH_CON_ADM_DAP_IVA_QCH_ENABLE, DMYQCH_CON_ADM_DAP_IVA_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADM_DAP_IVA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_IVA_QCH, QCH_CON_BTM_IVA_QCH_ENABLE, QCH_CON_BTM_IVA_QCH_CLOCK_REQ, QCH_CON_BTM_IVA_QCH_EXPIRE_VAL, QCH_CON_BTM_IVA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(IVA_QCH_IVA, QCH_CON_IVA_QCH_IVA_ENABLE, QCH_CON_IVA_QCH_IVA_CLOCK_REQ, QCH_CON_IVA_QCH_IVA_EXPIRE_VAL, QCH_CON_IVA_QCH_IVA_IGNORE_FORCE_PM_EN),
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CLK_QCH(IVA_QCH_IVA_DEBUG, QCH_CON_IVA_QCH_IVA_DEBUG_ENABLE, QCH_CON_IVA_QCH_IVA_DEBUG_CLOCK_REQ, QCH_CON_IVA_QCH_IVA_DEBUG_EXPIRE_VAL, QCH_CON_IVA_QCH_IVA_DEBUG_IGNORE_FORCE_PM_EN),
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CLK_QCH(IVA_CMU_IVA_QCH, QCH_CON_IVA_CMU_IVA_QCH_ENABLE, QCH_CON_IVA_CMU_IVA_QCH_CLOCK_REQ, QCH_CON_IVA_CMU_IVA_QCH_EXPIRE_VAL, QCH_CON_IVA_CMU_IVA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(IVA_INTMEM_QCH, QCH_CON_IVA_INTMEM_QCH_ENABLE, QCH_CON_IVA_INTMEM_QCH_CLOCK_REQ, QCH_CON_IVA_INTMEM_QCH_EXPIRE_VAL, QCH_CON_IVA_INTMEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_DSPSIVA_QCH, QCH_CON_LHM_AXI_D_DSPSIVA_QCH_ENABLE, QCH_CON_LHM_AXI_D_DSPSIVA_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_DSPSIVA_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_DSPSIVA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_IVASC_QCH, QCH_CON_LHM_AXI_D_IVASC_QCH_ENABLE, QCH_CON_LHM_AXI_D_IVASC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_IVASC_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_IVASC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_DSPMIVA_QCH, QCH_CON_LHM_AXI_P_DSPMIVA_QCH_ENABLE, QCH_CON_LHM_AXI_P_DSPMIVA_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DSPMIVA_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_DSPMIVA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_IVA_QCH, QCH_CON_LHM_AXI_P_IVA_QCH_ENABLE, QCH_CON_LHM_AXI_P_IVA_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_IVA_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_IVA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D_IVA_QCH, QCH_CON_LHS_ACEL_D_IVA_QCH_ENABLE, QCH_CON_LHS_ACEL_D_IVA_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_IVA_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_IVA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_IVADSPS_QCH, QCH_CON_LHS_AXI_D_IVADSPS_QCH_ENABLE, QCH_CON_LHS_AXI_D_IVADSPS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_IVADSPS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_IVADSPS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_IVADSPM_QCH, QCH_CON_LHS_AXI_P_IVADSPM_QCH_ENABLE, QCH_CON_LHS_AXI_P_IVADSPM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_IVADSPM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_IVADSPM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PGEN_LITE_IVA_QCH, QCH_CON_PGEN_LITE_IVA_QCH_ENABLE, QCH_CON_PGEN_LITE_IVA_QCH_CLOCK_REQ, QCH_CON_PGEN_LITE_IVA_QCH_EXPIRE_VAL, QCH_CON_PGEN_LITE_IVA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_IVA_QCH, QCH_CON_PPMU_IVA_QCH_ENABLE, QCH_CON_PPMU_IVA_QCH_CLOCK_REQ, QCH_CON_PPMU_IVA_QCH_EXPIRE_VAL, QCH_CON_PPMU_IVA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_IVA_QCH, QCH_CON_SYSMMU_IVA_QCH_ENABLE, QCH_CON_SYSMMU_IVA_QCH_CLOCK_REQ, QCH_CON_SYSMMU_IVA_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_IVA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_IVA_QCH, QCH_CON_SYSREG_IVA_QCH_ENABLE, QCH_CON_SYSREG_IVA_QCH_CLOCK_REQ, QCH_CON_SYSREG_IVA_QCH_EXPIRE_VAL, QCH_CON_SYSREG_IVA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_RB_IVA_QCH, QCH_CON_TREX_RB_IVA_QCH_ENABLE, QCH_CON_TREX_RB_IVA_QCH_CLOCK_REQ, QCH_CON_TREX_RB_IVA_QCH_EXPIRE_VAL, QCH_CON_TREX_RB_IVA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_MFCD0_QCH, QCH_CON_BTM_MFCD0_QCH_ENABLE, QCH_CON_BTM_MFCD0_QCH_CLOCK_REQ, QCH_CON_BTM_MFCD0_QCH_EXPIRE_VAL, QCH_CON_BTM_MFCD0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_MFCD1_QCH, QCH_CON_BTM_MFCD1_QCH_ENABLE, QCH_CON_BTM_MFCD1_QCH_CLOCK_REQ, QCH_CON_BTM_MFCD1_QCH_EXPIRE_VAL, QCH_CON_BTM_MFCD1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_MFC_QCH, QCH_CON_LHM_AXI_P_MFC_QCH_ENABLE, QCH_CON_LHM_AXI_P_MFC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MFC_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D0_MFC_QCH, QCH_CON_LHS_AXI_D0_MFC_QCH_ENABLE, QCH_CON_LHS_AXI_D0_MFC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_MFC_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D1_MFC_QCH, QCH_CON_LHS_AXI_D1_MFC_QCH_ENABLE, QCH_CON_LHS_AXI_D1_MFC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_MFC_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_ATB_QCH_MI, QCH_CON_LH_ATB_QCH_MI_ENABLE, QCH_CON_LH_ATB_QCH_MI_CLOCK_REQ, QCH_CON_LH_ATB_QCH_MI_EXPIRE_VAL, QCH_CON_LH_ATB_QCH_MI_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_ATB_QCH_SI, QCH_CON_LH_ATB_QCH_SI_ENABLE, QCH_CON_LH_ATB_QCH_SI_CLOCK_REQ, QCH_CON_LH_ATB_QCH_SI_EXPIRE_VAL, QCH_CON_LH_ATB_QCH_SI_IGNORE_FORCE_PM_EN),
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CLK_QCH(MFC_QCH, QCH_CON_MFC_QCH_ENABLE, QCH_CON_MFC_QCH_CLOCK_REQ, QCH_CON_MFC_QCH_EXPIRE_VAL, QCH_CON_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MFC_CMU_MFC_QCH, QCH_CON_MFC_CMU_MFC_QCH_ENABLE, QCH_CON_MFC_CMU_MFC_QCH_CLOCK_REQ, QCH_CON_MFC_CMU_MFC_QCH_EXPIRE_VAL, QCH_CON_MFC_CMU_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PGEN100_LITE_MFC_QCH, QCH_CON_PGEN100_LITE_MFC_QCH_ENABLE, QCH_CON_PGEN100_LITE_MFC_QCH_CLOCK_REQ, QCH_CON_PGEN100_LITE_MFC_QCH_EXPIRE_VAL, QCH_CON_PGEN100_LITE_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_MFCD0_QCH, QCH_CON_PPMU_MFCD0_QCH_ENABLE, QCH_CON_PPMU_MFCD0_QCH_CLOCK_REQ, QCH_CON_PPMU_MFCD0_QCH_EXPIRE_VAL, QCH_CON_PPMU_MFCD0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_MFCD1_QCH, QCH_CON_PPMU_MFCD1_QCH_ENABLE, QCH_CON_PPMU_MFCD1_QCH_CLOCK_REQ, QCH_CON_PPMU_MFCD1_QCH_EXPIRE_VAL, QCH_CON_PPMU_MFCD1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_MFCD2_QCH, QCH_CON_PPMU_MFCD2_QCH_ENABLE, QCH_CON_PPMU_MFCD2_QCH_CLOCK_REQ, QCH_CON_PPMU_MFCD2_QCH_EXPIRE_VAL, QCH_CON_PPMU_MFCD2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MI_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MI_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MI_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MI_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MI_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC_BUSD_LH_ATB_SI_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_SI_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_SI_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_SI_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_SI_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_MFCD0_QCH, QCH_CON_SYSMMU_MFCD0_QCH_ENABLE, QCH_CON_SYSMMU_MFCD0_QCH_CLOCK_REQ, QCH_CON_SYSMMU_MFCD0_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_MFCD0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_MFCD1_QCH, QCH_CON_SYSMMU_MFCD1_QCH_ENABLE, QCH_CON_SYSMMU_MFCD1_QCH_CLOCK_REQ, QCH_CON_SYSMMU_MFCD1_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_MFCD1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_MFC_QCH, QCH_CON_SYSREG_MFC_QCH_ENABLE, QCH_CON_SYSREG_MFC_QCH_CLOCK_REQ, QCH_CON_SYSREG_MFC_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WFD_QCH, QCH_CON_WFD_QCH_ENABLE, QCH_CON_WFD_QCH_CLOCK_REQ, QCH_CON_WFD_QCH_EXPIRE_VAL, QCH_CON_WFD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBBR_DDRPHY_QCH, QCH_CON_APBBR_DDRPHY_QCH_ENABLE, QCH_CON_APBBR_DDRPHY_QCH_CLOCK_REQ, QCH_CON_APBBR_DDRPHY_QCH_EXPIRE_VAL, QCH_CON_APBBR_DDRPHY_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBBR_DMC_QCH, QCH_CON_APBBR_DMC_QCH_ENABLE, QCH_CON_APBBR_DMC_QCH_CLOCK_REQ, QCH_CON_APBBR_DMC_QCH_EXPIRE_VAL, QCH_CON_APBBR_DMC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBBR_DMCTZ_QCH, QCH_CON_APBBR_DMCTZ_QCH_ENABLE, QCH_CON_APBBR_DMCTZ_QCH_CLOCK_REQ, QCH_CON_APBBR_DMCTZ_QCH_EXPIRE_VAL, QCH_CON_APBBR_DMCTZ_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_HPMMIF_QCH, QCH_CON_BUSIF_HPMMIF_QCH_ENABLE, QCH_CON_BUSIF_HPMMIF_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMMIF_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMMIF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_MIF_CMUREF_QCH, DMYQCH_CON_CMU_MIF_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_MIF_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_MIF_CMUREF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMC_QCH, QCH_CON_DMC_QCH_ENABLE, QCH_CON_DMC_QCH_CLOCK_REQ, QCH_CON_DMC_QCH_EXPIRE_VAL, QCH_CON_DMC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_MIF_QCH, QCH_CON_LHM_AXI_P_MIF_QCH_ENABLE, QCH_CON_LHM_AXI_P_MIF_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MIF_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_MIF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MIF_CMU_MIF_QCH, QCH_CON_MIF_CMU_MIF_QCH_ENABLE, QCH_CON_MIF_CMU_MIF_QCH_CLOCK_REQ, QCH_CON_MIF_CMU_MIF_QCH_EXPIRE_VAL, QCH_CON_MIF_CMU_MIF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QCH_ADAPTER_PPMUPPC_DEBUG_QCH, QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG_QCH_ENABLE, QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG_QCH_CLOCK_REQ, QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG_QCH_EXPIRE_VAL, QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QCH_ADAPTER_PPMUPPC_DVFS_QCH, QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS_QCH_ENABLE, QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS_QCH_CLOCK_REQ, QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS_QCH_EXPIRE_VAL, QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_MIF_QCH, QCH_CON_SYSREG_MIF_QCH_ENABLE, QCH_CON_SYSREG_MIF_QCH_CLOCK_REQ, QCH_CON_SYSREG_MIF_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MIF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPIO_PERIC0_QCH, QCH_CON_GPIO_PERIC0_QCH_ENABLE, QCH_CON_GPIO_PERIC0_QCH_CLOCK_REQ, QCH_CON_GPIO_PERIC0_QCH_EXPIRE_VAL, QCH_CON_GPIO_PERIC0_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(LHM_AXI_P_PERIC0_QCH, QCH_CON_LHM_AXI_P_PERIC0_QCH_ENABLE, QCH_CON_LHM_AXI_P_PERIC0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_PERIC0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(PERIC0_CMU_PERIC0_QCH, QCH_CON_PERIC0_CMU_PERIC0_QCH_ENABLE, QCH_CON_PERIC0_CMU_PERIC0_QCH_CLOCK_REQ, QCH_CON_PERIC0_CMU_PERIC0_QCH_EXPIRE_VAL, QCH_CON_PERIC0_CMU_PERIC0_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(PWM_QCH, QCH_CON_PWM_QCH_ENABLE, QCH_CON_PWM_QCH_CLOCK_REQ, QCH_CON_PWM_QCH_EXPIRE_VAL, QCH_CON_PWM_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(SYSREG_PERIC0_QCH, QCH_CON_SYSREG_PERIC0_QCH_ENABLE, QCH_CON_SYSREG_PERIC0_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERIC0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_PERIC0_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(UART_DBG_QCH, QCH_CON_UART_DBG_QCH_ENABLE, QCH_CON_UART_DBG_QCH_CLOCK_REQ, QCH_CON_UART_DBG_QCH_EXPIRE_VAL, QCH_CON_UART_DBG_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(USI00_I2C_QCH, QCH_CON_USI00_I2C_QCH_ENABLE, QCH_CON_USI00_I2C_QCH_CLOCK_REQ, QCH_CON_USI00_I2C_QCH_EXPIRE_VAL, QCH_CON_USI00_I2C_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(USI00_USI_QCH, QCH_CON_USI00_USI_QCH_ENABLE, QCH_CON_USI00_USI_QCH_CLOCK_REQ, QCH_CON_USI00_USI_QCH_EXPIRE_VAL, QCH_CON_USI00_USI_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(USI01_I2C_QCH, QCH_CON_USI01_I2C_QCH_ENABLE, QCH_CON_USI01_I2C_QCH_CLOCK_REQ, QCH_CON_USI01_I2C_QCH_EXPIRE_VAL, QCH_CON_USI01_I2C_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(USI01_USI_QCH, QCH_CON_USI01_USI_QCH_ENABLE, QCH_CON_USI01_USI_QCH_CLOCK_REQ, QCH_CON_USI01_USI_QCH_EXPIRE_VAL, QCH_CON_USI01_USI_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(USI02_I2C_QCH, QCH_CON_USI02_I2C_QCH_ENABLE, QCH_CON_USI02_I2C_QCH_CLOCK_REQ, QCH_CON_USI02_I2C_QCH_EXPIRE_VAL, QCH_CON_USI02_I2C_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(USI02_USI_QCH, QCH_CON_USI02_USI_QCH_ENABLE, QCH_CON_USI02_USI_QCH_CLOCK_REQ, QCH_CON_USI02_USI_QCH_EXPIRE_VAL, QCH_CON_USI02_USI_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(USI03_I2C_QCH, QCH_CON_USI03_I2C_QCH_ENABLE, QCH_CON_USI03_I2C_QCH_CLOCK_REQ, QCH_CON_USI03_I2C_QCH_EXPIRE_VAL, QCH_CON_USI03_I2C_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(USI03_USI_QCH, QCH_CON_USI03_USI_QCH_ENABLE, QCH_CON_USI03_USI_QCH_CLOCK_REQ, QCH_CON_USI03_USI_QCH_EXPIRE_VAL, QCH_CON_USI03_USI_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(USI04_I2C_QCH, QCH_CON_USI04_I2C_QCH_ENABLE, QCH_CON_USI04_I2C_QCH_CLOCK_REQ, QCH_CON_USI04_I2C_QCH_EXPIRE_VAL, QCH_CON_USI04_I2C_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(USI04_USI_QCH, QCH_CON_USI04_USI_QCH_ENABLE, QCH_CON_USI04_USI_QCH_CLOCK_REQ, QCH_CON_USI04_USI_QCH_EXPIRE_VAL, QCH_CON_USI04_USI_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(USI05_I2C_QCH, QCH_CON_USI05_I2C_QCH_ENABLE, QCH_CON_USI05_I2C_QCH_CLOCK_REQ, QCH_CON_USI05_I2C_QCH_EXPIRE_VAL, QCH_CON_USI05_I2C_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(USI05_USI_QCH, QCH_CON_USI05_USI_QCH_ENABLE, QCH_CON_USI05_USI_QCH_CLOCK_REQ, QCH_CON_USI05_USI_QCH_EXPIRE_VAL, QCH_CON_USI05_USI_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(USI12_I2C_QCH, QCH_CON_USI12_I2C_QCH_ENABLE, QCH_CON_USI12_I2C_QCH_CLOCK_REQ, QCH_CON_USI12_I2C_QCH_EXPIRE_VAL, QCH_CON_USI12_I2C_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(USI12_USI_QCH, QCH_CON_USI12_USI_QCH_ENABLE, QCH_CON_USI12_USI_QCH_CLOCK_REQ, QCH_CON_USI12_USI_QCH_EXPIRE_VAL, QCH_CON_USI12_USI_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(USI13_I2C_QCH, QCH_CON_USI13_I2C_QCH_ENABLE, QCH_CON_USI13_I2C_QCH_CLOCK_REQ, QCH_CON_USI13_I2C_QCH_EXPIRE_VAL, QCH_CON_USI13_I2C_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(USI13_USI_QCH, QCH_CON_USI13_USI_QCH_ENABLE, QCH_CON_USI13_USI_QCH_CLOCK_REQ, QCH_CON_USI13_USI_QCH_EXPIRE_VAL, QCH_CON_USI13_USI_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(USI14_I2C_QCH, QCH_CON_USI14_I2C_QCH_ENABLE, QCH_CON_USI14_I2C_QCH_CLOCK_REQ, QCH_CON_USI14_I2C_QCH_EXPIRE_VAL, QCH_CON_USI14_I2C_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(USI14_USI_QCH, QCH_CON_USI14_USI_QCH_ENABLE, QCH_CON_USI14_USI_QCH_CLOCK_REQ, QCH_CON_USI14_USI_QCH_EXPIRE_VAL, QCH_CON_USI14_USI_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(GPIO_PERIC1_QCH, QCH_CON_GPIO_PERIC1_QCH_ENABLE, QCH_CON_GPIO_PERIC1_QCH_CLOCK_REQ, QCH_CON_GPIO_PERIC1_QCH_EXPIRE_VAL, QCH_CON_GPIO_PERIC1_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(I2C_CAM0_QCH, QCH_CON_I2C_CAM0_QCH_ENABLE, QCH_CON_I2C_CAM0_QCH_CLOCK_REQ, QCH_CON_I2C_CAM0_QCH_EXPIRE_VAL, QCH_CON_I2C_CAM0_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(I2C_CAM1_QCH, QCH_CON_I2C_CAM1_QCH_ENABLE, QCH_CON_I2C_CAM1_QCH_CLOCK_REQ, QCH_CON_I2C_CAM1_QCH_EXPIRE_VAL, QCH_CON_I2C_CAM1_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(I2C_CAM2_QCH, QCH_CON_I2C_CAM2_QCH_ENABLE, QCH_CON_I2C_CAM2_QCH_CLOCK_REQ, QCH_CON_I2C_CAM2_QCH_EXPIRE_VAL, QCH_CON_I2C_CAM2_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(I2C_CAM3_QCH, QCH_CON_I2C_CAM3_QCH_ENABLE, QCH_CON_I2C_CAM3_QCH_CLOCK_REQ, QCH_CON_I2C_CAM3_QCH_EXPIRE_VAL, QCH_CON_I2C_CAM3_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(LHM_AXI_P_PERIC1_QCH, QCH_CON_LHM_AXI_P_PERIC1_QCH_ENABLE, QCH_CON_LHM_AXI_P_PERIC1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_PERIC1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(PERIC1_CMU_PERIC1_QCH, QCH_CON_PERIC1_CMU_PERIC1_QCH_ENABLE, QCH_CON_PERIC1_CMU_PERIC1_QCH_CLOCK_REQ, QCH_CON_PERIC1_CMU_PERIC1_QCH_EXPIRE_VAL, QCH_CON_PERIC1_CMU_PERIC1_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(SPI_CAM0_QCH, QCH_CON_SPI_CAM0_QCH_ENABLE, QCH_CON_SPI_CAM0_QCH_CLOCK_REQ, QCH_CON_SPI_CAM0_QCH_EXPIRE_VAL, QCH_CON_SPI_CAM0_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(SYSREG_PERIC1_QCH, QCH_CON_SYSREG_PERIC1_QCH_ENABLE, QCH_CON_SYSREG_PERIC1_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERIC1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_PERIC1_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(UART_BT_QCH, QCH_CON_UART_BT_QCH_ENABLE, QCH_CON_UART_BT_QCH_CLOCK_REQ, QCH_CON_UART_BT_QCH_EXPIRE_VAL, QCH_CON_UART_BT_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(USI06_I2C_QCH, QCH_CON_USI06_I2C_QCH_ENABLE, QCH_CON_USI06_I2C_QCH_CLOCK_REQ, QCH_CON_USI06_I2C_QCH_EXPIRE_VAL, QCH_CON_USI06_I2C_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI06_USI_QCH, QCH_CON_USI06_USI_QCH_ENABLE, QCH_CON_USI06_USI_QCH_CLOCK_REQ, QCH_CON_USI06_USI_QCH_EXPIRE_VAL, QCH_CON_USI06_USI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI07_I2C_QCH, QCH_CON_USI07_I2C_QCH_ENABLE, QCH_CON_USI07_I2C_QCH_CLOCK_REQ, QCH_CON_USI07_I2C_QCH_EXPIRE_VAL, QCH_CON_USI07_I2C_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI07_USI_QCH, QCH_CON_USI07_USI_QCH_ENABLE, QCH_CON_USI07_USI_QCH_CLOCK_REQ, QCH_CON_USI07_USI_QCH_EXPIRE_VAL, QCH_CON_USI07_USI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI08_I2C_QCH, QCH_CON_USI08_I2C_QCH_ENABLE, QCH_CON_USI08_I2C_QCH_CLOCK_REQ, QCH_CON_USI08_I2C_QCH_EXPIRE_VAL, QCH_CON_USI08_I2C_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI08_USI_QCH, QCH_CON_USI08_USI_QCH_ENABLE, QCH_CON_USI08_USI_QCH_CLOCK_REQ, QCH_CON_USI08_USI_QCH_EXPIRE_VAL, QCH_CON_USI08_USI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI09_I2C_QCH, QCH_CON_USI09_I2C_QCH_ENABLE, QCH_CON_USI09_I2C_QCH_CLOCK_REQ, QCH_CON_USI09_I2C_QCH_EXPIRE_VAL, QCH_CON_USI09_I2C_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI09_USI_QCH, QCH_CON_USI09_USI_QCH_ENABLE, QCH_CON_USI09_USI_QCH_CLOCK_REQ, QCH_CON_USI09_USI_QCH_EXPIRE_VAL, QCH_CON_USI09_USI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI10_I2C_QCH, QCH_CON_USI10_I2C_QCH_ENABLE, QCH_CON_USI10_I2C_QCH_CLOCK_REQ, QCH_CON_USI10_I2C_QCH_EXPIRE_VAL, QCH_CON_USI10_I2C_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI10_USI_QCH, QCH_CON_USI10_USI_QCH_ENABLE, QCH_CON_USI10_USI_QCH_CLOCK_REQ, QCH_CON_USI10_USI_QCH_EXPIRE_VAL, QCH_CON_USI10_USI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI11_I2C_QCH, QCH_CON_USI11_I2C_QCH_ENABLE, QCH_CON_USI11_I2C_QCH_CLOCK_REQ, QCH_CON_USI11_I2C_QCH_EXPIRE_VAL, QCH_CON_USI11_I2C_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI11_USI_QCH, QCH_CON_USI11_USI_QCH_ENABLE, QCH_CON_USI11_USI_QCH_CLOCK_REQ, QCH_CON_USI11_USI_QCH_EXPIRE_VAL, QCH_CON_USI11_USI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_TMU_QCH, QCH_CON_BUSIF_TMU_QCH_ENABLE, QCH_CON_BUSIF_TMU_QCH_CLOCK_REQ, QCH_CON_BUSIF_TMU_QCH_EXPIRE_VAL, QCH_CON_BUSIF_TMU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GIC_QCH, QCH_CON_GIC_QCH_ENABLE, QCH_CON_GIC_QCH_CLOCK_REQ, QCH_CON_GIC_QCH_EXPIRE_VAL, QCH_CON_GIC_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(LHM_AXI_P_PERIS_QCH, QCH_CON_LHM_AXI_P_PERIS_QCH_ENABLE, QCH_CON_LHM_AXI_P_PERIS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_PERIS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_PERIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MCT_QCH, QCH_CON_MCT_QCH_ENABLE, QCH_CON_MCT_QCH_CLOCK_REQ, QCH_CON_MCT_QCH_EXPIRE_VAL, QCH_CON_MCT_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(OTP_CON_BIRA_QCH, QCH_CON_OTP_CON_BIRA_QCH_ENABLE, QCH_CON_OTP_CON_BIRA_QCH_CLOCK_REQ, QCH_CON_OTP_CON_BIRA_QCH_EXPIRE_VAL, QCH_CON_OTP_CON_BIRA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(OTP_CON_TOP_QCH, QCH_CON_OTP_CON_TOP_QCH_ENABLE, QCH_CON_OTP_CON_TOP_QCH_CLOCK_REQ, QCH_CON_OTP_CON_TOP_QCH_EXPIRE_VAL, QCH_CON_OTP_CON_TOP_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(PERIS_CMU_PERIS_QCH, QCH_CON_PERIS_CMU_PERIS_QCH_ENABLE, QCH_CON_PERIS_CMU_PERIS_QCH_CLOCK_REQ, QCH_CON_PERIS_CMU_PERIS_QCH_EXPIRE_VAL, QCH_CON_PERIS_CMU_PERIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_PERIS_QCH, QCH_CON_SYSREG_PERIS_QCH_ENABLE, QCH_CON_SYSREG_PERIS_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERIS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_PERIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WDT_CLUSTER0_QCH, QCH_CON_WDT_CLUSTER0_QCH_ENABLE, QCH_CON_WDT_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_WDT_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_WDT_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WDT_CLUSTER1_QCH, QCH_CON_WDT_CLUSTER1_QCH_ENABLE, QCH_CON_WDT_CLUSTER1_QCH_CLOCK_REQ, QCH_CON_WDT_CLUSTER1_QCH_EXPIRE_VAL, QCH_CON_WDT_CLUSTER1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(S2D_CMU_S2D_QCH, QCH_CON_S2D_CMU_S2D_QCH_ENABLE, QCH_CON_S2D_CMU_S2D_QCH_CLOCK_REQ, QCH_CON_S2D_CMU_S2D_QCH_EXPIRE_VAL, QCH_CON_S2D_CMU_S2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(AHB_BUSMATRIX_QCH_SYS, QCH_CON_AHB_BUSMATRIX_QCH_SYS_ENABLE, QCH_CON_AHB_BUSMATRIX_QCH_SYS_CLOCK_REQ, QCH_CON_AHB_BUSMATRIX_QCH_SYS_EXPIRE_VAL, QCH_CON_AHB_BUSMATRIX_QCH_SYS_IGNORE_FORCE_PM_EN),
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CLK_QCH(ASYNCAHBM_VTS_QCH, QCH_CON_ASYNCAHBM_VTS_QCH_ENABLE, QCH_CON_ASYNCAHBM_VTS_QCH_CLOCK_REQ, QCH_CON_ASYNCAHBM_VTS_QCH_EXPIRE_VAL, QCH_CON_ASYNCAHBM_VTS_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(CORTEXM4INTEGRATION_QCH_CPU, QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_ENABLE, QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_CLOCK_REQ, QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_EXPIRE_VAL, QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_AHB0_QCH_PCLK, QCH_CON_DMIC_AHB0_QCH_PCLK_ENABLE, QCH_CON_DMIC_AHB0_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AHB0_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_AHB0_QCH_PCLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMIC_AHB1_QCH_PCLK, QCH_CON_DMIC_AHB1_QCH_PCLK_ENABLE, QCH_CON_DMIC_AHB1_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AHB1_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_AHB1_QCH_PCLK_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(DMIC_IF_QCH_PCLK, QCH_CON_DMIC_IF_QCH_PCLK_ENABLE, QCH_CON_DMIC_IF_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_IF_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_IF_QCH_PCLK_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(DMIC_IF_QCH_DMIC_CLK, DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK_ENABLE, DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(GPIO_VTS_QCH, QCH_CON_GPIO_VTS_QCH_ENABLE, QCH_CON_GPIO_VTS_QCH_CLOCK_REQ, QCH_CON_GPIO_VTS_QCH_EXPIRE_VAL, QCH_CON_GPIO_VTS_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(HWACG_SYS_DMIC0_QCH, QCH_CON_HWACG_SYS_DMIC0_QCH_ENABLE, QCH_CON_HWACG_SYS_DMIC0_QCH_CLOCK_REQ, QCH_CON_HWACG_SYS_DMIC0_QCH_EXPIRE_VAL, QCH_CON_HWACG_SYS_DMIC0_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(HWACG_SYS_DMIC1_QCH, QCH_CON_HWACG_SYS_DMIC1_QCH_ENABLE, QCH_CON_HWACG_SYS_DMIC1_QCH_CLOCK_REQ, QCH_CON_HWACG_SYS_DMIC1_QCH_EXPIRE_VAL, QCH_CON_HWACG_SYS_DMIC1_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(MAILBOX_VTS2CHUB_QCH, QCH_CON_MAILBOX_VTS2CHUB_QCH_ENABLE, QCH_CON_MAILBOX_VTS2CHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_VTS2CHUB_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_VTS2CHUB_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(SYSREG_VTS_QCH, QCH_CON_SYSREG_VTS_QCH_ENABLE, QCH_CON_SYSREG_VTS_QCH_CLOCK_REQ, QCH_CON_SYSREG_VTS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_VTS_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(VTS_CMU_VTS_QCH, QCH_CON_VTS_CMU_VTS_QCH_ENABLE, QCH_CON_VTS_CMU_VTS_QCH_CLOCK_REQ, QCH_CON_VTS_CMU_VTS_QCH_EXPIRE_VAL, QCH_CON_VTS_CMU_VTS_QCH_IGNORE_FORCE_PM_EN),
|
|
CLK_QCH(WDT_VTS_QCH, QCH_CON_WDT_VTS_QCH_ENABLE, QCH_CON_WDT_VTS_QCH_CLOCK_REQ, QCH_CON_WDT_VTS_QCH_EXPIRE_VAL, QCH_CON_WDT_VTS_QCH_IGNORE_FORCE_PM_EN),
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|
CLK_QCH(U_DMIC_CLK_MUX_QCH, DMYQCH_CON_U_DMIC_CLK_MUX_QCH_ENABLE, DMYQCH_CON_U_DMIC_CLK_MUX_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_U_DMIC_CLK_MUX_QCH_IGNORE_FORCE_PM_EN),
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|
};
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|
|
|
/*====================The section of controller option nodes===================*/
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|
unsigned int cmucal_option_size = 31;
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|
|
|
|
|
struct cmucal_option cmucal_option_list[] = {
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|
CLK_OPTION(CTRL_OPTION_BLK_APM, APM_ENABLE_POWER_MANAGEMENT, APM_ENABLE_AUTOMATIC_CLKGATING),
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|
CLK_OPTION(CTRL_OPTION_BLK_AUD, AUD_ENABLE_POWER_MANAGEMENT, AUD_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_OPTION(CTRL_OPTION_BLK_BUS1, BUS1_ENABLE_POWER_MANAGEMENT, BUS1_ENABLE_AUTOMATIC_CLKGATING),
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|
CLK_OPTION(CTRL_OPTION_BLK_BUSC, BUSC_ENABLE_POWER_MANAGEMENT, BUSC_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_OPTION(CTRL_OPTION_BLK_CHUB, CHUB_ENABLE_POWER_MANAGEMENT, CHUB_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_CMGP, CMGP_ENABLE_POWER_MANAGEMENT, CMGP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_CMU, CMU_ENABLE_POWER_MANAGEMENT, CMU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_CORE, CORE_ENABLE_POWER_MANAGEMENT, CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_CPUCL0, CPUCL0_ENABLE_POWER_MANAGEMENT, CPUCL0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_CPUCL1, CPUCL1_ENABLE_POWER_MANAGEMENT, CPUCL1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_DCF, DCF_ENABLE_POWER_MANAGEMENT, DCF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_DCPOST, DCPOST_ENABLE_POWER_MANAGEMENT, DCPOST_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_DCRD, DCRD_ENABLE_POWER_MANAGEMENT, DCRD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_DPU, DPU_ENABLE_POWER_MANAGEMENT, DPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_DSPM, DSPM_ENABLE_POWER_MANAGEMENT, DSPM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_DSPS, DSPS_ENABLE_POWER_MANAGEMENT, DSPS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_FSYS0, FSYS0_ENABLE_POWER_MANAGEMENT, FSYS0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_FSYS1, FSYS1_ENABLE_POWER_MANAGEMENT, FSYS1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_G2D, G2D_ENABLE_POWER_MANAGEMENT, G2D_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_G3D, G3D_ENABLE_POWER_MANAGEMENT, G3D_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_ISPHQ, ISPHQ_ENABLE_POWER_MANAGEMENT, ISPHQ_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_ISPLP, ISPLP_ENABLE_POWER_MANAGEMENT, ISPLP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_ISPPRE, ISPPRE_ENABLE_POWER_MANAGEMENT, ISPPRE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_IVA, IVA_ENABLE_POWER_MANAGEMENT, IVA_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_MFC, MFC_ENABLE_POWER_MANAGEMENT, MFC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_MIF, MIF_ENABLE_POWER_MANAGEMENT, MIF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_PERIC0, PERIC0_ENABLE_POWER_MANAGEMENT, PERIC0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_PERIC1, PERIC1_ENABLE_POWER_MANAGEMENT, PERIC1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_PERIS, PERIS_ENABLE_POWER_MANAGEMENT, PERIS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_S2D, S2D_ENABLE_POWER_MANAGEMENT, S2D_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_BLK_VTS, VTS_ENABLE_POWER_MANAGEMENT, VTS_ENABLE_AUTOMATIC_CLKGATING),
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};
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