5552 lines
571 KiB
C
Executable File
5552 lines
571 KiB
C
Executable File
#include "../cmucal.h"
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#include "cmucal-sfr.h"
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/*=================CMUCAL version: S5E9610================================*/
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/*====================The section of SFR Block instance===================*/
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struct sfr_block cmucal_sfr_block_list[] __initdata = {
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SFR_BLOCK(APM, 0x11800000, 0x8000),
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SFR_BLOCK(CAM, 0x14500000, 0x8000),
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SFR_BLOCK(CMGP, 0x11c00000, 0x8000),
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SFR_BLOCK(TOP, 0x12100000, 0x8000),
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SFR_BLOCK(CORE, 0x120f0000, 0x8000),
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SFR_BLOCK(CPUCL0, 0x10900000, 0x8000),
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SFR_BLOCK(CPUCL1, 0x10800000, 0x8000),
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SFR_BLOCK(DISPAUD, 0x14980000, 0x8000),
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SFR_BLOCK(FSYS, 0x13400000, 0x8000),
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SFR_BLOCK(G2D, 0x12e00000, 0x8000),
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SFR_BLOCK(G3D, 0x11430000, 0x8000),
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SFR_BLOCK(ISP, 0x14700000, 0x8000),
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SFR_BLOCK(MFC, 0x12c00000, 0x8000),
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SFR_BLOCK(MIF, 0x10400000, 0x8000),
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SFR_BLOCK(MIF1, 0x10500000, 0x8000),
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SFR_BLOCK(PERI, 0x10030000, 0x8000),
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SFR_BLOCK(SHUB, 0x11000000, 0x8000),
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SFR_BLOCK(USB, 0x13030000, 0x8000),
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SFR_BLOCK(VIPX1, 0x10c90000, 0x8000),
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SFR_BLOCK(VIPX2, 0x10e90000, 0x8000),
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};
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unsigned int cmucal_sfr_block_size = 20;
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/*====================The section of SFR instance===================*/
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struct sfr cmucal_sfr_list[] __initdata = {
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SFR(PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 0x0100, APM),
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SFR(PLL_CON2_MUX_CLKCMU_APM_BUS_USER, 0x0108, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK, 0x2034, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, 0x2044, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK, 0x2060, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK, 0x2064, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK, 0x2068, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK, 0x2070, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, 0x20a8, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK, 0x209c, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, 0x2018, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, 0x2014, APM),
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SFR(CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, 0x2004, APM),
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SFR(CLK_CON_DIV_DIV_CLK_APM_BUS, 0x1804, APM),
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SFR(CLK_CON_MUX_MUX_CLK_APM_BUS, 0x1004, APM),
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SFR(PLL_CON0_MUX_DLL_USER, 0x0120, APM),
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SFR(PLL_CON2_MUX_DLL_USER, 0x0128, APM),
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SFR(CLK_CON_MUX_MUX_CLKCMU_SHUB_BUS, 0x1000, APM),
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SFR(CLK_CON_DIV_CLKCMU_SHUB_BUS, 0x1800, APM),
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SFR(CLK_CON_GAT_GATE_CLKCMU_SHUB_BUS, 0x2010, APM),
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SFR(CLK_CON_GAT_CLKCMU_CMGP_BUS, 0x2000, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK, 0x2090, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, 0x201c, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK, 0x2020, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, 0x2028, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, 0x202c, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_SHUB_IPCLKPORT_I_CLK, 0x203c, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_MODEM_IPCLKPORT_I_CLK, 0x2038, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK, 0x2030, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_SHUB_IPCLKPORT_I_CLK, 0x2048, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK, 0x204c, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK, 0x2050, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK, 0x2054, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2SHUB_IPCLKPORT_PCLK, 0x2058, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2WLBT_IPCLKPORT_PCLK, 0x205c, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2SHUB_IPCLKPORT_PCLK, 0x206c, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2GNSS_IPCLKPORT_PCLK, 0x208c, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2GNSS_IPCLKPORT_PCLK, 0x2080, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2ABOX_IPCLKPORT_PCLK, 0x2088, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_LITE_APM_IPCLKPORT_CLK, 0x2094, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, 0x2098, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_WLBT_IPCLKPORT_I_CLK, 0x2040, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 0x20b0, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 0x20ac, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2WLBT_IPCLKPORT_PCLK, 0x2084, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2GNSS_IPCLKPORT_PCLK, 0x2074, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2SHUB_IPCLKPORT_PCLK, 0x2078, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2WLBT_IPCLKPORT_PCLK, 0x207c, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, 0x20a4, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK, 0x20a0, APM),
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SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, 0x2024, APM),
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SFR(CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_IPCLKPORT_CLK, 0x2008, APM),
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SFR(CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_RCO_IPCLKPORT_CLK, 0x200c, APM),
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SFR(QCH_CON_APBIF_GPIO_ALIVE_QCH, 0x301c, APM),
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SFR(QCH_CON_APBIF_PMU_ALIVE_QCH, 0x3020, APM),
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SFR(QCH_CON_APBIF_RTC_QCH, 0x3024, APM),
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SFR(QCH_CON_APBIF_TOP_RTC_QCH, 0x3028, APM),
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SFR(QCH_CON_APM_CMU_APM_QCH, 0x302c, APM),
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SFR(QCH_CON_GREBEINTEGRATION_QCH_GREBE, 0x3034, APM),
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SFR(QCH_CON_GREBEINTEGRATION_QCH_DBG, 0x3030, APM),
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SFR(QCH_CON_INTMEM_QCH, 0x3038, APM),
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SFR(QCH_CON_LHM_AXI_P_APM_QCH, 0x3044, APM),
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SFR(QCH_CON_LHM_AXI_P_APM_GNSS_QCH, 0x303c, APM),
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SFR(QCH_CON_LHM_AXI_P_APM_MODEM_QCH, 0x3040, APM),
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SFR(QCH_CON_LHM_AXI_P_APM_SHUB_QCH, 0x3048, APM),
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SFR(QCH_CON_LHM_AXI_P_APM_WLBT_QCH, 0x304c, APM),
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SFR(QCH_CON_LHS_AXI_D_APM_QCH, 0x3050, APM),
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SFR(QCH_CON_LHS_AXI_LP_SHUB_QCH, 0x3054, APM),
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SFR(QCH_CON_MAILBOX_AP2CP_QCH, 0x3058, APM),
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SFR(QCH_CON_MAILBOX_AP2CP_S_QCH, 0x305c, APM),
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SFR(QCH_CON_MAILBOX_AP2GNSS_QCH, 0x3060, APM),
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SFR(QCH_CON_MAILBOX_AP2SHUB_QCH, 0x3064, APM),
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SFR(QCH_CON_MAILBOX_AP2WLBT_QCH, 0x3068, APM),
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SFR(QCH_CON_MAILBOX_APM2AP_QCH, 0x306c, APM),
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SFR(QCH_CON_MAILBOX_APM2CP_QCH, 0x3070, APM),
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SFR(QCH_CON_MAILBOX_APM2GNSS_QCH, 0x3074, APM),
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SFR(QCH_CON_MAILBOX_APM2SHUB_QCH, 0x3078, APM),
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SFR(QCH_CON_MAILBOX_APM2WLBT_QCH, 0x307c, APM),
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SFR(QCH_CON_MAILBOX_CP2GNSS_QCH, 0x3080, APM),
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SFR(QCH_CON_MAILBOX_CP2SHUB_QCH, 0x3084, APM),
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SFR(QCH_CON_MAILBOX_CP2WLBT_QCH, 0x3088, APM),
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SFR(QCH_CON_MAILBOX_SHUB2GNSS_QCH, 0x308c, APM),
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SFR(QCH_CON_MAILBOX_SHUB2WLBT_QCH, 0x3090, APM),
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SFR(QCH_CON_MAILBOX_WLBT2ABOX_QCH, 0x3094, APM),
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SFR(QCH_CON_MAILBOX_WLBT2GNSS_QCH, 0x3098, APM),
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SFR(QCH_CON_PEM_QCH, 0x309c, APM),
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SFR(QCH_CON_PGEN_LITE_APM_QCH, 0x30a0, APM),
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SFR(QCH_CON_PMU_INTR_GEN_QCH, 0x30a4, APM),
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SFR(QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH, 0x30a8, APM),
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SFR(QCH_CON_SPEEDY_APM_QCH, 0x30ac, APM),
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SFR(QCH_CON_SYSREG_APM_QCH, 0x30b0, APM),
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SFR(QCH_CON_WDT_APM_QCH, 0x30b4, APM),
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SFR(PLL_CON0_MUX_CLKCMU_CAM_BUS_USER, 0x0100, CAM),
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SFR(PLL_CON2_MUX_CLKCMU_CAM_BUS_USER, 0x0108, CAM),
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SFR(CLK_CON_DIV_DIV_CLK_CAM_BUSP, 0x1800, CAM),
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SFR(CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK, 0x2000, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK, 0x205c, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ATB_CAMISP_IPCLKPORT_I_CLK, 0x2064, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ACEL_D_CAM_IPCLKPORT_I_CLK, 0x2060, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK, 0x2068, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK, 0x206c, CAM),
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SFR(CLK_CON_GAT_CLK_BLK_CAM_UID_RSTNSYNC_CLK_CAM_OSCCLK_IPCLKPORT_CLK, 0x2004, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_XIU_D_CAM, 0x204c, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PPMU_CAM, 0x2058, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PPMU_CAM, 0x2040, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_SMMU_CAM, 0x2048, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_3AA, 0x2014, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS0, 0x2018, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS1, 0x201c, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS2, 0x2020, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS3, 0x2024, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_BLK_CAM_IPCLKPORT_CLK_CAM_BUSD, 0x2008, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK, 0x2070, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM0, 0x2050, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_DMA, 0x2028, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PAFSTAT_CORE, 0x203c, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_RDMA, 0x2044, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_ACLK, 0x200c, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_PCLK, 0x2010, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS0, 0x202c, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS1, 0x2030, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS2, 0x2034, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS3, 0x2038, CAM),
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SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM1, 0x2054, CAM),
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SFR(QCH_CON_BTM_CAM_QCH, 0x300c, CAM),
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SFR(QCH_CON_CAM_CMU_CAM_QCH, 0x3010, CAM),
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SFR(QCH_CON_LHM_AXI_P_CAM_QCH, 0x3044, CAM),
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SFR(QCH_CON_LHS_ACEL_D_CAM_QCH, 0x3048, CAM),
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SFR(QCH_CON_LHS_ATB_CAMISP_QCH, 0x304c, CAM),
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SFR(QCH_CON_SYSREG_CAM_QCH, 0x3050, CAM),
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SFR(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS0, 0x3020, CAM),
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SFR(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS1, 0x3024, CAM),
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SFR(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS2, 0x3028, CAM),
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SFR(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS3, 0x302c, CAM),
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SFR(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_3AA, 0x301c, CAM),
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SFR(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PPMU, 0x3038, CAM),
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SFR(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_SMMU, 0x3040, CAM),
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SFR(QCH_CON_IS6P10P0_CAM_QCH_S_CAM0_PGEN_LITE, 0x3014, CAM),
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SFR(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE, 0x3030, CAM),
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SFR(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA, 0x3034, CAM),
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SFR(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_RDMA, 0x303c, CAM),
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SFR(QCH_CON_IS6P10P0_CAM_QCH_S_CAM1_PGEN_LITE, 0x3018, CAM),
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SFR(CLK_CON_DIV_DIV_CLK_CMGP_USI03, 0x1814, CMGP),
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SFR(CLK_CON_DIV_DIV_CLK_CMGP_USI00, 0x1808, CMGP),
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SFR(CLK_CON_DIV_DIV_CLK_CMGP_I2C, 0x1804, CMGP),
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SFR(CLK_CON_DIV_DIV_CLK_CMGP_USI01, 0x180c, CMGP),
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SFR(CLK_CON_DIV_DIV_CLK_CMGP_USI04, 0x1818, CMGP),
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SFR(CLK_CON_MUX_MUX_CLK_CMGP_USI01, 0x100c, CMGP),
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SFR(CLK_CON_MUX_MUX_CLK_CMGP_I2C, 0x1004, CMGP),
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SFR(CLK_CON_MUX_MUX_CLK_CMGP_USI00, 0x1008, CMGP),
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SFR(CLK_CON_MUX_MUX_CLK_CMGP_USI04, 0x1018, CMGP),
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SFR(CLK_CON_MUX_MUX_CLK_CMGP_USI02, 0x1010, CMGP),
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SFR(CLK_CON_DIV_DIV_CLK_CMGP_USI02, 0x1810, CMGP),
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SFR(CLK_CON_MUX_MUX_CLK_CMGP_USI03, 0x1014, CMGP),
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SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK, 0x2004, CMGP),
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SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK, 0x205c, CMGP),
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SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK, 0x2060, CMGP),
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SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2SHUB_IPCLKPORT_PCLK, 0x206c, CMGP),
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SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK, 0x2070, CMGP),
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SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK, 0x2014, CMGP),
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SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0, 0x200c, CMGP),
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SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1, 0x2010, CMGP),
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SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK, 0x201c, CMGP),
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SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK, 0x2024, CMGP),
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SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK, 0x202c, CMGP),
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SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK, 0x2034, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_PCLK, 0x203c, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK, 0x2074, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK, 0x207c, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK, 0x2084, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK, 0x208c, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK, 0x2094, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_PCLK, 0x209c, CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CMGP_ADC, 0x1000, CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0x1800, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI00_IPCLKPORT_CLK, 0x2048, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK, 0x2040, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK, 0x2044, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI01_IPCLKPORT_CLK, 0x204c, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI02_IPCLKPORT_CLK, 0x2050, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI03_IPCLKPORT_CLK, 0x2054, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI04_IPCLKPORT_CLK, 0x2058, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK, 0x2018, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK, 0x2020, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK, 0x2028, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK, 0x2030, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_IPCLK, 0x2038, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK, 0x2078, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK, 0x2080, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK, 0x2088, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK, 0x2090, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_IPCLK, 0x2098, CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK, 0x2008, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK, 0x2064, CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_SHUB_IPCLKPORT_PCLK, 0x2068, CMGP),
|
|
SFR(QCH_CON_ADC_CMGP_QCH_S0, 0x3004, CMGP),
|
|
SFR(QCH_CON_ADC_CMGP_QCH_S1, 0x3008, CMGP),
|
|
SFR(DMYQCH_CON_ADC_CMGP_QCH_ADC, 0x3000, CMGP),
|
|
SFR(QCH_CON_CMGP_CMU_CMGP_QCH, 0x300c, CMGP),
|
|
SFR(QCH_CON_GPIO_CMGP_QCH, 0x3010, CMGP),
|
|
SFR(QCH_CON_I2C_CMGP00_QCH, 0x3014, CMGP),
|
|
SFR(QCH_CON_I2C_CMGP01_QCH, 0x3018, CMGP),
|
|
SFR(QCH_CON_I2C_CMGP02_QCH, 0x301c, CMGP),
|
|
SFR(QCH_CON_I2C_CMGP03_QCH, 0x3020, CMGP),
|
|
SFR(QCH_CON_I2C_CMGP04_QCH, 0x3024, CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP_QCH, 0x3040, CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2CP_QCH, 0x3028, CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2GNSS_QCH, 0x302c, CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2PMU_AP_QCH, 0x3030, CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2PMU_SHUB_QCH, 0x3034, CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2SHUB_QCH, 0x3038, CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2WLBT_QCH, 0x303c, CMGP),
|
|
SFR(QCH_CON_USI_CMGP00_QCH, 0x3044, CMGP),
|
|
SFR(QCH_CON_USI_CMGP01_QCH, 0x3048, CMGP),
|
|
SFR(QCH_CON_USI_CMGP02_QCH, 0x304c, CMGP),
|
|
SFR(QCH_CON_USI_CMGP03_QCH, 0x3050, CMGP),
|
|
SFR(QCH_CON_USI_CMGP04_QCH, 0x3054, CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0x1050, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 0x2058, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_DISPAUD_DISP, 0x1038, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DISPAUD_DISP, 0x2040, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_DISPAUD_DISP, 0x1840, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS, 0x103c, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD, 0x1044, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD, 0x204c, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS, 0x2044, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_FSYS_BUS, 0x1844, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_G2D_MSCL, 0x1858, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0, 0x207c, TOP),
|
|
SFR(CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK, 0x1800, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0x1078, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 0x2084, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERI_BUS, 0x1880, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0x107c, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 0x2088, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERI_IP, 0x1884, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 0x2008, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_APM_BUS, 0x1808, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD, 0x1040, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD, 0x2048, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD, 0x1848, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CIS_CLK0, 0x1810, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CIS_CLK1, 0x1814, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CIS_CLK2, 0x1818, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 0x2010, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 0x2014, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 0x2018, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0x1008, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0x100c, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0x1010, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD, 0x184c, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1, 0x2080, TOP),
|
|
SFR(CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK, 0x1804, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CMU_CMUREF, 0x109c, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CMU_CMUREF, 0x1098, TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0x18a0, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0x1000, TOP),
|
|
SFR(PLL_CON0_PLL_SHARED0, 0x0120, TOP),
|
|
SFR(PLL_LOCKTIME_PLL_SHARED0, 0x0004, TOP),
|
|
SFR(PLL_CON0_PLL_SHARED1, 0x0140, TOP),
|
|
SFR(PLL_LOCKTIME_PLL_SHARED1, 0x0008, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 0x2020, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CORE_BUS, 0x1820, TOP),
|
|
SFR(CLK_CON_DIV_PLL_SHARED0_DIV3, 0x18ac, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0x182c, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG, 0x202c, TOP),
|
|
SFR(CLK_CON_DIV_PLL_SHARED0_DIV2, 0x18a8, TOP),
|
|
SFR(CLK_CON_DIV_PLL_SHARED0_DIV4, 0x18b0, TOP),
|
|
SFR(CLK_CON_DIV_PLL_SHARED1_DIV2, 0x18b4, TOP),
|
|
SFR(CLK_CON_DIV_PLL_SHARED1_DIV4, 0x18bc, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 0x2024, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CORE_CCI, 0x1824, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CORE_G3D, 0x2028, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CORE_G3D, 0x1828, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0x101c, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CORE_G3D, 0x1020, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0x1018, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0x1070, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 0x2078, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_MIF_BUSP, 0x1878, TOP),
|
|
SFR(CLK_CON_DIV_PLL_SHARED1_DIV3, 0x18b8, TOP),
|
|
SFR(PLL_CON0_PLL_MMC, 0x0100, TOP),
|
|
SFR(PLL_CON3_PLL_MMC, 0x010c, TOP),
|
|
SFR(PLL_LOCKTIME_PLL_MMC, 0x0000, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS_UFS_EMBD, 0x1048, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS_UFS_EMBD, 0x2050, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_FSYS_UFS_EMBD, 0x1850, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CAM_BUS, 0x180c, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CAM_BUS, 0x200c, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CAM_BUS, 0x1004, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_VIPX1_BUS, 0x1090, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_VIPX1_BUS, 0x209c, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_VIPX1_BUS, 0x1898, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_ISP_BUS, 0x1864, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_ISP_BUS, 0x105c, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_ISP_BUS, 0x2064, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_ISP_VRA, 0x186c, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_ISP_VRA, 0x1064, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_ISP_VRA, 0x206c, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_ISP_GDC, 0x1868, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_ISP_GDC, 0x2068, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_ISP_GDC, 0x1060, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_G2D_G2D, 0x1854, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0x104c, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 0x2054, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0x1028, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 0x2030, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0x1830, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 0x2034, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0x1834, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0x102c, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 0x205c, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0x185c, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0x1054, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DISPAUD_CPU, 0x203c, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_DISPAUD_CPU, 0x183c, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_DISPAUD_CPU, 0x1034, TOP),
|
|
SFR(CLK_CON_GAT_CLKCMU_MIF_SWITCH, 0x2000, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0x1074, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, 0x1024, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_USB_BUS, 0x1084, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_USB_BUS, 0x188c, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_USB_BUS, 0x2090, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_USB_USB30DRD, 0x108c, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_USB_USB30DRD, 0x1894, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_USB_USB30DRD, 0x2098, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_USB_DPGTC, 0x1088, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_USB_DPGTC, 0x2094, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_USB_DPGTC, 0x1890, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_DISPAUD_AUD, 0x1838, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DISPAUD_AUD, 0x2038, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_DISPAUD_AUD, 0x1030, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 0x2070, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MFC_WFD, 0x2074, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_MFC_MFC, 0x1870, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_MFC_WFD, 0x1874, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0x1068, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, 0x106c, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_HPM, 0x1058, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_HPM, 0x2060, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_HPM, 0x1860, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERI_UART, 0x1888, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0x1080, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 0x208c, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_OTP, 0x187c, TOP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMU_UID_OTP_IPCLKPORT_CLK, 0x2004, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_VIPX2_BUS, 0x20a0, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_VIPX2_BUS, 0x189c, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_VIPX2_BUS, 0x1094, TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CIS_CLK3, 0x181c, TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 0x201c, TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0x1014, TOP),
|
|
SFR(CLK_CON_DIV_PLL_MMC_DIV2, 0x18a4, TOP),
|
|
SFR(DMYQCH_CON_CMU_TOP_CMUREF_QCH, 0x3000, TOP),
|
|
SFR(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS0, 0x3004, TOP),
|
|
SFR(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS1, 0x3008, TOP),
|
|
SFR(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS2, 0x300c, TOP),
|
|
SFR(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS3, 0x3010, TOP),
|
|
SFR(DMYQCH_CON_OTP_QCH, 0x3014, TOP),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 0x0100, CORE),
|
|
SFR(PLL_CON2_MUX_CLKCMU_CORE_BUS_USER, 0x0108, CORE),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0x1800, CORE),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CORE_GIC, 0x1000, CORE),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 0x0120, CORE),
|
|
SFR(PLL_CON2_MUX_CLKCMU_CORE_CCI_USER, 0x0128, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM, 0x2024, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC400_AIHWACG_IPCLKPORT_CLK, 0x204c, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK, 0x207c, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK, 0x2080, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK, 0x208c, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK, 0x2084, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_DPU_IPCLKPORT_I_CLK, 0x2064, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_CAM_IPCLKPORT_I_CLK, 0x2060, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK, 0x20a4, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CPU_IPCLKPORT_I_CLK, 0x20a8, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CPU_IPCLKPORT_I_CLK, 0x20b8, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK, 0x20c8, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK, 0x20d0, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK, 0x20d4, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK, 0x20d8, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK, 0x20dc, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK, 0x20f0, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK, 0x2100, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK, 0x2128, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_ACLK, 0x2138, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_PCLK, 0x213c, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_ACLK, 0x2140, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_PCLK, 0x2144, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK, 0x2170, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK, 0x2180, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK, 0x2190, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_OCC_IPCLKPORT_CLK, 0x215c, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK, 0x2148, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_OCC_IPCLKPORT_CLK, 0x2154, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_CCI_550_IPCLKPORT_PCLKM, 0x2004, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK, 0x20f8, CORE),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CORE_G3D_USER, 0x0140, CORE),
|
|
SFR(PLL_CON2_MUX_CLKCMU_CORE_G3D_USER, 0x0148, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_OCC_IPCLKPORT_CLK, 0x2164, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK, 0x2124, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK, 0x2150, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_IPCLKPORT_CLK, 0x2158, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK, 0x2160, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK, 0x2098, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK, 0x2168, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK, 0x216c, CORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK, 0x2000, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_NRT_IPCLKPORT_I_CLK, 0x20b0, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_NRT_IPCLKPORT_I_CLK, 0x20c0, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC0_IPCLKPORT_I_PCLK, 0x2028, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_ISP_IPCLKPORT_I_CLK, 0x20ec, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK, 0x20fc, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM, 0x200c, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM, 0x2020, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK, 0x2090, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK, 0x2094, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_FSYS_IPCLKPORT_I_CLK, 0x2068, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK, 0x209c, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_ISP_IPCLKPORT_I_CLK, 0x2050, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_G2D_IPCLKPORT_I_CLK, 0x206c, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_SHUB_IPCLKPORT_I_CLK, 0x20a0, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_SHUB_IPCLKPORT_I_CLK, 0x2104, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_WLBT_IPCLKPORT_I_CLK, 0x2114, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK, 0x20e8, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0, 0x2118, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1, 0x217c, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK, 0x20f4, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_ISP_IPCLKPORT_I_CLK, 0x2058, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CP_IPCLKPORT_I_CLK, 0x20bc, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_RT_IPCLKPORT_I_CLK, 0x20c4, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_RT_IPCLKPORT_I_CLK, 0x20b4, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CP_IPCLKPORT_I_CLK, 0x20ac, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_MFC_IPCLKPORT_I_CLK, 0x2054, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_MFC_IPCLKPORT_I_CLK, 0x205c, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_USB_IPCLKPORT_I_CLK, 0x2070, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX1_IPCLKPORT_I_CLK, 0x2074, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX2_IPCLKPORT_I_CLK, 0x2078, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_USB_IPCLKPORT_I_CLK, 0x2108, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK, 0x20cc, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK, 0x20e0, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX1_IPCLKPORT_I_CLK, 0x210c, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC1_IPCLKPORT_I_PCLK, 0x202c, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK, 0x21a4, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK, 0x20e4, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM0_IPCLKPORT_CLK, 0x212c, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM1_IPCLKPORT_CLK, 0x2130, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_PERI_IPCLKPORT_CLK, 0x2134, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK, 0x2034, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK, 0x2038, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_SHUB_IPCLKPORT_I_PCLK, 0x203c, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK, 0x2040, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK, 0x2174, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK, 0x2178, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK, 0x2184, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE, 0x219c, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_550_IPCLKPORT_ACLK, 0x2044, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK, 0x2198, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK, 0x21ac, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_CCLK, 0x2188, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_IPCLKPORT_CLK, 0x214c, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_LITE_SIREX_IPCLKPORT_CLK, 0x211c, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK, 0x2088, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK, 0x218c, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK, 0x2194, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_CCLK_P_CORE, 0x21a0, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE, 0x21a8, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A, 0x2048, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM0_IPCLKPORT_PCLKM, 0x2014, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM1_IPCLKPORT_PCLKM, 0x2018, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_PERI_IPCLKPORT_PCLKM, 0x201c, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_US_A40_64TO128_DIT_IPCLKPORT_ACLK, 0x2030, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM, 0x2008, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX2_IPCLKPORT_I_CLK, 0x2110, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_PDMA_IPCLKPORT_CLK, 0x2120, CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PGEN_PDMA_IPCLKPORT_PCLKM, 0x2010, CORE),
|
|
SFR(QCH_CON_BAAW_P_GNSS_QCH, 0x30c8, CORE),
|
|
SFR(QCH_CON_BAAW_P_MODEM_QCH, 0x30cc, CORE),
|
|
SFR(QCH_CON_BAAW_P_SHUB_QCH, 0x30d0, CORE),
|
|
SFR(QCH_CON_BAAW_P_WLBT_QCH, 0x30d4, CORE),
|
|
SFR(QCH_CON_CCI_550_QCH, 0x30d8, CORE),
|
|
SFR(QCH_CON_CORE_CMU_CORE_QCH, 0x30dc, CORE),
|
|
SFR(QCH_CON_DIT_QCH, 0x30e0, CORE),
|
|
SFR(QCH_CON_GIC400_AIHWACG_QCH, 0x30e4, CORE),
|
|
SFR(QCH_CON_LHM_ACEL_D0_ISP_QCH, 0x30e8, CORE),
|
|
SFR(QCH_CON_LHM_ACEL_D0_MFC_QCH, 0x30ec, CORE),
|
|
SFR(QCH_CON_LHM_ACEL_D1_ISP_QCH, 0x30f0, CORE),
|
|
SFR(QCH_CON_LHM_ACEL_D1_MFC_QCH, 0x30f4, CORE),
|
|
SFR(QCH_CON_LHM_ACEL_D_CAM_QCH, 0x30f8, CORE),
|
|
SFR(QCH_CON_LHM_ACEL_D_DPU_QCH, 0x30fc, CORE),
|
|
SFR(QCH_CON_LHM_ACEL_D_FSYS_QCH, 0x3100, CORE),
|
|
SFR(QCH_CON_LHM_ACEL_D_G2D_QCH, 0x3104, CORE),
|
|
SFR(QCH_CON_LHM_ACEL_D_USB_QCH, 0x3108, CORE),
|
|
SFR(QCH_CON_LHM_ACEL_D_VIPX1_QCH, 0x310c, CORE),
|
|
SFR(QCH_CON_LHM_ACEL_D_VIPX2_QCH, 0x3110, CORE),
|
|
SFR(QCH_CON_LHM_ACE_D_CPUCL0_QCH, 0x3114, CORE),
|
|
SFR(QCH_CON_LHM_ACE_D_CPUCL1_QCH, 0x3118, CORE),
|
|
SFR(QCH_CON_LHM_AXI_D0_MODEM_QCH, 0x311c, CORE),
|
|
SFR(QCH_CON_LHM_AXI_D1_MODEM_QCH, 0x3120, CORE),
|
|
SFR(QCH_CON_LHM_AXI_D_ABOX_QCH, 0x3124, CORE),
|
|
SFR(QCH_CON_LHM_AXI_D_APM_QCH, 0x3128, CORE),
|
|
SFR(QCH_CON_LHM_AXI_D_CSSYS_QCH, 0x312c, CORE),
|
|
SFR(QCH_CON_LHM_AXI_D_G3D_QCH, 0x3130, CORE),
|
|
SFR(QCH_CON_LHM_AXI_D_GNSS_QCH, 0x3134, CORE),
|
|
SFR(QCH_CON_LHM_AXI_D_SHUB_QCH, 0x3138, CORE),
|
|
SFR(QCH_CON_LHM_AXI_D_WLBT_QCH, 0x313c, CORE),
|
|
SFR(QCH_CON_LHS_AXI_D0_MIF_CP_QCH, 0x3144, CORE),
|
|
SFR(QCH_CON_LHS_AXI_D0_MIF_CPU_QCH, 0x3140, CORE),
|
|
SFR(QCH_CON_LHS_AXI_D0_MIF_NRT_QCH, 0x3148, CORE),
|
|
SFR(QCH_CON_LHS_AXI_D0_MIF_RT_QCH, 0x314c, CORE),
|
|
SFR(QCH_CON_LHS_AXI_D1_MIF_CP_QCH, 0x3154, CORE),
|
|
SFR(QCH_CON_LHS_AXI_D1_MIF_CPU_QCH, 0x3150, CORE),
|
|
SFR(QCH_CON_LHS_AXI_D1_MIF_NRT_QCH, 0x3158, CORE),
|
|
SFR(QCH_CON_LHS_AXI_D1_MIF_RT_QCH, 0x315c, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_APM_QCH, 0x3160, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_CAM_QCH, 0x3164, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_CPUCL0_QCH, 0x3168, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_CPUCL1_QCH, 0x316c, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_DISPAUD_QCH, 0x3170, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_FSYS_QCH, 0x3174, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_G2D_QCH, 0x3178, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_G3D_QCH, 0x317c, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_GNSS_QCH, 0x3180, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_ISP_QCH, 0x3184, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_MFC_QCH, 0x3188, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_MIF0_QCH, 0x318c, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_MIF1_QCH, 0x3190, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_MODEM_QCH, 0x3194, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_PERI_QCH, 0x3198, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_SHUB_QCH, 0x319c, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_USB_QCH, 0x31a0, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_VIPX1_QCH, 0x31a4, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_VIPX2_QCH, 0x31a8, CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_WLBT_QCH, 0x31ac, CORE),
|
|
SFR(QCH_CON_PDMA_CORE_QCH, 0x31b0, CORE),
|
|
SFR(QCH_CON_PGEN_LITE_SIREX_QCH, 0x31b4, CORE),
|
|
SFR(QCH_CON_PGEN_PDMA_QCH, 0x31b8, CORE),
|
|
SFR(QCH_CON_PPCFW_G3D_QCH, 0x31bc, CORE),
|
|
SFR(QCH_CON_PPFW_CORE_MEM0_QCH, 0x31c0, CORE),
|
|
SFR(QCH_CON_PPFW_CORE_MEM1_QCH, 0x31c4, CORE),
|
|
SFR(QCH_CON_PPFW_CORE_PERI_QCH, 0x31c8, CORE),
|
|
SFR(QCH_CON_PPMU_ACE_CPUCL0_QCH, 0x31cc, CORE),
|
|
SFR(QCH_CON_PPMU_ACE_CPUCL1_QCH, 0x31d0, CORE),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_QCH, 0x31d4, CORE),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_CORE_BUSP_OCC_QCH, 0x31d8, CORE),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_CORE_CCI_OCC_QCH, 0x31dc, CORE),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_CORE_G3D_OCC_QCH, 0x31e0, CORE),
|
|
SFR(QCH_CON_SFR_APBIF_CMU_TOPC_QCH, 0x31e4, CORE),
|
|
SFR(QCH_CON_SIREX_QCH, 0x31e8, CORE),
|
|
SFR(QCH_CON_SPDMA_CORE_QCH, 0x31ec, CORE),
|
|
SFR(QCH_CON_SYSREG_CORE_QCH, 0x31f0, CORE),
|
|
SFR(QCH_CON_TREX_D_CORE_QCH, 0x31f4, CORE),
|
|
SFR(QCH_CON_TREX_D_NRT_QCH, 0x31f8, CORE),
|
|
SFR(QCH_CON_TREX_P_CORE_QCH, 0x31fc, CORE),
|
|
SFR(PLL_CON0_PLL_CPUCL0, 0x0140, CPUCL0),
|
|
SFR(PLL_LOCKTIME_PLL_CPUCL0, 0x0000, CPUCL0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, 0x0120, CPUCL0),
|
|
SFR(PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER, 0x0128, CPUCL0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL, 0x1000, CPUCL0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK, 0x1814, CPUCL0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF, 0x180c, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, 0x2050, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK, 0x2048, CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK, 0x2008, CPUCL0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, 0x1800, CPUCL0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG, 0x1808, CPUCL0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK, 0x1804, CPUCL0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_CPU, 0x1810, CPUCL0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER, 0x0100, CPUCL0),
|
|
SFR(PLL_CON2_MUX_CLKCMU_CPUCL0_DBG_USER, 0x0108, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_IPCLKPORT_CLK, 0x2044, CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK, 0x2000, CPUCL0),
|
|
SFR(CLK_CON_GAT_GATE_CLK_CLUSTER0_CPU, 0x2010, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CSSYS_CORE_IPCLKPORT_PCLKM, 0x2014, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_CSSYS_FSYS_IPCLKPORT_HCLKS, 0x2018, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKS, 0x201c, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_P8Q_IPCLKPORT_PCLKS, 0x2020, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM, 0x2024, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK, 0x2034, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_D_CSSYS_IPCLKPORT_I_CLK, 0x2040, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM, 0x2028, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK, 0x2038, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK, 0x202c, CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C, 0x2004, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG, 0x2030, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK, 0x204c, CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK, 0x203c, CPUCL0),
|
|
SFR(QCH_CON_BUSIF_HPMCPUCL0_QCH, 0x3018, CPUCL0),
|
|
SFR(DMYQCH_CON_CLUSTER0_QCH_CPU, 0x3000, CPUCL0),
|
|
SFR(DMYQCH_CON_CLUSTER0_QCH_DBG, 0x3004, CPUCL0),
|
|
SFR(QCH_CON_CLUSTER0_QCH_LHS_ACE_D_CPUCL0, 0x301c, CPUCL0),
|
|
SFR(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH, 0x3020, CPUCL0),
|
|
SFR(QCH_CON_CPUCL0_CMU_CPUCL0_QCH, 0x3024, CPUCL0),
|
|
SFR(DMYQCH_CON_CSSYS_DBG_QCH, 0x3008, CPUCL0),
|
|
SFR(QCH_CON_DUMP_PC_CPUCL0_QCH, 0x3028, CPUCL0),
|
|
SFR(QCH_CON_DUMP_PC_CPUCL1_QCH, 0x302c, CPUCL0),
|
|
SFR(QCH_CON_LHM_AXI_P_CPUCL0_QCH, 0x3030, CPUCL0),
|
|
SFR(QCH_CON_LHS_AXI_D_CSSYS_QCH, 0x3034, CPUCL0),
|
|
SFR(QCH_CON_SECJTAG_QCH, 0x3038, CPUCL0),
|
|
SFR(QCH_CON_SYSREG_CPUCL0_QCH, 0x303c, CPUCL0),
|
|
SFR(PLL_CON0_PLL_CPUCL1, 0x0120, CPUCL1),
|
|
SFR(PLL_LOCKTIME_PLL_CPUCL1, 0x0000, CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL, 0x1000, CPUCL1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, 0x0100, CPUCL1),
|
|
SFR(PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER, 0x0108, CPUCL1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK, 0x1814, CPUCL1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF, 0x180c, CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK, 0x202c, CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK, 0x2008, CPUCL1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, 0x1800, CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK, 0x2024, CPUCL1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_CPU, 0x1810, CPUCL1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK, 0x1804, CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK, 0x2000, CPUCL1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG, 0x1818, CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKM, 0x2014, CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK, 0x2028, CPUCL1),
|
|
SFR(CLK_CON_GAT_GATE_CLK_CLUSTER1_CPU, 0x2010, CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C, 0x2004, CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK, 0x2018, CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK, 0x2030, CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK, 0x201c, CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK, 0x2020, CPUCL1),
|
|
SFR(DMYQCH_CON_ADM_APB_G_CSSYS_CPUCL1_QCH, 0x3000, CPUCL1),
|
|
SFR(QCH_CON_BUSIF_HPMCPUCL1_QCH, 0x3014, CPUCL1),
|
|
SFR(DMYQCH_CON_CLUSTER1_QCH_CPU, 0x3004, CPUCL1),
|
|
SFR(DMYQCH_CON_CLUSTER1_QCH_DBG, 0x3008, CPUCL1),
|
|
SFR(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH, 0x3018, CPUCL1),
|
|
SFR(QCH_CON_CPUCL1_CMU_CPUCL1_QCH, 0x301c, CPUCL1),
|
|
SFR(QCH_CON_LHM_AXI_P_CPUCL1_QCH, 0x3020, CPUCL1),
|
|
SFR(QCH_CON_LHS_ACE_D_CPUCL1_QCH, 0x3024, CPUCL1),
|
|
SFR(QCH_CON_SYSREG_CPUCL1_QCH, 0x3028, CPUCL1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_CPU, 0x180c, DISPAUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_CPU, 0x1004, DISPAUD),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DISPAUD_CPU_USER, 0x0120, DISPAUD),
|
|
SFR(PLL_CON2_MUX_CLKCMU_DISPAUD_CPU_USER, 0x0128, DISPAUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0x1814, DISPAUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0x1810, DISPAUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0x1824, DISPAUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0x1800, DISPAUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0x182c, DISPAUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0x1828, DISPAUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0x1010, DISPAUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0x1018, DISPAUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0x1014, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB, 0x202c, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK, 0x203c, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK, 0x2098, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK, 0x209c, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_AUD_IPCLKPORT_CLK, 0x20a4, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM, 0x207c, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK, 0x2080, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_AUD_IPCLKPORT_PCLK, 0x20bc, DISPAUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_OSCCLK_IPCLKPORT_CLK, 0x201c, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK, 0x2058, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_ACLK, 0x2084, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_PCLK, 0x2088, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK, 0x20b0, DISPAUD),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DISPAUD_DISP_USER, 0x0140, DISPAUD),
|
|
SFR(PLL_CON2_MUX_CLKCMU_DISPAUD_DISP_USER, 0x0148, DISPAUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP, 0x1830, DISPAUD),
|
|
SFR(PLL_CON0_PLL_AUD, 0x0160, DISPAUD),
|
|
SFR(PLL_CON3_PLL_AUD, 0x016c, DISPAUD),
|
|
SFR(PLL_LOCKTIME_PLL_AUD, 0x0000, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_ACEL_D_DPU_IPCLKPORT_I_CLK, 0x2074, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_DISP_IPCLKPORT_CLK, 0x20ac, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK, 0x20a8, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_ACLK, 0x208c, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_PCLK, 0x2090, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK, 0x20b8, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK, 0x2070, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK, 0x2094, DISPAUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 0x1008, DISPAUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK, 0x200c, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK, 0x2078, DISPAUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_DSIF, 0x1818, DISPAUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 0x1820, DISPAUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_FM, 0x100c, DISPAUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_FM, 0x181c, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY, 0x2028, DISPAUD),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DISPAUD_AUD_USER, 0x0100, DISPAUD),
|
|
SFR(PLL_CON2_MUX_CLKCMU_DISPAUD_AUD_USER, 0x0108, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK, 0x20b4, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_DISP, 0x2044, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_DBG, 0x2034, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK, 0x20a0, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON, 0x2060, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP, 0x2068, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA, 0x2064, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK, 0x2020, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_DSIF, 0x2024, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_OSC_SPDY, 0x2038, DISPAUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0, 0x2000, DISPAUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1, 0x2004, DISPAUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2, 0x2008, DISPAUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK, 0x2010, DISPAUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK, 0x2014, DISPAUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK, 0x2018, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_ACLK, 0x2048, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_PCLK, 0x204c, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_ACLK, 0x2050, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_PCLK, 0x2054, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_AUD, 0x2040, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7, 0x2030, DISPAUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_BUS, 0x1808, DISPAUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_BUS, 0x1000, DISPAUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK, 0x206c, DISPAUD),
|
|
SFR(DMYQCH_CON_ABOX_QCH_CPU, 0x3000, DISPAUD),
|
|
SFR(QCH_CON_ABOX_QCH_S_ACLK, 0x3014, DISPAUD),
|
|
SFR(QCH_CON_ABOX_QCH_S_BCLK0, 0x3018, DISPAUD),
|
|
SFR(QCH_CON_ABOX_QCH_S_BCLK2, 0x3020, DISPAUD),
|
|
SFR(QCH_CON_ABOX_QCH_S_BCLK1, 0x301c, DISPAUD),
|
|
SFR(DMYQCH_CON_ABOX_QCH_FM, 0x3004, DISPAUD),
|
|
SFR(QCH_CON_ABOX_QCH_S_BCLK_DSIF, 0x3024, DISPAUD),
|
|
SFR(QCH_CON_BTM_ABOX_QCH, 0x3028, DISPAUD),
|
|
SFR(QCH_CON_BTM_DPU_QCH, 0x302c, DISPAUD),
|
|
SFR(QCH_CON_DISPAUD_CMU_DISPAUD_QCH, 0x3030, DISPAUD),
|
|
SFR(QCH_CON_DPU_QCH_S_DPP, 0x303c, DISPAUD),
|
|
SFR(QCH_CON_DPU_QCH_S_DMA, 0x3038, DISPAUD),
|
|
SFR(QCH_CON_DPU_QCH_S_DECON, 0x3034, DISPAUD),
|
|
SFR(QCH_CON_GPIO_DISPAUD_QCH, 0x3040, DISPAUD),
|
|
SFR(QCH_CON_LHM_AXI_P_DISPAUD_QCH, 0x3044, DISPAUD),
|
|
SFR(QCH_CON_LHS_ACEL_D_DPU_QCH, 0x3048, DISPAUD),
|
|
SFR(QCH_CON_LHS_AXI_D_ABOX_QCH, 0x304c, DISPAUD),
|
|
SFR(QCH_CON_PPMU_ABOX_QCH, 0x3050, DISPAUD),
|
|
SFR(QCH_CON_PPMU_DPU_QCH, 0x3054, DISPAUD),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_AUD_CPU_CLKIN_QCH, 0x3058, DISPAUD),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH, 0x305c, DISPAUD),
|
|
SFR(QCH_CON_SMMU_ABOX_QCH, 0x3060, DISPAUD),
|
|
SFR(QCH_CON_SMMU_DPU_QCH, 0x3064, DISPAUD),
|
|
SFR(QCH_CON_SYSREG_DISPAUD_QCH, 0x3068, DISPAUD),
|
|
SFR(QCH_CON_WDT_AUD_QCH, 0x306c, DISPAUD),
|
|
SFR(PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER, 0x0100, FSYS),
|
|
SFR(PLL_CON2_MUX_CLKCMU_FSYS_BUS_USER, 0x0108, FSYS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER, 0x0120, FSYS),
|
|
SFR(PLL_CON2_MUX_CLKCMU_FSYS_MMC_CARD_USER, 0x0128, FSYS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER, 0x0140, FSYS),
|
|
SFR(PLL_CON2_MUX_CLKCMU_FSYS_MMC_EMBD_USER, 0x0148, FSYS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK, 0x204c, FSYS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK, 0x2044, FSYS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK, 0x203c, FSYS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK, 0x2014, FSYS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK, 0x2018, FSYS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_ACEL_D_FSYS_IPCLKPORT_I_CLK, 0x201c, FSYS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK, 0x2034, FSYS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK, 0x2038, FSYS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK, 0x2050, FSYS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_OSCCLK_IPCLKPORT_CLK, 0x2004, FSYS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK, 0x2060, FSYS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, 0x2008, FSYS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_FSYS_UFS_EMBD_USER, 0x0160, FSYS),
|
|
SFR(PLL_CON2_MUX_CLKCMU_FSYS_UFS_EMBD_USER, 0x0168, FSYS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK, 0x2000, FSYS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK, 0x2020, FSYS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK, 0x2028, FSYS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK, 0x2040, FSYS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK, 0x2048, FSYS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_ACLK, 0x2054, FSYS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, 0x205c, FSYS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_PGEN_LITE_FSYS_IPCLKPORT_CLK, 0x2030, FSYS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_ACLK, 0x200c, FSYS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_PCLK, 0x2010, FSYS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN, 0x2024, FSYS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN, 0x202c, FSYS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, 0x2058, FSYS),
|
|
SFR(QCH_CON_ADM_AHB_SSS_QCH, 0x3008, FSYS),
|
|
SFR(QCH_CON_BTM_FSYS_QCH, 0x300c, FSYS),
|
|
SFR(QCH_CON_FSYS_CMU_FSYS_QCH, 0x3010, FSYS),
|
|
SFR(QCH_CON_GPIO_FSYS_QCH, 0x3014, FSYS),
|
|
SFR(QCH_CON_LHM_AXI_P_FSYS_QCH, 0x3018, FSYS),
|
|
SFR(QCH_CON_LHS_ACEL_D_FSYS_QCH, 0x301c, FSYS),
|
|
SFR(QCH_CON_MMC_CARD_QCH, 0x3020, FSYS),
|
|
SFR(QCH_CON_MMC_EMBD_QCH, 0x3024, FSYS),
|
|
SFR(QCH_CON_PGEN_LITE_FSYS_QCH, 0x3028, FSYS),
|
|
SFR(QCH_CON_PPMU_FSYS_QCH, 0x302c, FSYS),
|
|
SFR(QCH_CON_RTIC_QCH, 0x3030, FSYS),
|
|
SFR(QCH_CON_SSS_QCH, 0x3034, FSYS),
|
|
SFR(QCH_CON_SYSREG_FSYS_QCH, 0x3038, FSYS),
|
|
SFR(QCH_CON_UFS_EMBD_QCH_UFS, 0x3040, FSYS),
|
|
SFR(QCH_CON_UFS_EMBD_QCH_FMP, 0x303c, FSYS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER, 0x0120, G2D),
|
|
SFR(PLL_CON2_MUX_CLKCMU_G2D_MSCL_USER, 0x0128, G2D),
|
|
SFR(CLK_CON_DIV_DIV_CLK_G2D_BUSP, 0x1800, G2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK, 0x2030, G2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK, 0x2058, G2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_MSCL_IPCLKPORT_CLK, 0x2050, G2D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G2D_UID_RSTNSYNC_CLK_G2D_OSCCLK_IPCLKPORT_CLK, 0x2004, G2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK, 0x2048, G2D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK, 0x2000, G2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_PCLK, 0x2044, G2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_FIMP_CLK, 0x202c, G2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_MSCL_IPCLKPORT_ACLK, 0x2038, G2D),
|
|
SFR(PLL_CON0_MUX_CLKCMU_G2D_G2D_USER, 0x0100, G2D),
|
|
SFR(PLL_CON2_MUX_CLKCMU_G2D_G2D_USER, 0x0108, G2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_IPCLKPORT_CLK, 0x204c, G2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKM, 0x2008, G2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKS, 0x200c, G2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKS, 0x2014, G2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKM, 0x2010, G2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D_G2D_IPCLKPORT_I_CLK, 0x2034, G2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_ACLK, 0x2040, G2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_G2D_IPCLKPORT_CLK, 0x2054, G2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_MSCL_IPCLKPORT_ACLK, 0x205c, G2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK, 0x2028, G2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_PGEN100_LITE_G2D_IPCLKPORT_CLK, 0x203c, G2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_MSCL, 0x201c, G2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_G2D, 0x2018, G2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_ACLK, 0x2020, G2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_PCLK, 0x2024, G2D),
|
|
SFR(QCH_CON_BTM_G2D_QCH, 0x3008, G2D),
|
|
SFR(QCH_CON_G2D_QCH, 0x3010, G2D),
|
|
SFR(QCH_CON_G2D_CMU_G2D_QCH, 0x300c, G2D),
|
|
SFR(QCH_CON_JPEG_QCH, 0x3014, G2D),
|
|
SFR(QCH_CON_LHM_AXI_P_G2D_QCH, 0x3018, G2D),
|
|
SFR(QCH_CON_LHS_ACEL_D_G2D_QCH, 0x301c, G2D),
|
|
SFR(QCH_CON_MSCL_QCH, 0x3020, G2D),
|
|
SFR(QCH_CON_PGEN100_LITE_G2D_QCH, 0x3024, G2D),
|
|
SFR(QCH_CON_PPMU_G2D_QCH, 0x3028, G2D),
|
|
SFR(QCH_CON_SYSMMU_G2D_QCH, 0x302c, G2D),
|
|
SFR(QCH_CON_SYSREG_G2D_QCH, 0x3030, G2D),
|
|
SFR(CLK_CON_DIV_DIV_CLK_G3D_BUSP, 0x1804, G3D),
|
|
SFR(PLL_CON0_PLL_G3D, 0x0120, G3D),
|
|
SFR(PLL_LOCKTIME_PLL_G3D, 0x0000, G3D),
|
|
SFR(CLK_CON_MUX_MUX_CLK_G3D_BUSD, 0x1004, G3D),
|
|
SFR(PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 0x0100, G3D),
|
|
SFR(PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER, 0x0108, G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK, 0x2030, G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK, 0x2028, G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, 0x2040, G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK, 0x203c, G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK, 0x200c, G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK, 0x2038, G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK, 0x2024, G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK, 0x2000, G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK, 0x2020, G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK, 0x2034, G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C, 0x2008, G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK, 0x201c, G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_ACLK, 0x2014, G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_PCLK, 0x2018, G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_IPCLKPORT_CLK, 0x2004, G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK, 0x202c, G3D),
|
|
SFR(CLK_CON_DIV_DIV_CLK_G3D_BUSD, 0x1800, G3D),
|
|
SFR(QCH_CON_BTM_G3D_QCH, 0x3010, G3D),
|
|
SFR(QCH_CON_BUSIF_HPMG3D_QCH, 0x3014, G3D),
|
|
SFR(QCH_CON_G3D_QCH, 0x301c, G3D),
|
|
SFR(QCH_CON_G3D_CMU_G3D_QCH, 0x3018, G3D),
|
|
SFR(QCH_CON_LHM_AXI_G3DSFR_QCH, 0x3020, G3D),
|
|
SFR(QCH_CON_LHM_AXI_P_G3D_QCH, 0x3024, G3D),
|
|
SFR(QCH_CON_LHS_AXI_D_G3D_QCH, 0x3028, G3D),
|
|
SFR(QCH_CON_LHS_AXI_G3DSFR_QCH, 0x302c, G3D),
|
|
SFR(QCH_CON_PGEN_LITE_G3D_QCH, 0x3030, G3D),
|
|
SFR(QCH_CON_SYSREG_G3D_QCH, 0x3034, G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_OSCCLK_IPCLKPORT_CLK, 0x2004, ISP),
|
|
SFR(PLL_CON0_MUX_CLKCMU_ISP_BUS_USER, 0x0100, ISP),
|
|
SFR(PLL_CON2_MUX_CLKCMU_ISP_BUS_USER, 0x0108, ISP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_ISP_BUSP, 0x1800, ISP),
|
|
SFR(PLL_CON0_MUX_CLKCMU_ISP_VRA_USER, 0x0140, ISP),
|
|
SFR(PLL_CON2_MUX_CLKCMU_ISP_VRA_USER, 0x0148, ISP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK, 0x2000, ISP),
|
|
SFR(PLL_CON0_MUX_CLKCMU_ISP_GDC_USER, 0x0120, ISP),
|
|
SFR(PLL_CON2_MUX_CLKCMU_ISP_GDC_USER, 0x0128, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK, 0x2078, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK, 0x2074, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_GDC_IPCLKPORT_CLK, 0x207c, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_VRA_IPCLKPORT_CLK, 0x2080, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK, 0x2084, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_AXI_P_ISP_IPCLKPORT_I_CLK, 0x2068, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D1_ISP_IPCLKPORT_I_CLK, 0x2070, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D0_ISP_IPCLKPORT_I_CLK, 0x206c, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP1, 0x205c, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_VRA, 0x2048, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_VRA, 0x2050, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_GDC, 0x204c, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_GDC, 0x2044, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP0, 0x2030, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP0, 0x2058, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP0, 0x2038, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_GDC, 0x2024, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_ISP, 0x2028, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_VRA, 0x2040, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_ATB_CAMISP_IPCLKPORT_I_CLK, 0x2064, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_BUSD, 0x2008, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_GDC, 0x200c, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_VRA, 0x2010, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP1, 0x2034, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP1, 0x203c, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_D_ISP, 0x2054, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_MCSC, 0x202c, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PGEN_LITE_ISP_PCLK, 0x2060, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_ACLK, 0x2014, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_PCLK, 0x2018, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_ACLK, 0x201c, ISP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_PCLK, 0x2020, ISP),
|
|
SFR(QCH_CON_BTM_ISP0_QCH, 0x3010, ISP),
|
|
SFR(QCH_CON_BTM_ISP1_QCH, 0x3014, ISP),
|
|
SFR(QCH_CON_ISP_CMU_ISP_QCH, 0x303c, ISP),
|
|
SFR(QCH_CON_LHM_ATB_CAMISP_QCH, 0x3040, ISP),
|
|
SFR(QCH_CON_LHM_AXI_P_ISP_QCH, 0x3044, ISP),
|
|
SFR(QCH_CON_LHS_ACEL_D0_ISP_QCH, 0x3048, ISP),
|
|
SFR(QCH_CON_LHS_ACEL_D1_ISP_QCH, 0x304c, ISP),
|
|
SFR(QCH_CON_SYSREG_ISP_QCH, 0x3050, ISP),
|
|
SFR(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_ISP, 0x301c, ISP),
|
|
SFR(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_MCSC, 0x3020, ISP),
|
|
SFR(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_VRA, 0x3038, ISP),
|
|
SFR(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP1, 0x302c, ISP),
|
|
SFR(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP0, 0x3028, ISP),
|
|
SFR(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_GDC, 0x3018, ISP),
|
|
SFR(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0, 0x3030, ISP),
|
|
SFR(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1, 0x3034, ISP),
|
|
SFR(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PGEN_LITE_ISP, 0x3024, ISP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MFC_BUSP, 0x1800, MFC),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MFC_WFD_USER, 0x0120, MFC),
|
|
SFR(PLL_CON2_MUX_CLKCMU_MFC_WFD_USER, 0x0128, MFC),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MFC_MFC_USER, 0x0100, MFC),
|
|
SFR(PLL_CON2_MUX_CLKCMU_MFC_MFC_USER, 0x0108, MFC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK, 0x2000, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKS, 0x200c, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKM, 0x2008, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_SI, 0x2038, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_MI, 0x2034, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK, 0x203c, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_PGEN100_LITE_MFC_IPCLKPORT_CLK, 0x2040, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_ACLK, 0x2044, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_PCLK, 0x2048, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_ACLK, 0x204c, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_PCLK, 0x2050, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD0_IPCLKPORT_CLK, 0x2070, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD1_IPCLKPORT_CLK, 0x2074, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK, 0x2078, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_WFD_IPCLKPORT_ACLK, 0x207c, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_XIU_D_MFC_IPCLKPORT_ACLK, 0x2080, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_MFC, 0x2010, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_WFD, 0x2014, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_IPCLKPORT_CLK, 0x2060, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_IPCLKPORT_CLK, 0x2068, MFC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC_UID_RSTNSYNC_CLK_MFC_OSCCLK_IPCLKPORT_CLK, 0x2004, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK, 0x2054, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK, 0x201c, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK, 0x2018, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK, 0x2020, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK, 0x2024, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK, 0x2028, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D0_MFC_IPCLKPORT_I_CLK, 0x202c, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D1_MFC_IPCLKPORT_I_CLK, 0x2030, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_IPCLKPORT_CLK, 0x2058, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_IPCLKPORT_CLK, 0x205c, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_SW_RESET_IPCLKPORT_CLK, 0x2064, MFC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_SW_RESET_IPCLKPORT_CLK, 0x206c, MFC),
|
|
SFR(QCH_CON_BTM_MFCD0_QCH, 0x300c, MFC),
|
|
SFR(QCH_CON_BTM_MFCD1_QCH, 0x3010, MFC),
|
|
SFR(QCH_CON_LHM_AXI_P_MFC_QCH, 0x3014, MFC),
|
|
SFR(QCH_CON_LHS_ACEL_D0_MFC_QCH, 0x3018, MFC),
|
|
SFR(QCH_CON_LHS_ACEL_D1_MFC_QCH, 0x301c, MFC),
|
|
SFR(QCH_CON_LH_ATB_MFC_QCH_S_SI, 0x3024, MFC),
|
|
SFR(QCH_CON_LH_ATB_MFC_QCH_S_MI, 0x3020, MFC),
|
|
SFR(QCH_CON_MFC_QCH, 0x302c, MFC),
|
|
SFR(QCH_CON_MFC_CMU_MFC_QCH, 0x3028, MFC),
|
|
SFR(QCH_CON_PGEN100_LITE_MFC_QCH, 0x3030, MFC),
|
|
SFR(QCH_CON_PPMU_MFCD0_QCH, 0x3034, MFC),
|
|
SFR(QCH_CON_PPMU_MFCD1_QCH, 0x3038, MFC),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_QCH, 0x303c, MFC),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_QCH, 0x3040, MFC),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC_MFC_SW_RESET_QCH, 0x3044, MFC),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC_WFD_SW_RESET_QCH, 0x3048, MFC),
|
|
SFR(QCH_CON_SYSMMU_MFCD0_QCH, 0x304c, MFC),
|
|
SFR(QCH_CON_SYSMMU_MFCD1_QCH, 0x3050, MFC),
|
|
SFR(QCH_CON_SYSREG_MFC_QCH, 0x3054, MFC),
|
|
SFR(QCH_CON_WFD_QCH, 0x3058, MFC),
|
|
SFR(CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X, 0x1008, MIF),
|
|
SFR(CLK_CON_MUX_MUX_MIF_CMUREF, 0x100c, MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK, 0x201c, MIF),
|
|
SFR(CLK_CON_DIV_CLK_MIF_BUSD, 0x1800, MIF),
|
|
SFR(PLL_CON0_PLL_MIF, 0x0120, MIF),
|
|
SFR(PLL_LOCKTIME_PLL_MIF, 0x0004, MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK, 0x204c, MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK, 0x2044, MIF),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER, 0x0100, MIF),
|
|
SFR(PLL_CON2_MUX_CLKCMU_MIF_BUSP_USER, 0x0108, MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_DDR_PHY_IPCLKPORT_PCLK, 0x2024, MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU, 0x2034, MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK, 0x203c, MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK, 0x2040, MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK, 0x2048, MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK, 0x2050, MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDR_PHY_IPCLKPORT_PCLK, 0x2054, MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK, 0x2058, MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK, 0x2060, MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK, 0x2064, MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK, 0x2068, MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK, 0x2014, MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK, 0x2018, MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK, 0x205c, MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF, 0x2030, MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE, 0x2038, MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK, 0x202c, MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C, 0x2000, MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK, 0x2020, MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_ACLK, 0x2028, MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CP_IPCLKPORT_I_CLK, 0x2008, MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CPU_IPCLKPORT_I_CLK, 0x2004, MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_NRT_IPCLKPORT_I_CLK, 0x200c, MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_RT_IPCLKPORT_I_CLK, 0x2010, MIF),
|
|
SFR(QCH_CON_BUSIF_HPMMIF_QCH, 0x3018, MIF),
|
|
SFR(DMYQCH_CON_CMU_MIF_CMUREF_QCH, 0x3000, MIF),
|
|
SFR(QCH_CON_DMC_QCH, 0x301c, MIF),
|
|
SFR(QCH_CON_LHM_AXI_D_MIF_CP_QCH, 0x3024, MIF),
|
|
SFR(QCH_CON_LHM_AXI_D_MIF_CPU_QCH, 0x3020, MIF),
|
|
SFR(QCH_CON_LHM_AXI_D_MIF_NRT_QCH, 0x3028, MIF),
|
|
SFR(QCH_CON_LHM_AXI_D_MIF_RT_QCH, 0x302c, MIF),
|
|
SFR(QCH_CON_LHM_AXI_P_MIF_QCH, 0x3030, MIF),
|
|
SFR(QCH_CON_MIF_CMU_MIF_QCH, 0x3034, MIF),
|
|
SFR(QCH_CON_PPMU_DMC_CPU_QCH, 0x3038, MIF),
|
|
SFR(QCH_CON_QE_DMC_CPU_QCH, 0x303c, MIF),
|
|
SFR(QCH_CON_SFRAPB_BRIDGE_DDR_PHY_QCH, 0x3040, MIF),
|
|
SFR(QCH_CON_SFRAPB_BRIDGE_DMC_QCH, 0x304c, MIF),
|
|
SFR(QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH, 0x3044, MIF),
|
|
SFR(QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH, 0x3048, MIF),
|
|
SFR(QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH, 0x3050, MIF),
|
|
SFR(QCH_CON_SYSREG_MIF_QCH, 0x3054, MIF),
|
|
SFR(PLL_CON0_PLL_MIF1, 0x0120, MIF1),
|
|
SFR(PLL_LOCKTIME_PLL_MIF1, 0x0000, MIF1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_MIF1_DDRPHY_CLK2X, 0x1004, MIF1),
|
|
SFR(CLK_CON_DIV_CLK_MIF1_BUSD, 0x1800, MIF1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MIF1_BUSP_USER, 0x0100, MIF1),
|
|
SFR(PLL_CON2_MUX_CLKCMU_MIF1_BUSP_USER, 0x0108, MIF1),
|
|
SFR(CLK_CON_MUX_MUX_MIF1_CMUREF, 0x1008, MIF1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK, 0x2000, MIF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_ACLK, 0x200c, MIF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C, 0x2020, MIF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK, 0x2004, MIF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK, 0x2010, MIF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PF, 0x2014, MIF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PPMPU, 0x2018, MIF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_SECURE, 0x201c, MIF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CP_IPCLKPORT_I_CLK, 0x2028, MIF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CPU_IPCLKPORT_I_CLK, 0x2024, MIF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_NRT_IPCLKPORT_I_CLK, 0x202c, MIF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_RT_IPCLKPORT_I_CLK, 0x2030, MIF1),
|
|
SFR(QCH_CON_BUSIF_HPMMIF1_QCH, 0x3014, MIF1),
|
|
SFR(DMYQCH_CON_CMU_MIF1_CMUREF_QCH, 0x3000, MIF1),
|
|
SFR(QCH_CON_DMC1_QCH, 0x3018, MIF1),
|
|
SFR(QCH_CON_LHM_AXI_D_MIF1_CP_QCH, 0x3020, MIF1),
|
|
SFR(QCH_CON_LHM_AXI_D_MIF1_CPU_QCH, 0x301c, MIF1),
|
|
SFR(QCH_CON_LHM_AXI_D_MIF1_NRT_QCH, 0x3024, MIF1),
|
|
SFR(QCH_CON_LHM_AXI_D_MIF1_RT_QCH, 0x3028, MIF1),
|
|
SFR(QCH_CON_MIF1_CMU_MIF1_QCH, 0x302c, MIF1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK, 0x2004, PERI),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 0x0100, PERI),
|
|
SFR(PLL_CON2_MUX_CLKCMU_PERI_BUS_USER, 0x0108, PERI),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERI_IP_USER, 0x0120, PERI),
|
|
SFR(PLL_CON2_MUX_CLKCMU_PERI_IP_USER, 0x0128, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_ACLK, 0x2020, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK, 0x2024, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK, 0x2068, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK, 0x2070, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK, 0x2078, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK, 0x20b0, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, 0x20cc, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, 0x20d0, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK, 0x206c, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_MOTOR_IPCLKPORT_I_PCLK_S0, 0x2074, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK, 0x2048, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_PCLK, 0x209c, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_PCLK, 0x20a4, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_PCLK, 0x20b8, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_PCLK, 0x202c, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_PCLK, 0x2034, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_PCLK, 0x203c, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_PCLK, 0x2044, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK, 0x20c0, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK, 0x20c8, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_PCLK, 0x20ac, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_IPCLKPORT_CLK, 0x208c, PERI),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERI_I2C, 0x2008, PERI),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERI_SPI0, 0x200c, PERI),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERI_SPI1, 0x2010, PERI),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERI_USI_USI, 0x201c, PERI),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERI_USI_I2C, 0x2018, PERI),
|
|
SFR(CLK_CON_GAT_GATE_CLK_PERI_SPI2, 0x2014, PERI),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERI_I2C, 0x1800, PERI),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERI_SPI0, 0x1804, PERI),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERI_SPI1, 0x1808, PERI),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERI_USI_I2C, 0x1814, PERI),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERI_USI_USI, 0x1818, PERI),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERI_SPI2, 0x180c, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_I2C_IPCLKPORT_CLK, 0x207c, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_0_IPCLKPORT_CLK, 0x2080, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_1_IPCLKPORT_CLK, 0x2084, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_I2C_IPCLKPORT_CLK, 0x2090, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK, 0x2094, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_2_IPCLKPORT_CLK, 0x2088, PERI),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK, 0x2000, PERI),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 0x0140, PERI),
|
|
SFR(PLL_CON2_MUX_CLKCMU_PERI_UART_USER, 0x0148, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_IPCLK, 0x20b4, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_IPCLK, 0x2028, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_IPCLK, 0x2030, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_IPCLK, 0x2038, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_IPCLK, 0x2040, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_0_IPCLKPORT_PCLK, 0x204c, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_1_IPCLKPORT_PCLK, 0x2050, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_2_IPCLKPORT_PCLK, 0x2054, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_3_IPCLKPORT_PCLK, 0x2058, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_4_IPCLKPORT_PCLK, 0x205c, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_5_IPCLKPORT_PCLK, 0x2060, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_6_IPCLKPORT_PCLK, 0x2064, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_IPCLK, 0x2098, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_IPCLK, 0x20a0, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_IPCLK, 0x20a8, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK, 0x20bc, PERI),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK, 0x20c4, PERI),
|
|
SFR(QCH_CON_BUSIF_TMU_QCH, 0x3004, PERI),
|
|
SFR(QCH_CON_CAMI2C_0_QCH, 0x3008, PERI),
|
|
SFR(QCH_CON_CAMI2C_1_QCH, 0x300c, PERI),
|
|
SFR(QCH_CON_CAMI2C_2_QCH, 0x3010, PERI),
|
|
SFR(QCH_CON_CAMI2C_3_QCH, 0x3014, PERI),
|
|
SFR(QCH_CON_GPIO_PERI_QCH, 0x3018, PERI),
|
|
SFR(QCH_CON_I2C_0_QCH, 0x301c, PERI),
|
|
SFR(QCH_CON_I2C_1_QCH, 0x3020, PERI),
|
|
SFR(QCH_CON_I2C_2_QCH, 0x3024, PERI),
|
|
SFR(QCH_CON_I2C_3_QCH, 0x3028, PERI),
|
|
SFR(QCH_CON_I2C_4_QCH, 0x302c, PERI),
|
|
SFR(QCH_CON_I2C_5_QCH, 0x3030, PERI),
|
|
SFR(QCH_CON_I2C_6_QCH, 0x3034, PERI),
|
|
SFR(QCH_CON_LHM_AXI_P_PERI_QCH, 0x3038, PERI),
|
|
SFR(QCH_CON_MCT_QCH, 0x303c, PERI),
|
|
SFR(QCH_CON_OTP_CON_TOP_QCH, 0x3040, PERI),
|
|
SFR(QCH_CON_PERI_CMU_PERI_QCH, 0x3044, PERI),
|
|
SFR(QCH_CON_PWM_MOTOR_QCH, 0x3048, PERI),
|
|
SFR(QCH_CON_SPI_0_QCH, 0x304c, PERI),
|
|
SFR(QCH_CON_SPI_1_QCH, 0x3050, PERI),
|
|
SFR(QCH_CON_SPI_2_QCH, 0x3054, PERI),
|
|
SFR(QCH_CON_SYSREG_PERI_QCH, 0x3058, PERI),
|
|
SFR(QCH_CON_UART_QCH, 0x305c, PERI),
|
|
SFR(QCH_CON_USI00_I2C_QCH, 0x3060, PERI),
|
|
SFR(QCH_CON_USI00_USI_QCH, 0x3064, PERI),
|
|
SFR(QCH_CON_WDT_CLUSTER0_QCH, 0x3068, PERI),
|
|
SFR(QCH_CON_WDT_CLUSTER1_QCH, 0x306c, PERI),
|
|
SFR(CLK_CON_MUX_MUX_CLK_SHUB_USI00, 0x1004, SHUB),
|
|
SFR(PLL_CON0_MUX_CLKCMU_SHUB_BUS_USER, 0x0100, SHUB),
|
|
SFR(PLL_CON2_MUX_CLKCMU_SHUB_BUS_USER, 0x0108, SHUB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_SHUB_USI01, 0x1808, SHUB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_SHUB_I2C, 0x1800, SHUB),
|
|
SFR(CLK_CON_MUX_MUX_CLK_SHUB_USI01, 0x1008, SHUB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_SHUB_USI00, 0x1804, SHUB),
|
|
SFR(CLK_CON_MUX_MUX_CLK_SHUB_I2C, 0x1000, SHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SHUB_UID_SHUB_CMU_SHUB_IPCLKPORT_PCLK, 0x2008, SHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_D_SHUB_IPCLKPORT_I_PCLK, 0x200c, SHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_P_APM_SHUB_IPCLKPORT_I_PCLK, 0x2010, SHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SHUB_UID_GPIO_SHUB_IPCLKPORT_PCLK, 0x2018, SHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_PCLK, 0x2020, SHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_LP_SHUB_IPCLKPORT_I_CLK, 0x2024, SHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_P_SHUB_IPCLKPORT_I_CLK, 0x2028, SHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_D_SHUB_IPCLKPORT_I_CLK, 0x202c, SHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_P_APM_SHUB_IPCLKPORT_I_CLK, 0x2030, SHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SHUB_UID_PWM_SHUB_IPCLKPORT_I_PCLK_S0, 0x2038, SHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_D_SHUB_IPCLKPORT_ACLK, 0x204c, SHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_P_APM_SHUB_IPCLKPORT_ACLK, 0x2050, SHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SHUB_UID_SYSREG_SHUB_IPCLKPORT_PCLK, 0x2054, SHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SHUB_UID_TIMER_SHUB_IPCLKPORT_PCLK, 0x2058, SHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_PCLK, 0x2060, SHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SHUB_UID_WDT_SHUB_IPCLKPORT_PCLK, 0x2064, SHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_BUS_IPCLKPORT_CLK, 0x203c, SHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_I2C_IPCLKPORT_CLK, 0x2040, SHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_OSCCLK_IPCLKPORT_CLK, 0x2000, SHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_RTCCLK_IPCLKPORT_CLK, 0x2004, SHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_USI00_IPCLKPORT_CLK, 0x2044, SHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SHUB_UID_CM4_SHUB_IPCLKPORT_FCLK, 0x2014, SHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_IPCLK, 0x201c, SHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SHUB_UID_PDMA_SHUB_IPCLKPORT_ACLK, 0x2034, SHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_IPCLK, 0x205c, SHUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SHUB_UID_XIU_DP_SHUB_IPCLKPORT_ACLK, 0x2068, SHUB),
|
|
SFR(QCH_CON_BAAW_D_SHUB_QCH, 0x3010, SHUB),
|
|
SFR(QCH_CON_BAAW_P_APM_SHUB_QCH, 0x3014, SHUB),
|
|
SFR(QCH_CON_CM4_SHUB_QCH, 0x3018, SHUB),
|
|
SFR(QCH_CON_GPIO_SHUB_QCH, 0x301c, SHUB),
|
|
SFR(QCH_CON_I2C_SHUB00_QCH, 0x3020, SHUB),
|
|
SFR(QCH_CON_LHM_AXI_LP_SHUB_QCH, 0x3024, SHUB),
|
|
SFR(QCH_CON_LHM_AXI_P_SHUB_QCH, 0x3028, SHUB),
|
|
SFR(QCH_CON_LHS_AXI_D_SHUB_QCH, 0x302c, SHUB),
|
|
SFR(QCH_CON_LHS_AXI_P_APM_SHUB_QCH, 0x3030, SHUB),
|
|
SFR(QCH_CON_PDMA_SHUB_QCH, 0x3034, SHUB),
|
|
SFR(QCH_CON_PWM_SHUB_QCH, 0x3038, SHUB),
|
|
SFR(QCH_CON_SHUB_CMU_SHUB_QCH, 0x303c, SHUB),
|
|
SFR(QCH_CON_SWEEPER_D_SHUB_QCH, 0x3040, SHUB),
|
|
SFR(QCH_CON_SWEEPER_P_APM_SHUB_QCH, 0x3044, SHUB),
|
|
SFR(QCH_CON_SYSREG_SHUB_QCH, 0x3048, SHUB),
|
|
SFR(QCH_CON_TIMER_SHUB_QCH, 0x304c, SHUB),
|
|
SFR(QCH_CON_USI_SHUB00_QCH, 0x3050, SHUB),
|
|
SFR(QCH_CON_WDT_SHUB_QCH, 0x3054, SHUB),
|
|
SFR(PLL_CON0_MUX_CLKCMU_USB_BUS_USER, 0x0100, USB),
|
|
SFR(PLL_CON2_MUX_CLKCMU_USB_BUS_USER, 0x0108, USB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK, 0x2004, USB),
|
|
SFR(PLL_CON0_MUX_CLKCMU_USB_USB30DRD_USER, 0x0140, USB),
|
|
SFR(PLL_CON2_MUX_CLKCMU_USB_USB30DRD_USER, 0x0148, USB),
|
|
SFR(PLL_CON0_MUX_CLKCMU_USB_DPGTC_USER, 0x0120, USB),
|
|
SFR(PLL_CON2_MUX_CLKCMU_USB_DPGTC_USER, 0x0128, USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_LHM_AXI_P_USB_IPCLKPORT_I_CLK, 0x2018, USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK, 0x2024, USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK, 0x2028, USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK, 0x2030, USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_BUS_CLK_EARLY, 0x2040, USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_DP_GTC_CLK, 0x2010, USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK, 0x202c, USB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_USB_UID_RSTNSYNC_CLK_USB_OSCCLK_IPCLKPORT_CLK, 0x2000, USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_20, 0x2034, USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_PGEN_LITE_USB_IPCLKPORT_CLK, 0x2020, USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_1, 0x203c, USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_ACLK, 0x2008, USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_PCLK, 0x200c, USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_US_D_USB_IPCLKPORT_ACLK, 0x2048, USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_PCLK, 0x2014, USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_0, 0x2038, USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_USB30DRD_REF_CLK, 0x2044, USB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_USB_UID_LHS_ACEL_D_USB_IPCLKPORT_I_CLK, 0x201c, USB),
|
|
SFR(QCH_CON_BTM_USB_QCH, 0x3008, USB),
|
|
SFR(QCH_CON_DP_LINK_QCH_DP, 0x300c, USB),
|
|
SFR(QCH_CON_DP_LINK_QCH_GTC, 0x3010, USB),
|
|
SFR(QCH_CON_LHM_AXI_P_USB_QCH, 0x3014, USB),
|
|
SFR(QCH_CON_LHS_ACEL_D_USB_QCH, 0x3018, USB),
|
|
SFR(QCH_CON_PGEN_LITE_USB_QCH, 0x301c, USB),
|
|
SFR(QCH_CON_PPMU_USB_QCH, 0x3020, USB),
|
|
SFR(QCH_CON_SYSREG_USB_QCH, 0x3024, USB),
|
|
SFR(QCH_CON_USB30DRD_QCH_USB30, 0x3028, USB),
|
|
SFR(QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_0, 0x3030, USB),
|
|
SFR(QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_1, 0x3034, USB),
|
|
SFR(QCH_CON_USB30DRD_QCH_USBPHY_20CTRL, 0x302c, USB),
|
|
SFR(QCH_CON_USB_CMU_USB_QCH, 0x3038, USB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VIPX1_BUSP, 0x1800, VIPX1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_VIPX1_BUS_USER, 0x0100, VIPX1),
|
|
SFR(PLL_CON2_MUX_CLKCMU_VIPX1_BUS_USER, 0x0108, VIPX1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ACEL_D_VIPX1_IPCLKPORT_I_CLK, 0x201c, VIPX1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSD_IPCLKPORT_CLK, 0x2034, VIPX1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSP_IPCLKPORT_CLK, 0x2038, VIPX1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_OSCCLK_IPCLKPORT_CLK, 0x2000, VIPX1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SYSREG_VIPX1_IPCLKPORT_PCLK, 0x2040, VIPX1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VIPX1_UID_VIPX1_CMU_VIPX1_IPCLKPORT_PCLK, 0x2004, VIPX1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ATB_VIPX1_IPCLKPORT_I_CLK, 0x2020, VIPX1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BLK_VIPX1_IPCLKPORT_CLK_VIPX1_BUSD, 0x2008, VIPX1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_ACLK, 0x202c, VIPX1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_PCLK, 0x2030, VIPX1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SMMU_D_VIPX1_IPCLKPORT_CLK, 0x203c, VIPX1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_XIU_D_VIPX1_IPCLKPORT_ACLK, 0x2050, VIPX1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PGEN_LITE_VIPX1_IPCLKPORT_CLK, 0x2028, VIPX1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_VIPX1_IPCLKPORT_CLK, 0x2044, VIPX1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_ACLK, 0x200c, VIPX1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_PCLK, 0x2010, VIPX1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_AXI_P_VIPX1_IPCLKPORT_I_CLK, 0x2018, VIPX1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_ATB_VIPX1_IPCLKPORT_I_CLK, 0x2014, VIPX1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_AXI_P_VIPX1_LOCAL_IPCLKPORT_I_CLK, 0x2024, VIPX1),
|
|
SFR(QCH_CON_BTM_D_VIPX1_QCH, 0x3014, VIPX1),
|
|
SFR(QCH_CON_LHM_ATB_VIPX1_QCH, 0x3018, VIPX1),
|
|
SFR(QCH_CON_LHM_AXI_P_VIPX1_QCH, 0x301c, VIPX1),
|
|
SFR(QCH_CON_LHS_ACEL_D_VIPX1_QCH, 0x3020, VIPX1),
|
|
SFR(QCH_CON_LHS_ATB_VIPX1_QCH, 0x3024, VIPX1),
|
|
SFR(QCH_CON_LHS_AXI_P_VIPX1_LOCAL_QCH, 0x3028, VIPX1),
|
|
SFR(QCH_CON_PGEN_LITE_VIPX1_QCH, 0x302c, VIPX1),
|
|
SFR(QCH_CON_PPMU_D_VIPX1_QCH, 0x3030, VIPX1),
|
|
SFR(QCH_CON_SMMU_D_VIPX1_QCH, 0x3034, VIPX1),
|
|
SFR(QCH_CON_SYSREG_VIPX1_QCH, 0x3038, VIPX1),
|
|
SFR(QCH_CON_VIPX1_QCH, 0x3040, VIPX1),
|
|
SFR(QCH_CON_VIPX1_CMU_VIPX1_QCH, 0x303c, VIPX1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VIPX2_BUSP, 0x1800, VIPX2),
|
|
SFR(PLL_CON0_MUX_CLKCMU_VIPX2_BUS_USER, 0x0100, VIPX2),
|
|
SFR(PLL_CON2_MUX_CLKCMU_VIPX2_BUS_USER, 0x0108, VIPX2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VIPX2_UID_VIPX2_CMU_VIPX2_IPCLKPORT_PCLK, 0x2004, VIPX2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_ACLK, 0x200c, VIPX2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_PCLK, 0x2010, VIPX2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_ATB_VIPX2_IPCLKPORT_I_CLK, 0x2014, VIPX2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_IPCLKPORT_I_CLK, 0x2018, VIPX2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ACEL_D_VIPX2_IPCLKPORT_I_CLK, 0x2020, VIPX2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ATB_VIPX2_IPCLKPORT_I_CLK, 0x2024, VIPX2),
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SFR(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_LOCAL_IPCLKPORT_I_CLK, 0x201c, VIPX2),
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SFR(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PGEN_LITE_VIPX2_IPCLKPORT_CLK, 0x2028, VIPX2),
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SFR(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_ACLK, 0x202c, VIPX2),
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SFR(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_PCLK, 0x2030, VIPX2),
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SFR(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SMMU_D_VIPX2_IPCLKPORT_CLK, 0x203c, VIPX2),
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SFR(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SYSREG_VIPX2_IPCLKPORT_PCLK, 0x2040, VIPX2),
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SFR(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BLK_VIPX2_IPCLKPORT_CLK_VIPX2_BUSD, 0x2008, VIPX2),
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SFR(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_VIPX2_IPCLKPORT_CLK, 0x2044, VIPX2),
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SFR(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSD_IPCLKPORT_CLK, 0x2034, VIPX2),
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SFR(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSP_IPCLKPORT_CLK, 0x2038, VIPX2),
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SFR(CLK_CON_GAT_CLK_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_OSCCLK_IPCLKPORT_CLK, 0x2000, VIPX2),
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SFR(QCH_CON_BTM_D_VIPX2_QCH, 0x3014, VIPX2),
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SFR(QCH_CON_LHM_ATB_VIPX2_QCH, 0x3018, VIPX2),
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SFR(QCH_CON_LHM_AXI_P_VIPX2_QCH, 0x3020, VIPX2),
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SFR(QCH_CON_LHM_AXI_P_VIPX2_LOCAL_QCH, 0x301c, VIPX2),
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SFR(QCH_CON_LHS_ACEL_D_VIPX2_QCH, 0x3024, VIPX2),
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SFR(QCH_CON_LHS_ATB_VIPX2_QCH, 0x3028, VIPX2),
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SFR(QCH_CON_PGEN_LITE_VIPX2_QCH, 0x302c, VIPX2),
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SFR(QCH_CON_PPMU_D_VIPX2_QCH, 0x3030, VIPX2),
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SFR(QCH_CON_SMMU_D_VIPX2_QCH, 0x3034, VIPX2),
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SFR(QCH_CON_SYSREG_VIPX2_QCH, 0x3038, VIPX2),
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SFR(QCH_CON_VIPX2_QCH, 0x3040, VIPX2),
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SFR(QCH_CON_VIPX2_QCH_LOCAL, 0x3044, VIPX2),
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SFR(QCH_CON_VIPX2_CMU_VIPX2_QCH, 0x303c, VIPX2),
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/*====================The section of controller option SFR instance===================*/
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SFR(APM_CMU_APM_CONTROLLER_OPTION, 0x0800, APM),
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SFR(CAM_CMU_CAM_CONTROLLER_OPTION, 0x0800, CAM),
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SFR(CMGP_CMU_CMGP_CONTROLLER_OPTION, 0x0800, CMGP),
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SFR(CMU_CMU_TOP_CONTROLLER_OPTION, 0x0800, TOP),
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|
SFR(CORE_CMU_CORE_CONTROLLER_OPTION, 0x0800, CORE),
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|
SFR(CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION, 0x0800, CPUCL0),
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|
SFR(CPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTION, 0x0804, CPUCL0),
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|
SFR(CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION, 0x0800, CPUCL1),
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|
SFR(CPUCL1_EMBEDDED_CMU_CPUCL1_CONTROLLER_OPTION, 0x0804, CPUCL1),
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|
SFR(DISPAUD_CMU_DISPAUD_CONTROLLER_OPTION, 0x0800, DISPAUD),
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|
SFR(FSYS_CMU_FSYS_CONTROLLER_OPTION, 0x0800, FSYS),
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|
SFR(G2D_CMU_G2D_CONTROLLER_OPTION, 0x0800, G2D),
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|
SFR(G3D_CMU_G3D_CONTROLLER_OPTION, 0x0800, G3D),
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|
SFR(ISP_CMU_ISP_CONTROLLER_OPTION, 0x0800, ISP),
|
|
SFR(MFC_CMU_MFC_CONTROLLER_OPTION, 0x0800, MFC),
|
|
SFR(MIF_CMU_MIF_CONTROLLER_OPTION, 0x0800, MIF),
|
|
SFR(MIF1_CMU_MIF1_CONTROLLER_OPTION, 0x0800, MIF1),
|
|
SFR(PERI_CMU_PERI_CONTROLLER_OPTION, 0x0800, PERI),
|
|
SFR(SHUB_CMU_SHUB_CONTROLLER_OPTION, 0x0800, SHUB),
|
|
SFR(USB_CMU_USB_CONTROLLER_OPTION, 0x0800, USB),
|
|
SFR(VIPX1_CMU_VIPX1_CONTROLLER_OPTION, 0x0800, VIPX1),
|
|
SFR(VIPX2_CMU_VIPX2_CONTROLLER_OPTION, 0x0800, VIPX2),
|
|
};
|
|
|
|
unsigned int cmucal_sfr_size = 1318;
|
|
unsigned int dbg_offset = 0x4000;
|
|
|
|
/*====================The section of SFR Access instance===================*/
|
|
struct sfr_access cmucal_sfr_access_list[] __initdata = {
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_APM_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_APM_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_APM_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_APM_BUS_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_APM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_APM_BUS_USER),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_APM_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_APM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_APM_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_APM_BUS),
|
|
SFR_ACCESS(PLL_CON0_MUX_DLL_USER_BUSY, 7, 1, PLL_CON0_MUX_DLL_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_DLL_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_DLL_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_DLL_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_DLL_USER),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_SHUB_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_SHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_SHUB_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_SHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_SHUB_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_SHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_SHUB_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_SHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_SHUB_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_SHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_SHUB_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_SHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_SHUB_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_SHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_SHUB_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_SHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_SHUB_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_SHUB_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_CMGP_BUS_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_CMGP_BUS_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_SHUB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_SHUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_SHUB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_SHUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_SHUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_MODEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_MODEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_SHUB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_SHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_SHUB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_SHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_SHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2SHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2SHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2WLBT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2WLBT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2WLBT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2WLBT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2WLBT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2SHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2SHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2GNSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2GNSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2GNSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2GNSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2ABOX_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2ABOX_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2ABOX_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2ABOX_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2ABOX_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_LITE_APM_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_LITE_APM_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_LITE_APM_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_LITE_APM_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_LITE_APM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_LITE_APM_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_WLBT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_WLBT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_WLBT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_WLBT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_WLBT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_WLBT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2WLBT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2WLBT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2WLBT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2WLBT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2WLBT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2GNSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2GNSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2SHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2SHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2WLBT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2WLBT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2WLBT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2WLBT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2WLBT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_RCO_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_RCO_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_RCO_IPCLKPORT_CLK),
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SFR_ACCESS(QCH_CON_APBIF_GPIO_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_APBIF_GPIO_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_APBIF_GPIO_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_GPIO_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_APBIF_GPIO_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_GPIO_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_APBIF_GPIO_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_GPIO_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_APBIF_PMU_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_PMU_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_PMU_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_PMU_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_APBIF_RTC_QCH_ENABLE, 0, 1, QCH_CON_APBIF_RTC_QCH),
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SFR_ACCESS(QCH_CON_APBIF_RTC_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_RTC_QCH),
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SFR_ACCESS(QCH_CON_APBIF_RTC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_RTC_QCH),
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SFR_ACCESS(QCH_CON_APBIF_RTC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_RTC_QCH),
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SFR_ACCESS(QCH_CON_APBIF_TOP_RTC_QCH_ENABLE, 0, 1, QCH_CON_APBIF_TOP_RTC_QCH),
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SFR_ACCESS(QCH_CON_APBIF_TOP_RTC_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_TOP_RTC_QCH),
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SFR_ACCESS(QCH_CON_APBIF_TOP_RTC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_TOP_RTC_QCH),
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SFR_ACCESS(QCH_CON_APBIF_TOP_RTC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_TOP_RTC_QCH),
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SFR_ACCESS(QCH_CON_APM_CMU_APM_QCH_ENABLE, 0, 1, QCH_CON_APM_CMU_APM_QCH),
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SFR_ACCESS(QCH_CON_APM_CMU_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_APM_CMU_APM_QCH),
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SFR_ACCESS(QCH_CON_APM_CMU_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APM_CMU_APM_QCH),
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SFR_ACCESS(QCH_CON_APM_CMU_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APM_CMU_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_GREBE_ENABLE, 0, 1, QCH_CON_GREBEINTEGRATION_QCH_GREBE),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_GREBE_CLOCK_REQ, 1, 1, QCH_CON_GREBEINTEGRATION_QCH_GREBE),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_GREBE_EXPIRE_VAL, 16, 10, QCH_CON_GREBEINTEGRATION_QCH_GREBE),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_GREBE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GREBEINTEGRATION_QCH_GREBE),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_DBG_ENABLE, 0, 1, QCH_CON_GREBEINTEGRATION_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_DBG_CLOCK_REQ, 1, 1, QCH_CON_GREBEINTEGRATION_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_DBG_EXPIRE_VAL, 16, 10, QCH_CON_GREBEINTEGRATION_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_DBG_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GREBEINTEGRATION_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_INTMEM_QCH_ENABLE, 0, 1, QCH_CON_INTMEM_QCH),
|
|
SFR_ACCESS(QCH_CON_INTMEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_INTMEM_QCH),
|
|
SFR_ACCESS(QCH_CON_INTMEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_INTMEM_QCH),
|
|
SFR_ACCESS(QCH_CON_INTMEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_INTMEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_GNSS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_APM_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_APM_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_APM_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_APM_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_MODEM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_APM_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_APM_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_MODEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_APM_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_APM_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_SHUB_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_APM_SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_APM_SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_APM_SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_APM_SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_WLBT_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_APM_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_WLBT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_APM_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_WLBT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_APM_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_WLBT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_APM_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_APM_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_LP_SHUB_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_LP_SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_LP_SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_LP_SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_LP_SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_LP_SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_LP_SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_LP_SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2CP_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2CP_S_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP2CP_S_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2CP_S_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP2CP_S_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2CP_S_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP2CP_S_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2CP_S_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP2CP_S_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2GNSS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2SHUB_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP2SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP2SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP2SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP2SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2WLBT_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP2WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2WLBT_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP2WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2WLBT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP2WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP2WLBT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP2WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2AP_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM2AP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2AP_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM2AP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2AP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM2AP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2AP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM2AP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2CP_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2GNSS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2SHUB_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM2SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM2SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM2SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM2SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2WLBT_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM2WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2WLBT_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM2WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2WLBT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM2WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM2WLBT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM2WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP2GNSS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_CP2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP2GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_CP2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP2GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_CP2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP2GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_CP2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP2SHUB_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_CP2SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP2SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_CP2SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP2SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_CP2SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP2SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_CP2SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP2WLBT_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_CP2WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP2WLBT_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_CP2WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP2WLBT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_CP2WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP2WLBT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_CP2WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_SHUB2GNSS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_SHUB2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_SHUB2GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_SHUB2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_SHUB2GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_SHUB2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_SHUB2GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_SHUB2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_SHUB2WLBT_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_SHUB2WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_SHUB2WLBT_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_SHUB2WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_SHUB2WLBT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_SHUB2WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_SHUB2WLBT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_SHUB2WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_WLBT2ABOX_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_WLBT2ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_WLBT2ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_WLBT2ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_WLBT2ABOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_WLBT2ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_WLBT2ABOX_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_WLBT2ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_WLBT2GNSS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_WLBT2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_WLBT2GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_WLBT2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_WLBT2GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_WLBT2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_WLBT2GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_WLBT2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_PEM_QCH_ENABLE, 0, 1, QCH_CON_PEM_QCH),
|
|
SFR_ACCESS(QCH_CON_PEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_PEM_QCH),
|
|
SFR_ACCESS(QCH_CON_PEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PEM_QCH),
|
|
SFR_ACCESS(QCH_CON_PEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PEM_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_LITE_APM_QCH_ENABLE, 0, 1, QCH_CON_PGEN_LITE_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_LITE_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_PGEN_LITE_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_LITE_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PGEN_LITE_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_LITE_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PGEN_LITE_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_PMU_INTR_GEN_QCH_ENABLE, 0, 1, QCH_CON_PMU_INTR_GEN_QCH),
|
|
SFR_ACCESS(QCH_CON_PMU_INTR_GEN_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_INTR_GEN_QCH),
|
|
SFR_ACCESS(QCH_CON_PMU_INTR_GEN_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_INTR_GEN_QCH),
|
|
SFR_ACCESS(QCH_CON_PMU_INTR_GEN_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PMU_INTR_GEN_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH),
|
|
SFR_ACCESS(QCH_CON_SPEEDY_APM_QCH_ENABLE, 0, 1, QCH_CON_SPEEDY_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SPEEDY_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPEEDY_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SPEEDY_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPEEDY_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SPEEDY_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPEEDY_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_APM_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_APM_QCH_ENABLE, 0, 1, QCH_CON_WDT_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_APM_QCH),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CAM_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CAM_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CAM_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CAM_BUS_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CAM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CAM_BUS_USER),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CAM_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CAM_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CAM_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CAM_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CAM_BUSP_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_CAM_BUSP),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ATB_CAMISP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ATB_CAMISP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ATB_CAMISP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ATB_CAMISP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ATB_CAMISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ATB_CAMISP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ACEL_D_CAM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ACEL_D_CAM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ACEL_D_CAM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ACEL_D_CAM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ACEL_D_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ACEL_D_CAM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CAM_UID_RSTNSYNC_CLK_CAM_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CAM_UID_RSTNSYNC_CLK_CAM_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CAM_UID_RSTNSYNC_CLK_CAM_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CAM_UID_RSTNSYNC_CLK_CAM_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CAM_UID_RSTNSYNC_CLK_CAM_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CAM_UID_RSTNSYNC_CLK_CAM_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_XIU_D_CAM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_XIU_D_CAM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_XIU_D_CAM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_XIU_D_CAM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_XIU_D_CAM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_XIU_D_CAM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PPMU_CAM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PPMU_CAM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PPMU_CAM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PPMU_CAM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PPMU_CAM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PPMU_CAM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PPMU_CAM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PPMU_CAM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PPMU_CAM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PPMU_CAM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PPMU_CAM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PPMU_CAM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_SMMU_CAM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_SMMU_CAM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_SMMU_CAM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_SMMU_CAM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_SMMU_CAM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_SMMU_CAM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_3AA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_3AA),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_3AA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_3AA),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_3AA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_3AA),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS2),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS2),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS2),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS3_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS3),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS3_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS3),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS3),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_BLK_CAM_IPCLKPORT_CLK_CAM_BUSD_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_BLK_CAM_IPCLKPORT_CLK_CAM_BUSD),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_BLK_CAM_IPCLKPORT_CLK_CAM_BUSD_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_BLK_CAM_IPCLKPORT_CLK_CAM_BUSD),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_BLK_CAM_IPCLKPORT_CLK_CAM_BUSD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_BLK_CAM_IPCLKPORT_CLK_CAM_BUSD),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_DMA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_DMA),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_DMA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_DMA),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_DMA),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PAFSTAT_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PAFSTAT_CORE),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PAFSTAT_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PAFSTAT_CORE),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PAFSTAT_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PAFSTAT_CORE),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_RDMA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_RDMA),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_RDMA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_RDMA),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_RDMA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_RDMA),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS2),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS2),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS2),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS3_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS3),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS3_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS3),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS3),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM1),
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SFR_ACCESS(QCH_CON_BTM_CAM_QCH_ENABLE, 0, 1, QCH_CON_BTM_CAM_QCH),
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SFR_ACCESS(QCH_CON_BTM_CAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_CAM_QCH),
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SFR_ACCESS(QCH_CON_BTM_CAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_CAM_QCH),
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SFR_ACCESS(QCH_CON_BTM_CAM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_CAM_QCH),
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SFR_ACCESS(QCH_CON_CAM_CMU_CAM_QCH_ENABLE, 0, 1, QCH_CON_CAM_CMU_CAM_QCH),
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SFR_ACCESS(QCH_CON_CAM_CMU_CAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_CAM_CMU_CAM_QCH),
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SFR_ACCESS(QCH_CON_CAM_CMU_CAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CAM_CMU_CAM_QCH),
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SFR_ACCESS(QCH_CON_CAM_CMU_CAM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CAM_CMU_CAM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_CAM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_CAM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_CAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_CAM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_CAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_CAM_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_CAM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_CAM_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_CAM_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D_CAM_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_CAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D_CAM_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_CAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D_CAM_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_CAM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D_CAM_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_CAMISP_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_CAMISP_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_CAMISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_CAMISP_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_CAMISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_CAMISP_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_CAMISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_CAMISP_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CAM_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CAM_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CAM_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CAM_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CAM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CAM_QCH),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS0_ENABLE, 0, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS0),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS0_CLOCK_REQ, 1, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS0),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS0_EXPIRE_VAL, 16, 10, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS0),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS0),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS1_ENABLE, 0, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS1),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS1_CLOCK_REQ, 1, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS1),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS1_EXPIRE_VAL, 16, 10, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS1),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS1),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS2_ENABLE, 0, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS2),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS2_CLOCK_REQ, 1, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS2),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS2_EXPIRE_VAL, 16, 10, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS2),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS2),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS3_ENABLE, 0, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS3),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS3_CLOCK_REQ, 1, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS3),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS3_EXPIRE_VAL, 16, 10, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS3),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS3_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS3),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_3AA_ENABLE, 0, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_3AA),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_3AA_CLOCK_REQ, 1, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_3AA),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_3AA_EXPIRE_VAL, 16, 10, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_3AA),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_3AA_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_3AA),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PPMU_ENABLE, 0, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PPMU),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PPMU_CLOCK_REQ, 1, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PPMU),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PPMU_EXPIRE_VAL, 16, 10, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PPMU),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PPMU_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PPMU),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_SMMU_ENABLE, 0, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_SMMU),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_SMMU_CLOCK_REQ, 1, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_SMMU),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_SMMU_EXPIRE_VAL, 16, 10, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_SMMU),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_SMMU_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_SMMU),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM0_PGEN_LITE_ENABLE, 0, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM0_PGEN_LITE),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM0_PGEN_LITE_CLOCK_REQ, 1, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM0_PGEN_LITE),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM0_PGEN_LITE_EXPIRE_VAL, 16, 10, QCH_CON_IS6P10P0_CAM_QCH_S_CAM0_PGEN_LITE),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM0_PGEN_LITE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM0_PGEN_LITE),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE_ENABLE, 0, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE_CLOCK_REQ, 1, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE_EXPIRE_VAL, 16, 10, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA_ENABLE, 0, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA_CLOCK_REQ, 1, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA_EXPIRE_VAL, 16, 10, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_RDMA_ENABLE, 0, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_RDMA),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_RDMA_CLOCK_REQ, 1, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_RDMA),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_RDMA_EXPIRE_VAL, 16, 10, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_RDMA),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM_RDMA_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_RDMA),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM1_PGEN_LITE_ENABLE, 0, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM1_PGEN_LITE),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM1_PGEN_LITE_CLOCK_REQ, 1, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM1_PGEN_LITE),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM1_PGEN_LITE_EXPIRE_VAL, 16, 10, QCH_CON_IS6P10P0_CAM_QCH_S_CAM1_PGEN_LITE),
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SFR_ACCESS(QCH_CON_IS6P10P0_CAM_QCH_S_CAM1_PGEN_LITE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM1_PGEN_LITE),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI03_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI03),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI03_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI03),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI03_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_USI03),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI00_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI00),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI00_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI00),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI00_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_USI00),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I2C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_I2C),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I2C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI01_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI01),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI01_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI01),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI01_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_USI01),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI04_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI04),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI04_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI04),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI04_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_USI04),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI01_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI01),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI01_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI01),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI01_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI01),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I2C_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_I2C),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_I2C),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I2C_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_I2C),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI00_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI00),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI00_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI00),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI00_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI00),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI04_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI04),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI04_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI04),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI04_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI04),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI02_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI02),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI02_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI02),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI02_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI02),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI02_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI02),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI02_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI02),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI02_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_USI02),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI03_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI03),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI03_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI03),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI03_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI03),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2SHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2SHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_ADC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_ADC),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_ADC),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_ADC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_ADC),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_ADC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_ADC),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_ADC),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_ADC_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_ADC),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI00_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI00_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI00_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI00_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI00_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI00_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI01_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI01_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI01_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI01_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI01_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI01_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI02_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI02_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI02_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI02_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI02_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI02_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI03_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI03_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI03_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI03_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI03_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI03_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI04_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI04_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI04_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI04_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI04_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI04_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_SHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_SHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(QCH_CON_ADC_CMGP_QCH_S0_ENABLE, 0, 1, QCH_CON_ADC_CMGP_QCH_S0),
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SFR_ACCESS(QCH_CON_ADC_CMGP_QCH_S0_CLOCK_REQ, 1, 1, QCH_CON_ADC_CMGP_QCH_S0),
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SFR_ACCESS(QCH_CON_ADC_CMGP_QCH_S0_EXPIRE_VAL, 16, 10, QCH_CON_ADC_CMGP_QCH_S0),
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SFR_ACCESS(QCH_CON_ADC_CMGP_QCH_S0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ADC_CMGP_QCH_S0),
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SFR_ACCESS(QCH_CON_ADC_CMGP_QCH_S1_ENABLE, 0, 1, QCH_CON_ADC_CMGP_QCH_S1),
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SFR_ACCESS(QCH_CON_ADC_CMGP_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_ADC_CMGP_QCH_S1),
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SFR_ACCESS(QCH_CON_ADC_CMGP_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_ADC_CMGP_QCH_S1),
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SFR_ACCESS(QCH_CON_ADC_CMGP_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ADC_CMGP_QCH_S1),
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SFR_ACCESS(DMYQCH_CON_ADC_CMGP_QCH_ADC_ENABLE, 0, 1, DMYQCH_CON_ADC_CMGP_QCH_ADC),
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SFR_ACCESS(DMYQCH_CON_ADC_CMGP_QCH_ADC_CLOCK_REQ, 1, 1, DMYQCH_CON_ADC_CMGP_QCH_ADC),
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SFR_ACCESS(DMYQCH_CON_ADC_CMGP_QCH_ADC_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADC_CMGP_QCH_ADC),
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SFR_ACCESS(QCH_CON_CMGP_CMU_CMGP_QCH_ENABLE, 0, 1, QCH_CON_CMGP_CMU_CMGP_QCH),
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SFR_ACCESS(QCH_CON_CMGP_CMU_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_CMGP_CMU_CMGP_QCH),
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SFR_ACCESS(QCH_CON_CMGP_CMU_CMGP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CMGP_CMU_CMGP_QCH),
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SFR_ACCESS(QCH_CON_CMGP_CMU_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CMGP_CMU_CMGP_QCH),
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|
SFR_ACCESS(QCH_CON_GPIO_CMGP_QCH_ENABLE, 0, 1, QCH_CON_GPIO_CMGP_QCH),
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SFR_ACCESS(QCH_CON_GPIO_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_CMGP_QCH),
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SFR_ACCESS(QCH_CON_GPIO_CMGP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_CMGP_QCH),
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SFR_ACCESS(QCH_CON_GPIO_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_CMGP_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CMGP00_QCH_ENABLE, 0, 1, QCH_CON_I2C_CMGP00_QCH),
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SFR_ACCESS(QCH_CON_I2C_CMGP00_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CMGP00_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CMGP00_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CMGP00_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CMGP00_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CMGP00_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CMGP01_QCH_ENABLE, 0, 1, QCH_CON_I2C_CMGP01_QCH),
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SFR_ACCESS(QCH_CON_I2C_CMGP01_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CMGP01_QCH),
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SFR_ACCESS(QCH_CON_I2C_CMGP01_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CMGP01_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CMGP01_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CMGP01_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CMGP02_QCH_ENABLE, 0, 1, QCH_CON_I2C_CMGP02_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CMGP02_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CMGP02_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_CMGP02_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CMGP02_QCH),
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SFR_ACCESS(QCH_CON_I2C_CMGP02_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CMGP02_QCH),
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SFR_ACCESS(QCH_CON_I2C_CMGP03_QCH_ENABLE, 0, 1, QCH_CON_I2C_CMGP03_QCH),
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SFR_ACCESS(QCH_CON_I2C_CMGP03_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CMGP03_QCH),
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SFR_ACCESS(QCH_CON_I2C_CMGP03_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CMGP03_QCH),
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SFR_ACCESS(QCH_CON_I2C_CMGP03_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CMGP03_QCH),
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SFR_ACCESS(QCH_CON_I2C_CMGP04_QCH_ENABLE, 0, 1, QCH_CON_I2C_CMGP04_QCH),
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SFR_ACCESS(QCH_CON_I2C_CMGP04_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CMGP04_QCH),
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SFR_ACCESS(QCH_CON_I2C_CMGP04_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CMGP04_QCH),
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SFR_ACCESS(QCH_CON_I2C_CMGP04_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CMGP04_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CMGP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CMGP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CMGP_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CMGP2CP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2CP_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CMGP2CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2CP_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CMGP2CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CMGP2CP_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CMGP2CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2CP_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CMGP2GNSS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2GNSS_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CMGP2GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2GNSS_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CMGP2GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CMGP2GNSS_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2GNSS_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_AP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2PMU_AP_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_AP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2PMU_AP_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_AP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CMGP2PMU_AP_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_AP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2PMU_AP_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_SHUB_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2PMU_SHUB_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2PMU_SHUB_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CMGP2PMU_SHUB_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2PMU_SHUB_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CMGP2SHUB_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2SHUB_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2SHUB_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CMGP2SHUB_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2SHUB_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2WLBT_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2WLBT_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2WLBT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2WLBT_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2WLBT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CMGP2WLBT_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2WLBT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2WLBT_QCH),
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|
SFR_ACCESS(QCH_CON_USI_CMGP00_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP00_QCH),
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|
SFR_ACCESS(QCH_CON_USI_CMGP00_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP00_QCH),
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|
SFR_ACCESS(QCH_CON_USI_CMGP00_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_CMGP00_QCH),
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|
SFR_ACCESS(QCH_CON_USI_CMGP00_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP00_QCH),
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|
SFR_ACCESS(QCH_CON_USI_CMGP01_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP01_QCH),
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|
SFR_ACCESS(QCH_CON_USI_CMGP01_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP01_QCH),
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|
SFR_ACCESS(QCH_CON_USI_CMGP01_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_CMGP01_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP01_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP01_QCH),
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|
SFR_ACCESS(QCH_CON_USI_CMGP02_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP02_QCH),
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|
SFR_ACCESS(QCH_CON_USI_CMGP02_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP02_QCH),
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|
SFR_ACCESS(QCH_CON_USI_CMGP02_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_CMGP02_QCH),
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|
SFR_ACCESS(QCH_CON_USI_CMGP02_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP02_QCH),
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|
SFR_ACCESS(QCH_CON_USI_CMGP03_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP03_QCH),
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|
SFR_ACCESS(QCH_CON_USI_CMGP03_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP03_QCH),
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|
SFR_ACCESS(QCH_CON_USI_CMGP03_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_CMGP03_QCH),
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|
SFR_ACCESS(QCH_CON_USI_CMGP03_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP03_QCH),
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|
SFR_ACCESS(QCH_CON_USI_CMGP04_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP04_QCH),
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|
SFR_ACCESS(QCH_CON_USI_CMGP04_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP04_QCH),
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|
SFR_ACCESS(QCH_CON_USI_CMGP04_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_CMGP04_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP04_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP04_QCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DISPAUD_DISP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_DISP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DISPAUD_DISP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_DISP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DISPAUD_DISP_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_DISP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DISPAUD_DISP_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_DISP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DISPAUD_DISP_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_DISP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DISPAUD_DISP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_DISP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DISPAUD_DISP_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_DISPAUD_DISP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DISPAUD_DISP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_DISPAUD_DISP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DISPAUD_DISP_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_DISPAUD_DISP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_FSYS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_FSYS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_MSCL_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_G2D_MSCL),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_G2D_MSCL),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_MSCL_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_G2D_MSCL),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0),
|
|
SFR_ACCESS(CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK_BUSY, 16, 1, CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK_DIVRATIO, 0, 4, CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERI_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERI_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERI_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_IP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_IP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_IP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_IP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_IP_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERI_IP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_IP_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_IP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_IP_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_IP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_IP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_IP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_IP_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERI_IP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_IP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERI_IP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_IP_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERI_IP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_APM_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_APM_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_APM_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_APM_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD_DIVRATIO, 0, 9, CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK0_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK0_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK1_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK2_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK2_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD_DIVRATIO, 0, 9, CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1),
|
|
SFR_ACCESS(CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK_BUSY, 16, 1, CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK_DIVRATIO, 0, 4, CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMU_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMU_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMU_CMUREF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMU_CMUREF_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_APM_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_APM_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_APM_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_APM_BUS),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED0_DIV_P, 8, 6, PLL_CON0_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED0_DIV_M, 16, 10, PLL_CON0_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED0_DIV_S, 0, 3, PLL_CON0_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED0_ENABLE, 31, 1, PLL_CON0_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED0_STABLE, 29, 1, PLL_CON0_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED0_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED1_DIV_P, 8, 6, PLL_CON0_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED1_DIV_M, 16, 10, PLL_CON0_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED1_DIV_S, 0, 3, PLL_CON0_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED1_ENABLE, 31, 1, PLL_CON0_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON0_PLL_SHARED1_STABLE, 29, 1, PLL_CON0_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED1_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV3_BUSY, 16, 1, CLK_CON_DIV_PLL_SHARED0_DIV3),
|
|
SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_PLL_SHARED0_DIV3),
|
|
SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV3_DIVRATIO, 0, 2, CLK_CON_DIV_PLL_SHARED0_DIV3),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL0_DBG),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_DBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL0_DBG),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_DBG_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CPUCL0_DBG),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG),
|
|
SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV2_BUSY, 16, 1, CLK_CON_DIV_PLL_SHARED0_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_PLL_SHARED0_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV2_DIVRATIO, 0, 1, CLK_CON_DIV_PLL_SHARED0_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV4_BUSY, 16, 1, CLK_CON_DIV_PLL_SHARED0_DIV4),
|
|
SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_PLL_SHARED0_DIV4),
|
|
SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV4_DIVRATIO, 0, 1, CLK_CON_DIV_PLL_SHARED0_DIV4),
|
|
SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV2_BUSY, 16, 1, CLK_CON_DIV_PLL_SHARED1_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_PLL_SHARED1_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV2_DIVRATIO, 0, 1, CLK_CON_DIV_PLL_SHARED1_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV4_BUSY, 16, 1, CLK_CON_DIV_PLL_SHARED1_DIV4),
|
|
SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_PLL_SHARED1_DIV4),
|
|
SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV4_DIVRATIO, 0, 1, CLK_CON_DIV_PLL_SHARED1_DIV4),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_CCI_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_CCI),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_CCI_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_CCI),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_CCI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_CCI),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_CCI_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CORE_CCI),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_CCI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CORE_CCI),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_CCI_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CORE_CCI),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_G3D_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_G3D_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_G3D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_G3D_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CORE_G3D),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_G3D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CORE_G3D),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_G3D_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CORE_G3D),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_CCI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CORE_CCI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_CCI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CORE_CCI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_CCI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CORE_CCI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_G3D_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_G3D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_G3D_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_BUSP_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV3_BUSY, 16, 1, CLK_CON_DIV_PLL_SHARED1_DIV3),
|
|
SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_PLL_SHARED1_DIV3),
|
|
SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV3_DIVRATIO, 0, 2, CLK_CON_DIV_PLL_SHARED1_DIV3),
|
|
SFR_ACCESS(PLL_CON0_PLL_MMC_DIV_P, 8, 6, PLL_CON0_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON0_PLL_MMC_DIV_M, 16, 10, PLL_CON0_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON0_PLL_MMC_DIV_S, 0, 3, PLL_CON0_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON0_PLL_MMC_ENABLE, 31, 1, PLL_CON0_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON0_PLL_MMC_STABLE, 29, 1, PLL_CON0_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON3_PLL_MMC_DIV_K, 0, 16, PLL_CON3_PLL_MMC),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_MMC_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MMC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS_UFS_EMBD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS_UFS_EMBD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_FSYS_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS_UFS_EMBD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS_UFS_EMBD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS_UFS_EMBD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_FSYS_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS_UFS_EMBD_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_FSYS_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CAM_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CAM_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CAM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CAM_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CAM_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CAM_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CAM_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CAM_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CAM_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CAM_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CAM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CAM_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CAM_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CAM_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CAM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CAM_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CAM_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CAM_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_VIPX1_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_VIPX1_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_VIPX1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_VIPX1_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_VIPX1_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_VIPX1_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_VIPX1_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_VIPX1_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_VIPX1_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_VIPX1_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_VIPX1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_VIPX1_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_VIPX1_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_VIPX1_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_VIPX1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_VIPX1_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_VIPX1_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_VIPX1_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISP_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_ISP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_ISP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISP_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_ISP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISP_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISP_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISP_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_ISP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISP_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_ISP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_ISP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISP_VRA_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_ISP_VRA),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISP_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_ISP_VRA),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISP_VRA_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_ISP_VRA),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISP_VRA_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_ISP_VRA),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISP_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_ISP_VRA),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISP_VRA_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_ISP_VRA),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISP_VRA_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_ISP_VRA),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISP_VRA_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_ISP_VRA),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISP_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_ISP_VRA),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISP_GDC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_ISP_GDC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISP_GDC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_ISP_GDC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISP_GDC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_ISP_GDC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISP_GDC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_ISP_GDC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISP_GDC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_ISP_GDC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISP_GDC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_ISP_GDC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISP_GDC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_ISP_GDC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISP_GDC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_ISP_GDC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISP_GDC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_ISP_GDC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_G2D_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_G2D_G2D),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_G2D_G2D),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_G2D_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_G2D_G2D),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DISPAUD_CPU_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DISPAUD_CPU_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DISPAUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DISPAUD_CPU_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_DISPAUD_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DISPAUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_DISPAUD_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DISPAUD_CPU_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_DISPAUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DISPAUD_CPU_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DISPAUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DISPAUD_CPU_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_MIF_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_MIF_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_MIF_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_USB_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_USB_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_USB_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_USB_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_USB_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_USB_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_USB_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_USB_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_USB_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_USB_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_USB_USB30DRD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_USB_USB30DRD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_USB_USB30DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_USB_USB30DRD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_USB_USB30DRD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_USB_USB30DRD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_USB_USB30DRD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_USB_USB30DRD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_USB_USB30DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_USB_USB30DRD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_USB_USB30DRD_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_USB_USB30DRD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_USB_USB30DRD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_USB_USB30DRD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_USB_USB30DRD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_USB_USB30DRD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_USB_USB30DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_USB_USB30DRD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_USB_DPGTC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_USB_DPGTC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_USB_DPGTC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_USB_DPGTC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_USB_DPGTC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_USB_DPGTC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_USB_DPGTC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_USB_DPGTC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_USB_DPGTC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_USB_DPGTC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_USB_DPGTC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_USB_DPGTC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_USB_DPGTC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_USB_DPGTC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_USB_DPGTC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_USB_DPGTC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_USB_DPGTC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_USB_DPGTC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DISPAUD_AUD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_DISPAUD_AUD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DISPAUD_AUD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_DISPAUD_AUD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DISPAUD_AUD_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_DISPAUD_AUD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DISPAUD_AUD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_AUD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DISPAUD_AUD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_AUD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DISPAUD_AUD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_AUD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DISPAUD_AUD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_AUD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DISPAUD_AUD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_AUD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DISPAUD_AUD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_AUD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC_WFD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MFC_WFD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC_WFD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MFC_WFD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MFC_WFD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC_MFC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MFC_MFC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MFC_MFC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC_MFC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MFC_MFC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC_WFD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MFC_WFD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MFC_WFD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC_WFD_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MFC_WFD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC_WFD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC_WFD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HPM_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HPM_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HPM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HPM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HPM_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HPM_DIVRATIO, 0, 2, CLK_CON_DIV_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_UART_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERI_UART),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_UART_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERI_UART),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERI_UART_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERI_UART),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_UART_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_UART),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_UART_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERI_UART),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERI_UART_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERI_UART),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_UART_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_UART),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_UART_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_UART),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERI_UART_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERI_UART),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_OTP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_OTP),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMU_UID_OTP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMU_UID_OTP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMU_UID_OTP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMU_UID_OTP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMU_UID_OTP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMU_UID_OTP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_VIPX2_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_VIPX2_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_VIPX2_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_VIPX2_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_VIPX2_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_VIPX2_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_VIPX2_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_VIPX2_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_VIPX2_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_VIPX2_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_VIPX2_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_VIPX2_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_VIPX2_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_VIPX2_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_VIPX2_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_VIPX2_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_VIPX2_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_VIPX2_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK3_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK3_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_DIV_PLL_MMC_DIV2_BUSY, 16, 1, CLK_CON_DIV_PLL_MMC_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_PLL_MMC_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_PLL_MMC_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_PLL_MMC_DIV2_DIVRATIO, 0, 1, CLK_CON_DIV_PLL_MMC_DIV2),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_TOP_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_TOP_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_TOP_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_TOP_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_TOP_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_TOP_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS0_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS0),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS0_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS0),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS0_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS0),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS1_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS1),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS1_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS1),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS1_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS1),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS2_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS2),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS2_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS2),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS2_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS2),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS3_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS3),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS3_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS3),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS3_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS3),
|
|
SFR_ACCESS(DMYQCH_CON_OTP_QCH_ENABLE, 0, 1, DMYQCH_CON_OTP_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_OTP_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_OTP_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_OTP_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_OTP_QCH),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CORE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CORE_BUS_USER),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CORE_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CORE_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CORE_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CORE_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CORE_BUSP_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_CORE_BUSP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CORE_GIC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CORE_GIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CORE_GIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CORE_GIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CORE_GIC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CORE_GIC),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CORE_CCI_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CORE_CCI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CORE_CCI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CORE_CCI_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CORE_CCI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CORE_CCI_USER),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM),
|
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC400_AIHWACG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC400_AIHWACG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC400_AIHWACG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC400_AIHWACG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC400_AIHWACG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC400_AIHWACG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_DPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_DPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_DPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_CAM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_CAM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_CAM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_CAM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_CAM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_OCC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_OCC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_OCC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_OCC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_OCC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_OCC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_OCC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_OCC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_OCC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_OCC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_OCC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_OCC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_CCI_550_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_CCI_550_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_CCI_550_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_CCI_550_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_CCI_550_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_CCI_550_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CORE_G3D_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CORE_G3D_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CORE_G3D_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CORE_G3D_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CORE_G3D_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CORE_G3D_USER),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_OCC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_OCC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_OCC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_OCC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_OCC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_OCC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_NRT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_NRT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_NRT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_NRT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_NRT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_NRT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_NRT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_NRT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_NRT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_NRT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC0_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC0_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC0_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC0_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC0_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_ISP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_ISP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_ISP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_ISP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_ISP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_FSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_FSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_FSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_FSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_FSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_FSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_ISP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_ISP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_ISP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_ISP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_ISP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_G2D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_G2D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_G2D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_G2D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_G2D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_SHUB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_SHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_SHUB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_SHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_SHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_SHUB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_SHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_SHUB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_SHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_SHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_WLBT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_WLBT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_WLBT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_WLBT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_WLBT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_WLBT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_ISP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_ISP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_ISP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_ISP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_ISP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_RT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_RT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_RT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_RT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_RT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_RT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_RT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_RT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_RT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_RT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_MFC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_MFC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_MFC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_MFC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_MFC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_MFC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_MFC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_MFC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_MFC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_MFC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_USB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_USB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_USB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_USB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_USB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_USB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_USB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_USB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_USB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_USB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC1_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC1_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_PERI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_PERI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_PERI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_PERI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_PERI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_PERI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_SHUB_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_SHUB_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_SHUB_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_SHUB_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_SHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_SHUB_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_550_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_550_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_550_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_550_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_550_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_550_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_CCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_CCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_CCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_CCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_CCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_CCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_LITE_SIREX_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_LITE_SIREX_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_LITE_SIREX_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_LITE_SIREX_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_LITE_SIREX_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_LITE_SIREX_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_CCLK_P_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_CCLK_P_CORE),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_CCLK_P_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_CCLK_P_CORE),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_CCLK_P_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_CCLK_P_CORE),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM1_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM1_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM1_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM1_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM1_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_PERI_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_PERI_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_PERI_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_PERI_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_PERI_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_PERI_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_US_A40_64TO128_DIT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_US_A40_64TO128_DIT_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_US_A40_64TO128_DIT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_US_A40_64TO128_DIT_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_US_A40_64TO128_DIT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_US_A40_64TO128_DIT_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_PDMA_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_PDMA_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_PDMA_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_PDMA_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_PDMA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_PDMA_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PGEN_PDMA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PGEN_PDMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PGEN_PDMA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PGEN_PDMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PGEN_PDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PGEN_PDMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(QCH_CON_BAAW_P_GNSS_QCH_ENABLE, 0, 1, QCH_CON_BAAW_P_GNSS_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_P_GNSS_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_P_GNSS_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_P_GNSS_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_MODEM_QCH_ENABLE, 0, 1, QCH_CON_BAAW_P_MODEM_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_P_MODEM_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_MODEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_P_MODEM_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_P_MODEM_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_SHUB_QCH_ENABLE, 0, 1, QCH_CON_BAAW_P_SHUB_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_P_SHUB_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_P_SHUB_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_P_SHUB_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_WLBT_QCH_ENABLE, 0, 1, QCH_CON_BAAW_P_WLBT_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_WLBT_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_P_WLBT_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_WLBT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_P_WLBT_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_WLBT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_P_WLBT_QCH),
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SFR_ACCESS(QCH_CON_CCI_550_QCH_ENABLE, 0, 1, QCH_CON_CCI_550_QCH),
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SFR_ACCESS(QCH_CON_CCI_550_QCH_CLOCK_REQ, 1, 1, QCH_CON_CCI_550_QCH),
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SFR_ACCESS(QCH_CON_CCI_550_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CCI_550_QCH),
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SFR_ACCESS(QCH_CON_CCI_550_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CCI_550_QCH),
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SFR_ACCESS(QCH_CON_CORE_CMU_CORE_QCH_ENABLE, 0, 1, QCH_CON_CORE_CMU_CORE_QCH),
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SFR_ACCESS(QCH_CON_CORE_CMU_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_CORE_CMU_CORE_QCH),
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SFR_ACCESS(QCH_CON_CORE_CMU_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CORE_CMU_CORE_QCH),
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SFR_ACCESS(QCH_CON_CORE_CMU_CORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CORE_CMU_CORE_QCH),
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SFR_ACCESS(QCH_CON_DIT_QCH_ENABLE, 0, 1, QCH_CON_DIT_QCH),
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SFR_ACCESS(QCH_CON_DIT_QCH_CLOCK_REQ, 1, 1, QCH_CON_DIT_QCH),
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SFR_ACCESS(QCH_CON_DIT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DIT_QCH),
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SFR_ACCESS(QCH_CON_DIT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DIT_QCH),
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SFR_ACCESS(QCH_CON_GIC400_AIHWACG_QCH_ENABLE, 0, 1, QCH_CON_GIC400_AIHWACG_QCH),
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SFR_ACCESS(QCH_CON_GIC400_AIHWACG_QCH_CLOCK_REQ, 1, 1, QCH_CON_GIC400_AIHWACG_QCH),
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SFR_ACCESS(QCH_CON_GIC400_AIHWACG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GIC400_AIHWACG_QCH),
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SFR_ACCESS(QCH_CON_GIC400_AIHWACG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GIC400_AIHWACG_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D0_ISP_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D0_ISP_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D0_ISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D0_ISP_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D0_ISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D0_ISP_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D0_ISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D0_ISP_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D0_MFC_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D0_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D0_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D0_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D0_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D0_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D0_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D0_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D1_ISP_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D1_ISP_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D1_ISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D1_ISP_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D1_ISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D1_ISP_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D1_ISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D1_ISP_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D1_MFC_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D1_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D1_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D1_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D1_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D1_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D1_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D1_MFC_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_CAM_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D_CAM_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D_CAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D_CAM_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D_CAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D_CAM_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_CAM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D_CAM_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_DPU_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D_DPU_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D_DPU_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D_DPU_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D_DPU_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_FSYS_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D_FSYS_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D_FSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D_FSYS_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D_FSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D_FSYS_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D_FSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D_FSYS_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_G2D_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D_G2D_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D_G2D_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D_G2D_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D_G2D_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_USB_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D_USB_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D_USB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D_USB_QCH),
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SFR_ACCESS(QCH_CON_LHM_ACEL_D_USB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D_USB_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_USB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D_USB_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_VIPX1_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D_VIPX1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_VIPX1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D_VIPX1_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_VIPX1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D_VIPX1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_VIPX1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D_VIPX1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_VIPX2_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D_VIPX2_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_VIPX2_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D_VIPX2_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_VIPX2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D_VIPX2_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_VIPX2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D_VIPX2_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACE_D_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACE_D_CPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_ACE_D_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACE_D_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACE_D_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACE_D_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACE_D_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACE_D_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACE_D_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D_CPUCL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACE_D_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_MODEM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D0_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D0_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_MODEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D0_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D0_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MODEM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D1_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D1_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MODEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D1_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D1_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_ABOX_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_ABOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_ABOX_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_APM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_GNSS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_SHUB_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_WLBT_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_WLBT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_WLBT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_WLBT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MIF_CP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D0_MIF_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MIF_CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D0_MIF_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MIF_CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D0_MIF_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MIF_CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D0_MIF_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MIF_CPU_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D0_MIF_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MIF_CPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D0_MIF_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MIF_CPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D0_MIF_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MIF_CPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D0_MIF_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MIF_NRT_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D0_MIF_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MIF_NRT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D0_MIF_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MIF_NRT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D0_MIF_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MIF_NRT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D0_MIF_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MIF_RT_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D0_MIF_RT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MIF_RT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D0_MIF_RT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MIF_RT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D0_MIF_RT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MIF_RT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D0_MIF_RT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MIF_CP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D1_MIF_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MIF_CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D1_MIF_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MIF_CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D1_MIF_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MIF_CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D1_MIF_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MIF_CPU_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D1_MIF_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MIF_CPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D1_MIF_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MIF_CPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D1_MIF_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MIF_CPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D1_MIF_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MIF_NRT_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D1_MIF_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MIF_NRT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D1_MIF_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MIF_NRT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D1_MIF_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MIF_NRT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D1_MIF_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MIF_RT_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D1_MIF_RT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MIF_RT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D1_MIF_RT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MIF_RT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D1_MIF_RT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MIF_RT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D1_MIF_RT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_APM_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CAM_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_CAM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_CAM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_CAM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CAM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_CAM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DISPAUD_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_DISPAUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DISPAUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_DISPAUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DISPAUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_DISPAUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DISPAUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_DISPAUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_FSYS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_FSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_FSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_FSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_FSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_FSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_FSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_FSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_G2D_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_G2D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_GNSS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_GNSS_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_GNSS_QCH),
|
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SFR_ACCESS(QCH_CON_LHS_AXI_P_GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_ISP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_ISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_ISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_ISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_ISP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MFC_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_MFC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MIF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MIF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MIF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_MIF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MIF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MIF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MIF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_MIF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MODEM_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MODEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERI_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERI_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_SHUB_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_SHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_USB_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_USB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_USB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_USB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VIPX1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_VIPX1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VIPX1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_VIPX1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VIPX1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_VIPX1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VIPX1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_VIPX1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VIPX2_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_VIPX2_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VIPX2_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_VIPX2_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VIPX2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_VIPX2_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VIPX2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_VIPX2_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_WLBT_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_WLBT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_WLBT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_WLBT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_WLBT_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_CORE_QCH_ENABLE, 0, 1, QCH_CON_PDMA_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_PDMA_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PDMA_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_CORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PDMA_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_LITE_SIREX_QCH_ENABLE, 0, 1, QCH_CON_PGEN_LITE_SIREX_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_LITE_SIREX_QCH_CLOCK_REQ, 1, 1, QCH_CON_PGEN_LITE_SIREX_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_LITE_SIREX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PGEN_LITE_SIREX_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_LITE_SIREX_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PGEN_LITE_SIREX_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_PDMA_QCH_ENABLE, 0, 1, QCH_CON_PGEN_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_PDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_PGEN_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_PDMA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PGEN_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_PGEN_PDMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PGEN_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_PPCFW_G3D_QCH_ENABLE, 0, 1, QCH_CON_PPCFW_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_PPCFW_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPCFW_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_PPCFW_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPCFW_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_PPCFW_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPCFW_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_CORE_MEM0_QCH_ENABLE, 0, 1, QCH_CON_PPFW_CORE_MEM0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_CORE_MEM0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPFW_CORE_MEM0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_CORE_MEM0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPFW_CORE_MEM0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_CORE_MEM0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPFW_CORE_MEM0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_CORE_MEM1_QCH_ENABLE, 0, 1, QCH_CON_PPFW_CORE_MEM1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_CORE_MEM1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPFW_CORE_MEM1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_CORE_MEM1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPFW_CORE_MEM1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_CORE_MEM1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPFW_CORE_MEM1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_CORE_PERI_QCH_ENABLE, 0, 1, QCH_CON_PPFW_CORE_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_CORE_PERI_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPFW_CORE_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_CORE_PERI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPFW_CORE_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_PPFW_CORE_PERI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPFW_CORE_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_ACE_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_ACE_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_ACE_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_ACE_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_ACE_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_ACE_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_ACE_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_ACE_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_ACE_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_ACE_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_ACE_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_ACE_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_ACE_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_ACE_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_ACE_CPUCL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_ACE_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CORE_BUSP_OCC_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_OCC_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CORE_BUSP_OCC_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_OCC_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CORE_BUSP_OCC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_OCC_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CORE_BUSP_OCC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_OCC_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CORE_CCI_OCC_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_CORE_CCI_OCC_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CORE_CCI_OCC_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_CORE_CCI_OCC_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CORE_CCI_OCC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_CORE_CCI_OCC_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CORE_CCI_OCC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_CORE_CCI_OCC_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CORE_G3D_OCC_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_CORE_G3D_OCC_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CORE_G3D_OCC_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_CORE_G3D_OCC_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CORE_G3D_OCC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_CORE_G3D_OCC_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CORE_G3D_OCC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_CORE_G3D_OCC_QCH),
|
|
SFR_ACCESS(QCH_CON_SFR_APBIF_CMU_TOPC_QCH_ENABLE, 0, 1, QCH_CON_SFR_APBIF_CMU_TOPC_QCH),
|
|
SFR_ACCESS(QCH_CON_SFR_APBIF_CMU_TOPC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SFR_APBIF_CMU_TOPC_QCH),
|
|
SFR_ACCESS(QCH_CON_SFR_APBIF_CMU_TOPC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SFR_APBIF_CMU_TOPC_QCH),
|
|
SFR_ACCESS(QCH_CON_SFR_APBIF_CMU_TOPC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SFR_APBIF_CMU_TOPC_QCH),
|
|
SFR_ACCESS(QCH_CON_SIREX_QCH_ENABLE, 0, 1, QCH_CON_SIREX_QCH),
|
|
SFR_ACCESS(QCH_CON_SIREX_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIREX_QCH),
|
|
SFR_ACCESS(QCH_CON_SIREX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SIREX_QCH),
|
|
SFR_ACCESS(QCH_CON_SIREX_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIREX_QCH),
|
|
SFR_ACCESS(QCH_CON_SPDMA_CORE_QCH_ENABLE, 0, 1, QCH_CON_SPDMA_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SPDMA_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPDMA_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SPDMA_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPDMA_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SPDMA_CORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPDMA_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CORE_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_CORE_QCH_ENABLE, 0, 1, QCH_CON_TREX_D_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_D_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_CORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_D_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_NRT_QCH_ENABLE, 0, 1, QCH_CON_TREX_D_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_NRT_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_NRT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_D_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_NRT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_D_NRT_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_CORE_QCH_ENABLE, 0, 1, QCH_CON_TREX_P_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_P_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_P_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_CORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_P_CORE_QCH),
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SFR_ACCESS(PLL_CON0_PLL_CPUCL0_DIV_P, 8, 6, PLL_CON0_PLL_CPUCL0),
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SFR_ACCESS(PLL_CON0_PLL_CPUCL0_DIV_M, 16, 10, PLL_CON0_PLL_CPUCL0),
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SFR_ACCESS(PLL_CON0_PLL_CPUCL0_DIV_S, 0, 3, PLL_CON0_PLL_CPUCL0),
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SFR_ACCESS(PLL_CON0_PLL_CPUCL0_ENABLE, 31, 1, PLL_CON0_PLL_CPUCL0),
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SFR_ACCESS(PLL_CON0_PLL_CPUCL0_STABLE, 29, 1, PLL_CON0_PLL_CPUCL0),
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SFR_ACCESS(PLL_LOCKTIME_PLL_CPUCL0_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_CPUCL0),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU),
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|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER),
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|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER),
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|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CPUCL0_DBG_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CPUCL0_DBG_USER),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CLUSTER0_CPU_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_CLUSTER0_CPU),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CLUSTER0_CPU_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_CLUSTER0_CPU),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CLUSTER0_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_CLUSTER0_CPU),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CSSYS_CORE_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CSSYS_CORE_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CSSYS_CORE_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CSSYS_CORE_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CSSYS_CORE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CSSYS_CORE_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_CSSYS_FSYS_IPCLKPORT_HCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_CSSYS_FSYS_IPCLKPORT_HCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_CSSYS_FSYS_IPCLKPORT_HCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_CSSYS_FSYS_IPCLKPORT_HCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_CSSYS_FSYS_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_CSSYS_FSYS_IPCLKPORT_HCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_P8Q_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_P8Q_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_P8Q_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_P8Q_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_P8Q_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_P8Q_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_D_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_D_CSSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_D_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_D_CSSYS_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_D_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_D_CSSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C),
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|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C),
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|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(QCH_CON_BUSIF_HPMCPUCL0_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPMCPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPMCPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPMCPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_BUSIF_HPMCPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPMCPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPMCPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_HPMCPUCL0_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CLUSTER0_QCH_CPU_ENABLE, 0, 1, DMYQCH_CON_CLUSTER0_QCH_CPU),
|
|
SFR_ACCESS(DMYQCH_CON_CLUSTER0_QCH_CPU_CLOCK_REQ, 1, 1, DMYQCH_CON_CLUSTER0_QCH_CPU),
|
|
SFR_ACCESS(DMYQCH_CON_CLUSTER0_QCH_CPU_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CLUSTER0_QCH_CPU),
|
|
SFR_ACCESS(DMYQCH_CON_CLUSTER0_QCH_DBG_ENABLE, 0, 1, DMYQCH_CON_CLUSTER0_QCH_DBG),
|
|
SFR_ACCESS(DMYQCH_CON_CLUSTER0_QCH_DBG_CLOCK_REQ, 1, 1, DMYQCH_CON_CLUSTER0_QCH_DBG),
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|
SFR_ACCESS(DMYQCH_CON_CLUSTER0_QCH_DBG_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CLUSTER0_QCH_DBG),
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|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_LHS_ACE_D_CPUCL0_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_LHS_ACE_D_CPUCL0),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_LHS_ACE_D_CPUCL0_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_LHS_ACE_D_CPUCL0),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_LHS_ACE_D_CPUCL0_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_LHS_ACE_D_CPUCL0),
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|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_LHS_ACE_D_CPUCL0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_LHS_ACE_D_CPUCL0),
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|
SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_ENABLE, 0, 1, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH),
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|
SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH),
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|
SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH),
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|
SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH),
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|
SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_CPUCL0_CMU_CPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_CPUCL0_CMU_CPUCL0_QCH),
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SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CPUCL0_CMU_CPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL0_CMU_CPUCL0_QCH),
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|
SFR_ACCESS(DMYQCH_CON_CSSYS_DBG_QCH_ENABLE, 0, 1, DMYQCH_CON_CSSYS_DBG_QCH),
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|
SFR_ACCESS(DMYQCH_CON_CSSYS_DBG_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CSSYS_DBG_QCH),
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|
SFR_ACCESS(DMYQCH_CON_CSSYS_DBG_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CSSYS_DBG_QCH),
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|
SFR_ACCESS(QCH_CON_DUMP_PC_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_DUMP_PC_CPUCL0_QCH),
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SFR_ACCESS(QCH_CON_DUMP_PC_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_DUMP_PC_CPUCL0_QCH),
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SFR_ACCESS(QCH_CON_DUMP_PC_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DUMP_PC_CPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_DUMP_PC_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DUMP_PC_CPUCL0_QCH),
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SFR_ACCESS(QCH_CON_DUMP_PC_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_DUMP_PC_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_DUMP_PC_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_DUMP_PC_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_DUMP_PC_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DUMP_PC_CPUCL1_QCH),
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|
SFR_ACCESS(QCH_CON_DUMP_PC_CPUCL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DUMP_PC_CPUCL1_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_CPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_CPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_CPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_CPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_CSSYS_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_CSSYS_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_CSSYS_QCH),
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|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SECJTAG_QCH_ENABLE, 0, 1, QCH_CON_SECJTAG_QCH),
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|
SFR_ACCESS(QCH_CON_SECJTAG_QCH_CLOCK_REQ, 1, 1, QCH_CON_SECJTAG_QCH),
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|
SFR_ACCESS(QCH_CON_SECJTAG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SECJTAG_QCH),
|
|
SFR_ACCESS(QCH_CON_SECJTAG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SECJTAG_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CPUCL0_QCH),
|
|
SFR_ACCESS(PLL_CON0_PLL_CPUCL1_DIV_P, 8, 6, PLL_CON0_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON0_PLL_CPUCL1_DIV_M, 16, 10, PLL_CON0_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON0_PLL_CPUCL1_DIV_S, 0, 3, PLL_CON0_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON0_PLL_CPUCL1_ENABLE, 31, 1, PLL_CON0_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON0_PLL_CPUCL1_STABLE, 29, 1, PLL_CON0_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_CPUCL1_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_CPUCL1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CLUSTER1_CPU_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_CLUSTER1_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CLUSTER1_CPU_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_CLUSTER1_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CLUSTER1_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_CLUSTER1_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(DMYQCH_CON_ADM_APB_G_CSSYS_CPUCL1_QCH_ENABLE, 0, 1, DMYQCH_CON_ADM_APB_G_CSSYS_CPUCL1_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADM_APB_G_CSSYS_CPUCL1_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADM_APB_G_CSSYS_CPUCL1_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADM_APB_G_CSSYS_CPUCL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADM_APB_G_CSSYS_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPMCPUCL1_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPMCPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPMCPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPMCPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPMCPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPMCPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPMCPUCL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_HPMCPUCL1_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CLUSTER1_QCH_CPU_ENABLE, 0, 1, DMYQCH_CON_CLUSTER1_QCH_CPU),
|
|
SFR_ACCESS(DMYQCH_CON_CLUSTER1_QCH_CPU_CLOCK_REQ, 1, 1, DMYQCH_CON_CLUSTER1_QCH_CPU),
|
|
SFR_ACCESS(DMYQCH_CON_CLUSTER1_QCH_CPU_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CLUSTER1_QCH_CPU),
|
|
SFR_ACCESS(DMYQCH_CON_CLUSTER1_QCH_DBG_ENABLE, 0, 1, DMYQCH_CON_CLUSTER1_QCH_DBG),
|
|
SFR_ACCESS(DMYQCH_CON_CLUSTER1_QCH_DBG_CLOCK_REQ, 1, 1, DMYQCH_CON_CLUSTER1_QCH_DBG),
|
|
SFR_ACCESS(DMYQCH_CON_CLUSTER1_QCH_DBG_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CLUSTER1_QCH_DBG),
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SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_ENABLE, 0, 1, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH),
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SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH),
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SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH),
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SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH),
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SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_CPUCL1_CMU_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_CPUCL1_CMU_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CPUCL1_CMU_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL1_CMU_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACE_D_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACE_D_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACE_D_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACE_D_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACE_D_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACE_D_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACE_D_CPUCL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACE_D_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CPUCL1_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_CPUCL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CPUCL1_QCH),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_AUD_CPU),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DISPAUD_CPU_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_DISPAUD_CPU_USER),
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|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DISPAUD_CPU_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DISPAUD_CPU_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_DISPAUD_CPU_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_DISPAUD_CPU_USER),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF0),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF0),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF0_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_UAIF0),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_AUDIF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_AUDIF),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_AUDIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_AUDIF),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_AUDIF_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_AUDIF),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF2_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF2),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF2_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF1_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF1_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF2_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_AUD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_AUD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_AUD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_AUD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_AUD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_AUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_AUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DISPAUD_DISP_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_DISPAUD_DISP_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DISPAUD_DISP_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DISPAUD_DISP_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_DISPAUD_DISP_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_DISPAUD_DISP_USER),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP),
|
|
SFR_ACCESS(PLL_CON0_PLL_AUD_DIV_P, 8, 6, PLL_CON0_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON0_PLL_AUD_DIV_M, 16, 10, PLL_CON0_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON0_PLL_AUD_DIV_S, 0, 3, PLL_CON0_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON0_PLL_AUD_ENABLE, 31, 1, PLL_CON0_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON0_PLL_AUD_STABLE, 29, 1, PLL_CON0_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD_DIV_K, 0, 16, PLL_CON3_PLL_AUD),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_AUD_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_AUD),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_ACEL_D_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_ACEL_D_DPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_ACEL_D_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_ACEL_D_DPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_ACEL_D_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_ACEL_D_DPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_DISP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_DISP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_DISP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_DISP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_DISP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_DISP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_DSIF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_DSIF),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_DSIF),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_DSIF_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_DSIF),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY_DIVRATIO, 0, 1, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_FM_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_FM),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_FM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_FM),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_FM_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_FM),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_FM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_FM),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_FM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_FM),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_FM_DIVRATIO, 0, 10, CLK_CON_DIV_DIV_CLK_AUD_FM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DISPAUD_AUD_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_DISPAUD_AUD_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DISPAUD_AUD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DISPAUD_AUD_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_DISPAUD_AUD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_DISPAUD_AUD_USER),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_DISP_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_DISP),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_DISP_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_DISP),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_DISP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_DISP),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_DBG_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_DBG),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_DBG_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_DBG),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_DBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_DBG),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_DSIF),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_DSIF),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_DSIF),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_OSC_SPDY_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_OSC_SPDY),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_OSC_SPDY_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_OSC_SPDY),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_OSC_SPDY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_OSC_SPDY),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_AUD_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_AUD),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_AUD_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_AUD),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_AUD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_AUD),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_BUS),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_BUS),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUD_BUS),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_BUS),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_BUS),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_BUS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK),
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|
SFR_ACCESS(DMYQCH_CON_ABOX_QCH_CPU_ENABLE, 0, 1, DMYQCH_CON_ABOX_QCH_CPU),
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|
SFR_ACCESS(DMYQCH_CON_ABOX_QCH_CPU_CLOCK_REQ, 1, 1, DMYQCH_CON_ABOX_QCH_CPU),
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|
SFR_ACCESS(DMYQCH_CON_ABOX_QCH_CPU_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ABOX_QCH_CPU),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_S_ACLK_ENABLE, 0, 1, QCH_CON_ABOX_QCH_S_ACLK),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_S_ACLK_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_S_ACLK),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_S_ACLK_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_S_ACLK),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_S_ACLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_S_ACLK),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_S_BCLK0_ENABLE, 0, 1, QCH_CON_ABOX_QCH_S_BCLK0),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_S_BCLK0_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_S_BCLK0),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_S_BCLK0_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_S_BCLK0),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_S_BCLK0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_S_BCLK0),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_S_BCLK2_ENABLE, 0, 1, QCH_CON_ABOX_QCH_S_BCLK2),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_S_BCLK2_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_S_BCLK2),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_S_BCLK2_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_S_BCLK2),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_S_BCLK2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_S_BCLK2),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_S_BCLK1_ENABLE, 0, 1, QCH_CON_ABOX_QCH_S_BCLK1),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_S_BCLK1_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_S_BCLK1),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_S_BCLK1_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_S_BCLK1),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_S_BCLK1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_S_BCLK1),
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|
SFR_ACCESS(DMYQCH_CON_ABOX_QCH_FM_ENABLE, 0, 1, DMYQCH_CON_ABOX_QCH_FM),
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|
SFR_ACCESS(DMYQCH_CON_ABOX_QCH_FM_CLOCK_REQ, 1, 1, DMYQCH_CON_ABOX_QCH_FM),
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|
SFR_ACCESS(DMYQCH_CON_ABOX_QCH_FM_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ABOX_QCH_FM),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_S_BCLK_DSIF_ENABLE, 0, 1, QCH_CON_ABOX_QCH_S_BCLK_DSIF),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_S_BCLK_DSIF_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_S_BCLK_DSIF),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_S_BCLK_DSIF_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_S_BCLK_DSIF),
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|
SFR_ACCESS(QCH_CON_ABOX_QCH_S_BCLK_DSIF_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_S_BCLK_DSIF),
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|
SFR_ACCESS(QCH_CON_BTM_ABOX_QCH_ENABLE, 0, 1, QCH_CON_BTM_ABOX_QCH),
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|
SFR_ACCESS(QCH_CON_BTM_ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_ABOX_QCH),
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|
SFR_ACCESS(QCH_CON_BTM_ABOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_ABOX_QCH),
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|
SFR_ACCESS(QCH_CON_BTM_ABOX_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_ABOX_QCH),
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|
SFR_ACCESS(QCH_CON_BTM_DPU_QCH_ENABLE, 0, 1, QCH_CON_BTM_DPU_QCH),
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SFR_ACCESS(QCH_CON_BTM_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_DPU_QCH),
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SFR_ACCESS(QCH_CON_BTM_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_DPU_QCH),
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SFR_ACCESS(QCH_CON_BTM_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_DPU_QCH),
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|
SFR_ACCESS(QCH_CON_DISPAUD_CMU_DISPAUD_QCH_ENABLE, 0, 1, QCH_CON_DISPAUD_CMU_DISPAUD_QCH),
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SFR_ACCESS(QCH_CON_DISPAUD_CMU_DISPAUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_DISPAUD_CMU_DISPAUD_QCH),
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|
SFR_ACCESS(QCH_CON_DISPAUD_CMU_DISPAUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DISPAUD_CMU_DISPAUD_QCH),
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|
SFR_ACCESS(QCH_CON_DISPAUD_CMU_DISPAUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DISPAUD_CMU_DISPAUD_QCH),
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|
SFR_ACCESS(QCH_CON_DPU_QCH_S_DPP_ENABLE, 0, 1, QCH_CON_DPU_QCH_S_DPP),
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|
SFR_ACCESS(QCH_CON_DPU_QCH_S_DPP_CLOCK_REQ, 1, 1, QCH_CON_DPU_QCH_S_DPP),
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|
SFR_ACCESS(QCH_CON_DPU_QCH_S_DPP_EXPIRE_VAL, 16, 10, QCH_CON_DPU_QCH_S_DPP),
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|
SFR_ACCESS(QCH_CON_DPU_QCH_S_DPP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPU_QCH_S_DPP),
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|
SFR_ACCESS(QCH_CON_DPU_QCH_S_DMA_ENABLE, 0, 1, QCH_CON_DPU_QCH_S_DMA),
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|
SFR_ACCESS(QCH_CON_DPU_QCH_S_DMA_CLOCK_REQ, 1, 1, QCH_CON_DPU_QCH_S_DMA),
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|
SFR_ACCESS(QCH_CON_DPU_QCH_S_DMA_EXPIRE_VAL, 16, 10, QCH_CON_DPU_QCH_S_DMA),
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|
SFR_ACCESS(QCH_CON_DPU_QCH_S_DMA_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPU_QCH_S_DMA),
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|
SFR_ACCESS(QCH_CON_DPU_QCH_S_DECON_ENABLE, 0, 1, QCH_CON_DPU_QCH_S_DECON),
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|
SFR_ACCESS(QCH_CON_DPU_QCH_S_DECON_CLOCK_REQ, 1, 1, QCH_CON_DPU_QCH_S_DECON),
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|
SFR_ACCESS(QCH_CON_DPU_QCH_S_DECON_EXPIRE_VAL, 16, 10, QCH_CON_DPU_QCH_S_DECON),
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|
SFR_ACCESS(QCH_CON_DPU_QCH_S_DECON_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPU_QCH_S_DECON),
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|
SFR_ACCESS(QCH_CON_GPIO_DISPAUD_QCH_ENABLE, 0, 1, QCH_CON_GPIO_DISPAUD_QCH),
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|
SFR_ACCESS(QCH_CON_GPIO_DISPAUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_DISPAUD_QCH),
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|
SFR_ACCESS(QCH_CON_GPIO_DISPAUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_DISPAUD_QCH),
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|
SFR_ACCESS(QCH_CON_GPIO_DISPAUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_DISPAUD_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_DISPAUD_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_DISPAUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_DISPAUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_DISPAUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_DISPAUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_DISPAUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_DISPAUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_DISPAUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_DPU_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_ABOX_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_ABOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_ABOX_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_ABOX_QCH_ENABLE, 0, 1, QCH_CON_PPMU_ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_ABOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_ABOX_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPU_QCH_ENABLE, 0, 1, QCH_CON_PPMU_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_DPU_QCH),
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|
SFR_ACCESS(QCH_CON_PPMU_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU_CLKIN_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU_CLKIN_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU_CLKIN_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU_CLKIN_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU_CLKIN_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_AUD_CPU_CLKIN_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU_CLKIN_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU_CLKIN_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH),
|
|
SFR_ACCESS(QCH_CON_SMMU_ABOX_QCH_ENABLE, 0, 1, QCH_CON_SMMU_ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_SMMU_ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_SMMU_ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_SMMU_ABOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SMMU_ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_SMMU_ABOX_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SMMU_ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_SMMU_DPU_QCH_ENABLE, 0, 1, QCH_CON_SMMU_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SMMU_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_SMMU_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SMMU_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SMMU_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SMMU_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SMMU_DPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DISPAUD_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DISPAUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DISPAUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DISPAUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DISPAUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_DISPAUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DISPAUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_DISPAUD_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_AUD_QCH_ENABLE, 0, 1, QCH_CON_WDT_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_AUD_QCH),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS_MMC_CARD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS_MMC_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS_MMC_EMBD_USER),
|
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_ACEL_D_FSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_ACEL_D_FSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_ACEL_D_FSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_ACEL_D_FSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_ACEL_D_FSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_ACEL_D_FSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS_UFS_EMBD_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS_UFS_EMBD_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS_UFS_EMBD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS_UFS_EMBD_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS_UFS_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS_UFS_EMBD_USER),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_PGEN_LITE_FSYS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PGEN_LITE_FSYS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_PGEN_LITE_FSYS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PGEN_LITE_FSYS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_PGEN_LITE_FSYS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PGEN_LITE_FSYS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO),
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SFR_ACCESS(QCH_CON_ADM_AHB_SSS_QCH_ENABLE, 0, 1, QCH_CON_ADM_AHB_SSS_QCH),
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SFR_ACCESS(QCH_CON_ADM_AHB_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_ADM_AHB_SSS_QCH),
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SFR_ACCESS(QCH_CON_ADM_AHB_SSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ADM_AHB_SSS_QCH),
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SFR_ACCESS(QCH_CON_ADM_AHB_SSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ADM_AHB_SSS_QCH),
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SFR_ACCESS(QCH_CON_BTM_FSYS_QCH_ENABLE, 0, 1, QCH_CON_BTM_FSYS_QCH),
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SFR_ACCESS(QCH_CON_BTM_FSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_FSYS_QCH),
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SFR_ACCESS(QCH_CON_BTM_FSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_FSYS_QCH),
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SFR_ACCESS(QCH_CON_BTM_FSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_FSYS_QCH),
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SFR_ACCESS(QCH_CON_FSYS_CMU_FSYS_QCH_ENABLE, 0, 1, QCH_CON_FSYS_CMU_FSYS_QCH),
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SFR_ACCESS(QCH_CON_FSYS_CMU_FSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_FSYS_CMU_FSYS_QCH),
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SFR_ACCESS(QCH_CON_FSYS_CMU_FSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_FSYS_CMU_FSYS_QCH),
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SFR_ACCESS(QCH_CON_FSYS_CMU_FSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_FSYS_CMU_FSYS_QCH),
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SFR_ACCESS(QCH_CON_GPIO_FSYS_QCH_ENABLE, 0, 1, QCH_CON_GPIO_FSYS_QCH),
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SFR_ACCESS(QCH_CON_GPIO_FSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_FSYS_QCH),
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SFR_ACCESS(QCH_CON_GPIO_FSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_FSYS_QCH),
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SFR_ACCESS(QCH_CON_GPIO_FSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_FSYS_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_FSYS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_FSYS_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_FSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_FSYS_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_FSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_FSYS_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_FSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_FSYS_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_FSYS_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D_FSYS_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_FSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D_FSYS_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_FSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D_FSYS_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_FSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D_FSYS_QCH),
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SFR_ACCESS(QCH_CON_MMC_CARD_QCH_ENABLE, 0, 1, QCH_CON_MMC_CARD_QCH),
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SFR_ACCESS(QCH_CON_MMC_CARD_QCH_CLOCK_REQ, 1, 1, QCH_CON_MMC_CARD_QCH),
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SFR_ACCESS(QCH_CON_MMC_CARD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MMC_CARD_QCH),
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SFR_ACCESS(QCH_CON_MMC_CARD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MMC_CARD_QCH),
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SFR_ACCESS(QCH_CON_MMC_EMBD_QCH_ENABLE, 0, 1, QCH_CON_MMC_EMBD_QCH),
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SFR_ACCESS(QCH_CON_MMC_EMBD_QCH_CLOCK_REQ, 1, 1, QCH_CON_MMC_EMBD_QCH),
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SFR_ACCESS(QCH_CON_MMC_EMBD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MMC_EMBD_QCH),
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SFR_ACCESS(QCH_CON_MMC_EMBD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MMC_EMBD_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_FSYS_QCH_ENABLE, 0, 1, QCH_CON_PGEN_LITE_FSYS_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_FSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_PGEN_LITE_FSYS_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_FSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PGEN_LITE_FSYS_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_FSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PGEN_LITE_FSYS_QCH),
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SFR_ACCESS(QCH_CON_PPMU_FSYS_QCH_ENABLE, 0, 1, QCH_CON_PPMU_FSYS_QCH),
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SFR_ACCESS(QCH_CON_PPMU_FSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_FSYS_QCH),
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SFR_ACCESS(QCH_CON_PPMU_FSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_FSYS_QCH),
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SFR_ACCESS(QCH_CON_PPMU_FSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_FSYS_QCH),
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SFR_ACCESS(QCH_CON_RTIC_QCH_ENABLE, 0, 1, QCH_CON_RTIC_QCH),
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SFR_ACCESS(QCH_CON_RTIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_RTIC_QCH),
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SFR_ACCESS(QCH_CON_RTIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RTIC_QCH),
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SFR_ACCESS(QCH_CON_RTIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RTIC_QCH),
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SFR_ACCESS(QCH_CON_SSS_QCH_ENABLE, 0, 1, QCH_CON_SSS_QCH),
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SFR_ACCESS(QCH_CON_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSS_QCH),
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SFR_ACCESS(QCH_CON_SSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSS_QCH),
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SFR_ACCESS(QCH_CON_SSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSS_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_FSYS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_FSYS_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_FSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_FSYS_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_FSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_FSYS_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_FSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_FSYS_QCH),
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SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_UFS_ENABLE, 0, 1, QCH_CON_UFS_EMBD_QCH_UFS),
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SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_UFS_CLOCK_REQ, 1, 1, QCH_CON_UFS_EMBD_QCH_UFS),
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SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_UFS_EXPIRE_VAL, 16, 10, QCH_CON_UFS_EMBD_QCH_UFS),
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SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_UFS_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UFS_EMBD_QCH_UFS),
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SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_ENABLE, 0, 1, QCH_CON_UFS_EMBD_QCH_FMP),
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SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_CLOCK_REQ, 1, 1, QCH_CON_UFS_EMBD_QCH_FMP),
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SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_EXPIRE_VAL, 16, 10, QCH_CON_UFS_EMBD_QCH_FMP),
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SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UFS_EMBD_QCH_FMP),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_G2D_MSCL_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_G2D_MSCL_USER),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G2D_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_G2D_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G2D_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_G2D_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G2D_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_G2D_BUSP),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_MSCL_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_MSCL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_MSCL_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_MSCL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_MSCL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_MSCL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G2D_UID_RSTNSYNC_CLK_G2D_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G2D_UID_RSTNSYNC_CLK_G2D_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G2D_UID_RSTNSYNC_CLK_G2D_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G2D_UID_RSTNSYNC_CLK_G2D_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G2D_UID_RSTNSYNC_CLK_G2D_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G2D_UID_RSTNSYNC_CLK_G2D_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_FIMP_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_FIMP_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_FIMP_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_FIMP_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_FIMP_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_FIMP_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_MSCL_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_MSCL_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_MSCL_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_MSCL_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_MSCL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_MSCL_IPCLKPORT_ACLK),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_G2D_G2D_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_G2D_G2D_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_G2D_G2D_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_G2D_G2D_USER),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D_G2D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D_G2D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D_G2D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D_G2D_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D_G2D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_G2D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_G2D_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_G2D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_G2D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_G2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_G2D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_MSCL_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_MSCL_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_MSCL_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_MSCL_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_MSCL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_MSCL_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PGEN100_LITE_G2D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PGEN100_LITE_G2D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PGEN100_LITE_G2D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PGEN100_LITE_G2D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PGEN100_LITE_G2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PGEN100_LITE_G2D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_MSCL_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_MSCL),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_MSCL_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_MSCL),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_MSCL),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_G2D_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_G2D),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_G2D_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_G2D),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_G2D),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_PCLK),
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SFR_ACCESS(QCH_CON_BTM_G2D_QCH_ENABLE, 0, 1, QCH_CON_BTM_G2D_QCH),
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SFR_ACCESS(QCH_CON_BTM_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_G2D_QCH),
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SFR_ACCESS(QCH_CON_BTM_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_G2D_QCH),
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SFR_ACCESS(QCH_CON_BTM_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_G2D_QCH),
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SFR_ACCESS(QCH_CON_G2D_QCH_ENABLE, 0, 1, QCH_CON_G2D_QCH),
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SFR_ACCESS(QCH_CON_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_G2D_QCH),
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SFR_ACCESS(QCH_CON_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_G2D_QCH),
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SFR_ACCESS(QCH_CON_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_G2D_QCH),
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SFR_ACCESS(QCH_CON_G2D_CMU_G2D_QCH_ENABLE, 0, 1, QCH_CON_G2D_CMU_G2D_QCH),
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SFR_ACCESS(QCH_CON_G2D_CMU_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_G2D_CMU_G2D_QCH),
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SFR_ACCESS(QCH_CON_G2D_CMU_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_G2D_CMU_G2D_QCH),
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SFR_ACCESS(QCH_CON_G2D_CMU_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_G2D_CMU_G2D_QCH),
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SFR_ACCESS(QCH_CON_JPEG_QCH_ENABLE, 0, 1, QCH_CON_JPEG_QCH),
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SFR_ACCESS(QCH_CON_JPEG_QCH_CLOCK_REQ, 1, 1, QCH_CON_JPEG_QCH),
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SFR_ACCESS(QCH_CON_JPEG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_JPEG_QCH),
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SFR_ACCESS(QCH_CON_JPEG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_JPEG_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_G2D_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_G2D_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_G2D_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_G2D_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_G2D_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_G2D_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D_G2D_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D_G2D_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D_G2D_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D_G2D_QCH),
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SFR_ACCESS(QCH_CON_MSCL_QCH_ENABLE, 0, 1, QCH_CON_MSCL_QCH),
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SFR_ACCESS(QCH_CON_MSCL_QCH_CLOCK_REQ, 1, 1, QCH_CON_MSCL_QCH),
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SFR_ACCESS(QCH_CON_MSCL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MSCL_QCH),
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SFR_ACCESS(QCH_CON_MSCL_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MSCL_QCH),
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SFR_ACCESS(QCH_CON_PGEN100_LITE_G2D_QCH_ENABLE, 0, 1, QCH_CON_PGEN100_LITE_G2D_QCH),
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SFR_ACCESS(QCH_CON_PGEN100_LITE_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_PGEN100_LITE_G2D_QCH),
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SFR_ACCESS(QCH_CON_PGEN100_LITE_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PGEN100_LITE_G2D_QCH),
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SFR_ACCESS(QCH_CON_PGEN100_LITE_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PGEN100_LITE_G2D_QCH),
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SFR_ACCESS(QCH_CON_PPMU_G2D_QCH_ENABLE, 0, 1, QCH_CON_PPMU_G2D_QCH),
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SFR_ACCESS(QCH_CON_PPMU_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_G2D_QCH),
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SFR_ACCESS(QCH_CON_PPMU_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_G2D_QCH),
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SFR_ACCESS(QCH_CON_PPMU_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_G2D_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_G2D_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_G2D_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_G2D_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_G2D_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_G2D_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_G2D_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_G2D_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_G2D_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_G2D_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_G2D_QCH),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_G3D_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_G3D_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_G3D_BUSP),
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SFR_ACCESS(PLL_CON0_PLL_G3D_DIV_P, 8, 6, PLL_CON0_PLL_G3D),
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SFR_ACCESS(PLL_CON0_PLL_G3D_DIV_M, 16, 10, PLL_CON0_PLL_G3D),
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SFR_ACCESS(PLL_CON0_PLL_G3D_DIV_S, 0, 3, PLL_CON0_PLL_G3D),
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SFR_ACCESS(PLL_CON0_PLL_G3D_ENABLE, 31, 1, PLL_CON0_PLL_G3D),
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SFR_ACCESS(PLL_CON0_PLL_G3D_STABLE, 29, 1, PLL_CON0_PLL_G3D),
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SFR_ACCESS(PLL_LOCKTIME_PLL_G3D_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_G3D),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_BUSD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_G3D_BUSD),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_G3D_BUSD),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_BUSD_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_G3D_BUSD),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSD_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_G3D_BUSD),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_G3D_BUSD),
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SFR_ACCESS(QCH_CON_BTM_G3D_QCH_ENABLE, 0, 1, QCH_CON_BTM_G3D_QCH),
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SFR_ACCESS(QCH_CON_BTM_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_G3D_QCH),
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SFR_ACCESS(QCH_CON_BTM_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_G3D_QCH),
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SFR_ACCESS(QCH_CON_BTM_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_G3D_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_HPMG3D_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPMG3D_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_HPMG3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPMG3D_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_HPMG3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPMG3D_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_HPMG3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_HPMG3D_QCH),
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SFR_ACCESS(QCH_CON_G3D_QCH_ENABLE, 0, 1, QCH_CON_G3D_QCH),
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SFR_ACCESS(QCH_CON_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_G3D_QCH),
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SFR_ACCESS(QCH_CON_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_G3D_QCH),
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SFR_ACCESS(QCH_CON_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_G3D_QCH),
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SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_ENABLE, 0, 1, QCH_CON_G3D_CMU_G3D_QCH),
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SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_G3D_CMU_G3D_QCH),
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SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_G3D_CMU_G3D_QCH),
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SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_G3D_CMU_G3D_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_G3DSFR_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_G3DSFR_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_G3DSFR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_G3DSFR_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_G3DSFR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_G3DSFR_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_G3DSFR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_G3DSFR_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_G3D_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_G3D_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_G3D_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_G3D_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_G3D_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_G3D_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_G3D_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_G3D_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_G3DSFR_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_G3DSFR_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_G3DSFR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_G3DSFR_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_G3DSFR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_G3DSFR_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_G3DSFR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_G3DSFR_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_G3D_QCH_ENABLE, 0, 1, QCH_CON_PGEN_LITE_G3D_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_PGEN_LITE_G3D_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PGEN_LITE_G3D_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PGEN_LITE_G3D_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_G3D_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_G3D_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_G3D_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_G3D_QCH),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ISP_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_ISP_BUS_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ISP_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_ISP_BUS_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_ISP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_ISP_BUS_USER),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ISP_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ISP_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ISP_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ISP_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ISP_BUSP_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_ISP_BUSP),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ISP_VRA_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_ISP_VRA_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ISP_VRA_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_ISP_VRA_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_ISP_VRA_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_ISP_VRA_USER),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ISP_GDC_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_ISP_GDC_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ISP_GDC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_ISP_GDC_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_ISP_GDC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_ISP_GDC_USER),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_GDC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_GDC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_GDC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_GDC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_GDC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_VRA_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_VRA_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_VRA_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_VRA_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_VRA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_VRA_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_AXI_P_ISP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_AXI_P_ISP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_AXI_P_ISP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_AXI_P_ISP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_AXI_P_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_AXI_P_ISP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D1_ISP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D1_ISP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D1_ISP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D1_ISP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D1_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D1_ISP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D0_ISP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D0_ISP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D0_ISP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D0_ISP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D0_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D0_ISP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_VRA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_VRA),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_VRA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_VRA),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_VRA),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_VRA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_VRA),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_VRA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_VRA),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_VRA),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_GDC_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_GDC),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_GDC_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_GDC),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_GDC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_GDC),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_GDC_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_GDC),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_GDC_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_GDC),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_GDC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_GDC),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_GDC_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_GDC),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_GDC_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_GDC),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_GDC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_GDC),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_ISP_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_ISP),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_ISP_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_ISP),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_ISP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_ISP),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_VRA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_VRA),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_VRA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_VRA),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_VRA),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_ATB_CAMISP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_ATB_CAMISP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_ATB_CAMISP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_ATB_CAMISP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_ATB_CAMISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_ATB_CAMISP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_BUSD_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_BUSD),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_BUSD_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_BUSD),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_BUSD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_BUSD),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_GDC_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_GDC),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_GDC_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_GDC),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_GDC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_GDC),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_VRA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_VRA),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_VRA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_VRA),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_VRA),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP1),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_D_ISP_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_D_ISP),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_D_ISP_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_D_ISP),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_D_ISP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_D_ISP),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_MCSC_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_MCSC),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_MCSC_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_MCSC),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_MCSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_MCSC),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PGEN_LITE_ISP_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PGEN_LITE_ISP_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PGEN_LITE_ISP_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PGEN_LITE_ISP_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PGEN_LITE_ISP_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PGEN_LITE_ISP_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(QCH_CON_BTM_ISP0_QCH_ENABLE, 0, 1, QCH_CON_BTM_ISP0_QCH),
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SFR_ACCESS(QCH_CON_BTM_ISP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_ISP0_QCH),
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SFR_ACCESS(QCH_CON_BTM_ISP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_ISP0_QCH),
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SFR_ACCESS(QCH_CON_BTM_ISP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_ISP0_QCH),
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SFR_ACCESS(QCH_CON_BTM_ISP1_QCH_ENABLE, 0, 1, QCH_CON_BTM_ISP1_QCH),
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SFR_ACCESS(QCH_CON_BTM_ISP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_ISP1_QCH),
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SFR_ACCESS(QCH_CON_BTM_ISP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_ISP1_QCH),
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SFR_ACCESS(QCH_CON_BTM_ISP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_ISP1_QCH),
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SFR_ACCESS(QCH_CON_ISP_CMU_ISP_QCH_ENABLE, 0, 1, QCH_CON_ISP_CMU_ISP_QCH),
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SFR_ACCESS(QCH_CON_ISP_CMU_ISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_ISP_CMU_ISP_QCH),
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SFR_ACCESS(QCH_CON_ISP_CMU_ISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ISP_CMU_ISP_QCH),
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SFR_ACCESS(QCH_CON_ISP_CMU_ISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ISP_CMU_ISP_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_CAMISP_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_CAMISP_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_CAMISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_CAMISP_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_CAMISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_CAMISP_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_CAMISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_CAMISP_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_ISP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_ISP_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_ISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_ISP_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_ISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_ISP_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_ISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_ISP_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D0_ISP_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D0_ISP_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D0_ISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D0_ISP_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D0_ISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D0_ISP_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D0_ISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D0_ISP_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D1_ISP_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D1_ISP_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D1_ISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D1_ISP_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D1_ISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D1_ISP_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D1_ISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D1_ISP_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_ISP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_ISP_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_ISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_ISP_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_ISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_ISP_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_ISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_ISP_QCH),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_ISP_ENABLE, 0, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_ISP),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_ISP_CLOCK_REQ, 1, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_ISP),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_ISP_EXPIRE_VAL, 16, 10, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_ISP),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_ISP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_ISP),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_MCSC_ENABLE, 0, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_MCSC),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_MCSC_CLOCK_REQ, 1, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_MCSC),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_MCSC_EXPIRE_VAL, 16, 10, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_MCSC),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_MCSC_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_MCSC),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_VRA_ENABLE, 0, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_VRA),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_VRA_CLOCK_REQ, 1, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_VRA),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_VRA_EXPIRE_VAL, 16, 10, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_VRA),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_VRA_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_VRA),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP1_ENABLE, 0, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP1),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP1_CLOCK_REQ, 1, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP1),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP1_EXPIRE_VAL, 16, 10, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP1),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP1),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP0_ENABLE, 0, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP0),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP0_CLOCK_REQ, 1, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP0),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP0_EXPIRE_VAL, 16, 10, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP0),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP0),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_GDC_ENABLE, 0, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_GDC),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_GDC_CLOCK_REQ, 1, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_GDC),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_GDC_EXPIRE_VAL, 16, 10, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_GDC),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_GDC_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_GDC),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0_ENABLE, 0, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0_CLOCK_REQ, 1, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0_EXPIRE_VAL, 16, 10, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1_ENABLE, 0, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1_CLOCK_REQ, 1, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1_EXPIRE_VAL, 16, 10, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PGEN_LITE_ISP_ENABLE, 0, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PGEN_LITE_ISP),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PGEN_LITE_ISP_CLOCK_REQ, 1, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PGEN_LITE_ISP),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PGEN_LITE_ISP_EXPIRE_VAL, 16, 10, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PGEN_LITE_ISP),
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SFR_ACCESS(QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PGEN_LITE_ISP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PGEN_LITE_ISP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MFC_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MFC_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MFC_BUSP),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC_WFD_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_MFC_WFD_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC_WFD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MFC_WFD_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_MFC_WFD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_MFC_WFD_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC_MFC_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_MFC_MFC_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC_MFC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MFC_MFC_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_MFC_MFC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_MFC_MFC_USER),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKS),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKM),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_SI_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_SI),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_SI_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_SI),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_SI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_SI),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_MI_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_MI),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_MI_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_MI),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_MI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_MI),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PGEN100_LITE_MFC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PGEN100_LITE_MFC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PGEN100_LITE_MFC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PGEN100_LITE_MFC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PGEN100_LITE_MFC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PGEN100_LITE_MFC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_WFD_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_WFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_WFD_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_WFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_WFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_WFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_XIU_D_MFC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_XIU_D_MFC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_XIU_D_MFC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_XIU_D_MFC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_XIU_D_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_XIU_D_MFC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_MFC_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_MFC),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_MFC_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_MFC),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_MFC),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_WFD_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_WFD),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_WFD_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_WFD),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_WFD),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC_UID_RSTNSYNC_CLK_MFC_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC_UID_RSTNSYNC_CLK_MFC_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC_UID_RSTNSYNC_CLK_MFC_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC_UID_RSTNSYNC_CLK_MFC_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC_UID_RSTNSYNC_CLK_MFC_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC_UID_RSTNSYNC_CLK_MFC_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D0_MFC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D0_MFC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D0_MFC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D0_MFC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D0_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D0_MFC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D1_MFC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D1_MFC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D1_MFC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D1_MFC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D1_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D1_MFC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(QCH_CON_BTM_MFCD0_QCH_ENABLE, 0, 1, QCH_CON_BTM_MFCD0_QCH),
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SFR_ACCESS(QCH_CON_BTM_MFCD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_MFCD0_QCH),
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SFR_ACCESS(QCH_CON_BTM_MFCD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_MFCD0_QCH),
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SFR_ACCESS(QCH_CON_BTM_MFCD0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_MFCD0_QCH),
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SFR_ACCESS(QCH_CON_BTM_MFCD1_QCH_ENABLE, 0, 1, QCH_CON_BTM_MFCD1_QCH),
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SFR_ACCESS(QCH_CON_BTM_MFCD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_MFCD1_QCH),
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SFR_ACCESS(QCH_CON_BTM_MFCD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_MFCD1_QCH),
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SFR_ACCESS(QCH_CON_BTM_MFCD1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_MFCD1_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_MFC_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D0_MFC_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D0_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D0_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D0_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D0_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D0_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D0_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D0_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D1_MFC_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D1_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D1_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D1_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D1_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D1_MFC_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D1_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D1_MFC_QCH),
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SFR_ACCESS(QCH_CON_LH_ATB_MFC_QCH_S_SI_ENABLE, 0, 1, QCH_CON_LH_ATB_MFC_QCH_S_SI),
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SFR_ACCESS(QCH_CON_LH_ATB_MFC_QCH_S_SI_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MFC_QCH_S_SI),
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SFR_ACCESS(QCH_CON_LH_ATB_MFC_QCH_S_SI_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MFC_QCH_S_SI),
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SFR_ACCESS(QCH_CON_LH_ATB_MFC_QCH_S_SI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MFC_QCH_S_SI),
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SFR_ACCESS(QCH_CON_LH_ATB_MFC_QCH_S_MI_ENABLE, 0, 1, QCH_CON_LH_ATB_MFC_QCH_S_MI),
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SFR_ACCESS(QCH_CON_LH_ATB_MFC_QCH_S_MI_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MFC_QCH_S_MI),
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SFR_ACCESS(QCH_CON_LH_ATB_MFC_QCH_S_MI_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MFC_QCH_S_MI),
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SFR_ACCESS(QCH_CON_LH_ATB_MFC_QCH_S_MI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MFC_QCH_S_MI),
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SFR_ACCESS(QCH_CON_MFC_QCH_ENABLE, 0, 1, QCH_CON_MFC_QCH),
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SFR_ACCESS(QCH_CON_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_MFC_QCH),
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SFR_ACCESS(QCH_CON_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MFC_QCH),
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SFR_ACCESS(QCH_CON_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MFC_QCH),
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SFR_ACCESS(QCH_CON_MFC_CMU_MFC_QCH_ENABLE, 0, 1, QCH_CON_MFC_CMU_MFC_QCH),
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SFR_ACCESS(QCH_CON_MFC_CMU_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_MFC_CMU_MFC_QCH),
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SFR_ACCESS(QCH_CON_MFC_CMU_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MFC_CMU_MFC_QCH),
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SFR_ACCESS(QCH_CON_MFC_CMU_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MFC_CMU_MFC_QCH),
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SFR_ACCESS(QCH_CON_PGEN100_LITE_MFC_QCH_ENABLE, 0, 1, QCH_CON_PGEN100_LITE_MFC_QCH),
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SFR_ACCESS(QCH_CON_PGEN100_LITE_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PGEN100_LITE_MFC_QCH),
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SFR_ACCESS(QCH_CON_PGEN100_LITE_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PGEN100_LITE_MFC_QCH),
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SFR_ACCESS(QCH_CON_PGEN100_LITE_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PGEN100_LITE_MFC_QCH),
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SFR_ACCESS(QCH_CON_PPMU_MFCD0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_MFCD0_QCH),
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SFR_ACCESS(QCH_CON_PPMU_MFCD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_MFCD0_QCH),
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SFR_ACCESS(QCH_CON_PPMU_MFCD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_MFCD0_QCH),
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SFR_ACCESS(QCH_CON_PPMU_MFCD0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_MFCD0_QCH),
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SFR_ACCESS(QCH_CON_PPMU_MFCD1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_MFCD1_QCH),
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SFR_ACCESS(QCH_CON_PPMU_MFCD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_MFCD1_QCH),
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SFR_ACCESS(QCH_CON_PPMU_MFCD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_MFCD1_QCH),
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SFR_ACCESS(QCH_CON_PPMU_MFCD1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_MFCD1_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_MFC_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC_MFC_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_MFC_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC_MFC_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_MFC_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC_MFC_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_MFC_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC_MFC_SW_RESET_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_WFD_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC_WFD_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_WFD_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC_WFD_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_WFD_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC_WFD_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_WFD_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC_WFD_SW_RESET_QCH),
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|
SFR_ACCESS(QCH_CON_SYSMMU_MFCD0_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_MFCD0_QCH),
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|
SFR_ACCESS(QCH_CON_SYSMMU_MFCD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MFCD0_QCH),
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|
SFR_ACCESS(QCH_CON_SYSMMU_MFCD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_MFCD0_QCH),
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|
SFR_ACCESS(QCH_CON_SYSMMU_MFCD0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MFCD0_QCH),
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|
SFR_ACCESS(QCH_CON_SYSMMU_MFCD1_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_MFCD1_QCH),
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|
SFR_ACCESS(QCH_CON_SYSMMU_MFCD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MFCD1_QCH),
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|
SFR_ACCESS(QCH_CON_SYSMMU_MFCD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_MFCD1_QCH),
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|
SFR_ACCESS(QCH_CON_SYSMMU_MFCD1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MFCD1_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_MFC_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MFC_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MFC_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_MFC_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_MFC_QCH),
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|
SFR_ACCESS(QCH_CON_WFD_QCH_ENABLE, 0, 1, QCH_CON_WFD_QCH),
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|
SFR_ACCESS(QCH_CON_WFD_QCH_CLOCK_REQ, 1, 1, QCH_CON_WFD_QCH),
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|
SFR_ACCESS(QCH_CON_WFD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WFD_QCH),
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|
SFR_ACCESS(QCH_CON_WFD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WFD_QCH),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X),
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SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_MIF_CMUREF),
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SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_MIF_CMUREF),
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SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_MIF_CMUREF),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_DIV_CLK_MIF_BUSD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_MIF_BUSD),
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SFR_ACCESS(PLL_CON0_PLL_MIF_DIV_P, 8, 6, PLL_CON0_PLL_MIF),
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SFR_ACCESS(PLL_CON0_PLL_MIF_DIV_M, 16, 10, PLL_CON0_PLL_MIF),
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SFR_ACCESS(PLL_CON0_PLL_MIF_DIV_S, 0, 3, PLL_CON0_PLL_MIF),
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SFR_ACCESS(PLL_CON0_PLL_MIF_ENABLE, 31, 1, PLL_CON0_PLL_MIF),
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SFR_ACCESS(PLL_CON0_PLL_MIF_STABLE, 29, 1, PLL_CON0_PLL_MIF),
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SFR_ACCESS(PLL_LOCKTIME_PLL_MIF_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MIF),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_MIF_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_MIF_BUSP_USER),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DDR_PHY_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDR_PHY_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DDR_PHY_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDR_PHY_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DDR_PHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDR_PHY_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDR_PHY_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDR_PHY_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDR_PHY_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDR_PHY_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDR_PHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDR_PHY_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_NRT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_NRT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_NRT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_NRT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_NRT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_RT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_RT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_RT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_RT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_RT_IPCLKPORT_I_CLK),
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SFR_ACCESS(QCH_CON_BUSIF_HPMMIF_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPMMIF_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_HPMMIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPMMIF_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_HPMMIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPMMIF_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_HPMMIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_HPMMIF_QCH),
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SFR_ACCESS(DMYQCH_CON_CMU_MIF_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_MIF_CMUREF_QCH),
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SFR_ACCESS(DMYQCH_CON_CMU_MIF_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_MIF_CMUREF_QCH),
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SFR_ACCESS(DMYQCH_CON_CMU_MIF_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_MIF_CMUREF_QCH),
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SFR_ACCESS(QCH_CON_DMC_QCH_ENABLE, 0, 1, QCH_CON_DMC_QCH),
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SFR_ACCESS(QCH_CON_DMC_QCH_CLOCK_REQ, 1, 1, QCH_CON_DMC_QCH),
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SFR_ACCESS(QCH_CON_DMC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DMC_QCH),
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SFR_ACCESS(QCH_CON_DMC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMC_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF_CP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_MIF_CP_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF_CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_MIF_CP_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF_CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_MIF_CP_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF_CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_MIF_CP_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF_CPU_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_MIF_CPU_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF_CPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_MIF_CPU_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF_CPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_MIF_CPU_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF_CPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_MIF_CPU_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF_NRT_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_MIF_NRT_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF_NRT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_MIF_NRT_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF_NRT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_MIF_NRT_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF_NRT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_MIF_NRT_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF_RT_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_MIF_RT_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF_RT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_MIF_RT_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF_RT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_MIF_RT_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF_RT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_MIF_RT_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_MIF_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_MIF_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_MIF_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_MIF_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_MIF_QCH),
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SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_ENABLE, 0, 1, QCH_CON_MIF_CMU_MIF_QCH),
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SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_MIF_CMU_MIF_QCH),
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SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MIF_CMU_MIF_QCH),
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SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIF_CMU_MIF_QCH),
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SFR_ACCESS(QCH_CON_PPMU_DMC_CPU_QCH_ENABLE, 0, 1, QCH_CON_PPMU_DMC_CPU_QCH),
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SFR_ACCESS(QCH_CON_PPMU_DMC_CPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_DMC_CPU_QCH),
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SFR_ACCESS(QCH_CON_PPMU_DMC_CPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_DMC_CPU_QCH),
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SFR_ACCESS(QCH_CON_PPMU_DMC_CPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_DMC_CPU_QCH),
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SFR_ACCESS(QCH_CON_QE_DMC_CPU_QCH_ENABLE, 0, 1, QCH_CON_QE_DMC_CPU_QCH),
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SFR_ACCESS(QCH_CON_QE_DMC_CPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_DMC_CPU_QCH),
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SFR_ACCESS(QCH_CON_QE_DMC_CPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_DMC_CPU_QCH),
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SFR_ACCESS(QCH_CON_QE_DMC_CPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_DMC_CPU_QCH),
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SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DDR_PHY_QCH_ENABLE, 0, 1, QCH_CON_SFRAPB_BRIDGE_DDR_PHY_QCH),
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SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DDR_PHY_QCH_CLOCK_REQ, 1, 1, QCH_CON_SFRAPB_BRIDGE_DDR_PHY_QCH),
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SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DDR_PHY_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SFRAPB_BRIDGE_DDR_PHY_QCH),
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SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DDR_PHY_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SFRAPB_BRIDGE_DDR_PHY_QCH),
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SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_QCH_ENABLE, 0, 1, QCH_CON_SFRAPB_BRIDGE_DMC_QCH),
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SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SFRAPB_BRIDGE_DMC_QCH),
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SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SFRAPB_BRIDGE_DMC_QCH),
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SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SFRAPB_BRIDGE_DMC_QCH),
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SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH_ENABLE, 0, 1, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH),
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SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH_CLOCK_REQ, 1, 1, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH),
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SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH),
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SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH),
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SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH_ENABLE, 0, 1, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH),
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SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH),
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SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH),
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SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH),
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SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH_ENABLE, 0, 1, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH),
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SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH),
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SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH),
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SFR_ACCESS(QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MIF_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MIF_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_MIF_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_MIF_QCH),
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SFR_ACCESS(PLL_CON0_PLL_MIF1_DIV_P, 8, 6, PLL_CON0_PLL_MIF1),
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SFR_ACCESS(PLL_CON0_PLL_MIF1_DIV_M, 16, 10, PLL_CON0_PLL_MIF1),
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SFR_ACCESS(PLL_CON0_PLL_MIF1_DIV_S, 0, 3, PLL_CON0_PLL_MIF1),
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SFR_ACCESS(PLL_CON0_PLL_MIF1_ENABLE, 31, 1, PLL_CON0_PLL_MIF1),
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SFR_ACCESS(PLL_CON0_PLL_MIF1_STABLE, 29, 1, PLL_CON0_PLL_MIF1),
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SFR_ACCESS(PLL_LOCKTIME_PLL_MIF1_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MIF1),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_MIF1_DDRPHY_CLK2X_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_MIF1_DDRPHY_CLK2X),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_MIF1_DDRPHY_CLK2X_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_MIF1_DDRPHY_CLK2X),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_MIF1_DDRPHY_CLK2X_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_MIF1_DDRPHY_CLK2X),
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SFR_ACCESS(CLK_CON_DIV_CLK_MIF1_BUSD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_MIF1_BUSD),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MIF1_BUSP_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_MIF1_BUSP_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MIF1_BUSP_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MIF1_BUSP_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_MIF1_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_MIF1_BUSP_USER),
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SFR_ACCESS(CLK_CON_MUX_MUX_MIF1_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_MIF1_CMUREF),
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SFR_ACCESS(CLK_CON_MUX_MUX_MIF1_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_MIF1_CMUREF),
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SFR_ACCESS(CLK_CON_MUX_MUX_MIF1_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_MIF1_CMUREF),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PF_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PF),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PF_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PF),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PF),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PPMPU_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PPMPU),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PPMPU_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PPMPU),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PPMPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PPMPU),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_SECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_SECURE),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_SECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_SECURE),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_SECURE),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CP_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CP_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CP_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CPU_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CPU_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CPU_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_NRT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_NRT_IPCLKPORT_I_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_NRT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_NRT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_NRT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_RT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_RT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_RT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_RT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_RT_IPCLKPORT_I_CLK),
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SFR_ACCESS(QCH_CON_BUSIF_HPMMIF1_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPMMIF1_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_HPMMIF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPMMIF1_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_HPMMIF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPMMIF1_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_HPMMIF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_HPMMIF1_QCH),
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SFR_ACCESS(DMYQCH_CON_CMU_MIF1_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_MIF1_CMUREF_QCH),
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SFR_ACCESS(DMYQCH_CON_CMU_MIF1_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_MIF1_CMUREF_QCH),
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SFR_ACCESS(DMYQCH_CON_CMU_MIF1_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_MIF1_CMUREF_QCH),
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SFR_ACCESS(QCH_CON_DMC1_QCH_ENABLE, 0, 1, QCH_CON_DMC1_QCH),
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SFR_ACCESS(QCH_CON_DMC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_DMC1_QCH),
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SFR_ACCESS(QCH_CON_DMC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DMC1_QCH),
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SFR_ACCESS(QCH_CON_DMC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMC1_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF1_CP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_MIF1_CP_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF1_CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_MIF1_CP_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF1_CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_MIF1_CP_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF1_CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_MIF1_CP_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF1_CPU_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_MIF1_CPU_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF1_CPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_MIF1_CPU_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF1_CPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_MIF1_CPU_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF1_CPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_MIF1_CPU_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF1_NRT_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_MIF1_NRT_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF1_NRT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_MIF1_NRT_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF1_NRT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_MIF1_NRT_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF1_NRT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_MIF1_NRT_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF1_RT_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_MIF1_RT_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF1_RT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_MIF1_RT_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF1_RT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_MIF1_RT_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_D_MIF1_RT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_MIF1_RT_QCH),
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SFR_ACCESS(QCH_CON_MIF1_CMU_MIF1_QCH_ENABLE, 0, 1, QCH_CON_MIF1_CMU_MIF1_QCH),
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SFR_ACCESS(QCH_CON_MIF1_CMU_MIF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_MIF1_CMU_MIF1_QCH),
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SFR_ACCESS(QCH_CON_MIF1_CMU_MIF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MIF1_CMU_MIF1_QCH),
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SFR_ACCESS(QCH_CON_MIF1_CMU_MIF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIF1_CMU_MIF1_QCH),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERI_BUS_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERI_BUS_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERI_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERI_BUS_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_IP_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERI_IP_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_IP_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERI_IP_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERI_IP_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERI_IP_USER),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_MOTOR_IPCLKPORT_I_PCLK_S0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_MOTOR_IPCLKPORT_I_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_MOTOR_IPCLKPORT_I_PCLK_S0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_MOTOR_IPCLKPORT_I_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_MOTOR_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_MOTOR_IPCLKPORT_I_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERI_I2C_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERI_I2C),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERI_I2C_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERI_I2C),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERI_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERI_I2C),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERI_SPI0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERI_SPI0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERI_SPI0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERI_SPI0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERI_SPI0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERI_SPI0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERI_SPI1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERI_SPI1),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERI_SPI1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERI_SPI1),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERI_SPI1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERI_SPI1),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERI_USI_USI_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERI_USI_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERI_USI_USI_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERI_USI_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERI_USI_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERI_USI_USI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERI_USI_I2C_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERI_USI_I2C),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERI_USI_I2C_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERI_USI_I2C),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERI_USI_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERI_USI_I2C),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERI_SPI2_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_PERI_SPI2),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERI_SPI2_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_PERI_SPI2),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLK_PERI_SPI2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_PERI_SPI2),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_I2C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERI_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERI_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_I2C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERI_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_SPI0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERI_SPI0),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_SPI0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERI_SPI0),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_SPI0_DIVRATIO, 0, 8, CLK_CON_DIV_DIV_CLK_PERI_SPI0),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_SPI1_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERI_SPI1),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_SPI1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERI_SPI1),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_SPI1_DIVRATIO, 0, 8, CLK_CON_DIV_DIV_CLK_PERI_SPI1),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI_I2C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI_I2C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERI_USI_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERI_USI_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_USI_USI_DIVRATIO, 0, 8, CLK_CON_DIV_DIV_CLK_PERI_USI_USI),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_SPI2_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERI_SPI2),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_SPI2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERI_SPI2),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERI_SPI2_DIVRATIO, 0, 8, CLK_CON_DIV_DIV_CLK_PERI_SPI2),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_UART_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERI_UART_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERI_UART_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERI_UART_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERI_UART_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERI_UART_USER),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_4_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_4_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_4_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_4_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_4_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_5_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_5_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_5_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_5_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_5_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_5_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_6_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_6_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_6_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_6_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_6_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_6_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(QCH_CON_BUSIF_TMU_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_TMU_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_TMU_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_TMU_QCH),
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|
SFR_ACCESS(QCH_CON_BUSIF_TMU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_TMU_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_TMU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_TMU_QCH),
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SFR_ACCESS(QCH_CON_CAMI2C_0_QCH_ENABLE, 0, 1, QCH_CON_CAMI2C_0_QCH),
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SFR_ACCESS(QCH_CON_CAMI2C_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_CAMI2C_0_QCH),
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SFR_ACCESS(QCH_CON_CAMI2C_0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CAMI2C_0_QCH),
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SFR_ACCESS(QCH_CON_CAMI2C_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CAMI2C_0_QCH),
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SFR_ACCESS(QCH_CON_CAMI2C_1_QCH_ENABLE, 0, 1, QCH_CON_CAMI2C_1_QCH),
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|
SFR_ACCESS(QCH_CON_CAMI2C_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_CAMI2C_1_QCH),
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SFR_ACCESS(QCH_CON_CAMI2C_1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CAMI2C_1_QCH),
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|
SFR_ACCESS(QCH_CON_CAMI2C_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CAMI2C_1_QCH),
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|
SFR_ACCESS(QCH_CON_CAMI2C_2_QCH_ENABLE, 0, 1, QCH_CON_CAMI2C_2_QCH),
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|
SFR_ACCESS(QCH_CON_CAMI2C_2_QCH_CLOCK_REQ, 1, 1, QCH_CON_CAMI2C_2_QCH),
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|
SFR_ACCESS(QCH_CON_CAMI2C_2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CAMI2C_2_QCH),
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|
SFR_ACCESS(QCH_CON_CAMI2C_2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CAMI2C_2_QCH),
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|
SFR_ACCESS(QCH_CON_CAMI2C_3_QCH_ENABLE, 0, 1, QCH_CON_CAMI2C_3_QCH),
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|
SFR_ACCESS(QCH_CON_CAMI2C_3_QCH_CLOCK_REQ, 1, 1, QCH_CON_CAMI2C_3_QCH),
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|
SFR_ACCESS(QCH_CON_CAMI2C_3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CAMI2C_3_QCH),
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|
SFR_ACCESS(QCH_CON_CAMI2C_3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CAMI2C_3_QCH),
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|
SFR_ACCESS(QCH_CON_GPIO_PERI_QCH_ENABLE, 0, 1, QCH_CON_GPIO_PERI_QCH),
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|
SFR_ACCESS(QCH_CON_GPIO_PERI_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_PERI_QCH),
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|
SFR_ACCESS(QCH_CON_GPIO_PERI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_PERI_QCH),
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|
SFR_ACCESS(QCH_CON_GPIO_PERI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_PERI_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_0_QCH_ENABLE, 0, 1, QCH_CON_I2C_0_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_0_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_0_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_0_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_1_QCH_ENABLE, 0, 1, QCH_CON_I2C_1_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_1_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_1_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_1_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_2_QCH_ENABLE, 0, 1, QCH_CON_I2C_2_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_2_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_2_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_2_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_2_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_3_QCH_ENABLE, 0, 1, QCH_CON_I2C_3_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_3_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_3_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_3_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_3_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_4_QCH_ENABLE, 0, 1, QCH_CON_I2C_4_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_4_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_4_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_4_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_4_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_4_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_4_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_5_QCH_ENABLE, 0, 1, QCH_CON_I2C_5_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_5_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_5_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_5_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_5_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_5_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_5_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_6_QCH_ENABLE, 0, 1, QCH_CON_I2C_6_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_6_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_6_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_6_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_6_QCH),
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|
SFR_ACCESS(QCH_CON_I2C_6_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_6_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERI_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_PERI_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERI_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_PERI_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_PERI_QCH),
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|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_PERI_QCH),
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|
SFR_ACCESS(QCH_CON_MCT_QCH_ENABLE, 0, 1, QCH_CON_MCT_QCH),
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|
SFR_ACCESS(QCH_CON_MCT_QCH_CLOCK_REQ, 1, 1, QCH_CON_MCT_QCH),
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|
SFR_ACCESS(QCH_CON_MCT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MCT_QCH),
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|
SFR_ACCESS(QCH_CON_MCT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCT_QCH),
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|
SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_ENABLE, 0, 1, QCH_CON_OTP_CON_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_OTP_CON_TOP_QCH),
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|
SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_OTP_CON_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_OTP_CON_TOP_QCH),
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|
SFR_ACCESS(QCH_CON_PERI_CMU_PERI_QCH_ENABLE, 0, 1, QCH_CON_PERI_CMU_PERI_QCH),
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|
SFR_ACCESS(QCH_CON_PERI_CMU_PERI_QCH_CLOCK_REQ, 1, 1, QCH_CON_PERI_CMU_PERI_QCH),
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|
SFR_ACCESS(QCH_CON_PERI_CMU_PERI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PERI_CMU_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_PERI_CMU_PERI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERI_CMU_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_PWM_MOTOR_QCH_ENABLE, 0, 1, QCH_CON_PWM_MOTOR_QCH),
|
|
SFR_ACCESS(QCH_CON_PWM_MOTOR_QCH_CLOCK_REQ, 1, 1, QCH_CON_PWM_MOTOR_QCH),
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|
SFR_ACCESS(QCH_CON_PWM_MOTOR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PWM_MOTOR_QCH),
|
|
SFR_ACCESS(QCH_CON_PWM_MOTOR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PWM_MOTOR_QCH),
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|
SFR_ACCESS(QCH_CON_SPI_0_QCH_ENABLE, 0, 1, QCH_CON_SPI_0_QCH),
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|
SFR_ACCESS(QCH_CON_SPI_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPI_0_QCH),
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|
SFR_ACCESS(QCH_CON_SPI_0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPI_0_QCH),
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|
SFR_ACCESS(QCH_CON_SPI_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPI_0_QCH),
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|
SFR_ACCESS(QCH_CON_SPI_1_QCH_ENABLE, 0, 1, QCH_CON_SPI_1_QCH),
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|
SFR_ACCESS(QCH_CON_SPI_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPI_1_QCH),
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|
SFR_ACCESS(QCH_CON_SPI_1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPI_1_QCH),
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|
SFR_ACCESS(QCH_CON_SPI_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPI_1_QCH),
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|
SFR_ACCESS(QCH_CON_SPI_2_QCH_ENABLE, 0, 1, QCH_CON_SPI_2_QCH),
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|
SFR_ACCESS(QCH_CON_SPI_2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPI_2_QCH),
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|
SFR_ACCESS(QCH_CON_SPI_2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPI_2_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPI_2_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERI_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_PERI_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_PERI_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_PERI_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_PERI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_PERI_QCH),
|
|
SFR_ACCESS(QCH_CON_UART_QCH_ENABLE, 0, 1, QCH_CON_UART_QCH),
|
|
SFR_ACCESS(QCH_CON_UART_QCH_CLOCK_REQ, 1, 1, QCH_CON_UART_QCH),
|
|
SFR_ACCESS(QCH_CON_UART_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UART_QCH),
|
|
SFR_ACCESS(QCH_CON_UART_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UART_QCH),
|
|
SFR_ACCESS(QCH_CON_USI00_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI00_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI00_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI00_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI00_I2C_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI00_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI00_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI00_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI00_USI_QCH_ENABLE, 0, 1, QCH_CON_USI00_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI00_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI00_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI00_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI00_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI00_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI00_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_WDT_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CLUSTER1_QCH_ENABLE, 0, 1, QCH_CON_WDT_CLUSTER1_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CLUSTER1_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_CLUSTER1_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CLUSTER1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_CLUSTER1_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CLUSTER1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_CLUSTER1_QCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_SHUB_USI00_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_SHUB_USI00),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_SHUB_USI00_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_SHUB_USI00),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_SHUB_USI00_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_SHUB_USI00),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_SHUB_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_SHUB_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_SHUB_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_SHUB_BUS_USER),
|
|
SFR_ACCESS(PLL_CON2_MUX_CLKCMU_SHUB_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_SHUB_BUS_USER),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SHUB_USI01_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_SHUB_USI01),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SHUB_USI01_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_SHUB_USI01),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SHUB_USI01_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_SHUB_USI01),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SHUB_I2C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_SHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SHUB_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_SHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SHUB_I2C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_SHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_SHUB_USI01_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_SHUB_USI01),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_SHUB_USI01_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_SHUB_USI01),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_SHUB_USI01_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_SHUB_USI01),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SHUB_USI00_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_SHUB_USI00),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SHUB_USI00_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_SHUB_USI00),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SHUB_USI00_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_SHUB_USI00),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_SHUB_I2C_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_SHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_SHUB_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_SHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_SHUB_I2C_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_SHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SHUB_UID_SHUB_CMU_SHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SHUB_UID_SHUB_CMU_SHUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SHUB_UID_SHUB_CMU_SHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SHUB_UID_SHUB_CMU_SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SHUB_UID_SHUB_CMU_SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SHUB_UID_SHUB_CMU_SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_D_SHUB_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_D_SHUB_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_D_SHUB_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_D_SHUB_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_D_SHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_D_SHUB_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_P_APM_SHUB_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_P_APM_SHUB_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_P_APM_SHUB_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_P_APM_SHUB_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_P_APM_SHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_P_APM_SHUB_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_GPIO_SHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_GPIO_SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_GPIO_SHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_GPIO_SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_GPIO_SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_GPIO_SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_LP_SHUB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_LP_SHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_LP_SHUB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_LP_SHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_LP_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_LP_SHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_P_SHUB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_P_SHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_P_SHUB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_P_SHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_P_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_P_SHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_D_SHUB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_D_SHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_D_SHUB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_D_SHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_D_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_D_SHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_P_APM_SHUB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_P_APM_SHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_P_APM_SHUB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_P_APM_SHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_P_APM_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_P_APM_SHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_PWM_SHUB_IPCLKPORT_I_PCLK_S0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PWM_SHUB_IPCLKPORT_I_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_PWM_SHUB_IPCLKPORT_I_PCLK_S0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PWM_SHUB_IPCLKPORT_I_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_PWM_SHUB_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PWM_SHUB_IPCLKPORT_I_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_D_SHUB_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_D_SHUB_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_D_SHUB_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_D_SHUB_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_D_SHUB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_D_SHUB_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_P_APM_SHUB_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_P_APM_SHUB_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_P_APM_SHUB_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_P_APM_SHUB_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_P_APM_SHUB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_P_APM_SHUB_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_SYSREG_SHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SYSREG_SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_SYSREG_SHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SYSREG_SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_SYSREG_SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SYSREG_SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_TIMER_SHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_TIMER_SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_TIMER_SHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_TIMER_SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_TIMER_SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_TIMER_SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_WDT_SHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_WDT_SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_WDT_SHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_WDT_SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_WDT_SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_WDT_SHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_BUS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_BUS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_BUS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_RTCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_RTCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_RTCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_RTCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_RTCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_RTCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_USI00_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_USI00_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_USI00_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_USI00_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_USI00_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_USI00_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_CM4_SHUB_IPCLKPORT_FCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_CM4_SHUB_IPCLKPORT_FCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_CM4_SHUB_IPCLKPORT_FCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_CM4_SHUB_IPCLKPORT_FCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_CM4_SHUB_IPCLKPORT_FCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_CM4_SHUB_IPCLKPORT_FCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_PDMA_SHUB_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PDMA_SHUB_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_PDMA_SHUB_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PDMA_SHUB_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_PDMA_SHUB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PDMA_SHUB_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_XIU_DP_SHUB_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_XIU_DP_SHUB_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_XIU_DP_SHUB_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_XIU_DP_SHUB_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SHUB_UID_XIU_DP_SHUB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SHUB_UID_XIU_DP_SHUB_IPCLKPORT_ACLK),
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SFR_ACCESS(QCH_CON_BAAW_D_SHUB_QCH_ENABLE, 0, 1, QCH_CON_BAAW_D_SHUB_QCH),
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SFR_ACCESS(QCH_CON_BAAW_D_SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_D_SHUB_QCH),
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SFR_ACCESS(QCH_CON_BAAW_D_SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_D_SHUB_QCH),
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SFR_ACCESS(QCH_CON_BAAW_D_SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_D_SHUB_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_APM_SHUB_QCH_ENABLE, 0, 1, QCH_CON_BAAW_P_APM_SHUB_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_APM_SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_P_APM_SHUB_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_APM_SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_P_APM_SHUB_QCH),
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SFR_ACCESS(QCH_CON_BAAW_P_APM_SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_P_APM_SHUB_QCH),
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SFR_ACCESS(QCH_CON_CM4_SHUB_QCH_ENABLE, 0, 1, QCH_CON_CM4_SHUB_QCH),
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SFR_ACCESS(QCH_CON_CM4_SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_CM4_SHUB_QCH),
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SFR_ACCESS(QCH_CON_CM4_SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CM4_SHUB_QCH),
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SFR_ACCESS(QCH_CON_CM4_SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CM4_SHUB_QCH),
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SFR_ACCESS(QCH_CON_GPIO_SHUB_QCH_ENABLE, 0, 1, QCH_CON_GPIO_SHUB_QCH),
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SFR_ACCESS(QCH_CON_GPIO_SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_SHUB_QCH),
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SFR_ACCESS(QCH_CON_GPIO_SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_SHUB_QCH),
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SFR_ACCESS(QCH_CON_GPIO_SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_SHUB_QCH),
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SFR_ACCESS(QCH_CON_I2C_SHUB00_QCH_ENABLE, 0, 1, QCH_CON_I2C_SHUB00_QCH),
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SFR_ACCESS(QCH_CON_I2C_SHUB00_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_SHUB00_QCH),
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SFR_ACCESS(QCH_CON_I2C_SHUB00_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_SHUB00_QCH),
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SFR_ACCESS(QCH_CON_I2C_SHUB00_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_SHUB00_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_LP_SHUB_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_LP_SHUB_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_LP_SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_LP_SHUB_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_LP_SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_LP_SHUB_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_LP_SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_LP_SHUB_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_SHUB_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_SHUB_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_SHUB_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_SHUB_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_SHUB_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_SHUB_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_SHUB_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_SHUB_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_SHUB_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_D_SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_SHUB_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_APM_SHUB_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_APM_SHUB_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_APM_SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_APM_SHUB_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_APM_SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_APM_SHUB_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_APM_SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_APM_SHUB_QCH),
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SFR_ACCESS(QCH_CON_PDMA_SHUB_QCH_ENABLE, 0, 1, QCH_CON_PDMA_SHUB_QCH),
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SFR_ACCESS(QCH_CON_PDMA_SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_PDMA_SHUB_QCH),
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SFR_ACCESS(QCH_CON_PDMA_SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PDMA_SHUB_QCH),
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SFR_ACCESS(QCH_CON_PDMA_SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PDMA_SHUB_QCH),
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SFR_ACCESS(QCH_CON_PWM_SHUB_QCH_ENABLE, 0, 1, QCH_CON_PWM_SHUB_QCH),
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SFR_ACCESS(QCH_CON_PWM_SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_PWM_SHUB_QCH),
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SFR_ACCESS(QCH_CON_PWM_SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PWM_SHUB_QCH),
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SFR_ACCESS(QCH_CON_PWM_SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PWM_SHUB_QCH),
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SFR_ACCESS(QCH_CON_SHUB_CMU_SHUB_QCH_ENABLE, 0, 1, QCH_CON_SHUB_CMU_SHUB_QCH),
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SFR_ACCESS(QCH_CON_SHUB_CMU_SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SHUB_CMU_SHUB_QCH),
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SFR_ACCESS(QCH_CON_SHUB_CMU_SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SHUB_CMU_SHUB_QCH),
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SFR_ACCESS(QCH_CON_SHUB_CMU_SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SHUB_CMU_SHUB_QCH),
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SFR_ACCESS(QCH_CON_SWEEPER_D_SHUB_QCH_ENABLE, 0, 1, QCH_CON_SWEEPER_D_SHUB_QCH),
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SFR_ACCESS(QCH_CON_SWEEPER_D_SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SWEEPER_D_SHUB_QCH),
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SFR_ACCESS(QCH_CON_SWEEPER_D_SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SWEEPER_D_SHUB_QCH),
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SFR_ACCESS(QCH_CON_SWEEPER_D_SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SWEEPER_D_SHUB_QCH),
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SFR_ACCESS(QCH_CON_SWEEPER_P_APM_SHUB_QCH_ENABLE, 0, 1, QCH_CON_SWEEPER_P_APM_SHUB_QCH),
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SFR_ACCESS(QCH_CON_SWEEPER_P_APM_SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SWEEPER_P_APM_SHUB_QCH),
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SFR_ACCESS(QCH_CON_SWEEPER_P_APM_SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SWEEPER_P_APM_SHUB_QCH),
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SFR_ACCESS(QCH_CON_SWEEPER_P_APM_SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SWEEPER_P_APM_SHUB_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_SHUB_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_SHUB_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_SHUB_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_SHUB_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_SHUB_QCH),
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SFR_ACCESS(QCH_CON_TIMER_SHUB_QCH_ENABLE, 0, 1, QCH_CON_TIMER_SHUB_QCH),
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SFR_ACCESS(QCH_CON_TIMER_SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_TIMER_SHUB_QCH),
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SFR_ACCESS(QCH_CON_TIMER_SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TIMER_SHUB_QCH),
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SFR_ACCESS(QCH_CON_TIMER_SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TIMER_SHUB_QCH),
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SFR_ACCESS(QCH_CON_USI_SHUB00_QCH_ENABLE, 0, 1, QCH_CON_USI_SHUB00_QCH),
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SFR_ACCESS(QCH_CON_USI_SHUB00_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_SHUB00_QCH),
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SFR_ACCESS(QCH_CON_USI_SHUB00_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_SHUB00_QCH),
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SFR_ACCESS(QCH_CON_USI_SHUB00_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_SHUB00_QCH),
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SFR_ACCESS(QCH_CON_WDT_SHUB_QCH_ENABLE, 0, 1, QCH_CON_WDT_SHUB_QCH),
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SFR_ACCESS(QCH_CON_WDT_SHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_SHUB_QCH),
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SFR_ACCESS(QCH_CON_WDT_SHUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_SHUB_QCH),
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SFR_ACCESS(QCH_CON_WDT_SHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_SHUB_QCH),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_USB_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_USB_BUS_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_USB_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_USB_BUS_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_USB_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_USB_BUS_USER),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_USB_USB30DRD_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_USB_USB30DRD_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_USB_USB30DRD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_USB_USB30DRD_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_USB_USB30DRD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_USB_USB30DRD_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_USB_DPGTC_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_USB_DPGTC_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_USB_DPGTC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_USB_DPGTC_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_USB_DPGTC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_USB_DPGTC_USER),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_LHM_AXI_P_USB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_LHM_AXI_P_USB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_LHM_AXI_P_USB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_LHM_AXI_P_USB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_LHM_AXI_P_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_LHM_AXI_P_USB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_BUS_CLK_EARLY_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_BUS_CLK_EARLY),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_BUS_CLK_EARLY_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_BUS_CLK_EARLY),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_BUS_CLK_EARLY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_BUS_CLK_EARLY),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_DP_GTC_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_DP_GTC_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_DP_GTC_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_DP_GTC_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_DP_GTC_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_DP_GTC_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_USB_UID_RSTNSYNC_CLK_USB_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_USB_UID_RSTNSYNC_CLK_USB_OSCCLK_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_USB_UID_RSTNSYNC_CLK_USB_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_USB_UID_RSTNSYNC_CLK_USB_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_USB_UID_RSTNSYNC_CLK_USB_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_USB_UID_RSTNSYNC_CLK_USB_OSCCLK_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_20_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_20),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_20_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_20),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_20_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_20),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_PGEN_LITE_USB_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_PGEN_LITE_USB_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_PGEN_LITE_USB_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_PGEN_LITE_USB_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_PGEN_LITE_USB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_PGEN_LITE_USB_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_1),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_1),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_1),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_US_D_USB_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_US_D_USB_IPCLKPORT_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_US_D_USB_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_US_D_USB_IPCLKPORT_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_US_D_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_US_D_USB_IPCLKPORT_ACLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_0),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_0),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_0),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_USB30DRD_REF_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_USB30DRD_REF_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_USB30DRD_REF_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_USB30DRD_REF_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_USB30DRD_REF_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_USB30DRD_REF_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_LHS_ACEL_D_USB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_LHS_ACEL_D_USB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_LHS_ACEL_D_USB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_LHS_ACEL_D_USB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_USB_UID_LHS_ACEL_D_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_USB_UID_LHS_ACEL_D_USB_IPCLKPORT_I_CLK),
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SFR_ACCESS(QCH_CON_BTM_USB_QCH_ENABLE, 0, 1, QCH_CON_BTM_USB_QCH),
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SFR_ACCESS(QCH_CON_BTM_USB_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_USB_QCH),
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SFR_ACCESS(QCH_CON_BTM_USB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_USB_QCH),
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SFR_ACCESS(QCH_CON_BTM_USB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_USB_QCH),
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SFR_ACCESS(QCH_CON_DP_LINK_QCH_DP_ENABLE, 0, 1, QCH_CON_DP_LINK_QCH_DP),
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SFR_ACCESS(QCH_CON_DP_LINK_QCH_DP_CLOCK_REQ, 1, 1, QCH_CON_DP_LINK_QCH_DP),
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SFR_ACCESS(QCH_CON_DP_LINK_QCH_DP_EXPIRE_VAL, 16, 10, QCH_CON_DP_LINK_QCH_DP),
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SFR_ACCESS(QCH_CON_DP_LINK_QCH_DP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DP_LINK_QCH_DP),
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SFR_ACCESS(QCH_CON_DP_LINK_QCH_GTC_ENABLE, 0, 1, QCH_CON_DP_LINK_QCH_GTC),
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SFR_ACCESS(QCH_CON_DP_LINK_QCH_GTC_CLOCK_REQ, 1, 1, QCH_CON_DP_LINK_QCH_GTC),
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SFR_ACCESS(QCH_CON_DP_LINK_QCH_GTC_EXPIRE_VAL, 16, 10, QCH_CON_DP_LINK_QCH_GTC),
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SFR_ACCESS(QCH_CON_DP_LINK_QCH_GTC_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DP_LINK_QCH_GTC),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_USB_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_USB_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_USB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_USB_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_USB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_USB_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_USB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_USB_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_USB_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D_USB_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_USB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D_USB_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_USB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D_USB_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_USB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D_USB_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_USB_QCH_ENABLE, 0, 1, QCH_CON_PGEN_LITE_USB_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_USB_QCH_CLOCK_REQ, 1, 1, QCH_CON_PGEN_LITE_USB_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_USB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PGEN_LITE_USB_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_USB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PGEN_LITE_USB_QCH),
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SFR_ACCESS(QCH_CON_PPMU_USB_QCH_ENABLE, 0, 1, QCH_CON_PPMU_USB_QCH),
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SFR_ACCESS(QCH_CON_PPMU_USB_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_USB_QCH),
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SFR_ACCESS(QCH_CON_PPMU_USB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_USB_QCH),
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SFR_ACCESS(QCH_CON_PPMU_USB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_USB_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_USB_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_USB_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_USB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_USB_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_USB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_USB_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_USB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_USB_QCH),
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SFR_ACCESS(QCH_CON_USB30DRD_QCH_USB30_ENABLE, 0, 1, QCH_CON_USB30DRD_QCH_USB30),
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SFR_ACCESS(QCH_CON_USB30DRD_QCH_USB30_CLOCK_REQ, 1, 1, QCH_CON_USB30DRD_QCH_USB30),
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SFR_ACCESS(QCH_CON_USB30DRD_QCH_USB30_EXPIRE_VAL, 16, 10, QCH_CON_USB30DRD_QCH_USB30),
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SFR_ACCESS(QCH_CON_USB30DRD_QCH_USB30_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB30DRD_QCH_USB30),
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SFR_ACCESS(QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_0_ENABLE, 0, 1, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_0),
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SFR_ACCESS(QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_0_CLOCK_REQ, 1, 1, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_0),
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SFR_ACCESS(QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_0_EXPIRE_VAL, 16, 10, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_0),
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SFR_ACCESS(QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_0),
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SFR_ACCESS(QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_1_ENABLE, 0, 1, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_1),
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SFR_ACCESS(QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_1_CLOCK_REQ, 1, 1, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_1),
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SFR_ACCESS(QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_1_EXPIRE_VAL, 16, 10, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_1),
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SFR_ACCESS(QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_1),
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SFR_ACCESS(QCH_CON_USB30DRD_QCH_USBPHY_20CTRL_ENABLE, 0, 1, QCH_CON_USB30DRD_QCH_USBPHY_20CTRL),
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SFR_ACCESS(QCH_CON_USB30DRD_QCH_USBPHY_20CTRL_CLOCK_REQ, 1, 1, QCH_CON_USB30DRD_QCH_USBPHY_20CTRL),
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SFR_ACCESS(QCH_CON_USB30DRD_QCH_USBPHY_20CTRL_EXPIRE_VAL, 16, 10, QCH_CON_USB30DRD_QCH_USBPHY_20CTRL),
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SFR_ACCESS(QCH_CON_USB30DRD_QCH_USBPHY_20CTRL_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB30DRD_QCH_USBPHY_20CTRL),
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SFR_ACCESS(QCH_CON_USB_CMU_USB_QCH_ENABLE, 0, 1, QCH_CON_USB_CMU_USB_QCH),
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SFR_ACCESS(QCH_CON_USB_CMU_USB_QCH_CLOCK_REQ, 1, 1, QCH_CON_USB_CMU_USB_QCH),
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SFR_ACCESS(QCH_CON_USB_CMU_USB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USB_CMU_USB_QCH),
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SFR_ACCESS(QCH_CON_USB_CMU_USB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB_CMU_USB_QCH),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VIPX1_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VIPX1_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VIPX1_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VIPX1_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VIPX1_BUSP_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_VIPX1_BUSP),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_VIPX1_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_VIPX1_BUS_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_VIPX1_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_VIPX1_BUS_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_VIPX1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_VIPX1_BUS_USER),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ACEL_D_VIPX1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ACEL_D_VIPX1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ACEL_D_VIPX1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ACEL_D_VIPX1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ACEL_D_VIPX1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ACEL_D_VIPX1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SYSREG_VIPX1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SYSREG_VIPX1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SYSREG_VIPX1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SYSREG_VIPX1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SYSREG_VIPX1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SYSREG_VIPX1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VIPX1_UID_VIPX1_CMU_VIPX1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VIPX1_UID_VIPX1_CMU_VIPX1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VIPX1_UID_VIPX1_CMU_VIPX1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VIPX1_UID_VIPX1_CMU_VIPX1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VIPX1_UID_VIPX1_CMU_VIPX1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VIPX1_UID_VIPX1_CMU_VIPX1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ATB_VIPX1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ATB_VIPX1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ATB_VIPX1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ATB_VIPX1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ATB_VIPX1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ATB_VIPX1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BLK_VIPX1_IPCLKPORT_CLK_VIPX1_BUSD_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BLK_VIPX1_IPCLKPORT_CLK_VIPX1_BUSD),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BLK_VIPX1_IPCLKPORT_CLK_VIPX1_BUSD_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BLK_VIPX1_IPCLKPORT_CLK_VIPX1_BUSD),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BLK_VIPX1_IPCLKPORT_CLK_VIPX1_BUSD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BLK_VIPX1_IPCLKPORT_CLK_VIPX1_BUSD),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SMMU_D_VIPX1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SMMU_D_VIPX1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SMMU_D_VIPX1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SMMU_D_VIPX1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SMMU_D_VIPX1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SMMU_D_VIPX1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_XIU_D_VIPX1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_XIU_D_VIPX1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_XIU_D_VIPX1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_XIU_D_VIPX1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_XIU_D_VIPX1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_XIU_D_VIPX1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PGEN_LITE_VIPX1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PGEN_LITE_VIPX1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PGEN_LITE_VIPX1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PGEN_LITE_VIPX1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PGEN_LITE_VIPX1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PGEN_LITE_VIPX1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_VIPX1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_VIPX1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_VIPX1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_VIPX1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_VIPX1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_VIPX1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_AXI_P_VIPX1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_AXI_P_VIPX1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_AXI_P_VIPX1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_AXI_P_VIPX1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_AXI_P_VIPX1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_AXI_P_VIPX1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_ATB_VIPX1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_ATB_VIPX1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_ATB_VIPX1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_ATB_VIPX1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_ATB_VIPX1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_ATB_VIPX1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_AXI_P_VIPX1_LOCAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_AXI_P_VIPX1_LOCAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_AXI_P_VIPX1_LOCAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_AXI_P_VIPX1_LOCAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_AXI_P_VIPX1_LOCAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_AXI_P_VIPX1_LOCAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(QCH_CON_BTM_D_VIPX1_QCH_ENABLE, 0, 1, QCH_CON_BTM_D_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_BTM_D_VIPX1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_D_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_BTM_D_VIPX1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_D_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_BTM_D_VIPX1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_D_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_VIPX1_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_VIPX1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_VIPX1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_VIPX1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_VIPX1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_VIPX1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_VIPX1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_VIPX1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_VIPX1_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_VIPX1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_VIPX1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_VIPX1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_VIPX1_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_VIPX1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_VIPX1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_VIPX1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_VIPX1_LOCAL_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_VIPX1_LOCAL_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_VIPX1_LOCAL_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_VIPX1_LOCAL_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_VIPX1_LOCAL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_VIPX1_LOCAL_QCH),
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SFR_ACCESS(QCH_CON_LHS_AXI_P_VIPX1_LOCAL_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_VIPX1_LOCAL_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_VIPX1_QCH_ENABLE, 0, 1, QCH_CON_PGEN_LITE_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_VIPX1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PGEN_LITE_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_VIPX1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PGEN_LITE_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_VIPX1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PGEN_LITE_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D_VIPX1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D_VIPX1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D_VIPX1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D_VIPX1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_SMMU_D_VIPX1_QCH_ENABLE, 0, 1, QCH_CON_SMMU_D_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_SMMU_D_VIPX1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SMMU_D_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_SMMU_D_VIPX1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SMMU_D_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_SMMU_D_VIPX1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SMMU_D_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_VIPX1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_VIPX1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_VIPX1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_VIPX1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_VIPX1_QCH_ENABLE, 0, 1, QCH_CON_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_VIPX1_QCH_CLOCK_REQ, 1, 1, QCH_CON_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_VIPX1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_VIPX1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_VIPX1_CMU_VIPX1_QCH_ENABLE, 0, 1, QCH_CON_VIPX1_CMU_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_VIPX1_CMU_VIPX1_QCH_CLOCK_REQ, 1, 1, QCH_CON_VIPX1_CMU_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_VIPX1_CMU_VIPX1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VIPX1_CMU_VIPX1_QCH),
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SFR_ACCESS(QCH_CON_VIPX1_CMU_VIPX1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VIPX1_CMU_VIPX1_QCH),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VIPX2_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VIPX2_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VIPX2_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VIPX2_BUSP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VIPX2_BUSP_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_VIPX2_BUSP),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_VIPX2_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_VIPX2_BUS_USER),
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SFR_ACCESS(PLL_CON0_MUX_CLKCMU_VIPX2_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_VIPX2_BUS_USER),
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SFR_ACCESS(PLL_CON2_MUX_CLKCMU_VIPX2_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_VIPX2_BUS_USER),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VIPX2_UID_VIPX2_CMU_VIPX2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VIPX2_UID_VIPX2_CMU_VIPX2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VIPX2_UID_VIPX2_CMU_VIPX2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VIPX2_UID_VIPX2_CMU_VIPX2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VIPX2_UID_VIPX2_CMU_VIPX2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VIPX2_UID_VIPX2_CMU_VIPX2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_ATB_VIPX2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_ATB_VIPX2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_ATB_VIPX2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_ATB_VIPX2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_ATB_VIPX2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_ATB_VIPX2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ACEL_D_VIPX2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ACEL_D_VIPX2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ACEL_D_VIPX2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ACEL_D_VIPX2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ACEL_D_VIPX2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ACEL_D_VIPX2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ATB_VIPX2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ATB_VIPX2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ATB_VIPX2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ATB_VIPX2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ATB_VIPX2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ATB_VIPX2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_LOCAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_LOCAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_LOCAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_LOCAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_LOCAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_LOCAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PGEN_LITE_VIPX2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PGEN_LITE_VIPX2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PGEN_LITE_VIPX2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PGEN_LITE_VIPX2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PGEN_LITE_VIPX2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PGEN_LITE_VIPX2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SMMU_D_VIPX2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SMMU_D_VIPX2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SMMU_D_VIPX2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SMMU_D_VIPX2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SMMU_D_VIPX2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SMMU_D_VIPX2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SYSREG_VIPX2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SYSREG_VIPX2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SYSREG_VIPX2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SYSREG_VIPX2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SYSREG_VIPX2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SYSREG_VIPX2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BLK_VIPX2_IPCLKPORT_CLK_VIPX2_BUSD_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BLK_VIPX2_IPCLKPORT_CLK_VIPX2_BUSD),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BLK_VIPX2_IPCLKPORT_CLK_VIPX2_BUSD_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BLK_VIPX2_IPCLKPORT_CLK_VIPX2_BUSD),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BLK_VIPX2_IPCLKPORT_CLK_VIPX2_BUSD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BLK_VIPX2_IPCLKPORT_CLK_VIPX2_BUSD),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_VIPX2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_VIPX2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_VIPX2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_VIPX2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_VIPX2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_VIPX2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(QCH_CON_BTM_D_VIPX2_QCH_ENABLE, 0, 1, QCH_CON_BTM_D_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_BTM_D_VIPX2_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_D_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_BTM_D_VIPX2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_D_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_BTM_D_VIPX2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BTM_D_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_VIPX2_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_VIPX2_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_VIPX2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_LHM_ATB_VIPX2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_VIPX2_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_VIPX2_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_VIPX2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_VIPX2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_VIPX2_LOCAL_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_VIPX2_LOCAL_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_VIPX2_LOCAL_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_VIPX2_LOCAL_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_VIPX2_LOCAL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_VIPX2_LOCAL_QCH),
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SFR_ACCESS(QCH_CON_LHM_AXI_P_VIPX2_LOCAL_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_VIPX2_LOCAL_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_VIPX2_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_VIPX2_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_VIPX2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_LHS_ACEL_D_VIPX2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_VIPX2_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_VIPX2_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_VIPX2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_LHS_ATB_VIPX2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_VIPX2_QCH_ENABLE, 0, 1, QCH_CON_PGEN_LITE_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_VIPX2_QCH_CLOCK_REQ, 1, 1, QCH_CON_PGEN_LITE_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_VIPX2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PGEN_LITE_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_PGEN_LITE_VIPX2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PGEN_LITE_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D_VIPX2_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D_VIPX2_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D_VIPX2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D_VIPX2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_SMMU_D_VIPX2_QCH_ENABLE, 0, 1, QCH_CON_SMMU_D_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_SMMU_D_VIPX2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SMMU_D_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_SMMU_D_VIPX2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SMMU_D_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_SMMU_D_VIPX2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SMMU_D_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_VIPX2_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_VIPX2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_VIPX2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_VIPX2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_VIPX2_QCH_ENABLE, 0, 1, QCH_CON_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_VIPX2_QCH_CLOCK_REQ, 1, 1, QCH_CON_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_VIPX2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_VIPX2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_VIPX2_QCH_LOCAL_ENABLE, 0, 1, QCH_CON_VIPX2_QCH_LOCAL),
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SFR_ACCESS(QCH_CON_VIPX2_QCH_LOCAL_CLOCK_REQ, 1, 1, QCH_CON_VIPX2_QCH_LOCAL),
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SFR_ACCESS(QCH_CON_VIPX2_QCH_LOCAL_EXPIRE_VAL, 16, 10, QCH_CON_VIPX2_QCH_LOCAL),
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SFR_ACCESS(QCH_CON_VIPX2_QCH_LOCAL_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VIPX2_QCH_LOCAL),
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SFR_ACCESS(QCH_CON_VIPX2_CMU_VIPX2_QCH_ENABLE, 0, 1, QCH_CON_VIPX2_CMU_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_VIPX2_CMU_VIPX2_QCH_CLOCK_REQ, 1, 1, QCH_CON_VIPX2_CMU_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_VIPX2_CMU_VIPX2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VIPX2_CMU_VIPX2_QCH),
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SFR_ACCESS(QCH_CON_VIPX2_CMU_VIPX2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VIPX2_CMU_VIPX2_QCH),
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/*====================The section of controller option SFR ACCESS instance===================*/
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SFR_ACCESS(APM_CMU_APM_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, APM_CMU_APM_CONTROLLER_OPTION),
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SFR_ACCESS(APM_CMU_APM_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, APM_CMU_APM_CONTROLLER_OPTION),
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SFR_ACCESS(CAM_CMU_CAM_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CAM_CMU_CAM_CONTROLLER_OPTION),
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SFR_ACCESS(CAM_CMU_CAM_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CAM_CMU_CAM_CONTROLLER_OPTION),
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SFR_ACCESS(CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CMGP_CMU_CMGP_CONTROLLER_OPTION),
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SFR_ACCESS(CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CMGP_CMU_CMGP_CONTROLLER_OPTION),
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SFR_ACCESS(CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CMU_CMU_TOP_CONTROLLER_OPTION),
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SFR_ACCESS(CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CMU_CMU_TOP_CONTROLLER_OPTION),
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SFR_ACCESS(CORE_CMU_CORE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CORE_CMU_CORE_CONTROLLER_OPTION),
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SFR_ACCESS(CORE_CMU_CORE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CORE_CMU_CORE_CONTROLLER_OPTION),
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SFR_ACCESS(CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION),
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SFR_ACCESS(CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION),
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SFR_ACCESS(CPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTION),
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SFR_ACCESS(CPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTION),
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SFR_ACCESS(CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION),
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SFR_ACCESS(CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION),
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SFR_ACCESS(CPUCL1_EMBEDDED_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL1_EMBEDDED_CMU_CPUCL1_CONTROLLER_OPTION),
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SFR_ACCESS(CPUCL1_EMBEDDED_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL1_EMBEDDED_CMU_CPUCL1_CONTROLLER_OPTION),
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SFR_ACCESS(DISPAUD_CMU_DISPAUD_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, DISPAUD_CMU_DISPAUD_CONTROLLER_OPTION),
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SFR_ACCESS(DISPAUD_CMU_DISPAUD_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DISPAUD_CMU_DISPAUD_CONTROLLER_OPTION),
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SFR_ACCESS(FSYS_CMU_FSYS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, FSYS_CMU_FSYS_CONTROLLER_OPTION),
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SFR_ACCESS(FSYS_CMU_FSYS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, FSYS_CMU_FSYS_CONTROLLER_OPTION),
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SFR_ACCESS(G2D_CMU_G2D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, G2D_CMU_G2D_CONTROLLER_OPTION),
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SFR_ACCESS(G2D_CMU_G2D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, G2D_CMU_G2D_CONTROLLER_OPTION),
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SFR_ACCESS(G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, G3D_CMU_G3D_CONTROLLER_OPTION),
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SFR_ACCESS(G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, G3D_CMU_G3D_CONTROLLER_OPTION),
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SFR_ACCESS(ISP_CMU_ISP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, ISP_CMU_ISP_CONTROLLER_OPTION),
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SFR_ACCESS(ISP_CMU_ISP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, ISP_CMU_ISP_CONTROLLER_OPTION),
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SFR_ACCESS(MFC_CMU_MFC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, MFC_CMU_MFC_CONTROLLER_OPTION),
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SFR_ACCESS(MFC_CMU_MFC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MFC_CMU_MFC_CONTROLLER_OPTION),
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SFR_ACCESS(MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, MIF_CMU_MIF_CONTROLLER_OPTION),
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SFR_ACCESS(MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MIF_CMU_MIF_CONTROLLER_OPTION),
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SFR_ACCESS(MIF1_CMU_MIF1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, MIF1_CMU_MIF1_CONTROLLER_OPTION),
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SFR_ACCESS(MIF1_CMU_MIF1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MIF1_CMU_MIF1_CONTROLLER_OPTION),
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SFR_ACCESS(PERI_CMU_PERI_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, PERI_CMU_PERI_CONTROLLER_OPTION),
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SFR_ACCESS(PERI_CMU_PERI_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PERI_CMU_PERI_CONTROLLER_OPTION),
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SFR_ACCESS(SHUB_CMU_SHUB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, SHUB_CMU_SHUB_CONTROLLER_OPTION),
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SFR_ACCESS(SHUB_CMU_SHUB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, SHUB_CMU_SHUB_CONTROLLER_OPTION),
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SFR_ACCESS(USB_CMU_USB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, USB_CMU_USB_CONTROLLER_OPTION),
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SFR_ACCESS(USB_CMU_USB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, USB_CMU_USB_CONTROLLER_OPTION),
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SFR_ACCESS(VIPX1_CMU_VIPX1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, VIPX1_CMU_VIPX1_CONTROLLER_OPTION),
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SFR_ACCESS(VIPX1_CMU_VIPX1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, VIPX1_CMU_VIPX1_CONTROLLER_OPTION),
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SFR_ACCESS(VIPX2_CMU_VIPX2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, VIPX2_CMU_VIPX2_CONTROLLER_OPTION),
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SFR_ACCESS(VIPX2_CMU_VIPX2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, VIPX2_CMU_VIPX2_CONTROLLER_OPTION),
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};
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unsigned int cmucal_sfr_access_size = 4188;
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