433 lines
75 KiB
C
Executable File
433 lines
75 KiB
C
Executable File
#include "../cmucal.h"
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#include "cmucal-sfr.h"
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#include "cmucal-qch.h"
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/*=================CMUCAL version: S5E9610================================*/
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/*====================The section of QCH nodes===================*/
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unsigned int cmucal_qch_size = 391;
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struct cmucal_qch cmucal_qch_list[] = {
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CLK_QCH(APBIF_GPIO_ALIVE_QCH, QCH_CON_APBIF_GPIO_ALIVE_QCH_ENABLE, QCH_CON_APBIF_GPIO_ALIVE_QCH_CLOCK_REQ, QCH_CON_APBIF_GPIO_ALIVE_QCH_EXPIRE_VAL, QCH_CON_APBIF_GPIO_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_PMU_ALIVE_QCH, QCH_CON_APBIF_PMU_ALIVE_QCH_ENABLE, QCH_CON_APBIF_PMU_ALIVE_QCH_CLOCK_REQ, QCH_CON_APBIF_PMU_ALIVE_QCH_EXPIRE_VAL, QCH_CON_APBIF_PMU_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_RTC_QCH, QCH_CON_APBIF_RTC_QCH_ENABLE, QCH_CON_APBIF_RTC_QCH_CLOCK_REQ, QCH_CON_APBIF_RTC_QCH_EXPIRE_VAL, QCH_CON_APBIF_RTC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_TOP_RTC_QCH, QCH_CON_APBIF_TOP_RTC_QCH_ENABLE, QCH_CON_APBIF_TOP_RTC_QCH_CLOCK_REQ, QCH_CON_APBIF_TOP_RTC_QCH_EXPIRE_VAL, QCH_CON_APBIF_TOP_RTC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APM_CMU_APM_QCH, QCH_CON_APM_CMU_APM_QCH_ENABLE, QCH_CON_APM_CMU_APM_QCH_CLOCK_REQ, QCH_CON_APM_CMU_APM_QCH_EXPIRE_VAL, QCH_CON_APM_CMU_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GREBEINTEGRATION_QCH_GREBE, QCH_CON_GREBEINTEGRATION_QCH_GREBE_ENABLE, QCH_CON_GREBEINTEGRATION_QCH_GREBE_CLOCK_REQ, QCH_CON_GREBEINTEGRATION_QCH_GREBE_EXPIRE_VAL, QCH_CON_GREBEINTEGRATION_QCH_GREBE_IGNORE_FORCE_PM_EN),
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CLK_QCH(GREBEINTEGRATION_QCH_DBG, QCH_CON_GREBEINTEGRATION_QCH_DBG_ENABLE, QCH_CON_GREBEINTEGRATION_QCH_DBG_CLOCK_REQ, QCH_CON_GREBEINTEGRATION_QCH_DBG_EXPIRE_VAL, QCH_CON_GREBEINTEGRATION_QCH_DBG_IGNORE_FORCE_PM_EN),
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CLK_QCH(INTMEM_QCH, QCH_CON_INTMEM_QCH_ENABLE, QCH_CON_INTMEM_QCH_CLOCK_REQ, QCH_CON_INTMEM_QCH_EXPIRE_VAL, QCH_CON_INTMEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_APM_QCH, QCH_CON_LHM_AXI_P_APM_QCH_ENABLE, QCH_CON_LHM_AXI_P_APM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_APM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_APM_GNSS_QCH, QCH_CON_LHM_AXI_P_APM_GNSS_QCH_ENABLE, QCH_CON_LHM_AXI_P_APM_GNSS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_APM_GNSS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_APM_GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_APM_MODEM_QCH, QCH_CON_LHM_AXI_P_APM_MODEM_QCH_ENABLE, QCH_CON_LHM_AXI_P_APM_MODEM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_APM_MODEM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_APM_MODEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_APM_SHUB_QCH, QCH_CON_LHM_AXI_P_APM_SHUB_QCH_ENABLE, QCH_CON_LHM_AXI_P_APM_SHUB_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_APM_SHUB_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_APM_SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_APM_WLBT_QCH, QCH_CON_LHM_AXI_P_APM_WLBT_QCH_ENABLE, QCH_CON_LHM_AXI_P_APM_WLBT_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_APM_WLBT_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_APM_WLBT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_APM_QCH, QCH_CON_LHS_AXI_D_APM_QCH_ENABLE, QCH_CON_LHS_AXI_D_APM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_APM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_LP_SHUB_QCH, QCH_CON_LHS_AXI_LP_SHUB_QCH_ENABLE, QCH_CON_LHS_AXI_LP_SHUB_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_LP_SHUB_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_LP_SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP2CP_QCH, QCH_CON_MAILBOX_AP2CP_QCH_ENABLE, QCH_CON_MAILBOX_AP2CP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP2CP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP2CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP2CP_S_QCH, QCH_CON_MAILBOX_AP2CP_S_QCH_ENABLE, QCH_CON_MAILBOX_AP2CP_S_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP2CP_S_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP2CP_S_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP2GNSS_QCH, QCH_CON_MAILBOX_AP2GNSS_QCH_ENABLE, QCH_CON_MAILBOX_AP2GNSS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP2GNSS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP2GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP2SHUB_QCH, QCH_CON_MAILBOX_AP2SHUB_QCH_ENABLE, QCH_CON_MAILBOX_AP2SHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP2SHUB_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP2SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP2WLBT_QCH, QCH_CON_MAILBOX_AP2WLBT_QCH_ENABLE, QCH_CON_MAILBOX_AP2WLBT_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP2WLBT_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP2WLBT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM2AP_QCH, QCH_CON_MAILBOX_APM2AP_QCH_ENABLE, QCH_CON_MAILBOX_APM2AP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM2AP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM2AP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM2CP_QCH, QCH_CON_MAILBOX_APM2CP_QCH_ENABLE, QCH_CON_MAILBOX_APM2CP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM2CP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM2CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM2GNSS_QCH, QCH_CON_MAILBOX_APM2GNSS_QCH_ENABLE, QCH_CON_MAILBOX_APM2GNSS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM2GNSS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM2GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM2SHUB_QCH, QCH_CON_MAILBOX_APM2SHUB_QCH_ENABLE, QCH_CON_MAILBOX_APM2SHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM2SHUB_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM2SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM2WLBT_QCH, QCH_CON_MAILBOX_APM2WLBT_QCH_ENABLE, QCH_CON_MAILBOX_APM2WLBT_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM2WLBT_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM2WLBT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_CP2GNSS_QCH, QCH_CON_MAILBOX_CP2GNSS_QCH_ENABLE, QCH_CON_MAILBOX_CP2GNSS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_CP2GNSS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_CP2GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_CP2SHUB_QCH, QCH_CON_MAILBOX_CP2SHUB_QCH_ENABLE, QCH_CON_MAILBOX_CP2SHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_CP2SHUB_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_CP2SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_CP2WLBT_QCH, QCH_CON_MAILBOX_CP2WLBT_QCH_ENABLE, QCH_CON_MAILBOX_CP2WLBT_QCH_CLOCK_REQ, QCH_CON_MAILBOX_CP2WLBT_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_CP2WLBT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_SHUB2GNSS_QCH, QCH_CON_MAILBOX_SHUB2GNSS_QCH_ENABLE, QCH_CON_MAILBOX_SHUB2GNSS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_SHUB2GNSS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_SHUB2GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_SHUB2WLBT_QCH, QCH_CON_MAILBOX_SHUB2WLBT_QCH_ENABLE, QCH_CON_MAILBOX_SHUB2WLBT_QCH_CLOCK_REQ, QCH_CON_MAILBOX_SHUB2WLBT_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_SHUB2WLBT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_WLBT2ABOX_QCH, QCH_CON_MAILBOX_WLBT2ABOX_QCH_ENABLE, QCH_CON_MAILBOX_WLBT2ABOX_QCH_CLOCK_REQ, QCH_CON_MAILBOX_WLBT2ABOX_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_WLBT2ABOX_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_WLBT2GNSS_QCH, QCH_CON_MAILBOX_WLBT2GNSS_QCH_ENABLE, QCH_CON_MAILBOX_WLBT2GNSS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_WLBT2GNSS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_WLBT2GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PEM_QCH, QCH_CON_PEM_QCH_ENABLE, QCH_CON_PEM_QCH_CLOCK_REQ, QCH_CON_PEM_QCH_EXPIRE_VAL, QCH_CON_PEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PGEN_LITE_APM_QCH, QCH_CON_PGEN_LITE_APM_QCH_ENABLE, QCH_CON_PGEN_LITE_APM_QCH_CLOCK_REQ, QCH_CON_PGEN_LITE_APM_QCH_EXPIRE_VAL, QCH_CON_PGEN_LITE_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PMU_INTR_GEN_QCH, QCH_CON_PMU_INTR_GEN_QCH_ENABLE, QCH_CON_PMU_INTR_GEN_QCH_CLOCK_REQ, QCH_CON_PMU_INTR_GEN_QCH_EXPIRE_VAL, QCH_CON_PMU_INTR_GEN_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_APM_GREBE_QCH, QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SPEEDY_APM_QCH, QCH_CON_SPEEDY_APM_QCH_ENABLE, QCH_CON_SPEEDY_APM_QCH_CLOCK_REQ, QCH_CON_SPEEDY_APM_QCH_EXPIRE_VAL, QCH_CON_SPEEDY_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_APM_QCH, QCH_CON_SYSREG_APM_QCH_ENABLE, QCH_CON_SYSREG_APM_QCH_CLOCK_REQ, QCH_CON_SYSREG_APM_QCH_EXPIRE_VAL, QCH_CON_SYSREG_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WDT_APM_QCH, QCH_CON_WDT_APM_QCH_ENABLE, QCH_CON_WDT_APM_QCH_CLOCK_REQ, QCH_CON_WDT_APM_QCH_EXPIRE_VAL, QCH_CON_WDT_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_CAM_QCH, QCH_CON_BTM_CAM_QCH_ENABLE, QCH_CON_BTM_CAM_QCH_CLOCK_REQ, QCH_CON_BTM_CAM_QCH_EXPIRE_VAL, QCH_CON_BTM_CAM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CAM_CMU_CAM_QCH, QCH_CON_CAM_CMU_CAM_QCH_ENABLE, QCH_CON_CAM_CMU_CAM_QCH_CLOCK_REQ, QCH_CON_CAM_CMU_CAM_QCH_EXPIRE_VAL, QCH_CON_CAM_CMU_CAM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_CAM_QCH, QCH_CON_LHM_AXI_P_CAM_QCH_ENABLE, QCH_CON_LHM_AXI_P_CAM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_CAM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_CAM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D_CAM_QCH, QCH_CON_LHS_ACEL_D_CAM_QCH_ENABLE, QCH_CON_LHS_ACEL_D_CAM_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_CAM_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_CAM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_CAMISP_QCH, QCH_CON_LHS_ATB_CAMISP_QCH_ENABLE, QCH_CON_LHS_ATB_CAMISP_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_CAMISP_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_CAMISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CAM_QCH, QCH_CON_SYSREG_CAM_QCH_ENABLE, QCH_CON_SYSREG_CAM_QCH_CLOCK_REQ, QCH_CON_SYSREG_CAM_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CAM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS6P10P0_CAM_QCH_S_CAM_CSIS0, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS0_ENABLE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS0_CLOCK_REQ, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS0_EXPIRE_VAL, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS0_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS6P10P0_CAM_QCH_S_CAM_CSIS1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS1_ENABLE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS1_CLOCK_REQ, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS1_EXPIRE_VAL, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS1_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS6P10P0_CAM_QCH_S_CAM_CSIS2, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS2_ENABLE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS2_CLOCK_REQ, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS2_EXPIRE_VAL, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS2_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS6P10P0_CAM_QCH_S_CAM_CSIS3, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS3_ENABLE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS3_CLOCK_REQ, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS3_EXPIRE_VAL, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS3_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS6P10P0_CAM_QCH_S_CAM_3AA, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_3AA_ENABLE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_3AA_CLOCK_REQ, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_3AA_EXPIRE_VAL, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_3AA_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS6P10P0_CAM_QCH_S_CAM_PPMU, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PPMU_ENABLE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PPMU_CLOCK_REQ, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PPMU_EXPIRE_VAL, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PPMU_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS6P10P0_CAM_QCH_S_CAM_SMMU, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_SMMU_ENABLE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_SMMU_CLOCK_REQ, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_SMMU_EXPIRE_VAL, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_SMMU_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS6P10P0_CAM_QCH_S_CAM0_PGEN_LITE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM0_PGEN_LITE_ENABLE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM0_PGEN_LITE_CLOCK_REQ, QCH_CON_IS6P10P0_CAM_QCH_S_CAM0_PGEN_LITE_EXPIRE_VAL, QCH_CON_IS6P10P0_CAM_QCH_S_CAM0_PGEN_LITE_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS6P10P0_CAM_QCH_S_CAM_PDP_CORE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE_ENABLE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE_CLOCK_REQ, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE_EXPIRE_VAL, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS6P10P0_CAM_QCH_S_CAM_PDP_DMA, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA_ENABLE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA_CLOCK_REQ, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA_EXPIRE_VAL, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS6P10P0_CAM_QCH_S_CAM_RDMA, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_RDMA_ENABLE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_RDMA_CLOCK_REQ, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_RDMA_EXPIRE_VAL, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_RDMA_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS6P10P0_CAM_QCH_S_CAM1_PGEN_LITE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM1_PGEN_LITE_ENABLE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM1_PGEN_LITE_CLOCK_REQ, QCH_CON_IS6P10P0_CAM_QCH_S_CAM1_PGEN_LITE_EXPIRE_VAL, QCH_CON_IS6P10P0_CAM_QCH_S_CAM1_PGEN_LITE_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADC_CMGP_QCH_S0, QCH_CON_ADC_CMGP_QCH_S0_ENABLE, QCH_CON_ADC_CMGP_QCH_S0_CLOCK_REQ, QCH_CON_ADC_CMGP_QCH_S0_EXPIRE_VAL, QCH_CON_ADC_CMGP_QCH_S0_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADC_CMGP_QCH_S1, QCH_CON_ADC_CMGP_QCH_S1_ENABLE, QCH_CON_ADC_CMGP_QCH_S1_CLOCK_REQ, QCH_CON_ADC_CMGP_QCH_S1_EXPIRE_VAL, QCH_CON_ADC_CMGP_QCH_S1_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADC_CMGP_QCH_ADC, DMYQCH_CON_ADC_CMGP_QCH_ADC_ENABLE, DMYQCH_CON_ADC_CMGP_QCH_ADC_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADC_CMGP_QCH_ADC_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMGP_CMU_CMGP_QCH, QCH_CON_CMGP_CMU_CMGP_QCH_ENABLE, QCH_CON_CMGP_CMU_CMGP_QCH_CLOCK_REQ, QCH_CON_CMGP_CMU_CMGP_QCH_EXPIRE_VAL, QCH_CON_CMGP_CMU_CMGP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPIO_CMGP_QCH, QCH_CON_GPIO_CMGP_QCH_ENABLE, QCH_CON_GPIO_CMGP_QCH_CLOCK_REQ, QCH_CON_GPIO_CMGP_QCH_EXPIRE_VAL, QCH_CON_GPIO_CMGP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_CMGP00_QCH, QCH_CON_I2C_CMGP00_QCH_ENABLE, QCH_CON_I2C_CMGP00_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP00_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP00_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_CMGP01_QCH, QCH_CON_I2C_CMGP01_QCH_ENABLE, QCH_CON_I2C_CMGP01_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP01_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP01_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_CMGP02_QCH, QCH_CON_I2C_CMGP02_QCH_ENABLE, QCH_CON_I2C_CMGP02_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP02_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP02_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_CMGP03_QCH, QCH_CON_I2C_CMGP03_QCH_ENABLE, QCH_CON_I2C_CMGP03_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP03_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP03_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_CMGP04_QCH, QCH_CON_I2C_CMGP04_QCH_ENABLE, QCH_CON_I2C_CMGP04_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP04_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP04_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CMGP_QCH, QCH_CON_SYSREG_CMGP_QCH_ENABLE, QCH_CON_SYSREG_CMGP_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CMGP2CP_QCH, QCH_CON_SYSREG_CMGP2CP_QCH_ENABLE, QCH_CON_SYSREG_CMGP2CP_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2CP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CMGP2GNSS_QCH, QCH_CON_SYSREG_CMGP2GNSS_QCH_ENABLE, QCH_CON_SYSREG_CMGP2GNSS_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2GNSS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CMGP2PMU_AP_QCH, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_ENABLE, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CMGP2PMU_SHUB_QCH, QCH_CON_SYSREG_CMGP2PMU_SHUB_QCH_ENABLE, QCH_CON_SYSREG_CMGP2PMU_SHUB_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2PMU_SHUB_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2PMU_SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CMGP2SHUB_QCH, QCH_CON_SYSREG_CMGP2SHUB_QCH_ENABLE, QCH_CON_SYSREG_CMGP2SHUB_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2SHUB_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CMGP2WLBT_QCH, QCH_CON_SYSREG_CMGP2WLBT_QCH_ENABLE, QCH_CON_SYSREG_CMGP2WLBT_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2WLBT_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2WLBT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_CMGP00_QCH, QCH_CON_USI_CMGP00_QCH_ENABLE, QCH_CON_USI_CMGP00_QCH_CLOCK_REQ, QCH_CON_USI_CMGP00_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP00_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_CMGP01_QCH, QCH_CON_USI_CMGP01_QCH_ENABLE, QCH_CON_USI_CMGP01_QCH_CLOCK_REQ, QCH_CON_USI_CMGP01_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP01_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_CMGP02_QCH, QCH_CON_USI_CMGP02_QCH_ENABLE, QCH_CON_USI_CMGP02_QCH_CLOCK_REQ, QCH_CON_USI_CMGP02_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP02_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_CMGP03_QCH, QCH_CON_USI_CMGP03_QCH_ENABLE, QCH_CON_USI_CMGP03_QCH_CLOCK_REQ, QCH_CON_USI_CMGP03_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP03_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_CMGP04_QCH, QCH_CON_USI_CMGP04_QCH_ENABLE, QCH_CON_USI_CMGP04_QCH_CLOCK_REQ, QCH_CON_USI_CMGP04_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP04_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_TOP_CMUREF_QCH, DMYQCH_CON_CMU_TOP_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_TOP_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_TOP_CMUREF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DFTMUX_TOP_QCH_CLK_CSIS0, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS0_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS0_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS0_IGNORE_FORCE_PM_EN),
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CLK_QCH(DFTMUX_TOP_QCH_CLK_CSIS1, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS1_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS1_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS1_IGNORE_FORCE_PM_EN),
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CLK_QCH(DFTMUX_TOP_QCH_CLK_CSIS2, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS2_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS2_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS2_IGNORE_FORCE_PM_EN),
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CLK_QCH(DFTMUX_TOP_QCH_CLK_CSIS3, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS3_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS3_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS3_IGNORE_FORCE_PM_EN),
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CLK_QCH(OTP_QCH, DMYQCH_CON_OTP_QCH_ENABLE, DMYQCH_CON_OTP_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_OTP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_P_GNSS_QCH, QCH_CON_BAAW_P_GNSS_QCH_ENABLE, QCH_CON_BAAW_P_GNSS_QCH_CLOCK_REQ, QCH_CON_BAAW_P_GNSS_QCH_EXPIRE_VAL, QCH_CON_BAAW_P_GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_P_MODEM_QCH, QCH_CON_BAAW_P_MODEM_QCH_ENABLE, QCH_CON_BAAW_P_MODEM_QCH_CLOCK_REQ, QCH_CON_BAAW_P_MODEM_QCH_EXPIRE_VAL, QCH_CON_BAAW_P_MODEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_P_SHUB_QCH, QCH_CON_BAAW_P_SHUB_QCH_ENABLE, QCH_CON_BAAW_P_SHUB_QCH_CLOCK_REQ, QCH_CON_BAAW_P_SHUB_QCH_EXPIRE_VAL, QCH_CON_BAAW_P_SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_P_WLBT_QCH, QCH_CON_BAAW_P_WLBT_QCH_ENABLE, QCH_CON_BAAW_P_WLBT_QCH_CLOCK_REQ, QCH_CON_BAAW_P_WLBT_QCH_EXPIRE_VAL, QCH_CON_BAAW_P_WLBT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CCI_550_QCH, QCH_CON_CCI_550_QCH_ENABLE, QCH_CON_CCI_550_QCH_CLOCK_REQ, QCH_CON_CCI_550_QCH_EXPIRE_VAL, QCH_CON_CCI_550_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CORE_CMU_CORE_QCH, QCH_CON_CORE_CMU_CORE_QCH_ENABLE, QCH_CON_CORE_CMU_CORE_QCH_CLOCK_REQ, QCH_CON_CORE_CMU_CORE_QCH_EXPIRE_VAL, QCH_CON_CORE_CMU_CORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DIT_QCH, QCH_CON_DIT_QCH_ENABLE, QCH_CON_DIT_QCH_CLOCK_REQ, QCH_CON_DIT_QCH_EXPIRE_VAL, QCH_CON_DIT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GIC400_AIHWACG_QCH, QCH_CON_GIC400_AIHWACG_QCH_ENABLE, QCH_CON_GIC400_AIHWACG_QCH_CLOCK_REQ, QCH_CON_GIC400_AIHWACG_QCH_EXPIRE_VAL, QCH_CON_GIC400_AIHWACG_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D0_ISP_QCH, QCH_CON_LHM_ACEL_D0_ISP_QCH_ENABLE, QCH_CON_LHM_ACEL_D0_ISP_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D0_ISP_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D0_ISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D0_MFC_QCH, QCH_CON_LHM_ACEL_D0_MFC_QCH_ENABLE, QCH_CON_LHM_ACEL_D0_MFC_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D0_MFC_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D0_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D1_ISP_QCH, QCH_CON_LHM_ACEL_D1_ISP_QCH_ENABLE, QCH_CON_LHM_ACEL_D1_ISP_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D1_ISP_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D1_ISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D1_MFC_QCH, QCH_CON_LHM_ACEL_D1_MFC_QCH_ENABLE, QCH_CON_LHM_ACEL_D1_MFC_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D1_MFC_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D1_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D_CAM_QCH, QCH_CON_LHM_ACEL_D_CAM_QCH_ENABLE, QCH_CON_LHM_ACEL_D_CAM_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_CAM_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_CAM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D_DPU_QCH, QCH_CON_LHM_ACEL_D_DPU_QCH_ENABLE, QCH_CON_LHM_ACEL_D_DPU_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_DPU_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D_FSYS_QCH, QCH_CON_LHM_ACEL_D_FSYS_QCH_ENABLE, QCH_CON_LHM_ACEL_D_FSYS_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_FSYS_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_FSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D_G2D_QCH, QCH_CON_LHM_ACEL_D_G2D_QCH_ENABLE, QCH_CON_LHM_ACEL_D_G2D_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_G2D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_G2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D_USB_QCH, QCH_CON_LHM_ACEL_D_USB_QCH_ENABLE, QCH_CON_LHM_ACEL_D_USB_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_USB_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_USB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D_VIPX1_QCH, QCH_CON_LHM_ACEL_D_VIPX1_QCH_ENABLE, QCH_CON_LHM_ACEL_D_VIPX1_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_VIPX1_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_VIPX1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACEL_D_VIPX2_QCH, QCH_CON_LHM_ACEL_D_VIPX2_QCH_ENABLE, QCH_CON_LHM_ACEL_D_VIPX2_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_VIPX2_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_VIPX2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACE_D_CPUCL0_QCH, QCH_CON_LHM_ACE_D_CPUCL0_QCH_ENABLE, QCH_CON_LHM_ACE_D_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ACE_D_CPUCL1_QCH, QCH_CON_LHM_ACE_D_CPUCL1_QCH_ENABLE, QCH_CON_LHM_ACE_D_CPUCL1_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D_CPUCL1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D0_MODEM_QCH, QCH_CON_LHM_AXI_D0_MODEM_QCH_ENABLE, QCH_CON_LHM_AXI_D0_MODEM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_MODEM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_MODEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D1_MODEM_QCH, QCH_CON_LHM_AXI_D1_MODEM_QCH_ENABLE, QCH_CON_LHM_AXI_D1_MODEM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_MODEM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_MODEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_ABOX_QCH, QCH_CON_LHM_AXI_D_ABOX_QCH_ENABLE, QCH_CON_LHM_AXI_D_ABOX_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_ABOX_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_ABOX_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_APM_QCH, QCH_CON_LHM_AXI_D_APM_QCH_ENABLE, QCH_CON_LHM_AXI_D_APM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_APM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_CSSYS_QCH, QCH_CON_LHM_AXI_D_CSSYS_QCH_ENABLE, QCH_CON_LHM_AXI_D_CSSYS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_CSSYS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_CSSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_G3D_QCH, QCH_CON_LHM_AXI_D_G3D_QCH_ENABLE, QCH_CON_LHM_AXI_D_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_GNSS_QCH, QCH_CON_LHM_AXI_D_GNSS_QCH_ENABLE, QCH_CON_LHM_AXI_D_GNSS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_GNSS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_SHUB_QCH, QCH_CON_LHM_AXI_D_SHUB_QCH_ENABLE, QCH_CON_LHM_AXI_D_SHUB_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_SHUB_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_WLBT_QCH, QCH_CON_LHM_AXI_D_WLBT_QCH_ENABLE, QCH_CON_LHM_AXI_D_WLBT_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_WLBT_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_WLBT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D0_MIF_CP_QCH, QCH_CON_LHS_AXI_D0_MIF_CP_QCH_ENABLE, QCH_CON_LHS_AXI_D0_MIF_CP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_MIF_CP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_MIF_CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D0_MIF_CPU_QCH, QCH_CON_LHS_AXI_D0_MIF_CPU_QCH_ENABLE, QCH_CON_LHS_AXI_D0_MIF_CPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_MIF_CPU_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_MIF_CPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D0_MIF_NRT_QCH, QCH_CON_LHS_AXI_D0_MIF_NRT_QCH_ENABLE, QCH_CON_LHS_AXI_D0_MIF_NRT_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_MIF_NRT_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_MIF_NRT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D0_MIF_RT_QCH, QCH_CON_LHS_AXI_D0_MIF_RT_QCH_ENABLE, QCH_CON_LHS_AXI_D0_MIF_RT_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_MIF_RT_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_MIF_RT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D1_MIF_CP_QCH, QCH_CON_LHS_AXI_D1_MIF_CP_QCH_ENABLE, QCH_CON_LHS_AXI_D1_MIF_CP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_MIF_CP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_MIF_CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D1_MIF_CPU_QCH, QCH_CON_LHS_AXI_D1_MIF_CPU_QCH_ENABLE, QCH_CON_LHS_AXI_D1_MIF_CPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_MIF_CPU_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_MIF_CPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D1_MIF_NRT_QCH, QCH_CON_LHS_AXI_D1_MIF_NRT_QCH_ENABLE, QCH_CON_LHS_AXI_D1_MIF_NRT_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_MIF_NRT_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_MIF_NRT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D1_MIF_RT_QCH, QCH_CON_LHS_AXI_D1_MIF_RT_QCH_ENABLE, QCH_CON_LHS_AXI_D1_MIF_RT_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_MIF_RT_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_MIF_RT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_APM_QCH, QCH_CON_LHS_AXI_P_APM_QCH_ENABLE, QCH_CON_LHS_AXI_P_APM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_APM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_CAM_QCH, QCH_CON_LHS_AXI_P_CAM_QCH_ENABLE, QCH_CON_LHS_AXI_P_CAM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_CAM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_CAM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_CPUCL0_QCH, QCH_CON_LHS_AXI_P_CPUCL0_QCH_ENABLE, QCH_CON_LHS_AXI_P_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_CPUCL1_QCH, QCH_CON_LHS_AXI_P_CPUCL1_QCH_ENABLE, QCH_CON_LHS_AXI_P_CPUCL1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_CPUCL1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_DISPAUD_QCH, QCH_CON_LHS_AXI_P_DISPAUD_QCH_ENABLE, QCH_CON_LHS_AXI_P_DISPAUD_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_DISPAUD_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_DISPAUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_FSYS_QCH, QCH_CON_LHS_AXI_P_FSYS_QCH_ENABLE, QCH_CON_LHS_AXI_P_FSYS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_FSYS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_FSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_G2D_QCH, QCH_CON_LHS_AXI_P_G2D_QCH_ENABLE, QCH_CON_LHS_AXI_P_G2D_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_G2D_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_G2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_G3D_QCH, QCH_CON_LHS_AXI_P_G3D_QCH_ENABLE, QCH_CON_LHS_AXI_P_G3D_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_G3D_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_GNSS_QCH, QCH_CON_LHS_AXI_P_GNSS_QCH_ENABLE, QCH_CON_LHS_AXI_P_GNSS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_GNSS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_ISP_QCH, QCH_CON_LHS_AXI_P_ISP_QCH_ENABLE, QCH_CON_LHS_AXI_P_ISP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_ISP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_ISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_MFC_QCH, QCH_CON_LHS_AXI_P_MFC_QCH_ENABLE, QCH_CON_LHS_AXI_P_MFC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MFC_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_MIF0_QCH, QCH_CON_LHS_AXI_P_MIF0_QCH_ENABLE, QCH_CON_LHS_AXI_P_MIF0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MIF0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MIF0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_MIF1_QCH, QCH_CON_LHS_AXI_P_MIF1_QCH_ENABLE, QCH_CON_LHS_AXI_P_MIF1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MIF1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MIF1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_MODEM_QCH, QCH_CON_LHS_AXI_P_MODEM_QCH_ENABLE, QCH_CON_LHS_AXI_P_MODEM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MODEM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MODEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_PERI_QCH, QCH_CON_LHS_AXI_P_PERI_QCH_ENABLE, QCH_CON_LHS_AXI_P_PERI_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_PERI_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_PERI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_SHUB_QCH, QCH_CON_LHS_AXI_P_SHUB_QCH_ENABLE, QCH_CON_LHS_AXI_P_SHUB_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_SHUB_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_USB_QCH, QCH_CON_LHS_AXI_P_USB_QCH_ENABLE, QCH_CON_LHS_AXI_P_USB_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_USB_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_USB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_VIPX1_QCH, QCH_CON_LHS_AXI_P_VIPX1_QCH_ENABLE, QCH_CON_LHS_AXI_P_VIPX1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_VIPX1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_VIPX1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_VIPX2_QCH, QCH_CON_LHS_AXI_P_VIPX2_QCH_ENABLE, QCH_CON_LHS_AXI_P_VIPX2_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_VIPX2_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_VIPX2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_WLBT_QCH, QCH_CON_LHS_AXI_P_WLBT_QCH_ENABLE, QCH_CON_LHS_AXI_P_WLBT_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_WLBT_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_WLBT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PDMA_CORE_QCH, QCH_CON_PDMA_CORE_QCH_ENABLE, QCH_CON_PDMA_CORE_QCH_CLOCK_REQ, QCH_CON_PDMA_CORE_QCH_EXPIRE_VAL, QCH_CON_PDMA_CORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PGEN_LITE_SIREX_QCH, QCH_CON_PGEN_LITE_SIREX_QCH_ENABLE, QCH_CON_PGEN_LITE_SIREX_QCH_CLOCK_REQ, QCH_CON_PGEN_LITE_SIREX_QCH_EXPIRE_VAL, QCH_CON_PGEN_LITE_SIREX_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PGEN_PDMA_QCH, QCH_CON_PGEN_PDMA_QCH_ENABLE, QCH_CON_PGEN_PDMA_QCH_CLOCK_REQ, QCH_CON_PGEN_PDMA_QCH_EXPIRE_VAL, QCH_CON_PGEN_PDMA_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPCFW_G3D_QCH, QCH_CON_PPCFW_G3D_QCH_ENABLE, QCH_CON_PPCFW_G3D_QCH_CLOCK_REQ, QCH_CON_PPCFW_G3D_QCH_EXPIRE_VAL, QCH_CON_PPCFW_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPFW_CORE_MEM0_QCH, QCH_CON_PPFW_CORE_MEM0_QCH_ENABLE, QCH_CON_PPFW_CORE_MEM0_QCH_CLOCK_REQ, QCH_CON_PPFW_CORE_MEM0_QCH_EXPIRE_VAL, QCH_CON_PPFW_CORE_MEM0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPFW_CORE_MEM1_QCH, QCH_CON_PPFW_CORE_MEM1_QCH_ENABLE, QCH_CON_PPFW_CORE_MEM1_QCH_CLOCK_REQ, QCH_CON_PPFW_CORE_MEM1_QCH_EXPIRE_VAL, QCH_CON_PPFW_CORE_MEM1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPFW_CORE_PERI_QCH, QCH_CON_PPFW_CORE_PERI_QCH_ENABLE, QCH_CON_PPFW_CORE_PERI_QCH_CLOCK_REQ, QCH_CON_PPFW_CORE_PERI_QCH_EXPIRE_VAL, QCH_CON_PPFW_CORE_PERI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_ACE_CPUCL0_QCH, QCH_CON_PPMU_ACE_CPUCL0_QCH_ENABLE, QCH_CON_PPMU_ACE_CPUCL0_QCH_CLOCK_REQ, QCH_CON_PPMU_ACE_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_PPMU_ACE_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_ACE_CPUCL1_QCH, QCH_CON_PPMU_ACE_CPUCL1_QCH_ENABLE, QCH_CON_PPMU_ACE_CPUCL1_QCH_CLOCK_REQ, QCH_CON_PPMU_ACE_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_PPMU_ACE_CPUCL1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_QCH, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_CORE_BUSP_OCC_QCH, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_OCC_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_OCC_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_OCC_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_OCC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_CORE_CCI_OCC_QCH, QCH_CON_RSTNSYNC_CLK_CORE_CCI_OCC_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CORE_CCI_OCC_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CORE_CCI_OCC_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_CORE_CCI_OCC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_CORE_G3D_OCC_QCH, QCH_CON_RSTNSYNC_CLK_CORE_G3D_OCC_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CORE_G3D_OCC_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CORE_G3D_OCC_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_CORE_G3D_OCC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SFR_APBIF_CMU_TOPC_QCH, QCH_CON_SFR_APBIF_CMU_TOPC_QCH_ENABLE, QCH_CON_SFR_APBIF_CMU_TOPC_QCH_CLOCK_REQ, QCH_CON_SFR_APBIF_CMU_TOPC_QCH_EXPIRE_VAL, QCH_CON_SFR_APBIF_CMU_TOPC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SIREX_QCH, QCH_CON_SIREX_QCH_ENABLE, QCH_CON_SIREX_QCH_CLOCK_REQ, QCH_CON_SIREX_QCH_EXPIRE_VAL, QCH_CON_SIREX_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SPDMA_CORE_QCH, QCH_CON_SPDMA_CORE_QCH_ENABLE, QCH_CON_SPDMA_CORE_QCH_CLOCK_REQ, QCH_CON_SPDMA_CORE_QCH_EXPIRE_VAL, QCH_CON_SPDMA_CORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CORE_QCH, QCH_CON_SYSREG_CORE_QCH_ENABLE, QCH_CON_SYSREG_CORE_QCH_CLOCK_REQ, QCH_CON_SYSREG_CORE_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_D_CORE_QCH, QCH_CON_TREX_D_CORE_QCH_ENABLE, QCH_CON_TREX_D_CORE_QCH_CLOCK_REQ, QCH_CON_TREX_D_CORE_QCH_EXPIRE_VAL, QCH_CON_TREX_D_CORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_D_NRT_QCH, QCH_CON_TREX_D_NRT_QCH_ENABLE, QCH_CON_TREX_D_NRT_QCH_CLOCK_REQ, QCH_CON_TREX_D_NRT_QCH_EXPIRE_VAL, QCH_CON_TREX_D_NRT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TREX_P_CORE_QCH, QCH_CON_TREX_P_CORE_QCH_ENABLE, QCH_CON_TREX_P_CORE_QCH_CLOCK_REQ, QCH_CON_TREX_P_CORE_QCH_EXPIRE_VAL, QCH_CON_TREX_P_CORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_HPMCPUCL0_QCH, QCH_CON_BUSIF_HPMCPUCL0_QCH_ENABLE, QCH_CON_BUSIF_HPMCPUCL0_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMCPUCL0_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMCPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER0_QCH_CPU, DMYQCH_CON_CLUSTER0_QCH_CPU_ENABLE, DMYQCH_CON_CLUSTER0_QCH_CPU_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CLUSTER0_QCH_CPU_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER0_QCH_DBG, DMYQCH_CON_CLUSTER0_QCH_DBG_ENABLE, DMYQCH_CON_CLUSTER0_QCH_DBG_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CLUSTER0_QCH_DBG_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER0_QCH_LHS_ACE_D_CPUCL0, QCH_CON_CLUSTER0_QCH_LHS_ACE_D_CPUCL0_ENABLE, QCH_CON_CLUSTER0_QCH_LHS_ACE_D_CPUCL0_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_LHS_ACE_D_CPUCL0_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_LHS_ACE_D_CPUCL0_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_CPUCL0_SHORTSTOP_QCH, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_EXPIRE_VAL, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CPUCL0_CMU_CPUCL0_QCH, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_ENABLE, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_CLOCK_REQ, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CSSYS_DBG_QCH, DMYQCH_CON_CSSYS_DBG_QCH_ENABLE, DMYQCH_CON_CSSYS_DBG_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CSSYS_DBG_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DUMP_PC_CPUCL0_QCH, QCH_CON_DUMP_PC_CPUCL0_QCH_ENABLE, QCH_CON_DUMP_PC_CPUCL0_QCH_CLOCK_REQ, QCH_CON_DUMP_PC_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_DUMP_PC_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DUMP_PC_CPUCL1_QCH, QCH_CON_DUMP_PC_CPUCL1_QCH_ENABLE, QCH_CON_DUMP_PC_CPUCL1_QCH_CLOCK_REQ, QCH_CON_DUMP_PC_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_DUMP_PC_CPUCL1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_CPUCL0_QCH, QCH_CON_LHM_AXI_P_CPUCL0_QCH_ENABLE, QCH_CON_LHM_AXI_P_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_CSSYS_QCH, QCH_CON_LHS_AXI_D_CSSYS_QCH_ENABLE, QCH_CON_LHS_AXI_D_CSSYS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_CSSYS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_CSSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SECJTAG_QCH, QCH_CON_SECJTAG_QCH_ENABLE, QCH_CON_SECJTAG_QCH_CLOCK_REQ, QCH_CON_SECJTAG_QCH_EXPIRE_VAL, QCH_CON_SECJTAG_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CPUCL0_QCH, QCH_CON_SYSREG_CPUCL0_QCH_ENABLE, QCH_CON_SYSREG_CPUCL0_QCH_CLOCK_REQ, QCH_CON_SYSREG_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADM_APB_G_CSSYS_CPUCL1_QCH, DMYQCH_CON_ADM_APB_G_CSSYS_CPUCL1_QCH_ENABLE, DMYQCH_CON_ADM_APB_G_CSSYS_CPUCL1_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADM_APB_G_CSSYS_CPUCL1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_HPMCPUCL1_QCH, QCH_CON_BUSIF_HPMCPUCL1_QCH_ENABLE, QCH_CON_BUSIF_HPMCPUCL1_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMCPUCL1_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMCPUCL1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER1_QCH_CPU, DMYQCH_CON_CLUSTER1_QCH_CPU_ENABLE, DMYQCH_CON_CLUSTER1_QCH_CPU_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CLUSTER1_QCH_CPU_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLUSTER1_QCH_DBG, DMYQCH_CON_CLUSTER1_QCH_DBG_ENABLE, DMYQCH_CON_CLUSTER1_QCH_DBG_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CLUSTER1_QCH_DBG_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_CPUCL1_SHORTSTOP_QCH, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_EXPIRE_VAL, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CPUCL1_CMU_CPUCL1_QCH, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_ENABLE, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_CLOCK_REQ, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_CPUCL1_QCH, QCH_CON_LHM_AXI_P_CPUCL1_QCH_ENABLE, QCH_CON_LHM_AXI_P_CPUCL1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_CPUCL1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACE_D_CPUCL1_QCH, QCH_CON_LHS_ACE_D_CPUCL1_QCH_ENABLE, QCH_CON_LHS_ACE_D_CPUCL1_QCH_CLOCK_REQ, QCH_CON_LHS_ACE_D_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_LHS_ACE_D_CPUCL1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_CPUCL1_QCH, QCH_CON_SYSREG_CPUCL1_QCH_ENABLE, QCH_CON_SYSREG_CPUCL1_QCH_CLOCK_REQ, QCH_CON_SYSREG_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CPUCL1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_CPU, DMYQCH_CON_ABOX_QCH_CPU_ENABLE, DMYQCH_CON_ABOX_QCH_CPU_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ABOX_QCH_CPU_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_S_ACLK, QCH_CON_ABOX_QCH_S_ACLK_ENABLE, QCH_CON_ABOX_QCH_S_ACLK_CLOCK_REQ, QCH_CON_ABOX_QCH_S_ACLK_EXPIRE_VAL, QCH_CON_ABOX_QCH_S_ACLK_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_S_BCLK0, QCH_CON_ABOX_QCH_S_BCLK0_ENABLE, QCH_CON_ABOX_QCH_S_BCLK0_CLOCK_REQ, QCH_CON_ABOX_QCH_S_BCLK0_EXPIRE_VAL, QCH_CON_ABOX_QCH_S_BCLK0_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_S_BCLK2, QCH_CON_ABOX_QCH_S_BCLK2_ENABLE, QCH_CON_ABOX_QCH_S_BCLK2_CLOCK_REQ, QCH_CON_ABOX_QCH_S_BCLK2_EXPIRE_VAL, QCH_CON_ABOX_QCH_S_BCLK2_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_S_BCLK1, QCH_CON_ABOX_QCH_S_BCLK1_ENABLE, QCH_CON_ABOX_QCH_S_BCLK1_CLOCK_REQ, QCH_CON_ABOX_QCH_S_BCLK1_EXPIRE_VAL, QCH_CON_ABOX_QCH_S_BCLK1_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_FM, DMYQCH_CON_ABOX_QCH_FM_ENABLE, DMYQCH_CON_ABOX_QCH_FM_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ABOX_QCH_FM_IGNORE_FORCE_PM_EN),
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CLK_QCH(ABOX_QCH_S_BCLK_DSIF, QCH_CON_ABOX_QCH_S_BCLK_DSIF_ENABLE, QCH_CON_ABOX_QCH_S_BCLK_DSIF_CLOCK_REQ, QCH_CON_ABOX_QCH_S_BCLK_DSIF_EXPIRE_VAL, QCH_CON_ABOX_QCH_S_BCLK_DSIF_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_ABOX_QCH, QCH_CON_BTM_ABOX_QCH_ENABLE, QCH_CON_BTM_ABOX_QCH_CLOCK_REQ, QCH_CON_BTM_ABOX_QCH_EXPIRE_VAL, QCH_CON_BTM_ABOX_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_DPU_QCH, QCH_CON_BTM_DPU_QCH_ENABLE, QCH_CON_BTM_DPU_QCH_CLOCK_REQ, QCH_CON_BTM_DPU_QCH_EXPIRE_VAL, QCH_CON_BTM_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DISPAUD_CMU_DISPAUD_QCH, QCH_CON_DISPAUD_CMU_DISPAUD_QCH_ENABLE, QCH_CON_DISPAUD_CMU_DISPAUD_QCH_CLOCK_REQ, QCH_CON_DISPAUD_CMU_DISPAUD_QCH_EXPIRE_VAL, QCH_CON_DISPAUD_CMU_DISPAUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DPU_QCH_S_DPP, QCH_CON_DPU_QCH_S_DPP_ENABLE, QCH_CON_DPU_QCH_S_DPP_CLOCK_REQ, QCH_CON_DPU_QCH_S_DPP_EXPIRE_VAL, QCH_CON_DPU_QCH_S_DPP_IGNORE_FORCE_PM_EN),
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CLK_QCH(DPU_QCH_S_DMA, QCH_CON_DPU_QCH_S_DMA_ENABLE, QCH_CON_DPU_QCH_S_DMA_CLOCK_REQ, QCH_CON_DPU_QCH_S_DMA_EXPIRE_VAL, QCH_CON_DPU_QCH_S_DMA_IGNORE_FORCE_PM_EN),
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CLK_QCH(DPU_QCH_S_DECON, QCH_CON_DPU_QCH_S_DECON_ENABLE, QCH_CON_DPU_QCH_S_DECON_CLOCK_REQ, QCH_CON_DPU_QCH_S_DECON_EXPIRE_VAL, QCH_CON_DPU_QCH_S_DECON_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPIO_DISPAUD_QCH, QCH_CON_GPIO_DISPAUD_QCH_ENABLE, QCH_CON_GPIO_DISPAUD_QCH_CLOCK_REQ, QCH_CON_GPIO_DISPAUD_QCH_EXPIRE_VAL, QCH_CON_GPIO_DISPAUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_DISPAUD_QCH, QCH_CON_LHM_AXI_P_DISPAUD_QCH_ENABLE, QCH_CON_LHM_AXI_P_DISPAUD_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DISPAUD_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_DISPAUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D_DPU_QCH, QCH_CON_LHS_ACEL_D_DPU_QCH_ENABLE, QCH_CON_LHS_ACEL_D_DPU_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_DPU_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_ABOX_QCH, QCH_CON_LHS_AXI_D_ABOX_QCH_ENABLE, QCH_CON_LHS_AXI_D_ABOX_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_ABOX_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_ABOX_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_ABOX_QCH, QCH_CON_PPMU_ABOX_QCH_ENABLE, QCH_CON_PPMU_ABOX_QCH_CLOCK_REQ, QCH_CON_PPMU_ABOX_QCH_EXPIRE_VAL, QCH_CON_PPMU_ABOX_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_DPU_QCH, QCH_CON_PPMU_DPU_QCH_ENABLE, QCH_CON_PPMU_DPU_QCH_CLOCK_REQ, QCH_CON_PPMU_DPU_QCH_EXPIRE_VAL, QCH_CON_PPMU_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_AUD_CPU_CLKIN_QCH, QCH_CON_RSTNSYNC_CLK_AUD_CPU_CLKIN_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_AUD_CPU_CLKIN_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_AUD_CPU_CLKIN_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_AUD_CPU_CLKIN_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SMMU_ABOX_QCH, QCH_CON_SMMU_ABOX_QCH_ENABLE, QCH_CON_SMMU_ABOX_QCH_CLOCK_REQ, QCH_CON_SMMU_ABOX_QCH_EXPIRE_VAL, QCH_CON_SMMU_ABOX_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SMMU_DPU_QCH, QCH_CON_SMMU_DPU_QCH_ENABLE, QCH_CON_SMMU_DPU_QCH_CLOCK_REQ, QCH_CON_SMMU_DPU_QCH_EXPIRE_VAL, QCH_CON_SMMU_DPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_DISPAUD_QCH, QCH_CON_SYSREG_DISPAUD_QCH_ENABLE, QCH_CON_SYSREG_DISPAUD_QCH_CLOCK_REQ, QCH_CON_SYSREG_DISPAUD_QCH_EXPIRE_VAL, QCH_CON_SYSREG_DISPAUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WDT_AUD_QCH, QCH_CON_WDT_AUD_QCH_ENABLE, QCH_CON_WDT_AUD_QCH_CLOCK_REQ, QCH_CON_WDT_AUD_QCH_EXPIRE_VAL, QCH_CON_WDT_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ADM_AHB_SSS_QCH, QCH_CON_ADM_AHB_SSS_QCH_ENABLE, QCH_CON_ADM_AHB_SSS_QCH_CLOCK_REQ, QCH_CON_ADM_AHB_SSS_QCH_EXPIRE_VAL, QCH_CON_ADM_AHB_SSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_FSYS_QCH, QCH_CON_BTM_FSYS_QCH_ENABLE, QCH_CON_BTM_FSYS_QCH_CLOCK_REQ, QCH_CON_BTM_FSYS_QCH_EXPIRE_VAL, QCH_CON_BTM_FSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(FSYS_CMU_FSYS_QCH, QCH_CON_FSYS_CMU_FSYS_QCH_ENABLE, QCH_CON_FSYS_CMU_FSYS_QCH_CLOCK_REQ, QCH_CON_FSYS_CMU_FSYS_QCH_EXPIRE_VAL, QCH_CON_FSYS_CMU_FSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPIO_FSYS_QCH, QCH_CON_GPIO_FSYS_QCH_ENABLE, QCH_CON_GPIO_FSYS_QCH_CLOCK_REQ, QCH_CON_GPIO_FSYS_QCH_EXPIRE_VAL, QCH_CON_GPIO_FSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_FSYS_QCH, QCH_CON_LHM_AXI_P_FSYS_QCH_ENABLE, QCH_CON_LHM_AXI_P_FSYS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_FSYS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_FSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D_FSYS_QCH, QCH_CON_LHS_ACEL_D_FSYS_QCH_ENABLE, QCH_CON_LHS_ACEL_D_FSYS_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_FSYS_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_FSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MMC_CARD_QCH, QCH_CON_MMC_CARD_QCH_ENABLE, QCH_CON_MMC_CARD_QCH_CLOCK_REQ, QCH_CON_MMC_CARD_QCH_EXPIRE_VAL, QCH_CON_MMC_CARD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MMC_EMBD_QCH, QCH_CON_MMC_EMBD_QCH_ENABLE, QCH_CON_MMC_EMBD_QCH_CLOCK_REQ, QCH_CON_MMC_EMBD_QCH_EXPIRE_VAL, QCH_CON_MMC_EMBD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PGEN_LITE_FSYS_QCH, QCH_CON_PGEN_LITE_FSYS_QCH_ENABLE, QCH_CON_PGEN_LITE_FSYS_QCH_CLOCK_REQ, QCH_CON_PGEN_LITE_FSYS_QCH_EXPIRE_VAL, QCH_CON_PGEN_LITE_FSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_FSYS_QCH, QCH_CON_PPMU_FSYS_QCH_ENABLE, QCH_CON_PPMU_FSYS_QCH_CLOCK_REQ, QCH_CON_PPMU_FSYS_QCH_EXPIRE_VAL, QCH_CON_PPMU_FSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RTIC_QCH, QCH_CON_RTIC_QCH_ENABLE, QCH_CON_RTIC_QCH_CLOCK_REQ, QCH_CON_RTIC_QCH_EXPIRE_VAL, QCH_CON_RTIC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SSS_QCH, QCH_CON_SSS_QCH_ENABLE, QCH_CON_SSS_QCH_CLOCK_REQ, QCH_CON_SSS_QCH_EXPIRE_VAL, QCH_CON_SSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_FSYS_QCH, QCH_CON_SYSREG_FSYS_QCH_ENABLE, QCH_CON_SYSREG_FSYS_QCH_CLOCK_REQ, QCH_CON_SYSREG_FSYS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_FSYS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(UFS_EMBD_QCH_UFS, QCH_CON_UFS_EMBD_QCH_UFS_ENABLE, QCH_CON_UFS_EMBD_QCH_UFS_CLOCK_REQ, QCH_CON_UFS_EMBD_QCH_UFS_EXPIRE_VAL, QCH_CON_UFS_EMBD_QCH_UFS_IGNORE_FORCE_PM_EN),
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CLK_QCH(UFS_EMBD_QCH_FMP, QCH_CON_UFS_EMBD_QCH_FMP_ENABLE, QCH_CON_UFS_EMBD_QCH_FMP_CLOCK_REQ, QCH_CON_UFS_EMBD_QCH_FMP_EXPIRE_VAL, QCH_CON_UFS_EMBD_QCH_FMP_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_G2D_QCH, QCH_CON_BTM_G2D_QCH_ENABLE, QCH_CON_BTM_G2D_QCH_CLOCK_REQ, QCH_CON_BTM_G2D_QCH_EXPIRE_VAL, QCH_CON_BTM_G2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(G2D_QCH, QCH_CON_G2D_QCH_ENABLE, QCH_CON_G2D_QCH_CLOCK_REQ, QCH_CON_G2D_QCH_EXPIRE_VAL, QCH_CON_G2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(G2D_CMU_G2D_QCH, QCH_CON_G2D_CMU_G2D_QCH_ENABLE, QCH_CON_G2D_CMU_G2D_QCH_CLOCK_REQ, QCH_CON_G2D_CMU_G2D_QCH_EXPIRE_VAL, QCH_CON_G2D_CMU_G2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(JPEG_QCH, QCH_CON_JPEG_QCH_ENABLE, QCH_CON_JPEG_QCH_CLOCK_REQ, QCH_CON_JPEG_QCH_EXPIRE_VAL, QCH_CON_JPEG_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_G2D_QCH, QCH_CON_LHM_AXI_P_G2D_QCH_ENABLE, QCH_CON_LHM_AXI_P_G2D_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_G2D_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_G2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D_G2D_QCH, QCH_CON_LHS_ACEL_D_G2D_QCH_ENABLE, QCH_CON_LHS_ACEL_D_G2D_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_G2D_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_G2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MSCL_QCH, QCH_CON_MSCL_QCH_ENABLE, QCH_CON_MSCL_QCH_CLOCK_REQ, QCH_CON_MSCL_QCH_EXPIRE_VAL, QCH_CON_MSCL_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PGEN100_LITE_G2D_QCH, QCH_CON_PGEN100_LITE_G2D_QCH_ENABLE, QCH_CON_PGEN100_LITE_G2D_QCH_CLOCK_REQ, QCH_CON_PGEN100_LITE_G2D_QCH_EXPIRE_VAL, QCH_CON_PGEN100_LITE_G2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_G2D_QCH, QCH_CON_PPMU_G2D_QCH_ENABLE, QCH_CON_PPMU_G2D_QCH_CLOCK_REQ, QCH_CON_PPMU_G2D_QCH_EXPIRE_VAL, QCH_CON_PPMU_G2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_G2D_QCH, QCH_CON_SYSMMU_G2D_QCH_ENABLE, QCH_CON_SYSMMU_G2D_QCH_CLOCK_REQ, QCH_CON_SYSMMU_G2D_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_G2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_G2D_QCH, QCH_CON_SYSREG_G2D_QCH_ENABLE, QCH_CON_SYSREG_G2D_QCH_CLOCK_REQ, QCH_CON_SYSREG_G2D_QCH_EXPIRE_VAL, QCH_CON_SYSREG_G2D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_G3D_QCH, QCH_CON_BTM_G3D_QCH_ENABLE, QCH_CON_BTM_G3D_QCH_CLOCK_REQ, QCH_CON_BTM_G3D_QCH_EXPIRE_VAL, QCH_CON_BTM_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_HPMG3D_QCH, QCH_CON_BUSIF_HPMG3D_QCH_ENABLE, QCH_CON_BUSIF_HPMG3D_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMG3D_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMG3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(G3D_QCH, QCH_CON_G3D_QCH_ENABLE, QCH_CON_G3D_QCH_CLOCK_REQ, QCH_CON_G3D_QCH_EXPIRE_VAL, QCH_CON_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(G3D_CMU_G3D_QCH, QCH_CON_G3D_CMU_G3D_QCH_ENABLE, QCH_CON_G3D_CMU_G3D_QCH_CLOCK_REQ, QCH_CON_G3D_CMU_G3D_QCH_EXPIRE_VAL, QCH_CON_G3D_CMU_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_G3DSFR_QCH, QCH_CON_LHM_AXI_G3DSFR_QCH_ENABLE, QCH_CON_LHM_AXI_G3DSFR_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_G3DSFR_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_G3DSFR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_G3D_QCH, QCH_CON_LHM_AXI_P_G3D_QCH_ENABLE, QCH_CON_LHM_AXI_P_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_G3D_QCH, QCH_CON_LHS_AXI_D_G3D_QCH_ENABLE, QCH_CON_LHS_AXI_D_G3D_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_G3D_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_G3DSFR_QCH, QCH_CON_LHS_AXI_G3DSFR_QCH_ENABLE, QCH_CON_LHS_AXI_G3DSFR_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G3DSFR_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_G3DSFR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PGEN_LITE_G3D_QCH, QCH_CON_PGEN_LITE_G3D_QCH_ENABLE, QCH_CON_PGEN_LITE_G3D_QCH_CLOCK_REQ, QCH_CON_PGEN_LITE_G3D_QCH_EXPIRE_VAL, QCH_CON_PGEN_LITE_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_G3D_QCH, QCH_CON_SYSREG_G3D_QCH_ENABLE, QCH_CON_SYSREG_G3D_QCH_CLOCK_REQ, QCH_CON_SYSREG_G3D_QCH_EXPIRE_VAL, QCH_CON_SYSREG_G3D_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_ISP0_QCH, QCH_CON_BTM_ISP0_QCH_ENABLE, QCH_CON_BTM_ISP0_QCH_CLOCK_REQ, QCH_CON_BTM_ISP0_QCH_EXPIRE_VAL, QCH_CON_BTM_ISP0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_ISP1_QCH, QCH_CON_BTM_ISP1_QCH_ENABLE, QCH_CON_BTM_ISP1_QCH_CLOCK_REQ, QCH_CON_BTM_ISP1_QCH_EXPIRE_VAL, QCH_CON_BTM_ISP1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ISP_CMU_ISP_QCH, QCH_CON_ISP_CMU_ISP_QCH_ENABLE, QCH_CON_ISP_CMU_ISP_QCH_CLOCK_REQ, QCH_CON_ISP_CMU_ISP_QCH_EXPIRE_VAL, QCH_CON_ISP_CMU_ISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_CAMISP_QCH, QCH_CON_LHM_ATB_CAMISP_QCH_ENABLE, QCH_CON_LHM_ATB_CAMISP_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_CAMISP_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_CAMISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_ISP_QCH, QCH_CON_LHM_AXI_P_ISP_QCH_ENABLE, QCH_CON_LHM_AXI_P_ISP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_ISP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_ISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D0_ISP_QCH, QCH_CON_LHS_ACEL_D0_ISP_QCH_ENABLE, QCH_CON_LHS_ACEL_D0_ISP_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D0_ISP_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D0_ISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D1_ISP_QCH, QCH_CON_LHS_ACEL_D1_ISP_QCH_ENABLE, QCH_CON_LHS_ACEL_D1_ISP_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D1_ISP_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D1_ISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_ISP_QCH, QCH_CON_SYSREG_ISP_QCH_ENABLE, QCH_CON_SYSREG_ISP_QCH_CLOCK_REQ, QCH_CON_SYSREG_ISP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_ISP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS6P10P0_ISP_QCH_S_ISP_ISP, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_ISP_ENABLE, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_ISP_CLOCK_REQ, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_ISP_EXPIRE_VAL, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_ISP_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS6P10P0_ISP_QCH_S_ISP_MCSC, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_MCSC_ENABLE, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_MCSC_CLOCK_REQ, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_MCSC_EXPIRE_VAL, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_MCSC_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS6P10P0_ISP_QCH_S_ISP_VRA, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_VRA_ENABLE, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_VRA_CLOCK_REQ, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_VRA_EXPIRE_VAL, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_VRA_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP1_ENABLE, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP1_CLOCK_REQ, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP1_EXPIRE_VAL, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP1_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP0, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP0_ENABLE, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP0_CLOCK_REQ, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP0_EXPIRE_VAL, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP0_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS6P10P0_ISP_QCH_S_ISP_GDC, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_GDC_ENABLE, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_GDC_CLOCK_REQ, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_GDC_EXPIRE_VAL, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_GDC_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0_ENABLE, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0_CLOCK_REQ, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0_EXPIRE_VAL, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1_ENABLE, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1_CLOCK_REQ, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1_EXPIRE_VAL, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1_IGNORE_FORCE_PM_EN),
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CLK_QCH(IS6P10P0_ISP_QCH_S_ISP_PGEN_LITE_ISP, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PGEN_LITE_ISP_ENABLE, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PGEN_LITE_ISP_CLOCK_REQ, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PGEN_LITE_ISP_EXPIRE_VAL, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PGEN_LITE_ISP_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_MFCD0_QCH, QCH_CON_BTM_MFCD0_QCH_ENABLE, QCH_CON_BTM_MFCD0_QCH_CLOCK_REQ, QCH_CON_BTM_MFCD0_QCH_EXPIRE_VAL, QCH_CON_BTM_MFCD0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_MFCD1_QCH, QCH_CON_BTM_MFCD1_QCH_ENABLE, QCH_CON_BTM_MFCD1_QCH_CLOCK_REQ, QCH_CON_BTM_MFCD1_QCH_EXPIRE_VAL, QCH_CON_BTM_MFCD1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_MFC_QCH, QCH_CON_LHM_AXI_P_MFC_QCH_ENABLE, QCH_CON_LHM_AXI_P_MFC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MFC_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D0_MFC_QCH, QCH_CON_LHS_ACEL_D0_MFC_QCH_ENABLE, QCH_CON_LHS_ACEL_D0_MFC_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D0_MFC_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D0_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D1_MFC_QCH, QCH_CON_LHS_ACEL_D1_MFC_QCH_ENABLE, QCH_CON_LHS_ACEL_D1_MFC_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D1_MFC_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D1_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_ATB_MFC_QCH_S_SI, QCH_CON_LH_ATB_MFC_QCH_S_SI_ENABLE, QCH_CON_LH_ATB_MFC_QCH_S_SI_CLOCK_REQ, QCH_CON_LH_ATB_MFC_QCH_S_SI_EXPIRE_VAL, QCH_CON_LH_ATB_MFC_QCH_S_SI_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_ATB_MFC_QCH_S_MI, QCH_CON_LH_ATB_MFC_QCH_S_MI_ENABLE, QCH_CON_LH_ATB_MFC_QCH_S_MI_CLOCK_REQ, QCH_CON_LH_ATB_MFC_QCH_S_MI_EXPIRE_VAL, QCH_CON_LH_ATB_MFC_QCH_S_MI_IGNORE_FORCE_PM_EN),
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CLK_QCH(MFC_QCH, QCH_CON_MFC_QCH_ENABLE, QCH_CON_MFC_QCH_CLOCK_REQ, QCH_CON_MFC_QCH_EXPIRE_VAL, QCH_CON_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MFC_CMU_MFC_QCH, QCH_CON_MFC_CMU_MFC_QCH_ENABLE, QCH_CON_MFC_CMU_MFC_QCH_CLOCK_REQ, QCH_CON_MFC_CMU_MFC_QCH_EXPIRE_VAL, QCH_CON_MFC_CMU_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PGEN100_LITE_MFC_QCH, QCH_CON_PGEN100_LITE_MFC_QCH_ENABLE, QCH_CON_PGEN100_LITE_MFC_QCH_CLOCK_REQ, QCH_CON_PGEN100_LITE_MFC_QCH_EXPIRE_VAL, QCH_CON_PGEN100_LITE_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_MFCD0_QCH, QCH_CON_PPMU_MFCD0_QCH_ENABLE, QCH_CON_PPMU_MFCD0_QCH_CLOCK_REQ, QCH_CON_PPMU_MFCD0_QCH_EXPIRE_VAL, QCH_CON_PPMU_MFCD0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_MFCD1_QCH, QCH_CON_PPMU_MFCD1_QCH_ENABLE, QCH_CON_PPMU_MFCD1_QCH_CLOCK_REQ, QCH_CON_PPMU_MFCD1_QCH_EXPIRE_VAL, QCH_CON_PPMU_MFCD1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC_MFC_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC_MFC_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC_MFC_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC_MFC_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC_MFC_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_MFC_WFD_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC_WFD_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC_WFD_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC_WFD_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC_WFD_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_MFCD0_QCH, QCH_CON_SYSMMU_MFCD0_QCH_ENABLE, QCH_CON_SYSMMU_MFCD0_QCH_CLOCK_REQ, QCH_CON_SYSMMU_MFCD0_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_MFCD0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSMMU_MFCD1_QCH, QCH_CON_SYSMMU_MFCD1_QCH_ENABLE, QCH_CON_SYSMMU_MFCD1_QCH_CLOCK_REQ, QCH_CON_SYSMMU_MFCD1_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_MFCD1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_MFC_QCH, QCH_CON_SYSREG_MFC_QCH_ENABLE, QCH_CON_SYSREG_MFC_QCH_CLOCK_REQ, QCH_CON_SYSREG_MFC_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MFC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WFD_QCH, QCH_CON_WFD_QCH_ENABLE, QCH_CON_WFD_QCH_CLOCK_REQ, QCH_CON_WFD_QCH_EXPIRE_VAL, QCH_CON_WFD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_HPMMIF_QCH, QCH_CON_BUSIF_HPMMIF_QCH_ENABLE, QCH_CON_BUSIF_HPMMIF_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMMIF_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMMIF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_MIF_CMUREF_QCH, DMYQCH_CON_CMU_MIF_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_MIF_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_MIF_CMUREF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMC_QCH, QCH_CON_DMC_QCH_ENABLE, QCH_CON_DMC_QCH_CLOCK_REQ, QCH_CON_DMC_QCH_EXPIRE_VAL, QCH_CON_DMC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_MIF_CP_QCH, QCH_CON_LHM_AXI_D_MIF_CP_QCH_ENABLE, QCH_CON_LHM_AXI_D_MIF_CP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_MIF_CP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_MIF_CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_MIF_CPU_QCH, QCH_CON_LHM_AXI_D_MIF_CPU_QCH_ENABLE, QCH_CON_LHM_AXI_D_MIF_CPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_MIF_CPU_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_MIF_CPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_MIF_NRT_QCH, QCH_CON_LHM_AXI_D_MIF_NRT_QCH_ENABLE, QCH_CON_LHM_AXI_D_MIF_NRT_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_MIF_NRT_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_MIF_NRT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_MIF_RT_QCH, QCH_CON_LHM_AXI_D_MIF_RT_QCH_ENABLE, QCH_CON_LHM_AXI_D_MIF_RT_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_MIF_RT_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_MIF_RT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_MIF_QCH, QCH_CON_LHM_AXI_P_MIF_QCH_ENABLE, QCH_CON_LHM_AXI_P_MIF_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MIF_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_MIF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MIF_CMU_MIF_QCH, QCH_CON_MIF_CMU_MIF_QCH_ENABLE, QCH_CON_MIF_CMU_MIF_QCH_CLOCK_REQ, QCH_CON_MIF_CMU_MIF_QCH_EXPIRE_VAL, QCH_CON_MIF_CMU_MIF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_DMC_CPU_QCH, QCH_CON_PPMU_DMC_CPU_QCH_ENABLE, QCH_CON_PPMU_DMC_CPU_QCH_CLOCK_REQ, QCH_CON_PPMU_DMC_CPU_QCH_EXPIRE_VAL, QCH_CON_PPMU_DMC_CPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(QE_DMC_CPU_QCH, QCH_CON_QE_DMC_CPU_QCH_ENABLE, QCH_CON_QE_DMC_CPU_QCH_CLOCK_REQ, QCH_CON_QE_DMC_CPU_QCH_EXPIRE_VAL, QCH_CON_QE_DMC_CPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SFRAPB_BRIDGE_DDR_PHY_QCH, QCH_CON_SFRAPB_BRIDGE_DDR_PHY_QCH_ENABLE, QCH_CON_SFRAPB_BRIDGE_DDR_PHY_QCH_CLOCK_REQ, QCH_CON_SFRAPB_BRIDGE_DDR_PHY_QCH_EXPIRE_VAL, QCH_CON_SFRAPB_BRIDGE_DDR_PHY_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SFRAPB_BRIDGE_DMC_QCH, QCH_CON_SFRAPB_BRIDGE_DMC_QCH_ENABLE, QCH_CON_SFRAPB_BRIDGE_DMC_QCH_CLOCK_REQ, QCH_CON_SFRAPB_BRIDGE_DMC_QCH_EXPIRE_VAL, QCH_CON_SFRAPB_BRIDGE_DMC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SFRAPB_BRIDGE_DMC_PF_QCH, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH_ENABLE, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH_CLOCK_REQ, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH_EXPIRE_VAL, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SFRAPB_BRIDGE_DMC_PPMPU_QCH, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH_ENABLE, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH_CLOCK_REQ, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH_EXPIRE_VAL, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SFRAPB_BRIDGE_DMC_SECURE_QCH, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH_ENABLE, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH_CLOCK_REQ, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH_EXPIRE_VAL, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_MIF_QCH, QCH_CON_SYSREG_MIF_QCH_ENABLE, QCH_CON_SYSREG_MIF_QCH_CLOCK_REQ, QCH_CON_SYSREG_MIF_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MIF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_HPMMIF1_QCH, QCH_CON_BUSIF_HPMMIF1_QCH_ENABLE, QCH_CON_BUSIF_HPMMIF1_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMMIF1_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMMIF1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CMU_MIF1_CMUREF_QCH, DMYQCH_CON_CMU_MIF1_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_MIF1_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_MIF1_CMUREF_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DMC1_QCH, QCH_CON_DMC1_QCH_ENABLE, QCH_CON_DMC1_QCH_CLOCK_REQ, QCH_CON_DMC1_QCH_EXPIRE_VAL, QCH_CON_DMC1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_MIF1_CP_QCH, QCH_CON_LHM_AXI_D_MIF1_CP_QCH_ENABLE, QCH_CON_LHM_AXI_D_MIF1_CP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_MIF1_CP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_MIF1_CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_MIF1_CPU_QCH, QCH_CON_LHM_AXI_D_MIF1_CPU_QCH_ENABLE, QCH_CON_LHM_AXI_D_MIF1_CPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_MIF1_CPU_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_MIF1_CPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_MIF1_NRT_QCH, QCH_CON_LHM_AXI_D_MIF1_NRT_QCH_ENABLE, QCH_CON_LHM_AXI_D_MIF1_NRT_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_MIF1_NRT_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_MIF1_NRT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_D_MIF1_RT_QCH, QCH_CON_LHM_AXI_D_MIF1_RT_QCH_ENABLE, QCH_CON_LHM_AXI_D_MIF1_RT_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_MIF1_RT_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_MIF1_RT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MIF1_CMU_MIF1_QCH, QCH_CON_MIF1_CMU_MIF1_QCH_ENABLE, QCH_CON_MIF1_CMU_MIF1_QCH_CLOCK_REQ, QCH_CON_MIF1_CMU_MIF1_QCH_EXPIRE_VAL, QCH_CON_MIF1_CMU_MIF1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BUSIF_TMU_QCH, QCH_CON_BUSIF_TMU_QCH_ENABLE, QCH_CON_BUSIF_TMU_QCH_CLOCK_REQ, QCH_CON_BUSIF_TMU_QCH_EXPIRE_VAL, QCH_CON_BUSIF_TMU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CAMI2C_0_QCH, QCH_CON_CAMI2C_0_QCH_ENABLE, QCH_CON_CAMI2C_0_QCH_CLOCK_REQ, QCH_CON_CAMI2C_0_QCH_EXPIRE_VAL, QCH_CON_CAMI2C_0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CAMI2C_1_QCH, QCH_CON_CAMI2C_1_QCH_ENABLE, QCH_CON_CAMI2C_1_QCH_CLOCK_REQ, QCH_CON_CAMI2C_1_QCH_EXPIRE_VAL, QCH_CON_CAMI2C_1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CAMI2C_2_QCH, QCH_CON_CAMI2C_2_QCH_ENABLE, QCH_CON_CAMI2C_2_QCH_CLOCK_REQ, QCH_CON_CAMI2C_2_QCH_EXPIRE_VAL, QCH_CON_CAMI2C_2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CAMI2C_3_QCH, QCH_CON_CAMI2C_3_QCH_ENABLE, QCH_CON_CAMI2C_3_QCH_CLOCK_REQ, QCH_CON_CAMI2C_3_QCH_EXPIRE_VAL, QCH_CON_CAMI2C_3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPIO_PERI_QCH, QCH_CON_GPIO_PERI_QCH_ENABLE, QCH_CON_GPIO_PERI_QCH_CLOCK_REQ, QCH_CON_GPIO_PERI_QCH_EXPIRE_VAL, QCH_CON_GPIO_PERI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_0_QCH, QCH_CON_I2C_0_QCH_ENABLE, QCH_CON_I2C_0_QCH_CLOCK_REQ, QCH_CON_I2C_0_QCH_EXPIRE_VAL, QCH_CON_I2C_0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_1_QCH, QCH_CON_I2C_1_QCH_ENABLE, QCH_CON_I2C_1_QCH_CLOCK_REQ, QCH_CON_I2C_1_QCH_EXPIRE_VAL, QCH_CON_I2C_1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_2_QCH, QCH_CON_I2C_2_QCH_ENABLE, QCH_CON_I2C_2_QCH_CLOCK_REQ, QCH_CON_I2C_2_QCH_EXPIRE_VAL, QCH_CON_I2C_2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_3_QCH, QCH_CON_I2C_3_QCH_ENABLE, QCH_CON_I2C_3_QCH_CLOCK_REQ, QCH_CON_I2C_3_QCH_EXPIRE_VAL, QCH_CON_I2C_3_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_4_QCH, QCH_CON_I2C_4_QCH_ENABLE, QCH_CON_I2C_4_QCH_CLOCK_REQ, QCH_CON_I2C_4_QCH_EXPIRE_VAL, QCH_CON_I2C_4_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_5_QCH, QCH_CON_I2C_5_QCH_ENABLE, QCH_CON_I2C_5_QCH_CLOCK_REQ, QCH_CON_I2C_5_QCH_EXPIRE_VAL, QCH_CON_I2C_5_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_6_QCH, QCH_CON_I2C_6_QCH_ENABLE, QCH_CON_I2C_6_QCH_CLOCK_REQ, QCH_CON_I2C_6_QCH_EXPIRE_VAL, QCH_CON_I2C_6_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_PERI_QCH, QCH_CON_LHM_AXI_P_PERI_QCH_ENABLE, QCH_CON_LHM_AXI_P_PERI_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_PERI_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_PERI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MCT_QCH, QCH_CON_MCT_QCH_ENABLE, QCH_CON_MCT_QCH_CLOCK_REQ, QCH_CON_MCT_QCH_EXPIRE_VAL, QCH_CON_MCT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(OTP_CON_TOP_QCH, QCH_CON_OTP_CON_TOP_QCH_ENABLE, QCH_CON_OTP_CON_TOP_QCH_CLOCK_REQ, QCH_CON_OTP_CON_TOP_QCH_EXPIRE_VAL, QCH_CON_OTP_CON_TOP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PERI_CMU_PERI_QCH, QCH_CON_PERI_CMU_PERI_QCH_ENABLE, QCH_CON_PERI_CMU_PERI_QCH_CLOCK_REQ, QCH_CON_PERI_CMU_PERI_QCH_EXPIRE_VAL, QCH_CON_PERI_CMU_PERI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PWM_MOTOR_QCH, QCH_CON_PWM_MOTOR_QCH_ENABLE, QCH_CON_PWM_MOTOR_QCH_CLOCK_REQ, QCH_CON_PWM_MOTOR_QCH_EXPIRE_VAL, QCH_CON_PWM_MOTOR_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SPI_0_QCH, QCH_CON_SPI_0_QCH_ENABLE, QCH_CON_SPI_0_QCH_CLOCK_REQ, QCH_CON_SPI_0_QCH_EXPIRE_VAL, QCH_CON_SPI_0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SPI_1_QCH, QCH_CON_SPI_1_QCH_ENABLE, QCH_CON_SPI_1_QCH_CLOCK_REQ, QCH_CON_SPI_1_QCH_EXPIRE_VAL, QCH_CON_SPI_1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SPI_2_QCH, QCH_CON_SPI_2_QCH_ENABLE, QCH_CON_SPI_2_QCH_CLOCK_REQ, QCH_CON_SPI_2_QCH_EXPIRE_VAL, QCH_CON_SPI_2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_PERI_QCH, QCH_CON_SYSREG_PERI_QCH_ENABLE, QCH_CON_SYSREG_PERI_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERI_QCH_EXPIRE_VAL, QCH_CON_SYSREG_PERI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(UART_QCH, QCH_CON_UART_QCH_ENABLE, QCH_CON_UART_QCH_CLOCK_REQ, QCH_CON_UART_QCH_EXPIRE_VAL, QCH_CON_UART_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI00_I2C_QCH, QCH_CON_USI00_I2C_QCH_ENABLE, QCH_CON_USI00_I2C_QCH_CLOCK_REQ, QCH_CON_USI00_I2C_QCH_EXPIRE_VAL, QCH_CON_USI00_I2C_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI00_USI_QCH, QCH_CON_USI00_USI_QCH_ENABLE, QCH_CON_USI00_USI_QCH_CLOCK_REQ, QCH_CON_USI00_USI_QCH_EXPIRE_VAL, QCH_CON_USI00_USI_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WDT_CLUSTER0_QCH, QCH_CON_WDT_CLUSTER0_QCH_ENABLE, QCH_CON_WDT_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_WDT_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_WDT_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WDT_CLUSTER1_QCH, QCH_CON_WDT_CLUSTER1_QCH_ENABLE, QCH_CON_WDT_CLUSTER1_QCH_CLOCK_REQ, QCH_CON_WDT_CLUSTER1_QCH_EXPIRE_VAL, QCH_CON_WDT_CLUSTER1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_D_SHUB_QCH, QCH_CON_BAAW_D_SHUB_QCH_ENABLE, QCH_CON_BAAW_D_SHUB_QCH_CLOCK_REQ, QCH_CON_BAAW_D_SHUB_QCH_EXPIRE_VAL, QCH_CON_BAAW_D_SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BAAW_P_APM_SHUB_QCH, QCH_CON_BAAW_P_APM_SHUB_QCH_ENABLE, QCH_CON_BAAW_P_APM_SHUB_QCH_CLOCK_REQ, QCH_CON_BAAW_P_APM_SHUB_QCH_EXPIRE_VAL, QCH_CON_BAAW_P_APM_SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CM4_SHUB_QCH, QCH_CON_CM4_SHUB_QCH_ENABLE, QCH_CON_CM4_SHUB_QCH_CLOCK_REQ, QCH_CON_CM4_SHUB_QCH_EXPIRE_VAL, QCH_CON_CM4_SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GPIO_SHUB_QCH, QCH_CON_GPIO_SHUB_QCH_ENABLE, QCH_CON_GPIO_SHUB_QCH_CLOCK_REQ, QCH_CON_GPIO_SHUB_QCH_EXPIRE_VAL, QCH_CON_GPIO_SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(I2C_SHUB00_QCH, QCH_CON_I2C_SHUB00_QCH_ENABLE, QCH_CON_I2C_SHUB00_QCH_CLOCK_REQ, QCH_CON_I2C_SHUB00_QCH_EXPIRE_VAL, QCH_CON_I2C_SHUB00_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_LP_SHUB_QCH, QCH_CON_LHM_AXI_LP_SHUB_QCH_ENABLE, QCH_CON_LHM_AXI_LP_SHUB_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_LP_SHUB_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_LP_SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_SHUB_QCH, QCH_CON_LHM_AXI_P_SHUB_QCH_ENABLE, QCH_CON_LHM_AXI_P_SHUB_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_SHUB_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_D_SHUB_QCH, QCH_CON_LHS_AXI_D_SHUB_QCH_ENABLE, QCH_CON_LHS_AXI_D_SHUB_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_SHUB_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_APM_SHUB_QCH, QCH_CON_LHS_AXI_P_APM_SHUB_QCH_ENABLE, QCH_CON_LHS_AXI_P_APM_SHUB_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_APM_SHUB_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_APM_SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PDMA_SHUB_QCH, QCH_CON_PDMA_SHUB_QCH_ENABLE, QCH_CON_PDMA_SHUB_QCH_CLOCK_REQ, QCH_CON_PDMA_SHUB_QCH_EXPIRE_VAL, QCH_CON_PDMA_SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PWM_SHUB_QCH, QCH_CON_PWM_SHUB_QCH_ENABLE, QCH_CON_PWM_SHUB_QCH_CLOCK_REQ, QCH_CON_PWM_SHUB_QCH_EXPIRE_VAL, QCH_CON_PWM_SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SHUB_CMU_SHUB_QCH, QCH_CON_SHUB_CMU_SHUB_QCH_ENABLE, QCH_CON_SHUB_CMU_SHUB_QCH_CLOCK_REQ, QCH_CON_SHUB_CMU_SHUB_QCH_EXPIRE_VAL, QCH_CON_SHUB_CMU_SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SWEEPER_D_SHUB_QCH, QCH_CON_SWEEPER_D_SHUB_QCH_ENABLE, QCH_CON_SWEEPER_D_SHUB_QCH_CLOCK_REQ, QCH_CON_SWEEPER_D_SHUB_QCH_EXPIRE_VAL, QCH_CON_SWEEPER_D_SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SWEEPER_P_APM_SHUB_QCH, QCH_CON_SWEEPER_P_APM_SHUB_QCH_ENABLE, QCH_CON_SWEEPER_P_APM_SHUB_QCH_CLOCK_REQ, QCH_CON_SWEEPER_P_APM_SHUB_QCH_EXPIRE_VAL, QCH_CON_SWEEPER_P_APM_SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_SHUB_QCH, QCH_CON_SYSREG_SHUB_QCH_ENABLE, QCH_CON_SYSREG_SHUB_QCH_CLOCK_REQ, QCH_CON_SYSREG_SHUB_QCH_EXPIRE_VAL, QCH_CON_SYSREG_SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TIMER_SHUB_QCH, QCH_CON_TIMER_SHUB_QCH_ENABLE, QCH_CON_TIMER_SHUB_QCH_CLOCK_REQ, QCH_CON_TIMER_SHUB_QCH_EXPIRE_VAL, QCH_CON_TIMER_SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USI_SHUB00_QCH, QCH_CON_USI_SHUB00_QCH_ENABLE, QCH_CON_USI_SHUB00_QCH_CLOCK_REQ, QCH_CON_USI_SHUB00_QCH_EXPIRE_VAL, QCH_CON_USI_SHUB00_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WDT_SHUB_QCH, QCH_CON_WDT_SHUB_QCH_ENABLE, QCH_CON_WDT_SHUB_QCH_CLOCK_REQ, QCH_CON_WDT_SHUB_QCH_EXPIRE_VAL, QCH_CON_WDT_SHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_USB_QCH, QCH_CON_BTM_USB_QCH_ENABLE, QCH_CON_BTM_USB_QCH_CLOCK_REQ, QCH_CON_BTM_USB_QCH_EXPIRE_VAL, QCH_CON_BTM_USB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DP_LINK_QCH_DP, QCH_CON_DP_LINK_QCH_DP_ENABLE, QCH_CON_DP_LINK_QCH_DP_CLOCK_REQ, QCH_CON_DP_LINK_QCH_DP_EXPIRE_VAL, QCH_CON_DP_LINK_QCH_DP_IGNORE_FORCE_PM_EN),
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CLK_QCH(DP_LINK_QCH_GTC, QCH_CON_DP_LINK_QCH_GTC_ENABLE, QCH_CON_DP_LINK_QCH_GTC_CLOCK_REQ, QCH_CON_DP_LINK_QCH_GTC_EXPIRE_VAL, QCH_CON_DP_LINK_QCH_GTC_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_USB_QCH, QCH_CON_LHM_AXI_P_USB_QCH_ENABLE, QCH_CON_LHM_AXI_P_USB_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_USB_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_USB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D_USB_QCH, QCH_CON_LHS_ACEL_D_USB_QCH_ENABLE, QCH_CON_LHS_ACEL_D_USB_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_USB_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_USB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PGEN_LITE_USB_QCH, QCH_CON_PGEN_LITE_USB_QCH_ENABLE, QCH_CON_PGEN_LITE_USB_QCH_CLOCK_REQ, QCH_CON_PGEN_LITE_USB_QCH_EXPIRE_VAL, QCH_CON_PGEN_LITE_USB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_USB_QCH, QCH_CON_PPMU_USB_QCH_ENABLE, QCH_CON_PPMU_USB_QCH_CLOCK_REQ, QCH_CON_PPMU_USB_QCH_EXPIRE_VAL, QCH_CON_PPMU_USB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_USB_QCH, QCH_CON_SYSREG_USB_QCH_ENABLE, QCH_CON_SYSREG_USB_QCH_CLOCK_REQ, QCH_CON_SYSREG_USB_QCH_EXPIRE_VAL, QCH_CON_SYSREG_USB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(USB30DRD_QCH_USB30, QCH_CON_USB30DRD_QCH_USB30_ENABLE, QCH_CON_USB30DRD_QCH_USB30_CLOCK_REQ, QCH_CON_USB30DRD_QCH_USB30_EXPIRE_VAL, QCH_CON_USB30DRD_QCH_USB30_IGNORE_FORCE_PM_EN),
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CLK_QCH(USB30DRD_QCH_USBPHY_30CTRL_0, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_0_ENABLE, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_0_CLOCK_REQ, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_0_EXPIRE_VAL, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_0_IGNORE_FORCE_PM_EN),
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CLK_QCH(USB30DRD_QCH_USBPHY_30CTRL_1, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_1_ENABLE, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_1_CLOCK_REQ, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_1_EXPIRE_VAL, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_1_IGNORE_FORCE_PM_EN),
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CLK_QCH(USB30DRD_QCH_USBPHY_20CTRL, QCH_CON_USB30DRD_QCH_USBPHY_20CTRL_ENABLE, QCH_CON_USB30DRD_QCH_USBPHY_20CTRL_CLOCK_REQ, QCH_CON_USB30DRD_QCH_USBPHY_20CTRL_EXPIRE_VAL, QCH_CON_USB30DRD_QCH_USBPHY_20CTRL_IGNORE_FORCE_PM_EN),
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CLK_QCH(USB_CMU_USB_QCH, QCH_CON_USB_CMU_USB_QCH_ENABLE, QCH_CON_USB_CMU_USB_QCH_CLOCK_REQ, QCH_CON_USB_CMU_USB_QCH_EXPIRE_VAL, QCH_CON_USB_CMU_USB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_D_VIPX1_QCH, QCH_CON_BTM_D_VIPX1_QCH_ENABLE, QCH_CON_BTM_D_VIPX1_QCH_CLOCK_REQ, QCH_CON_BTM_D_VIPX1_QCH_EXPIRE_VAL, QCH_CON_BTM_D_VIPX1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_VIPX1_QCH, QCH_CON_LHM_ATB_VIPX1_QCH_ENABLE, QCH_CON_LHM_ATB_VIPX1_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_VIPX1_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_VIPX1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_VIPX1_QCH, QCH_CON_LHM_AXI_P_VIPX1_QCH_ENABLE, QCH_CON_LHM_AXI_P_VIPX1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_VIPX1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_VIPX1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D_VIPX1_QCH, QCH_CON_LHS_ACEL_D_VIPX1_QCH_ENABLE, QCH_CON_LHS_ACEL_D_VIPX1_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_VIPX1_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_VIPX1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_VIPX1_QCH, QCH_CON_LHS_ATB_VIPX1_QCH_ENABLE, QCH_CON_LHS_ATB_VIPX1_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_VIPX1_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_VIPX1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_AXI_P_VIPX1_LOCAL_QCH, QCH_CON_LHS_AXI_P_VIPX1_LOCAL_QCH_ENABLE, QCH_CON_LHS_AXI_P_VIPX1_LOCAL_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_VIPX1_LOCAL_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_VIPX1_LOCAL_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PGEN_LITE_VIPX1_QCH, QCH_CON_PGEN_LITE_VIPX1_QCH_ENABLE, QCH_CON_PGEN_LITE_VIPX1_QCH_CLOCK_REQ, QCH_CON_PGEN_LITE_VIPX1_QCH_EXPIRE_VAL, QCH_CON_PGEN_LITE_VIPX1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_D_VIPX1_QCH, QCH_CON_PPMU_D_VIPX1_QCH_ENABLE, QCH_CON_PPMU_D_VIPX1_QCH_CLOCK_REQ, QCH_CON_PPMU_D_VIPX1_QCH_EXPIRE_VAL, QCH_CON_PPMU_D_VIPX1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SMMU_D_VIPX1_QCH, QCH_CON_SMMU_D_VIPX1_QCH_ENABLE, QCH_CON_SMMU_D_VIPX1_QCH_CLOCK_REQ, QCH_CON_SMMU_D_VIPX1_QCH_EXPIRE_VAL, QCH_CON_SMMU_D_VIPX1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_VIPX1_QCH, QCH_CON_SYSREG_VIPX1_QCH_ENABLE, QCH_CON_SYSREG_VIPX1_QCH_CLOCK_REQ, QCH_CON_SYSREG_VIPX1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_VIPX1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VIPX1_QCH, QCH_CON_VIPX1_QCH_ENABLE, QCH_CON_VIPX1_QCH_CLOCK_REQ, QCH_CON_VIPX1_QCH_EXPIRE_VAL, QCH_CON_VIPX1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VIPX1_CMU_VIPX1_QCH, QCH_CON_VIPX1_CMU_VIPX1_QCH_ENABLE, QCH_CON_VIPX1_CMU_VIPX1_QCH_CLOCK_REQ, QCH_CON_VIPX1_CMU_VIPX1_QCH_EXPIRE_VAL, QCH_CON_VIPX1_CMU_VIPX1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(BTM_D_VIPX2_QCH, QCH_CON_BTM_D_VIPX2_QCH_ENABLE, QCH_CON_BTM_D_VIPX2_QCH_CLOCK_REQ, QCH_CON_BTM_D_VIPX2_QCH_EXPIRE_VAL, QCH_CON_BTM_D_VIPX2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_ATB_VIPX2_QCH, QCH_CON_LHM_ATB_VIPX2_QCH_ENABLE, QCH_CON_LHM_ATB_VIPX2_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_VIPX2_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_VIPX2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_VIPX2_QCH, QCH_CON_LHM_AXI_P_VIPX2_QCH_ENABLE, QCH_CON_LHM_AXI_P_VIPX2_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_VIPX2_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_VIPX2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHM_AXI_P_VIPX2_LOCAL_QCH, QCH_CON_LHM_AXI_P_VIPX2_LOCAL_QCH_ENABLE, QCH_CON_LHM_AXI_P_VIPX2_LOCAL_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_VIPX2_LOCAL_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_VIPX2_LOCAL_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ACEL_D_VIPX2_QCH, QCH_CON_LHS_ACEL_D_VIPX2_QCH_ENABLE, QCH_CON_LHS_ACEL_D_VIPX2_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_VIPX2_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_VIPX2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LHS_ATB_VIPX2_QCH, QCH_CON_LHS_ATB_VIPX2_QCH_ENABLE, QCH_CON_LHS_ATB_VIPX2_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_VIPX2_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_VIPX2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PGEN_LITE_VIPX2_QCH, QCH_CON_PGEN_LITE_VIPX2_QCH_ENABLE, QCH_CON_PGEN_LITE_VIPX2_QCH_CLOCK_REQ, QCH_CON_PGEN_LITE_VIPX2_QCH_EXPIRE_VAL, QCH_CON_PGEN_LITE_VIPX2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PPMU_D_VIPX2_QCH, QCH_CON_PPMU_D_VIPX2_QCH_ENABLE, QCH_CON_PPMU_D_VIPX2_QCH_CLOCK_REQ, QCH_CON_PPMU_D_VIPX2_QCH_EXPIRE_VAL, QCH_CON_PPMU_D_VIPX2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SMMU_D_VIPX2_QCH, QCH_CON_SMMU_D_VIPX2_QCH_ENABLE, QCH_CON_SMMU_D_VIPX2_QCH_CLOCK_REQ, QCH_CON_SMMU_D_VIPX2_QCH_EXPIRE_VAL, QCH_CON_SMMU_D_VIPX2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_VIPX2_QCH, QCH_CON_SYSREG_VIPX2_QCH_ENABLE, QCH_CON_SYSREG_VIPX2_QCH_CLOCK_REQ, QCH_CON_SYSREG_VIPX2_QCH_EXPIRE_VAL, QCH_CON_SYSREG_VIPX2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VIPX2_QCH, QCH_CON_VIPX2_QCH_ENABLE, QCH_CON_VIPX2_QCH_CLOCK_REQ, QCH_CON_VIPX2_QCH_EXPIRE_VAL, QCH_CON_VIPX2_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VIPX2_QCH_LOCAL, QCH_CON_VIPX2_QCH_LOCAL_ENABLE, QCH_CON_VIPX2_QCH_LOCAL_CLOCK_REQ, QCH_CON_VIPX2_QCH_LOCAL_EXPIRE_VAL, QCH_CON_VIPX2_QCH_LOCAL_IGNORE_FORCE_PM_EN),
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CLK_QCH(VIPX2_CMU_VIPX2_QCH, QCH_CON_VIPX2_CMU_VIPX2_QCH_ENABLE, QCH_CON_VIPX2_CMU_VIPX2_QCH_CLOCK_REQ, QCH_CON_VIPX2_CMU_VIPX2_QCH_EXPIRE_VAL, QCH_CON_VIPX2_CMU_VIPX2_QCH_IGNORE_FORCE_PM_EN),
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};
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/*====================The section of controller option nodes===================*/
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unsigned int cmucal_option_size = 22;
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struct cmucal_option cmucal_option_list[] = {
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CLK_OPTION(CTRL_OPTION_CMU_APM, APM_CMU_APM_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, APM_CMU_APM_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_CAM, CAM_CMU_CAM_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CAM_CMU_CAM_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_CMGP, CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_TOP, CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_CORE, CORE_CMU_CORE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CORE_CMU_CORE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_CPUCL0, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_EMBEDDED_CMU_CPUCL0, CPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_CPUCL1, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_EMBEDDED_CMU_CPUCL1, CPUCL1_EMBEDDED_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL1_EMBEDDED_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_DISPAUD, DISPAUD_CMU_DISPAUD_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DISPAUD_CMU_DISPAUD_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_FSYS, FSYS_CMU_FSYS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, FSYS_CMU_FSYS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_G2D, G2D_CMU_G2D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, G2D_CMU_G2D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_G3D, G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_ISP, ISP_CMU_ISP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, ISP_CMU_ISP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_MFC, MFC_CMU_MFC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MFC_CMU_MFC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_MIF, MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_MIF1, MIF1_CMU_MIF1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MIF1_CMU_MIF1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_PERI, PERI_CMU_PERI_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, PERI_CMU_PERI_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_SHUB, SHUB_CMU_SHUB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, SHUB_CMU_SHUB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_USB, USB_CMU_USB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, USB_CMU_USB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_VIPX1, VIPX1_CMU_VIPX1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, VIPX1_CMU_VIPX1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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CLK_OPTION(CTRL_OPTION_CMU_VIPX2, VIPX2_CMU_VIPX2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, VIPX2_CMU_VIPX2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
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};
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