709 lines
14 KiB
C
Executable File
709 lines
14 KiB
C
Executable File
#ifndef __CMUCAL_VCLK_H__
|
|
#define __CMUCAL_VCLK_H__
|
|
|
|
#include "../cmucal.h"
|
|
|
|
/*=================CMUCAL version: S5E8895================================*/
|
|
|
|
enum vclk_id {
|
|
/* DVFS TYPE */
|
|
VCLK_VDDI = DFS_VCLK_TYPE,
|
|
VCLK_VDD_MIF,
|
|
VCLK_VDD_G3D,
|
|
VCLK_VDD_MNGS,
|
|
VCLK_VDD_APOLLO,
|
|
VCLK_DFS_ABOX,
|
|
end_of_dfs_vclk,
|
|
num_of_dfs_vclk = end_of_dfs_vclk - DFS_VCLK_TYPE,
|
|
|
|
/* SPECIAL TYPE */
|
|
VCLK_SPL_CLK_ABOX_UAIF0_BLK_ABOX = (MASK_OF_ID & end_of_dfs_vclk) | VCLK_TYPE,
|
|
VCLK_SPL_CLK_ABOX_UAIF2_BLK_ABOX,
|
|
VCLK_SPL_CLK_ABOX_UAIF4_BLK_ABOX,
|
|
VCLK_DIV_CLK_ABOX_DMIC_BLK_ABOX,
|
|
VCLK_SPL_CLK_ABOX_CPU_PCLKDBG_BLK_ABOX,
|
|
VCLK_SPL_CLK_ABOX_UAIF1_BLK_ABOX,
|
|
VCLK_SPL_CLK_ABOX_UAIF3_BLK_ABOX,
|
|
VCLK_SPL_CLK_ABOX_CPU_ACLK_BLK_ABOX,
|
|
VCLK_SPL_CLK_FSYS1_MMC_CARD_BLK_CMU,
|
|
VCLK_SPL_CLK_PERIC0_USI00_BLK_CMU,
|
|
VCLK_SPL_CLK_PERIC0_USI03_BLK_CMU,
|
|
VCLK_SPL_CLK_PERIC1_UART_BT_BLK_CMU,
|
|
VCLK_SPL_CLK_PERIC1_USI06_BLK_CMU,
|
|
VCLK_SPL_CLK_PERIC1_USI09_BLK_CMU,
|
|
VCLK_SPL_CLK_PERIC1_USI12_BLK_CMU,
|
|
VCLK_OCC_CMU_CMUREF_BLK_CMU,
|
|
VCLK_CLKCMU_CIS_CLK0_BLK_CMU,
|
|
VCLK_CLKCMU_CIS_CLK2_BLK_CMU,
|
|
VCLK_CLKCMU_HPM_BLK_CMU,
|
|
VCLK_SPL_CLK_FSYS0_DPGTC_BLK_CMU,
|
|
VCLK_SPL_CLK_FSYS0_MMC_EMBD_BLK_CMU,
|
|
VCLK_SPL_CLK_FSYS0_UFS_EMBD_BLK_CMU,
|
|
VCLK_SPL_CLK_FSYS0_USBDRD30_BLK_CMU,
|
|
VCLK_SPL_CLK_FSYS1_UFS_CARD_BLK_CMU,
|
|
VCLK_SPL_CLK_PERIC0_UART_DBG_BLK_CMU,
|
|
VCLK_SPL_CLK_PERIC0_USI01_BLK_CMU,
|
|
VCLK_SPL_CLK_PERIC0_USI02_BLK_CMU,
|
|
VCLK_SPL_CLK_PERIC1_SPI_CAM0_BLK_CMU,
|
|
VCLK_SPL_CLK_PERIC1_SPI_CAM1_BLK_CMU,
|
|
VCLK_SPL_CLK_PERIC1_USI04_BLK_CMU,
|
|
VCLK_SPL_CLK_PERIC1_USI05_BLK_CMU,
|
|
VCLK_SPL_CLK_PERIC1_USI07_BLK_CMU,
|
|
VCLK_SPL_CLK_PERIC1_USI08_BLK_CMU,
|
|
VCLK_SPL_CLK_PERIC1_USI10_BLK_CMU,
|
|
VCLK_SPL_CLK_PERIC1_USI11_BLK_CMU,
|
|
VCLK_SPL_CLK_PERIC1_USI13_BLK_CMU,
|
|
VCLK_CLKCMU_CIS_CLK1_BLK_CMU,
|
|
VCLK_CLKCMU_CIS_CLK3_BLK_CMU,
|
|
VCLK_OCC_CLK_FSYS1_PCIE_BLK_CMU,
|
|
VCLK_DIV_CLK_CLUSTER0_ATCLK_BLK_CPUCL0,
|
|
VCLK_SPL_CLK_CPUCL0_CMUREF_BLK_CPUCL0,
|
|
VCLK_DIV_CLK_CPUCL0_PCLKDBG_BLK_CPUCL0,
|
|
VCLK_DIV_CLK_CLUSTER1_CNTCLK_BLK_CPUCL1,
|
|
VCLK_DIV_CLK_CPUCL1_CMUREF_BLK_CPUCL1,
|
|
VCLK_DIV_CLK_CLUSTER1_ATCLK_BLK_CPUCL1,
|
|
VCLK_DIV_CLK_CLUSTER1_PCLKDBG_BLK_CPUCL1,
|
|
VCLK_SPL_CLK_DPU1_DECON2_BLK_DPU1,
|
|
VCLK_OCC_MIF_CMUREF_BLK_MIF,
|
|
VCLK_OCC_MIF1_CMUREF_BLK_MIF1,
|
|
VCLK_OCC_MIF2_CMUREF_BLK_MIF2,
|
|
VCLK_OCC_MIF3_CMUREF_BLK_MIF3,
|
|
VCLK_SPL_CLK_VTS_DMICIF_DIV2_BLK_VTS,
|
|
VCLK_DIV_CLK_VTS_DMIC_BLK_VTS,
|
|
end_of_vclk,
|
|
num_of_vclk = end_of_vclk - ((MASK_OF_ID & end_of_dfs_vclk) | VCLK_TYPE),
|
|
|
|
/* COMMON TYPE */
|
|
VCLK_BLK_ABOX = (MASK_OF_ID & end_of_vclk) | COMMON_VCLK_TYPE,
|
|
VCLK_BLK_BUS1,
|
|
VCLK_BLK_BUSC,
|
|
VCLK_BLK_CAM,
|
|
VCLK_BLK_CMU,
|
|
VCLK_BLK_CORE,
|
|
VCLK_BLK_CPUCL0,
|
|
VCLK_BLK_CPUCL1,
|
|
VCLK_BLK_DBG,
|
|
VCLK_BLK_DCAM,
|
|
VCLK_BLK_DPU0,
|
|
VCLK_BLK_DSP,
|
|
VCLK_BLK_G2D,
|
|
VCLK_BLK_G3D,
|
|
VCLK_BLK_ISPHQ,
|
|
VCLK_BLK_ISPLP,
|
|
VCLK_BLK_IVA,
|
|
VCLK_BLK_MFC,
|
|
VCLK_BLK_MIF,
|
|
VCLK_BLK_MIF1,
|
|
VCLK_BLK_MIF2,
|
|
VCLK_BLK_MIF3,
|
|
VCLK_BLK_SRDZ,
|
|
VCLK_BLK_VPU,
|
|
VCLK_BLK_VTS,
|
|
end_of_common_vclk,
|
|
num_of_common_vclk = end_of_common_vclk - ((MASK_OF_ID & end_of_vclk) | COMMON_VCLK_TYPE),
|
|
|
|
/* GATING TYPE */
|
|
VCLK_ABOX_CMU_ABOX = (MASK_OF_ID & end_of_common_vclk) | GATE_VCLK_TYPE,
|
|
VCLK_ABOX_DAP,
|
|
VCLK_ABOX_TOP,
|
|
VCLK_AXI_US_32to128,
|
|
VCLK_BTM_ABOX,
|
|
VCLK_DFTMUX_ABOX,
|
|
VCLK_DMIC,
|
|
VCLK_GPIO_ABOX,
|
|
VCLK_LHM_AXI_P_ABOX,
|
|
VCLK_LHS_ATB_ABOX,
|
|
VCLK_LHS_AXI_D_ABOX,
|
|
VCLK_PERI_AXI_ASB,
|
|
VCLK_PMU_ABOX,
|
|
VCLK_BCM_ABOX,
|
|
VCLK_SMMU_ABOX,
|
|
VCLK_SYSREG_ABOX,
|
|
VCLK_TREX_ABOX,
|
|
VCLK_WDT_ABOXCPU,
|
|
VCLK_WRAP2_CONV_ABOX,
|
|
VCLK_APM,
|
|
VCLK_APM_CMU_APM,
|
|
VCLK_LHM_AXI_P_ALIVE,
|
|
VCLK_LHS_AXI_D_ALIVE,
|
|
VCLK_MAILBOX_APM2AP,
|
|
VCLK_MAILBOX_APM2CP,
|
|
VCLK_MAILBOX_APM2GNSS,
|
|
VCLK_SCAN2AXI,
|
|
VCLK_SYSREG_APM,
|
|
VCLK_WDT_APM,
|
|
VCLK_AXI2APB_BUS1,
|
|
VCLK_AXI2APB_BUS1_TREX,
|
|
VCLK_BUS1_CMU_BUS1,
|
|
VCLK_LHM_ACEL_D_FSYS1,
|
|
VCLK_LHM_AXI_D_ALIVE,
|
|
VCLK_LHM_AXI_D_GNSS,
|
|
VCLK_LHS_AXI_P_ALIVE,
|
|
VCLK_LHS_AXI_P_FSYS1,
|
|
VCLK_PMU_BUS1,
|
|
VCLK_SYSREG_BUS1,
|
|
VCLK_TREX_D_BUS1,
|
|
VCLK_TREX_P_BUS1,
|
|
VCLK_ADCIF_BUSC,
|
|
VCLK_AD_APB_HSI2CDF,
|
|
VCLK_AD_APB_PDMA0,
|
|
VCLK_AD_APB_SPDMA,
|
|
VCLK_ASYNCSFR_WR_SCI,
|
|
VCLK_ASYNCSFR_WR_SMC,
|
|
VCLK_AXI2APB_BUSCP0,
|
|
VCLK_AXI2APB_BUSCP1,
|
|
VCLK_AXI2APB_BUSC_TDP,
|
|
VCLK_BUSC_CMU_BUSC,
|
|
VCLK_BUSIF_CMUTOPC,
|
|
VCLK_GNSSMBOX,
|
|
VCLK_GPIO_BUSC,
|
|
VCLK_HSI2CDF,
|
|
VCLK_LHM_ACEL_D0_G2D,
|
|
VCLK_LHM_ACEL_D1_G2D,
|
|
VCLK_LHM_ACEL_D2_G2D,
|
|
VCLK_LHM_ACEL_D_DSP,
|
|
VCLK_LHM_ACEL_D_FSYS0,
|
|
VCLK_LHM_ACEL_D_IVA,
|
|
VCLK_LHM_ACEL_D_VPU,
|
|
VCLK_LHM_AXI_D0_CAM,
|
|
VCLK_LHM_AXI_D0_DPU,
|
|
VCLK_LHM_AXI_D0_MFC,
|
|
VCLK_LHM_AXI_D1_CAM,
|
|
VCLK_LHM_AXI_D1_DPU,
|
|
VCLK_LHM_AXI_D1_MFC,
|
|
VCLK_LHM_AXI_D2_DPU,
|
|
VCLK_LHM_AXI_D_ABOX,
|
|
VCLK_LHM_AXI_D_ISPLP,
|
|
VCLK_LHM_AXI_D_SRDZ,
|
|
VCLK_LHM_AXI_D_VTS,
|
|
VCLK_LHM_AXI_G_CSSYS,
|
|
VCLK_LHS_AXI_D_IVASC,
|
|
VCLK_LHS_AXI_P0_DPU,
|
|
VCLK_LHS_AXI_P1_DPU,
|
|
VCLK_LHS_AXI_P_ABOX,
|
|
VCLK_LHS_AXI_P_CAM,
|
|
VCLK_LHS_AXI_P_DSP,
|
|
VCLK_LHS_AXI_P_FSYS0,
|
|
VCLK_LHS_AXI_P_G2D,
|
|
VCLK_LHS_AXI_P_ISPHQ,
|
|
VCLK_LHS_AXI_P_ISPLP,
|
|
VCLK_LHS_AXI_P_IVA,
|
|
VCLK_LHS_AXI_P_MFC,
|
|
VCLK_LHS_AXI_P_MIF0,
|
|
VCLK_LHS_AXI_P_MIF1,
|
|
VCLK_LHS_AXI_P_MIF2,
|
|
VCLK_LHS_AXI_P_MIF3,
|
|
VCLK_LHS_AXI_P_PERIC0,
|
|
VCLK_LHS_AXI_P_PERIC1,
|
|
VCLK_LHS_AXI_P_PERIS,
|
|
VCLK_LHS_AXI_P_SRDZ,
|
|
VCLK_LHS_AXI_P_VPU,
|
|
VCLK_LHS_AXI_P_VTS,
|
|
VCLK_MBOX,
|
|
VCLK_PDMA0,
|
|
VCLK_PMU_BUSC,
|
|
VCLK_SECMBOX,
|
|
VCLK_SPDMA,
|
|
VCLK_SPEEDY,
|
|
VCLK_SPEEDY_BATCHER_WRAP,
|
|
VCLK_SYSREG_BUSC,
|
|
VCLK_TREX_D_BUSC,
|
|
VCLK_TREX_P_BUSC,
|
|
VCLK_BTM_CAMD0,
|
|
VCLK_BTM_CAMD1,
|
|
VCLK_CAM_CMU_CAM,
|
|
VCLK_ISP_EWGEN_CAM,
|
|
VCLK_IS_CAM,
|
|
VCLK_LHM_ATB_SRDZCAM,
|
|
VCLK_LHM_AXI_P_CAM,
|
|
VCLK_LHS_AXI_D0_CAM,
|
|
VCLK_LHS_AXI_D1_CAM,
|
|
VCLK_PMU_CAM,
|
|
VCLK_SYSREG_CAM,
|
|
VCLK_ADM_APB_G_BDU,
|
|
VCLK_APBBR_CCI,
|
|
VCLK_AXI2APB_CORE,
|
|
VCLK_AXI2APB_CORE_TP,
|
|
VCLK_BDU,
|
|
VCLK_BUSIF_HPMCORE,
|
|
VCLK_CCI,
|
|
VCLK_CORE_CMU_CORE,
|
|
VCLK_HPM_CORE,
|
|
VCLK_LHM_ACE_D0_G3D,
|
|
VCLK_LHM_ACE_D1_G3D,
|
|
VCLK_LHM_ACE_D2_G3D,
|
|
VCLK_LHM_ACE_D3_G3D,
|
|
VCLK_LHM_ACE_D_CPUCL1,
|
|
VCLK_LHM_AXI_D_CP,
|
|
VCLK_LHM_AXI_P_CP,
|
|
VCLK_LHM_CPACE_D_CPUCL0,
|
|
VCLK_LHM_DBG_G0_DMC,
|
|
VCLK_LHM_DBG_G1_DMC,
|
|
VCLK_LHM_DBG_G2_DMC,
|
|
VCLK_LHM_DBG_G3_DMC,
|
|
VCLK_LHS_ATB_T_BDU,
|
|
VCLK_LHS_AXI_P_CPUCL0,
|
|
VCLK_LHS_AXI_P_CPUCL1,
|
|
VCLK_LHS_AXI_P_DBG,
|
|
VCLK_LHS_AXI_P_G3D,
|
|
VCLK_LHS_AXI_P_IMEM,
|
|
VCLK_LHS_PSCDC_D_MIF0,
|
|
VCLK_LHS_PSCDC_D_MIF1,
|
|
VCLK_LHS_PSCDC_D_MIF2,
|
|
VCLK_LHS_PSCDC_D_MIF3,
|
|
VCLK_MPACE2AXI_0,
|
|
VCLK_MPACE2AXI_1,
|
|
VCLK_PMU_CORE,
|
|
VCLK_PPCFW_G3D,
|
|
VCLK_BCMPPC_CCI,
|
|
VCLK_BCM_CPUCL0,
|
|
VCLK_BCM_CPUCL1,
|
|
VCLK_BCM_G3D0,
|
|
VCLK_BCM_G3D1,
|
|
VCLK_BCM_G3D2,
|
|
VCLK_BCM_G3D3,
|
|
VCLK_SYSREG_CORE,
|
|
VCLK_TREX_D_CORE,
|
|
VCLK_TREX_P0_CORE,
|
|
VCLK_TREX_P1_CORE,
|
|
VCLK_AXI2APB_CPUCL0,
|
|
VCLK_BUSIF_DROOPDETECTOR_CPUCL0,
|
|
VCLK_BUSIF_HPMCPUCL0,
|
|
VCLK_CPUCL0_CMU_CPUCL0,
|
|
VCLK_DROOP_DETECTOR_CPUCL0_GRP0,
|
|
VCLK_DROOP_DETECTOR_CPUCL0_GRP1,
|
|
VCLK_HPM_CPUCL0,
|
|
VCLK_LHM_AXI_P_CPUCL0,
|
|
VCLK_PMU_CPUCL0,
|
|
VCLK_SYSREG_CPUCL0,
|
|
VCLK_AXI2APB_CPUCL1,
|
|
VCLK_BUSIF_HPMCPUCL1,
|
|
VCLK_CPUCL1_CMU_CPUCL1,
|
|
VCLK_HPM_CPUCL1,
|
|
VCLK_LHM_AXI_P_CPUCL1,
|
|
VCLK_PMU_CPUCL1,
|
|
VCLK_SYSREG_CPUCL1,
|
|
VCLK_AXI2APB_CORESIGHT,
|
|
VCLK_CSSYS,
|
|
VCLK_DBG_CMU_DBG,
|
|
VCLK_DUMPPC_CPUCL0,
|
|
VCLK_DUMPPC_CPUCL1,
|
|
VCLK_LHM_ATB_T0_CLUSTER0,
|
|
VCLK_LHM_ATB_T0_CLUSTER1,
|
|
VCLK_LHM_ATB_T1_CLUSTER0,
|
|
VCLK_LHM_ATB_T1_CLUSTER1,
|
|
VCLK_LHM_ATB_T2_CLUSTER0,
|
|
VCLK_LHM_ATB_T2_CLUSTER1,
|
|
VCLK_LHM_ATB_T3_CLUSTER0,
|
|
VCLK_LHM_ATB_T3_CLUSTER1,
|
|
VCLK_LHM_ATB_T_AUD,
|
|
VCLK_LHM_ATB_T_BDU,
|
|
VCLK_LHM_AXI_P_DBG,
|
|
VCLK_LHS_AXI_G_CSSYS,
|
|
VCLK_LHS_AXI_G_ETR,
|
|
VCLK_PMU_DBG,
|
|
VCLK_SECJTAG,
|
|
VCLK_STM_TXACTOR,
|
|
VCLK_SYSREG_DBG,
|
|
VCLK_AD_APB_DCAM,
|
|
VCLK_AXI2APB_DCAM,
|
|
VCLK_AXI2APB_DCAM_SYS,
|
|
VCLK_BTM_DCAM,
|
|
VCLK_DCAM_CMU_DCAM,
|
|
VCLK_DCP,
|
|
VCLK_LHM_AXI_P_SRDZDCAM,
|
|
VCLK_LHS_ATB_DCAMSRDZ,
|
|
VCLK_LHS_AXI_D_DCAMSRDZ,
|
|
VCLK_PMU_DCAM,
|
|
VCLK_BCM_DCAM,
|
|
VCLK_PXL_ASBM_DCAM,
|
|
VCLK_PXL_ASBS_DCAM,
|
|
VCLK_SYSREG_DCAM,
|
|
VCLK_XIU_P_DCAM,
|
|
VCLK_AD_APB_DECON0,
|
|
VCLK_AD_APB_DECON0_SECURE,
|
|
VCLK_AD_APB_DPP,
|
|
VCLK_AD_APB_DPP_SECURE,
|
|
VCLK_AD_APB_DPU_DMA,
|
|
VCLK_AD_APB_DPU_DMA_SECURE,
|
|
VCLK_AD_APB_DPU_WB_MUX,
|
|
VCLK_AD_APB_MIPI_DSIM0,
|
|
VCLK_AD_APB_MIPI_DSIM1,
|
|
VCLK_AXI2APB_DPU0P0,
|
|
VCLK_AXI2APB_DPU0P1,
|
|
VCLK_BTM_DPUD0,
|
|
VCLK_BTM_DPUD1,
|
|
VCLK_BTM_DPUD2,
|
|
VCLK_DECON0,
|
|
VCLK_DPP,
|
|
VCLK_DPU0_CMU_DPU0,
|
|
VCLK_DPU_DMA,
|
|
VCLK_DPU_WB_MUX,
|
|
VCLK_LHM_AXI_P0_DPU,
|
|
VCLK_LHS_AXI_D0_DPU,
|
|
VCLK_LHS_AXI_D1_DPU,
|
|
VCLK_LHS_AXI_D2_DPU,
|
|
VCLK_LHS_AXI_D_USBTV,
|
|
VCLK_PMU_DPU0,
|
|
VCLK_BCM_DPUD0,
|
|
VCLK_BCM_DPUD1,
|
|
VCLK_BCM_DPUD2,
|
|
VCLK_SYSMMU_DPUD0,
|
|
VCLK_SYSMMU_DPUD1,
|
|
VCLK_SYSMMU_DPUD2,
|
|
VCLK_SYSREG_DPU0,
|
|
VCLK_XIU_P0_DPU,
|
|
VCLK_AD_APB_DECON1,
|
|
VCLK_AD_APB_DECON2,
|
|
VCLK_AXI2APB_DPU1P0,
|
|
VCLK_DECON1,
|
|
VCLK_DECON2,
|
|
VCLK_DPU1_CMU_DPU1,
|
|
VCLK_LHM_AXI_P_DPU1,
|
|
VCLK_PMU_DPU1,
|
|
VCLK_SYSREG_DPU1,
|
|
VCLK_AD_APB_SCORE,
|
|
VCLK_AXI2APB_DSP,
|
|
VCLK_BTM_SCORE,
|
|
VCLK_DSP_CMU_DSP,
|
|
VCLK_LHM_AXI_D_IVADSP,
|
|
VCLK_LHM_AXI_D_VPUDSP,
|
|
VCLK_LHM_AXI_P_DSP,
|
|
VCLK_LHM_AXI_P_IVADSP,
|
|
VCLK_LHS_ACEL_D_DSP,
|
|
VCLK_LHS_AXI_P_DSPIVA,
|
|
VCLK_LHS_AXI_P_DSPVPU,
|
|
VCLK_PMU_DSP,
|
|
VCLK_BCM_SCORE,
|
|
VCLK_SCORE,
|
|
VCLK_SMMU_SCORE,
|
|
VCLK_SYSREG_DSP,
|
|
VCLK_WRAP2_CONV_DSP,
|
|
VCLK_XIU_D_DSP0,
|
|
VCLK_XIU_D_DSP1,
|
|
VCLK_XIU_P_DSP,
|
|
VCLK_AHBBR_FSYS0,
|
|
VCLK_AXI2AHB_FSYS0,
|
|
VCLK_AXI2AHB_USB_FSYS0,
|
|
VCLK_AXI2APB_FSYS0,
|
|
VCLK_BTM_FSYS0,
|
|
VCLK_DP_LINK,
|
|
VCLK_ETR_MIU,
|
|
VCLK_FSYS0_CMU_FSYS0,
|
|
VCLK_GPIO_FSYS0,
|
|
VCLK_LHM_AXI_D_USBTV,
|
|
VCLK_LHM_AXI_G_ETR,
|
|
VCLK_LHM_AXI_P_FSYS0,
|
|
VCLK_LHS_ACEL_D_FSYS0,
|
|
VCLK_MMC_EMBD,
|
|
VCLK_PMU_FSYS0,
|
|
VCLK_BCM_FSYS0,
|
|
VCLK_SYSREG_FSYS0,
|
|
VCLK_UFS_EMBD,
|
|
VCLK_USBTV,
|
|
VCLK_US_D_FSYS0_USB,
|
|
VCLK_XIU_D_FSYS0,
|
|
VCLK_XIU_D_FSYS0_USB,
|
|
VCLK_XIU_P_FSYS0,
|
|
VCLK_ADM_AHB_SSS,
|
|
VCLK_AHBBR_FSYS1,
|
|
VCLK_AXI2AHB_FSYS1,
|
|
VCLK_AXI2APB_FSYS1P0,
|
|
VCLK_AXI2APB_FSYS1P1,
|
|
VCLK_BTM_FSYS1,
|
|
VCLK_FSYS1_CMU_FSYS1,
|
|
VCLK_GPIO_FSYS1,
|
|
VCLK_LHM_AXI_P_FSYS1,
|
|
VCLK_LHS_ACEL_D_FSYS1,
|
|
VCLK_MMC_CARD,
|
|
VCLK_PCIE,
|
|
VCLK_PMU_FSYS1,
|
|
VCLK_BCM_FSYS1,
|
|
VCLK_RTIC,
|
|
VCLK_SSS,
|
|
VCLK_SYSREG_FSYS1,
|
|
VCLK_TOE_WIFI0,
|
|
VCLK_TOE_WIFI1,
|
|
VCLK_UFS_CARD,
|
|
VCLK_XIU_D_FSYS1,
|
|
VCLK_XIU_P_FSYS1,
|
|
VCLK_AS_P_G2DP,
|
|
VCLK_AS_P_JPEGP,
|
|
VCLK_AS_P_M2MSCALERP,
|
|
VCLK_AXI2APB_G2DP0,
|
|
VCLK_AXI2APB_G2DP1,
|
|
VCLK_BTM_G2DD0,
|
|
VCLK_BTM_G2DD1,
|
|
VCLK_BTM_G2DD2,
|
|
VCLK_G2D,
|
|
VCLK_G2D_CMU_G2D,
|
|
VCLK_JPEG,
|
|
VCLK_LHM_AXI_P_G2D,
|
|
VCLK_LHS_ACEL_D0_G2D,
|
|
VCLK_LHS_ACEL_D1_G2D,
|
|
VCLK_LHS_ACEL_D2_G2D,
|
|
VCLK_M2MSCALER,
|
|
VCLK_PMU_G2D,
|
|
VCLK_BCM_G2DD0,
|
|
VCLK_BCM_G2DD1,
|
|
VCLK_BCM_G2DD2,
|
|
VCLK_QE_JPEG,
|
|
VCLK_QE_M2MSCALER,
|
|
VCLK_SMMU_G2DD0,
|
|
VCLK_SMMU_G2DD1,
|
|
VCLK_SMMU_G2DD2,
|
|
VCLK_SYSREG_G2D,
|
|
VCLK_XIU_D_G2D,
|
|
VCLK_XIU_P_G2D,
|
|
VCLK_AXI2APB_G3D,
|
|
VCLK_BUSIF_HPMG3D,
|
|
VCLK_G3D_CMU_G3D,
|
|
VCLK_HPM_G3D,
|
|
VCLK_LHM_AXI_P_G3D,
|
|
VCLK_LHS_AXI_G3DSFR,
|
|
VCLK_PMU_G3D,
|
|
VCLK_SYSREG_G3D,
|
|
VCLK_XIU_P_G3D,
|
|
VCLK_AXI2APB_IMEM,
|
|
VCLK_IMEM_CMU_IMEM,
|
|
VCLK_IntMEM,
|
|
VCLK_LHM_AXI_P_IMEM,
|
|
VCLK_PMU_IMEM,
|
|
VCLK_SYSREG_IMEM,
|
|
VCLK_XIU_P_IMEM,
|
|
VCLK_ISPHQ_CMU_ISPHQ,
|
|
VCLK_ISP_EWGEN_ISPHQ,
|
|
VCLK_IS_ISPHQ,
|
|
VCLK_LHM_AXI_P_ISPHQ,
|
|
VCLK_LHS_AXI_LD_ISPHQ,
|
|
VCLK_PMU_ISPHQ,
|
|
VCLK_SYSREG_ISPHQ,
|
|
VCLK_BTM_ISPLP,
|
|
VCLK_ISPLP_CMU_ISPLP,
|
|
VCLK_ISP_EWGEN_ISPLP,
|
|
VCLK_IS_ISPLP,
|
|
VCLK_LHM_AXI_LD_ISPHQ,
|
|
VCLK_LHM_AXI_P_ISPLP,
|
|
VCLK_LHS_AXI_D_ISPLP,
|
|
VCLK_PMU_ISPLP,
|
|
VCLK_SYSREG_ISPLP,
|
|
VCLK_AD_APB_IVA,
|
|
VCLK_AXI2APB_2M_IVA,
|
|
VCLK_AXI2APB_IVA,
|
|
VCLK_BTM_IVA,
|
|
VCLK_IVA,
|
|
VCLK_IVA_CMU_IVA,
|
|
VCLK_IVA_IntMEM,
|
|
VCLK_LHM_AXI_D_IVASC,
|
|
VCLK_LHM_AXI_P_DSPIVA,
|
|
VCLK_LHM_AXI_P_IVA,
|
|
VCLK_LHS_ACEL_D_IVA,
|
|
VCLK_LHS_AXI_D_IVADSP,
|
|
VCLK_LHS_AXI_P_IVADSP,
|
|
VCLK_PMU_IVA,
|
|
VCLK_BCM_IVA,
|
|
VCLK_SMMU_IVA,
|
|
VCLK_SYSREG_IVA,
|
|
VCLK_XIU_D_IVA,
|
|
VCLK_XIU_P_IVA,
|
|
VCLK_AS_P_MFCP,
|
|
VCLK_AXI2APB_MFC,
|
|
VCLK_BTM_MFCD0,
|
|
VCLK_BTM_MFCD1,
|
|
VCLK_LHM_AXI_P_MFC,
|
|
VCLK_LHS_AXI_D0_MFC,
|
|
VCLK_LHS_AXI_D1_MFC,
|
|
VCLK_MFC,
|
|
VCLK_MFC_CMU_MFC,
|
|
VCLK_PMU_MFC,
|
|
VCLK_BCM_MFCD0,
|
|
VCLK_BCM_MFCD1,
|
|
VCLK_SMMU_MFCD0,
|
|
VCLK_SMMU_MFCD1,
|
|
VCLK_SYSREG_MFC,
|
|
VCLK_APBBR_DDRPHY,
|
|
VCLK_APBBR_DMC,
|
|
VCLK_APBBR_DMCTZ,
|
|
VCLK_AXI2APB_MIF,
|
|
VCLK_BUSIF_HPMMIF,
|
|
VCLK_DDRPHY,
|
|
VCLK_DMC,
|
|
VCLK_HPM_MIF,
|
|
VCLK_LHM_AXI_P_MIF,
|
|
VCLK_LHM_PSCDC_D_MIF,
|
|
VCLK_MIF_CMU_MIF,
|
|
VCLK_PMU_MIF,
|
|
VCLK_BCMPPC_DEBUG,
|
|
VCLK_BCMPPC_DVFS,
|
|
VCLK_SYSREG_MIF,
|
|
VCLK_APBBR_DDRPHY1,
|
|
VCLK_APBBR_DMC1,
|
|
VCLK_APBBR_DMCTZ1,
|
|
VCLK_AXI2APB_MIF1,
|
|
VCLK_BUSIF_HPMMIF1,
|
|
VCLK_DDRPHY1,
|
|
VCLK_DMC1,
|
|
VCLK_HPM_MIF1,
|
|
VCLK_LHM_AXI_P_MIF1,
|
|
VCLK_LHM_PSCDC_D_MIF1,
|
|
VCLK_MIF1_CMU_MIF1,
|
|
VCLK_PMU_MIF1,
|
|
VCLK_BCMPPC_DEBUG1,
|
|
VCLK_BCMPPC_DVFS1,
|
|
VCLK_SYSREG_MIF1,
|
|
VCLK_APBBR_DDRPHY2,
|
|
VCLK_APBBR_DMC2,
|
|
VCLK_APBBR_DMCTZ2,
|
|
VCLK_AXI2APB_MIF2,
|
|
VCLK_BUSIF_HPMMIF2,
|
|
VCLK_DDRPHY2,
|
|
VCLK_DMC2,
|
|
VCLK_HPM_MIF2,
|
|
VCLK_LHM_AXI_P_MIF2,
|
|
VCLK_LHM_PSCDC_D_MIF2,
|
|
VCLK_MIF2_CMU_MIF2,
|
|
VCLK_PMU_MIF2,
|
|
VCLK_BCMPPC_DEBUG2,
|
|
VCLK_BCMPPC_DVFS2,
|
|
VCLK_SYSREG_MIF2,
|
|
VCLK_APBBR_DDRPHY3,
|
|
VCLK_APBBR_DMC3,
|
|
VCLK_APBBR_DMCTZ3,
|
|
VCLK_AXI2APB_MIF3,
|
|
VCLK_BUSIF_HPMMIF3,
|
|
VCLK_DDRPHY3,
|
|
VCLK_DMC3,
|
|
VCLK_HPM_MIF3,
|
|
VCLK_LHM_AXI_P_MIF3,
|
|
VCLK_LHM_PSCDC_D_MIF3,
|
|
VCLK_MIF3_CMU_MIF3,
|
|
VCLK_PMU_MIF3,
|
|
VCLK_BCMPPC_DEBUG3,
|
|
VCLK_BCMPPC_DVFS3,
|
|
VCLK_SYSREG_MIF3,
|
|
VCLK_AXI2APB_PERIC0,
|
|
VCLK_GPIO_PERIC0,
|
|
VCLK_LHM_AXI_P_PERIC0,
|
|
VCLK_PERIC0_CMU_PERIC0,
|
|
VCLK_PMU_PERIC0,
|
|
VCLK_PWM,
|
|
VCLK_SPEEDY2_TSP,
|
|
VCLK_SYSREG_PERIC0,
|
|
VCLK_UART_DBG,
|
|
VCLK_USI00,
|
|
VCLK_USI01,
|
|
VCLK_USI02,
|
|
VCLK_USI03,
|
|
VCLK_AXI2APB_PERIC1P0,
|
|
VCLK_AXI2APB_PERIC1P1,
|
|
VCLK_AXI2APB_PERIC1P2,
|
|
VCLK_GPIO_PERIC1,
|
|
VCLK_HSI2C_CAM0,
|
|
VCLK_HSI2C_CAM1,
|
|
VCLK_HSI2C_CAM2,
|
|
VCLK_HSI2C_CAM3,
|
|
VCLK_LHM_AXI_P_PERIC1,
|
|
VCLK_PERIC1_CMU_PERIC1,
|
|
VCLK_PMU_PERIC1,
|
|
VCLK_SPEEDY2_DDI,
|
|
VCLK_SPEEDY2_DDI1,
|
|
VCLK_SPEEDY2_DDI2,
|
|
VCLK_SPEEDY2_TSP1,
|
|
VCLK_SPEEDY2_TSP2,
|
|
VCLK_SPI_CAM0,
|
|
VCLK_SPI_CAM1,
|
|
VCLK_SYSREG_PERIC1,
|
|
VCLK_UART_BT,
|
|
VCLK_USI04,
|
|
VCLK_USI05,
|
|
VCLK_USI06,
|
|
VCLK_USI07,
|
|
VCLK_USI08,
|
|
VCLK_USI09,
|
|
VCLK_USI10,
|
|
VCLK_USI11,
|
|
VCLK_USI12,
|
|
VCLK_USI13,
|
|
VCLK_XIU_P_PERIC1,
|
|
VCLK_AD_AXI_P_PERIS,
|
|
VCLK_AXI2APB_PERISP0,
|
|
VCLK_AXI2APB_PERISP1,
|
|
VCLK_BUSIF_TMU,
|
|
VCLK_GIC,
|
|
VCLK_LHM_AXI_P_PERIS,
|
|
VCLK_MCT,
|
|
VCLK_OTP_CON_BIRA,
|
|
VCLK_OTP_CON_TOP,
|
|
VCLK_PERIS_CMU_PERIS,
|
|
VCLK_PMU_PERIS,
|
|
VCLK_SYSREG_PERIS,
|
|
VCLK_TZPC00,
|
|
VCLK_TZPC01,
|
|
VCLK_TZPC02,
|
|
VCLK_TZPC03,
|
|
VCLK_TZPC04,
|
|
VCLK_TZPC05,
|
|
VCLK_TZPC06,
|
|
VCLK_TZPC07,
|
|
VCLK_TZPC08,
|
|
VCLK_TZPC09,
|
|
VCLK_TZPC10,
|
|
VCLK_TZPC11,
|
|
VCLK_TZPC12,
|
|
VCLK_TZPC13,
|
|
VCLK_TZPC14,
|
|
VCLK_TZPC15,
|
|
VCLK_WDT_CLUSTER0,
|
|
VCLK_WDT_CLUSTER1,
|
|
VCLK_XIU_P_PERIS,
|
|
VCLK_AD_APB_SRDZ,
|
|
VCLK_AXI2APB_SRDZ,
|
|
VCLK_AXI2APB_SRDZ_SYS,
|
|
VCLK_BTM_SRDZ,
|
|
VCLK_LHM_ATB_DCAMSRDZ,
|
|
VCLK_LHM_AXI_D_DCAMSRDZ,
|
|
VCLK_LHM_AXI_P_SRDZ,
|
|
VCLK_LHS_ATB_SRDZCAM,
|
|
VCLK_LHS_AXI_D_SRDZ,
|
|
VCLK_LHS_AXI_P_SRDZDCAM,
|
|
VCLK_PMU_SRDZ,
|
|
VCLK_BCM_SRDZ,
|
|
VCLK_PXL_ASBM_1to2_SRDZ,
|
|
VCLK_PXL_ASBS_SRDZ,
|
|
VCLK_SMMU_SRDZ,
|
|
VCLK_SRDZ,
|
|
VCLK_SRDZ_CMU_SRDZ,
|
|
VCLK_SYSREG_SRDZ,
|
|
VCLK_XIU_D_SRDZ,
|
|
VCLK_XIU_P_SRDZ,
|
|
VCLK_AXI2AHB_VPU,
|
|
VCLK_AXI2APB_VPU,
|
|
VCLK_BTM_VPU,
|
|
VCLK_LHM_AXI_P_DSPVPU,
|
|
VCLK_LHM_AXI_P_VPU,
|
|
VCLK_LHS_ACEL_D_VPU,
|
|
VCLK_LHS_AXI_D_VPUDSP,
|
|
VCLK_PMU_VPU,
|
|
VCLK_BCM_VPU,
|
|
VCLK_SMMU_VPU,
|
|
VCLK_SYSREG_VPU,
|
|
VCLK_VPU,
|
|
VCLK_VPU_CMU_VPU,
|
|
VCLK_XIU_D_VPU,
|
|
VCLK_XIU_P_VPU,
|
|
VCLK_DMIC_AHB,
|
|
VCLK_DMIC_IF,
|
|
VCLK_GPIO_VTS,
|
|
VCLK_LHM_AXI_P_VTS,
|
|
VCLK_LHS_AXI_D_VTS,
|
|
VCLK_MAILBOX_VTS2AP,
|
|
VCLK_SYSREG_VTS,
|
|
VCLK_VTS,
|
|
VCLK_VTS_CMU_VTS,
|
|
VCLK_WDT_VTS,
|
|
end_of_gating_vclk,
|
|
num_of_gating_vclk = end_of_gating_vclk - ((MASK_OF_ID & end_of_common_vclk) | GATE_VCLK_TYPE),
|
|
|
|
};
|
|
#endif
|