175 lines
6.7 KiB
C
Executable File
175 lines
6.7 KiB
C
Executable File
#ifndef __PHY_SAMSUNG_COMBO_H__
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#define __PHY_SAMSUNG_COMBO_H__
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#define EXYNOS_USBCON_CTRLVER (0x0)
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#define CTRLVER_CTRL_VER_MASK (0xFFFFFFFF)
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#define EXYNOS_USBCON_LINKCTRL (0x4)
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#define LINKCTRL_FORCE_RXELECIDLE (0x1 << 18)
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#define LINKCTRL_FORCE_PHYSTATUS (0x1 << 17)
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#define LINKCTRL_FORCE_PIPE_EN (0x1 << 16)
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#define LINKCTRL_DIS_BUSPEND_QACT (0x1 << 13)
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#define LINKCTRL_DIS_LINKGATE_QACT (0x1 << 12)
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#define LINKCTRL_DIS_ID0_QACT (0x1 << 11)
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#define LINKCTRL_DIS_VBUSVALID_QACT (0x1 << 10)
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#define LINKCTRL_DIS_BVALID_QACT (0x1 << 9)
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#define LINKCTRL_FORCE_QACT (0x1 << 8)
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#define LINKCTRL_BUS_FILTER_BYPASS_MASK (0xF << 4)
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#define LINKCTRL_HOST_SYSTEM_ERR (0x1 << 2)
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#define LINKCTRL_LINK_PME (0x1 << 1)
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#define LINKCTRL_PME_GENERATION (0x1 << 0)
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#define EXYNOS_USBCON_PHYCON_LINKPORT (0x08)
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#define PHYCON_LINKPORT_HOST_NUM_U3_MASK (0xF << 16)
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#define PHYCON_LINKPORT_HOST_NUM_U2_MASK (0xF << 12)
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#define PHYCON_LINKPORT_HOST_U3_PORT_DISABLE (0x1 << 9)
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#define PHYCON_LINKPORT_HOST_U2_PORT_DISABLE (0x1 << 8)
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#define PHYCON_LINKPORT_HOST_PORT_POWER_CON_PRESENT (0x1 << 6)
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#define PHYCON_LINKPORT_HUB_PORT_OVERCURRENT_U3 (0x1 << 5)
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#define PHYCON_LINKPORT_HUB_PORT_OVERCURRENT_U2 (0x1 << 4)
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#define PHYCON_LINKPORT_HUB_PORT_OVERCURRENT_SET_U3 (0x1 << 3)
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#define PHYCON_LINKPORT_HUB_PORT_OVERCURRENT_SET_U2 (0x1 << 2)
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#define PHYCON_LINKPORT_HUB_PERM_ATTACH_U3 (0x1 << 1)
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#define PHYCON_LINKPORT_HUB_PERM_ATTACH_U2 (0x1 << 0)
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#define EXYNOS_USBCON_LINK_DEBUG_L (0xC)
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#define LINK_DEBUG_L_DEBUG_L_MASK (0xFFFFFFFF)
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#define EXYNOS_USBCON_LINK_DEBUG_H (0x10)
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#define LINK_DEBUG_H_DEBUG_H_MASK (0xFFFFFFFF)
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#define EXYNOS_USBCON_LTSTATE_HIS (0x14)
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#define LTSTATE_HIS_LINKTRN_DONE (0x1 << 31)
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#define LTSTATE_HIS_LTSTATE_HIS4_MASK (0xF << 16)
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#define LTSTATE_HIS_LTSTATE_HIS3_MASK (0xF << 12)
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#define LTSTATE_HIS_LTSTATE_HIS2_MASK (0xF << 8)
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#define LTSTATE_HIS_LTSTATE_HIS1_MASK (0xF << 4)
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#define LTSTATE_HIS_LTSTATE_HIS0_MASK (0xF << 0)
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#define EXYNOS_USBCON_CLKRSTCTRL (0x20)
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#define CLKRSTCTRL_USBAUDIO_CLK_GATE_EN (0x1 << 9)
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#define CLKRSTCTRL_USBAUDIO_CLK_SEL (0x1 << 8)
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#define CLKRSTCTRL_LINK_PCLK_SEL (0x1 << 7)
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#define CLKRSTCTRL_REFCLKSEL (0x1 << 4)
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#define CLKRSTCTRL_PHY_SW_RST (0x1 << 3)
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#define CLKRSTCTRL_PHY_RESET_SEL (0x1 << 2)
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#define CLKRSTCTRL_PORTRESET (0x1 << 1)
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#define CLKRSTCTRL_LINK_SW_RST (0x1 << 0)
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#define EXYNOS_USBCON_PWRCTL (0x24)
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#define PWRCTL_FORCE_POWERDOWN (0x1 << 2)
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#define EXYNOS_USBCON_SSPPLLCTL (0x30)
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#define SSPPLLCTL_FSEL_MASK (0x3F << 0)
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#define EXYNOS_USBCON_SECPMACTL (0x48)
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#define SECPMACTL_PMA_PLL_REF_CLK_SEL_MASK (0x3 << 10)
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#define SECPMACTL_PMA_REF_FREQ_SEL_MASK (0x3 << 8)
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#define SECPMACTL_PMA_LOW_PWR (0x1 << 4)
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#define SECPMACTL_PMA_TRSV_SW_RST (0x1 << 3)
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#define SECPMACTL_PMA_CMN_SW_RST (0x1 << 2)
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#define SECPMACTL_PMA_INIT_SW_RST (0x1 << 1)
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#define SECPMACTL_PMA_APB_SW_RST (0x1 << 0)
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#define EXYNOS_USBCON_UTMICTRL (0x50)
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#define UTMICTRL_OPMODE_EN (0x1 << 8)
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#define UTMICTRL_FORCE_OPMODE_MASK (0x3 << 6)
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#define UTMICTRL_FORCE_VBUSVALID (0x1 << 5)
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#define UTMICTRL_FORCE_BVALID (0x1 << 4)
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#define UTMICTRL_FORCE_DPPULLDOWN (0x1 << 3)
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#define UTMICTRL_FORCE_DMPULLDOWN (0x1 << 2)
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#define UTMICTRL_FORCE_SUSPEND (0x1 << 1)
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#define UTMICTRL_FORCE_SLEEP (0x1 << 0)
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#define EXYNOS_USBCON_HSPCTRL (0x54)
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#define HSPCTRL_AUTORSM_ENB (0x1 << 29)
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#define HSPCTRL_RETENABLE_EN (0x1 << 28)
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#define HSPCTRL_FSLS_SPEED_SEL (0x1 << 25)
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#define HSPCTRL_FSV_OUT_EN (0x1 << 24)
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#define HSPCTRL_HS_XCVR_EXT_CTL (0x1 << 22)
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#define HSPCTRL_HS_RXDAT (0x1 << 21)
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#define HSPCTRL_HS_SQUELCH (0x1 << 20)
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#define HSPCTRL_FSVMINUS (0x1 << 17)
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#define HSPCTRL_FSVPLUS (0x1 << 16)
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#define HSPCTRL_VBUSVLDEXTSEL (0x1 << 13)
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#define HSPCTRL_VBUSVLDEXT (0x1 << 12)
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#define HSPCTRL_EN_UTMISUSPEND (0x1 << 9)
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#define HSPCTRL_COMMONONN (0x1 << 8)
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#define HSPCTRL_VATESTENB (0x1 << 6)
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#define HSPCTRL_CHGDET (0x1 << 5)
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#define HSPCTRL_VDATSRCENB (0x1 << 4)
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#define HSPCTRL_VDATDETENB (0x1 << 3)
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#define HSPCTRL_CHRGSEL (0x1 << 2)
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#define HSPCTRL_ACAENB (0x1 << 1)
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#define HSPCTRL_DEDENB (0x1 << 0)
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#define EXYNOS_USBCON_HSPPARACON (0x58)
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#define HSPPARACON_TXVREFTUNE_MASK (0xF << 28)
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#define HSPPARACON_TXRISETUNE_MASK (0x3 << 24)
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#define HSPPARACON_TXRESTUNE_MASK (0x3 << 21)
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#define HSPPARACON_TXPREEMPPULSETUNE (0x1 << 20)
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#define HSPPARACON_TXPREEMPAMPTUNE_MASK (0x3 << 18)
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#define HSPPARACON_TXHSXVTUNE_MASK (0x3 << 16)
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#define HSPPARACON_TXFSLSTUNE_MASK (0xF << 12)
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#define HSPPARACON_SQRXTUNE_MASK (0x7 << 8)
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#define HSPPARACON_OTGTUNE_MASK (0x7 << 4)
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#define HSPPARACON_COMPDISTUNE_MASK (0x7 << 0)
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#define EXYNOS_USBCON_HSPTEST (0x5C)
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#define HSPTEST_SIDDQ_PORT0 (0x1 << 24)
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#define HSPTEST_LINESTATE_PORT0_MASK (0x3 << 20)
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#define HSPTEST_TESTDATAOUT_PORT0_MASK (0xF << 16)
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#define HSPTEST_TESTCLK_PORT0 (0x1 << 13)
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#define HSPTEST_TESTDATAOUTSEL_PORT0 (0x1 << 12)
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#define HSPTEST_TESTADDR_PORT0_MASK (0xF << 8)
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#define HSPTEST_TESTDATAIN_PORT0_MASK (0xFF << 0)
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#define EXYNOS_USBCON_HSPPLLTUNE (0x60)
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#define HSPPLLTUNE_PLLBTUNE (0x1 << 8)
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#define HSPPLLTUNE_PLLITUNE_MASK (0x3 << 4)
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#define HSPPLLTUNE_PLLPTUNE_MASK (0xF << 0)
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#define EXYNOS_USBCON_REWA_CTRL (0x100)
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#define REWA_CTRL_HSREWA_EN (0x1 << 0)
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#define EXYNOS_USBCON_HSREWA_INTR (0x104)
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#define HSREWA_INTR_WAKEUP_MASK_MASK (0x1 << 12)
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#define HSREWA_INTR_TIMEOUT_INTR_MASK_MASK (0x1 << 8)
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#define HSREWA_INTR_EVENT_INT_MASK_MASK (0x1 << 4)
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#define HSREWA_INTR_WAKEUP_INTR_MASK_MASK (0x1 << 0)
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#define EXYNOS_USBCON_HSREWA_CTRL (0x108)
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#define HSREWA_CTRL_DIG_BYPASS_CON_EN (0x1 << 28)
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#define HSREWA_CTRL_DPDM_MONITOR_SEL (0x1 << 24)
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#define HSREWA_CTRL_HS_LINK_READY (0x1 << 20)
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#define HSREWA_CTRL_HS_SYS_VALID (0x1 << 16)
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#define HSREWA_CTRL_HS_REWA_ERROR (0x1 << 4)
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#define HSREWA_CTRL_HS_REWA_DONE (0x1 << 0)
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#define EXYNOS_USBCON_HSREWA_REFTO (0x10C)
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#define HSREWA_REFTO_HOST_K_TIMEOUT_MASK (0xFFFFFFFF << 0)
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#define EXYNOS_USBCON_HSREWA_HSTK (0x110)
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#define HSREWA_HSTK_HOST_K_DELAY_MASK (0xFFFFFFFF << 0)
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#define EXYNOS_USBCON_HSREWA_CNT (0x114)
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#define HSREWA_CNT_WAKEUP_CNT_MASK (0xFFFFFFFF << 0)
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#define EXYNOS_USBCON_HSREWA_INT1_EVNT (0x118)
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#define HSREWA_INT1_EVNT_ERR_SUS (0x1 << 18)
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#define HSREWA_INT1_EVNT_ERR_DEV_K (0x1 << 17)
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#define HSREWA_INT1_EVNT_DISCON (0x1 << 16)
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#define HSREWA_INT1_EVNT_BYPASS_DIS (0x1 << 2)
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#define HSREWA_INT1_EVNT_RET_DIS (0x1 << 1)
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#define HSREWA_INT1_EVNT_RET_EN (0x1 << 0)
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#define EXYNOS_USBCON_HSREWA_INT1_EVNT_MSK (0x11C)
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#define HSREWA_INT1_EVNT_MSK_ERR_SUS_MASK (0x1 << 18)
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#define HSREWA_INT1_EVNT_MSK_ERR_DEV_K_MASK (0x1 << 17)
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#define HSREWA_INT1_EVNT_MSK_DISCON_MASK (0x1 << 16)
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#define HSREWA_INT1_EVNT_MSK_BYPASS_DIS_MASK (0x1 << 2)
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#define HSREWA_INT1_EVNT_MSK_RET_DIS_MASK (0x1 << 1)
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#define HSREWA_INT1_EVNT_MSK_RET_EN_MASK (0x1 << 0)
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#endif
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