424 lines
11 KiB
C
Executable File
424 lines
11 KiB
C
Executable File
/*
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* TXx9 NAND flash memory controller driver
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* Based on RBTX49xx patch from CELF patch archive.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* (C) Copyright TOSHIBA CORPORATION 2004-2007
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* All Rights Reserved.
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/partitions.h>
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#include <linux/io.h>
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#include <asm/txx9/ndfmc.h>
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/* TXX9 NDFMC Registers */
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#define TXX9_NDFDTR 0x00
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#define TXX9_NDFMCR 0x04
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#define TXX9_NDFSR 0x08
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#define TXX9_NDFISR 0x0c
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#define TXX9_NDFIMR 0x10
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#define TXX9_NDFSPR 0x14
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#define TXX9_NDFRSTR 0x18 /* not TX4939 */
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/* NDFMCR : NDFMC Mode Control */
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#define TXX9_NDFMCR_WE 0x80
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#define TXX9_NDFMCR_ECC_ALL 0x60
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#define TXX9_NDFMCR_ECC_RESET 0x60
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#define TXX9_NDFMCR_ECC_READ 0x40
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#define TXX9_NDFMCR_ECC_ON 0x20
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#define TXX9_NDFMCR_ECC_OFF 0x00
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#define TXX9_NDFMCR_CE 0x10
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#define TXX9_NDFMCR_BSPRT 0x04 /* TX4925/TX4926 only */
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#define TXX9_NDFMCR_ALE 0x02
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#define TXX9_NDFMCR_CLE 0x01
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/* TX4939 only */
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#define TXX9_NDFMCR_X16 0x0400
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#define TXX9_NDFMCR_DMAREQ_MASK 0x0300
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#define TXX9_NDFMCR_DMAREQ_NODMA 0x0000
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#define TXX9_NDFMCR_DMAREQ_128 0x0100
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#define TXX9_NDFMCR_DMAREQ_256 0x0200
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#define TXX9_NDFMCR_DMAREQ_512 0x0300
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#define TXX9_NDFMCR_CS_MASK 0x0c
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#define TXX9_NDFMCR_CS(ch) ((ch) << 2)
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/* NDFMCR : NDFMC Status */
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#define TXX9_NDFSR_BUSY 0x80
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/* TX4939 only */
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#define TXX9_NDFSR_DMARUN 0x40
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/* NDFMCR : NDFMC Reset */
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#define TXX9_NDFRSTR_RST 0x01
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struct txx9ndfmc_priv {
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struct platform_device *dev;
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struct nand_chip chip;
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int cs;
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const char *mtdname;
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};
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#define MAX_TXX9NDFMC_DEV 4
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struct txx9ndfmc_drvdata {
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struct mtd_info *mtds[MAX_TXX9NDFMC_DEV];
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void __iomem *base;
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unsigned char hold; /* in gbusclock */
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unsigned char spw; /* in gbusclock */
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struct nand_hw_control hw_control;
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};
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static struct platform_device *mtd_to_platdev(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct txx9ndfmc_priv *txx9_priv = nand_get_controller_data(chip);
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return txx9_priv->dev;
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}
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static void __iomem *ndregaddr(struct platform_device *dev, unsigned int reg)
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{
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struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
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struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);
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return drvdata->base + (reg << plat->shift);
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}
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static u32 txx9ndfmc_read(struct platform_device *dev, unsigned int reg)
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{
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return __raw_readl(ndregaddr(dev, reg));
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}
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static void txx9ndfmc_write(struct platform_device *dev,
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u32 val, unsigned int reg)
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{
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__raw_writel(val, ndregaddr(dev, reg));
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}
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static uint8_t txx9ndfmc_read_byte(struct mtd_info *mtd)
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{
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struct platform_device *dev = mtd_to_platdev(mtd);
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return txx9ndfmc_read(dev, TXX9_NDFDTR);
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}
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static void txx9ndfmc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
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int len)
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{
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struct platform_device *dev = mtd_to_platdev(mtd);
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void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
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u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
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txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_WE, TXX9_NDFMCR);
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while (len--)
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__raw_writel(*buf++, ndfdtr);
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txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
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}
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static void txx9ndfmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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struct platform_device *dev = mtd_to_platdev(mtd);
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void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
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while (len--)
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*buf++ = __raw_readl(ndfdtr);
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}
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static void txx9ndfmc_cmd_ctrl(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct txx9ndfmc_priv *txx9_priv = nand_get_controller_data(chip);
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struct platform_device *dev = txx9_priv->dev;
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struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);
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if (ctrl & NAND_CTRL_CHANGE) {
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u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
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mcr &= ~(TXX9_NDFMCR_CLE | TXX9_NDFMCR_ALE | TXX9_NDFMCR_CE);
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mcr |= ctrl & NAND_CLE ? TXX9_NDFMCR_CLE : 0;
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mcr |= ctrl & NAND_ALE ? TXX9_NDFMCR_ALE : 0;
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/* TXX9_NDFMCR_CE bit is 0:high 1:low */
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mcr |= ctrl & NAND_NCE ? TXX9_NDFMCR_CE : 0;
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if (txx9_priv->cs >= 0 && (ctrl & NAND_NCE)) {
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mcr &= ~TXX9_NDFMCR_CS_MASK;
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mcr |= TXX9_NDFMCR_CS(txx9_priv->cs);
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}
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txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
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}
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if (cmd != NAND_CMD_NONE)
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txx9ndfmc_write(dev, cmd & 0xff, TXX9_NDFDTR);
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if (plat->flags & NDFMC_PLAT_FLAG_DUMMYWRITE) {
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/* dummy write to update external latch */
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if ((ctrl & NAND_CTRL_CHANGE) && cmd == NAND_CMD_NONE)
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txx9ndfmc_write(dev, 0, TXX9_NDFDTR);
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}
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mmiowb();
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}
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static int txx9ndfmc_dev_ready(struct mtd_info *mtd)
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{
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struct platform_device *dev = mtd_to_platdev(mtd);
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return !(txx9ndfmc_read(dev, TXX9_NDFSR) & TXX9_NDFSR_BUSY);
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}
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static int txx9ndfmc_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
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uint8_t *ecc_code)
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{
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struct platform_device *dev = mtd_to_platdev(mtd);
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struct nand_chip *chip = mtd_to_nand(mtd);
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int eccbytes;
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u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
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mcr &= ~TXX9_NDFMCR_ECC_ALL;
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txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
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txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_READ, TXX9_NDFMCR);
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for (eccbytes = chip->ecc.bytes; eccbytes > 0; eccbytes -= 3) {
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ecc_code[1] = txx9ndfmc_read(dev, TXX9_NDFDTR);
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ecc_code[0] = txx9ndfmc_read(dev, TXX9_NDFDTR);
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ecc_code[2] = txx9ndfmc_read(dev, TXX9_NDFDTR);
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ecc_code += 3;
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}
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txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
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return 0;
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}
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static int txx9ndfmc_correct_data(struct mtd_info *mtd, unsigned char *buf,
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unsigned char *read_ecc, unsigned char *calc_ecc)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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int eccsize;
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int corrected = 0;
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int stat;
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for (eccsize = chip->ecc.size; eccsize > 0; eccsize -= 256) {
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stat = __nand_correct_data(buf, read_ecc, calc_ecc, 256);
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if (stat < 0)
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return stat;
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corrected += stat;
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buf += 256;
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read_ecc += 3;
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calc_ecc += 3;
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}
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return corrected;
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}
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static void txx9ndfmc_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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struct platform_device *dev = mtd_to_platdev(mtd);
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u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
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mcr &= ~TXX9_NDFMCR_ECC_ALL;
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txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_RESET, TXX9_NDFMCR);
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txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
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txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_ON, TXX9_NDFMCR);
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}
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static void txx9ndfmc_initialize(struct platform_device *dev)
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{
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struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);
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struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
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int tmout = 100;
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if (plat->flags & NDFMC_PLAT_FLAG_NO_RSTR)
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; /* no NDFRSTR. Write to NDFSPR resets the NDFMC. */
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else {
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/* reset NDFMC */
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txx9ndfmc_write(dev,
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txx9ndfmc_read(dev, TXX9_NDFRSTR) |
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TXX9_NDFRSTR_RST,
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TXX9_NDFRSTR);
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while (txx9ndfmc_read(dev, TXX9_NDFRSTR) & TXX9_NDFRSTR_RST) {
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if (--tmout == 0) {
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dev_err(&dev->dev, "reset failed.\n");
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break;
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}
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udelay(1);
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}
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}
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/* setup Hold Time, Strobe Pulse Width */
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txx9ndfmc_write(dev, (drvdata->hold << 4) | drvdata->spw, TXX9_NDFSPR);
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txx9ndfmc_write(dev,
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(plat->flags & NDFMC_PLAT_FLAG_USE_BSPRT) ?
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TXX9_NDFMCR_BSPRT : 0, TXX9_NDFMCR);
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}
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#define TXX9NDFMC_NS_TO_CYC(gbusclk, ns) \
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DIV_ROUND_UP((ns) * DIV_ROUND_UP(gbusclk, 1000), 1000000)
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static int txx9ndfmc_nand_scan(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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int ret;
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ret = nand_scan_ident(mtd, 1, NULL);
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if (!ret) {
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if (mtd->writesize >= 512) {
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/* Hardware ECC 6 byte ECC per 512 Byte data */
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chip->ecc.size = 512;
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chip->ecc.bytes = 6;
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}
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ret = nand_scan_tail(mtd);
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}
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return ret;
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}
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static int __init txx9ndfmc_probe(struct platform_device *dev)
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{
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struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);
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int hold, spw;
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int i;
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struct txx9ndfmc_drvdata *drvdata;
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unsigned long gbusclk = plat->gbus_clock;
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struct resource *res;
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drvdata = devm_kzalloc(&dev->dev, sizeof(*drvdata), GFP_KERNEL);
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if (!drvdata)
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return -ENOMEM;
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res = platform_get_resource(dev, IORESOURCE_MEM, 0);
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drvdata->base = devm_ioremap_resource(&dev->dev, res);
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if (IS_ERR(drvdata->base))
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return PTR_ERR(drvdata->base);
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hold = plat->hold ?: 20; /* tDH */
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spw = plat->spw ?: 90; /* max(tREADID, tWP, tRP) */
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hold = TXX9NDFMC_NS_TO_CYC(gbusclk, hold);
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spw = TXX9NDFMC_NS_TO_CYC(gbusclk, spw);
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if (plat->flags & NDFMC_PLAT_FLAG_HOLDADD)
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hold -= 2; /* actual hold time : (HOLD + 2) BUSCLK */
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spw -= 1; /* actual wait time : (SPW + 1) BUSCLK */
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hold = clamp(hold, 1, 15);
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drvdata->hold = hold;
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spw = clamp(spw, 1, 15);
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drvdata->spw = spw;
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dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n",
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(gbusclk + 500000) / 1000000, hold, spw);
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nand_hw_control_init(&drvdata->hw_control);
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platform_set_drvdata(dev, drvdata);
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txx9ndfmc_initialize(dev);
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for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
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struct txx9ndfmc_priv *txx9_priv;
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struct nand_chip *chip;
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struct mtd_info *mtd;
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if (!(plat->ch_mask & (1 << i)))
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continue;
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txx9_priv = kzalloc(sizeof(struct txx9ndfmc_priv),
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GFP_KERNEL);
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if (!txx9_priv)
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continue;
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chip = &txx9_priv->chip;
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mtd = nand_to_mtd(chip);
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mtd->dev.parent = &dev->dev;
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chip->read_byte = txx9ndfmc_read_byte;
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chip->read_buf = txx9ndfmc_read_buf;
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chip->write_buf = txx9ndfmc_write_buf;
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chip->cmd_ctrl = txx9ndfmc_cmd_ctrl;
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chip->dev_ready = txx9ndfmc_dev_ready;
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chip->ecc.calculate = txx9ndfmc_calculate_ecc;
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chip->ecc.correct = txx9ndfmc_correct_data;
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chip->ecc.hwctl = txx9ndfmc_enable_hwecc;
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chip->ecc.mode = NAND_ECC_HW;
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/* txx9ndfmc_nand_scan will overwrite ecc.size and ecc.bytes */
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chip->ecc.size = 256;
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chip->ecc.bytes = 3;
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chip->ecc.strength = 1;
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chip->chip_delay = 100;
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chip->controller = &drvdata->hw_control;
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nand_set_controller_data(chip, txx9_priv);
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txx9_priv->dev = dev;
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if (plat->ch_mask != 1) {
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txx9_priv->cs = i;
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txx9_priv->mtdname = kasprintf(GFP_KERNEL, "%s.%u",
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dev_name(&dev->dev), i);
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} else {
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txx9_priv->cs = -1;
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txx9_priv->mtdname = kstrdup(dev_name(&dev->dev),
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GFP_KERNEL);
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}
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if (!txx9_priv->mtdname) {
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kfree(txx9_priv);
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dev_err(&dev->dev, "Unable to allocate MTD name.\n");
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continue;
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}
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if (plat->wide_mask & (1 << i))
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chip->options |= NAND_BUSWIDTH_16;
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if (txx9ndfmc_nand_scan(mtd)) {
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kfree(txx9_priv->mtdname);
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kfree(txx9_priv);
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continue;
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}
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mtd->name = txx9_priv->mtdname;
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mtd_device_parse_register(mtd, NULL, NULL, NULL, 0);
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drvdata->mtds[i] = mtd;
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}
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return 0;
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}
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static int __exit txx9ndfmc_remove(struct platform_device *dev)
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{
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struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
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int i;
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if (!drvdata)
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return 0;
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for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
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struct mtd_info *mtd = drvdata->mtds[i];
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struct nand_chip *chip;
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struct txx9ndfmc_priv *txx9_priv;
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if (!mtd)
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continue;
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chip = mtd_to_nand(mtd);
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txx9_priv = nand_get_controller_data(chip);
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nand_release(mtd);
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kfree(txx9_priv->mtdname);
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kfree(txx9_priv);
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}
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return 0;
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}
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#ifdef CONFIG_PM
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static int txx9ndfmc_resume(struct platform_device *dev)
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{
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if (platform_get_drvdata(dev))
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txx9ndfmc_initialize(dev);
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return 0;
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}
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#else
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#define txx9ndfmc_resume NULL
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#endif
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static struct platform_driver txx9ndfmc_driver = {
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.remove = __exit_p(txx9ndfmc_remove),
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.resume = txx9ndfmc_resume,
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.driver = {
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.name = "txx9ndfmc",
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},
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};
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module_platform_driver_probe(txx9ndfmc_driver, txx9ndfmc_probe);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("TXx9 SoC NAND flash controller driver");
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MODULE_ALIAS("platform:txx9ndfmc");
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