792 lines
19 KiB
C
Executable File
792 lines
19 KiB
C
Executable File
/*
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* (C) Copyright 2009-2010
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* Nokia Siemens Networks, michael.lawnick.ext@nsn.com
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*
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* Portions Copyright (C) 2010 - 2016 Cavium, Inc.
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*
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* This file contains the shared part of the driver for the i2c adapter in
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* Cavium Networks' OCTEON processors and ThunderX SOCs.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include "i2c-octeon-core.h"
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/* interrupt service routine */
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irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
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{
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struct octeon_i2c *i2c = dev_id;
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i2c->int_disable(i2c);
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wake_up(&i2c->queue);
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return IRQ_HANDLED;
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}
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static bool octeon_i2c_test_iflg(struct octeon_i2c *i2c)
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{
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return (octeon_i2c_ctl_read(i2c) & TWSI_CTL_IFLG);
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}
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/**
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* octeon_i2c_wait - wait for the IFLG to be set
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* @i2c: The struct octeon_i2c
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*
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* Returns 0 on success, otherwise a negative errno.
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*/
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static int octeon_i2c_wait(struct octeon_i2c *i2c)
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{
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long time_left;
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/*
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* Some chip revisions don't assert the irq in the interrupt
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* controller. So we must poll for the IFLG change.
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*/
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if (i2c->broken_irq_mode) {
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u64 end = get_jiffies_64() + i2c->adap.timeout;
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while (!octeon_i2c_test_iflg(i2c) &&
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time_before64(get_jiffies_64(), end))
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usleep_range(I2C_OCTEON_EVENT_WAIT / 2, I2C_OCTEON_EVENT_WAIT);
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return octeon_i2c_test_iflg(i2c) ? 0 : -ETIMEDOUT;
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}
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i2c->int_enable(i2c);
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time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_iflg(i2c),
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i2c->adap.timeout);
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i2c->int_disable(i2c);
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if (i2c->broken_irq_check && !time_left &&
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octeon_i2c_test_iflg(i2c)) {
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dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n");
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i2c->broken_irq_mode = true;
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return 0;
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}
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if (!time_left)
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return -ETIMEDOUT;
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return 0;
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}
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static bool octeon_i2c_hlc_test_valid(struct octeon_i2c *i2c)
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{
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return (__raw_readq(i2c->twsi_base + SW_TWSI(i2c)) & SW_TWSI_V) == 0;
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}
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static void octeon_i2c_hlc_int_clear(struct octeon_i2c *i2c)
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{
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/* clear ST/TS events, listen for neither */
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octeon_i2c_write_int(i2c, TWSI_INT_ST_INT | TWSI_INT_TS_INT);
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}
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/*
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* Cleanup low-level state & enable high-level controller.
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*/
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static void octeon_i2c_hlc_enable(struct octeon_i2c *i2c)
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{
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int try = 0;
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u64 val;
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if (i2c->hlc_enabled)
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return;
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i2c->hlc_enabled = true;
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while (1) {
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val = octeon_i2c_ctl_read(i2c);
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if (!(val & (TWSI_CTL_STA | TWSI_CTL_STP)))
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break;
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/* clear IFLG event */
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if (val & TWSI_CTL_IFLG)
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octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
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if (try++ > 100) {
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pr_err("%s: giving up\n", __func__);
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break;
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}
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/* spin until any start/stop has finished */
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udelay(10);
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}
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octeon_i2c_ctl_write(i2c, TWSI_CTL_CE | TWSI_CTL_AAK | TWSI_CTL_ENAB);
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}
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static void octeon_i2c_hlc_disable(struct octeon_i2c *i2c)
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{
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if (!i2c->hlc_enabled)
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return;
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i2c->hlc_enabled = false;
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octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
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}
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/**
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* octeon_i2c_hlc_wait - wait for an HLC operation to complete
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* @i2c: The struct octeon_i2c
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*
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* Returns 0 on success, otherwise -ETIMEDOUT.
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*/
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static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c)
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{
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int time_left;
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/*
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* Some cn38xx boards don't assert the irq in the interrupt
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* controller. So we must poll for the valid bit change.
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*/
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if (i2c->broken_irq_mode) {
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u64 end = get_jiffies_64() + i2c->adap.timeout;
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while (!octeon_i2c_hlc_test_valid(i2c) &&
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time_before64(get_jiffies_64(), end))
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usleep_range(I2C_OCTEON_EVENT_WAIT / 2, I2C_OCTEON_EVENT_WAIT);
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return octeon_i2c_hlc_test_valid(i2c) ? 0 : -ETIMEDOUT;
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}
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i2c->hlc_int_enable(i2c);
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time_left = wait_event_timeout(i2c->queue,
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octeon_i2c_hlc_test_valid(i2c),
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i2c->adap.timeout);
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i2c->hlc_int_disable(i2c);
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if (!time_left)
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octeon_i2c_hlc_int_clear(i2c);
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if (i2c->broken_irq_check && !time_left &&
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octeon_i2c_hlc_test_valid(i2c)) {
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dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n");
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i2c->broken_irq_mode = true;
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return 0;
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}
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if (!time_left)
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return -ETIMEDOUT;
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return 0;
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}
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static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read)
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{
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u8 stat;
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/*
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* This is ugly... in HLC mode the status is not in the status register
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* but in the lower 8 bits of SW_TWSI.
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*/
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if (i2c->hlc_enabled)
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stat = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
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else
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stat = octeon_i2c_stat_read(i2c);
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switch (stat) {
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/* Everything is fine */
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case STAT_IDLE:
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case STAT_AD2W_ACK:
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case STAT_RXADDR_ACK:
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case STAT_TXADDR_ACK:
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case STAT_TXDATA_ACK:
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return 0;
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/* ACK allowed on pre-terminal bytes only */
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case STAT_RXDATA_ACK:
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if (!final_read)
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return 0;
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return -EIO;
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/* NAK allowed on terminal byte only */
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case STAT_RXDATA_NAK:
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if (final_read)
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return 0;
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return -EIO;
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/* Arbitration lost */
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case STAT_LOST_ARB_38:
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case STAT_LOST_ARB_68:
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case STAT_LOST_ARB_78:
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case STAT_LOST_ARB_B0:
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return -EAGAIN;
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/* Being addressed as slave, should back off & listen */
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case STAT_SLAVE_60:
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case STAT_SLAVE_70:
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case STAT_GENDATA_ACK:
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case STAT_GENDATA_NAK:
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return -EOPNOTSUPP;
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/* Core busy as slave */
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case STAT_SLAVE_80:
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case STAT_SLAVE_88:
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case STAT_SLAVE_A0:
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case STAT_SLAVE_A8:
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case STAT_SLAVE_LOST:
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case STAT_SLAVE_NAK:
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case STAT_SLAVE_ACK:
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return -EOPNOTSUPP;
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case STAT_TXDATA_NAK:
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return -EIO;
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case STAT_TXADDR_NAK:
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case STAT_RXADDR_NAK:
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case STAT_AD2W_NAK:
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return -ENXIO;
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default:
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dev_err(i2c->dev, "unhandled state: %d\n", stat);
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return -EIO;
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}
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}
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static int octeon_i2c_recovery(struct octeon_i2c *i2c)
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{
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int ret;
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ret = i2c_recover_bus(&i2c->adap);
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if (ret)
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/* recover failed, try hardware re-init */
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ret = octeon_i2c_init_lowlevel(i2c);
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return ret;
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}
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/**
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* octeon_i2c_start - send START to the bus
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* @i2c: The struct octeon_i2c
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*
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* Returns 0 on success, otherwise a negative errno.
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*/
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static int octeon_i2c_start(struct octeon_i2c *i2c)
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{
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int ret;
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u8 stat;
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octeon_i2c_hlc_disable(i2c);
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octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STA);
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ret = octeon_i2c_wait(i2c);
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if (ret)
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goto error;
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stat = octeon_i2c_stat_read(i2c);
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if (stat == STAT_START || stat == STAT_REP_START)
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/* START successful, bail out */
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return 0;
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error:
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/* START failed, try to recover */
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ret = octeon_i2c_recovery(i2c);
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return (ret) ? ret : -EAGAIN;
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}
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/* send STOP to the bus */
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static void octeon_i2c_stop(struct octeon_i2c *i2c)
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{
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octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STP);
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}
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/**
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* octeon_i2c_read - receive data from the bus via low-level controller
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* @i2c: The struct octeon_i2c
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* @target: Target address
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* @data: Pointer to the location to store the data
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* @rlength: Length of the data
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* @recv_len: flag for length byte
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*
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* The address is sent over the bus, then the data is read.
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*
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* Returns 0 on success, otherwise a negative errno.
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*/
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static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
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u8 *data, u16 *rlength, bool recv_len)
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{
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int i, result, length = *rlength;
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bool final_read = false;
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octeon_i2c_data_write(i2c, (target << 1) | 1);
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octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
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result = octeon_i2c_wait(i2c);
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if (result)
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return result;
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/* address OK ? */
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result = octeon_i2c_check_status(i2c, false);
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if (result)
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return result;
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for (i = 0; i < length; i++) {
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/*
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* For the last byte to receive TWSI_CTL_AAK must not be set.
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*
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* A special case is I2C_M_RECV_LEN where we don't know the
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* additional length yet. If recv_len is set we assume we're
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* not reading the final byte and therefore need to set
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* TWSI_CTL_AAK.
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*/
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if ((i + 1 == length) && !(recv_len && i == 0))
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final_read = true;
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/* clear iflg to allow next event */
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if (final_read)
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octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
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else
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octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_AAK);
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result = octeon_i2c_wait(i2c);
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if (result)
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return result;
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data[i] = octeon_i2c_data_read(i2c, &result);
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if (result)
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return result;
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if (recv_len && i == 0) {
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if (data[i] > I2C_SMBUS_BLOCK_MAX + 1)
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return -EPROTO;
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length += data[i];
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}
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result = octeon_i2c_check_status(i2c, final_read);
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if (result)
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return result;
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}
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*rlength = length;
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return 0;
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}
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/**
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* octeon_i2c_write - send data to the bus via low-level controller
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* @i2c: The struct octeon_i2c
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* @target: Target address
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* @data: Pointer to the data to be sent
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* @length: Length of the data
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*
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* The address is sent over the bus, then the data.
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*
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* Returns 0 on success, otherwise a negative errno.
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*/
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static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
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const u8 *data, int length)
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{
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int i, result;
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octeon_i2c_data_write(i2c, target << 1);
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octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
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result = octeon_i2c_wait(i2c);
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if (result)
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return result;
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for (i = 0; i < length; i++) {
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result = octeon_i2c_check_status(i2c, false);
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if (result)
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return result;
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octeon_i2c_data_write(i2c, data[i]);
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octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
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result = octeon_i2c_wait(i2c);
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if (result)
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return result;
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}
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return 0;
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}
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/* high-level-controller pure read of up to 8 bytes */
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static int octeon_i2c_hlc_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
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{
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int i, j, ret = 0;
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u64 cmd;
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octeon_i2c_hlc_enable(i2c);
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octeon_i2c_hlc_int_clear(i2c);
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cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
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/* SIZE */
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cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;
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/* A */
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cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
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if (msgs[0].flags & I2C_M_TEN)
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cmd |= SW_TWSI_OP_10;
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else
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cmd |= SW_TWSI_OP_7;
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octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
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ret = octeon_i2c_hlc_wait(i2c);
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if (ret)
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goto err;
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cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
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if ((cmd & SW_TWSI_R) == 0)
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return octeon_i2c_check_status(i2c, false);
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for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--)
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msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
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if (msgs[0].len > 4) {
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cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT(i2c));
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for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)
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msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
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}
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err:
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return ret;
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}
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/* high-level-controller pure write of up to 8 bytes */
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static int octeon_i2c_hlc_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
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{
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int i, j, ret = 0;
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u64 cmd;
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octeon_i2c_hlc_enable(i2c);
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octeon_i2c_hlc_int_clear(i2c);
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cmd = SW_TWSI_V | SW_TWSI_SOVR;
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/* SIZE */
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cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;
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/* A */
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cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
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if (msgs[0].flags & I2C_M_TEN)
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cmd |= SW_TWSI_OP_10;
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else
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cmd |= SW_TWSI_OP_7;
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for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--)
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cmd |= (u64)msgs[0].buf[j] << (8 * i);
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if (msgs[0].len > 4) {
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u64 ext = 0;
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for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)
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ext |= (u64)msgs[0].buf[j] << (8 * i);
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octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
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}
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octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
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ret = octeon_i2c_hlc_wait(i2c);
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if (ret)
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goto err;
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cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
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if ((cmd & SW_TWSI_R) == 0)
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return octeon_i2c_check_status(i2c, false);
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err:
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return ret;
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}
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/* high-level-controller composite write+read, msg0=addr, msg1=data */
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static int octeon_i2c_hlc_comp_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
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{
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int i, j, ret = 0;
|
|
u64 cmd;
|
|
|
|
octeon_i2c_hlc_enable(i2c);
|
|
|
|
cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
|
|
/* SIZE */
|
|
cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;
|
|
/* A */
|
|
cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
|
|
|
|
if (msgs[0].flags & I2C_M_TEN)
|
|
cmd |= SW_TWSI_OP_10_IA;
|
|
else
|
|
cmd |= SW_TWSI_OP_7_IA;
|
|
|
|
if (msgs[0].len == 2) {
|
|
u64 ext = 0;
|
|
|
|
cmd |= SW_TWSI_EIA;
|
|
ext = (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
|
|
cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
|
|
octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
|
|
} else {
|
|
cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
|
|
}
|
|
|
|
octeon_i2c_hlc_int_clear(i2c);
|
|
octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
|
|
|
|
ret = octeon_i2c_hlc_wait(i2c);
|
|
if (ret)
|
|
goto err;
|
|
|
|
cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
|
|
if ((cmd & SW_TWSI_R) == 0)
|
|
return octeon_i2c_check_status(i2c, false);
|
|
|
|
for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--)
|
|
msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
|
|
|
|
if (msgs[1].len > 4) {
|
|
cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT(i2c));
|
|
for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)
|
|
msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
|
|
}
|
|
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
/* high-level-controller composite write+write, m[0]len<=2, m[1]len<=8 */
|
|
static int octeon_i2c_hlc_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
|
|
{
|
|
bool set_ext = false;
|
|
int i, j, ret = 0;
|
|
u64 cmd, ext = 0;
|
|
|
|
octeon_i2c_hlc_enable(i2c);
|
|
|
|
cmd = SW_TWSI_V | SW_TWSI_SOVR;
|
|
/* SIZE */
|
|
cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;
|
|
/* A */
|
|
cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
|
|
|
|
if (msgs[0].flags & I2C_M_TEN)
|
|
cmd |= SW_TWSI_OP_10_IA;
|
|
else
|
|
cmd |= SW_TWSI_OP_7_IA;
|
|
|
|
if (msgs[0].len == 2) {
|
|
cmd |= SW_TWSI_EIA;
|
|
ext |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
|
|
set_ext = true;
|
|
cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
|
|
} else {
|
|
cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
|
|
}
|
|
|
|
for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--)
|
|
cmd |= (u64)msgs[1].buf[j] << (8 * i);
|
|
|
|
if (msgs[1].len > 4) {
|
|
for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)
|
|
ext |= (u64)msgs[1].buf[j] << (8 * i);
|
|
set_ext = true;
|
|
}
|
|
if (set_ext)
|
|
octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
|
|
|
|
octeon_i2c_hlc_int_clear(i2c);
|
|
octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
|
|
|
|
ret = octeon_i2c_hlc_wait(i2c);
|
|
if (ret)
|
|
goto err;
|
|
|
|
cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
|
|
if ((cmd & SW_TWSI_R) == 0)
|
|
return octeon_i2c_check_status(i2c, false);
|
|
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* octeon_i2c_xfer - The driver's master_xfer function
|
|
* @adap: Pointer to the i2c_adapter structure
|
|
* @msgs: Pointer to the messages to be processed
|
|
* @num: Length of the MSGS array
|
|
*
|
|
* Returns the number of messages processed, or a negative errno on failure.
|
|
*/
|
|
int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
|
|
{
|
|
struct octeon_i2c *i2c = i2c_get_adapdata(adap);
|
|
int i, ret = 0;
|
|
|
|
if (num == 1) {
|
|
if (msgs[0].len > 0 && msgs[0].len <= 8) {
|
|
if (msgs[0].flags & I2C_M_RD)
|
|
ret = octeon_i2c_hlc_read(i2c, msgs);
|
|
else
|
|
ret = octeon_i2c_hlc_write(i2c, msgs);
|
|
goto out;
|
|
}
|
|
} else if (num == 2) {
|
|
if ((msgs[0].flags & I2C_M_RD) == 0 &&
|
|
(msgs[1].flags & I2C_M_RECV_LEN) == 0 &&
|
|
msgs[0].len > 0 && msgs[0].len <= 2 &&
|
|
msgs[1].len > 0 && msgs[1].len <= 8 &&
|
|
msgs[0].addr == msgs[1].addr) {
|
|
if (msgs[1].flags & I2C_M_RD)
|
|
ret = octeon_i2c_hlc_comp_read(i2c, msgs);
|
|
else
|
|
ret = octeon_i2c_hlc_comp_write(i2c, msgs);
|
|
goto out;
|
|
}
|
|
}
|
|
|
|
for (i = 0; ret == 0 && i < num; i++) {
|
|
struct i2c_msg *pmsg = &msgs[i];
|
|
|
|
/* zero-length messages are not supported */
|
|
if (!pmsg->len) {
|
|
ret = -EOPNOTSUPP;
|
|
break;
|
|
}
|
|
|
|
ret = octeon_i2c_start(i2c);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (pmsg->flags & I2C_M_RD)
|
|
ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
|
|
&pmsg->len, pmsg->flags & I2C_M_RECV_LEN);
|
|
else
|
|
ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
|
|
pmsg->len);
|
|
}
|
|
octeon_i2c_stop(i2c);
|
|
out:
|
|
return (ret != 0) ? ret : num;
|
|
}
|
|
|
|
/* calculate and set clock divisors */
|
|
void octeon_i2c_set_clock(struct octeon_i2c *i2c)
|
|
{
|
|
int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
|
|
int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
|
|
|
|
for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
|
|
/*
|
|
* An mdiv value of less than 2 seems to not work well
|
|
* with ds1337 RTCs, so we constrain it to larger values.
|
|
*/
|
|
for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
|
|
/*
|
|
* For given ndiv and mdiv values check the
|
|
* two closest thp values.
|
|
*/
|
|
tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
|
|
tclk *= (1 << ndiv_idx);
|
|
thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
|
|
|
|
for (inc = 0; inc <= 1; inc++) {
|
|
thp_idx = thp_base + inc;
|
|
if (thp_idx < 5 || thp_idx > 0xff)
|
|
continue;
|
|
|
|
foscl = i2c->sys_freq / (2 * (thp_idx + 1));
|
|
foscl = foscl / (1 << ndiv_idx);
|
|
foscl = foscl / (mdiv_idx + 1) / 10;
|
|
diff = abs(foscl - i2c->twsi_freq);
|
|
if (diff < delta_hz) {
|
|
delta_hz = diff;
|
|
thp = thp_idx;
|
|
mdiv = mdiv_idx;
|
|
ndiv = ndiv_idx;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
octeon_i2c_reg_write(i2c, SW_TWSI_OP_TWSI_CLK, thp);
|
|
octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
|
|
}
|
|
|
|
int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
|
|
{
|
|
u8 status = 0;
|
|
int tries;
|
|
|
|
/* reset controller */
|
|
octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0);
|
|
|
|
for (tries = 10; tries && status != STAT_IDLE; tries--) {
|
|
udelay(1);
|
|
status = octeon_i2c_stat_read(i2c);
|
|
if (status == STAT_IDLE)
|
|
break;
|
|
}
|
|
|
|
if (status != STAT_IDLE) {
|
|
dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n",
|
|
__func__, status);
|
|
return -EIO;
|
|
}
|
|
|
|
/* toggle twice to force both teardowns */
|
|
octeon_i2c_hlc_enable(i2c);
|
|
octeon_i2c_hlc_disable(i2c);
|
|
return 0;
|
|
}
|
|
|
|
static int octeon_i2c_get_scl(struct i2c_adapter *adap)
|
|
{
|
|
struct octeon_i2c *i2c = i2c_get_adapdata(adap);
|
|
u64 state;
|
|
|
|
state = octeon_i2c_read_int(i2c);
|
|
return state & TWSI_INT_SCL;
|
|
}
|
|
|
|
static void octeon_i2c_set_scl(struct i2c_adapter *adap, int val)
|
|
{
|
|
struct octeon_i2c *i2c = i2c_get_adapdata(adap);
|
|
|
|
octeon_i2c_write_int(i2c, val ? 0 : TWSI_INT_SCL_OVR);
|
|
}
|
|
|
|
static int octeon_i2c_get_sda(struct i2c_adapter *adap)
|
|
{
|
|
struct octeon_i2c *i2c = i2c_get_adapdata(adap);
|
|
u64 state;
|
|
|
|
state = octeon_i2c_read_int(i2c);
|
|
return state & TWSI_INT_SDA;
|
|
}
|
|
|
|
static void octeon_i2c_prepare_recovery(struct i2c_adapter *adap)
|
|
{
|
|
struct octeon_i2c *i2c = i2c_get_adapdata(adap);
|
|
|
|
octeon_i2c_hlc_disable(i2c);
|
|
octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0);
|
|
/* wait for software reset to settle */
|
|
udelay(5);
|
|
|
|
/*
|
|
* Bring control register to a good state regardless
|
|
* of HLC state.
|
|
*/
|
|
octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);
|
|
|
|
octeon_i2c_write_int(i2c, 0);
|
|
}
|
|
|
|
static void octeon_i2c_unprepare_recovery(struct i2c_adapter *adap)
|
|
{
|
|
struct octeon_i2c *i2c = i2c_get_adapdata(adap);
|
|
|
|
/*
|
|
* Generate STOP to finish the unfinished transaction.
|
|
* Can't generate STOP via the TWSI CTL register
|
|
* since it could bring the TWSI controller into an inoperable state.
|
|
*/
|
|
octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR | TWSI_INT_SCL_OVR);
|
|
udelay(5);
|
|
octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR);
|
|
udelay(5);
|
|
octeon_i2c_write_int(i2c, 0);
|
|
}
|
|
|
|
struct i2c_bus_recovery_info octeon_i2c_recovery_info = {
|
|
.recover_bus = i2c_generic_scl_recovery,
|
|
.get_scl = octeon_i2c_get_scl,
|
|
.set_scl = octeon_i2c_set_scl,
|
|
.get_sda = octeon_i2c_get_sda,
|
|
.prepare_recovery = octeon_i2c_prepare_recovery,
|
|
.unprepare_recovery = octeon_i2c_unprepare_recovery,
|
|
};
|