536 lines
14 KiB
C
Executable File
536 lines
14 KiB
C
Executable File
/*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This file contains the utility functions for composite clocks.
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*/
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#ifndef __SAMSUNG_CLK_COMPOSITE_H
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#define __SAMSUNG_CLK_COMPOSITE_H
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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/*
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* struct samsung_clk_provider: information about clock provider
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* @reg_base: virtual address for the register base.
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* @clk_data: holds clock related data like clk* and number of clocks.
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* @lock: maintains exclusion bwtween callbacks for a given clock-provider.
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*/
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struct samsung_clk_provider {
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void __iomem *reg_base;
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struct clk_onecell_data clk_data;
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spinlock_t lock;
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};
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/*
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* struct samsung_clk_reg_dump: register dump of clock controller registers.
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* @offset: clock register offset from the controller base address.
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* @value: the value to be register at offset.
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*/
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struct samsung_clk_reg_dump {
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unsigned long offset;
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u32 value;
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};
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/*
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* struct samsung_fixed_rate_clock: information about fixed-rate clock
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* @id: platform specific id of the clock.
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* @name: name of this fixed-rate clock.
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* @parent_name: optional parent clock name.
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* @flags: optional fixed-rate clock flags.
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* @fixed-rate: fixed clock rate of this clock.
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*/
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struct samsung_fixed_rate {
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unsigned int id;
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char *name;
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const char *parent_name;
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unsigned long flags;
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unsigned long fixed_rate;
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};
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#define FRATE(_id, cname, pname, f, frate) \
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{ \
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.id = _id, \
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.name = cname, \
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.parent_name = pname, \
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.flags = f, \
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.fixed_rate = frate, \
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}
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extern void __init samsung_register_fixed_rate(
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struct samsung_clk_provider *ctx,
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struct samsung_fixed_rate *list,
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unsigned int nr_clk);
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/*
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* struct samsung_fixed_factor_clock: information about fixed-factor clock
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* @id: platform specific id of the clock.
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* @name: name of this fixed-factor clock.
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* @parent_name: parent clock name.
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* @mult: fixed multiplication factor.
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* @div: fixed division factor.
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* @flags: optional fixed-factor clock flags.
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*/
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struct samsung_fixed_factor {
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unsigned int id;
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char *name;
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const char *parent_name;
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unsigned long mult;
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unsigned long div;
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unsigned long flags;
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};
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#define FFACTOR(_id, cname, pname, m, d, f) \
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{ \
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.id = _id, \
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.name = cname, \
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.parent_name = pname, \
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.mult = m, \
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.div = d, \
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.flags = f, \
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}
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extern void __init samsung_register_fixed_factor(
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struct samsung_clk_provider *ctx,
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struct samsung_fixed_factor *list,
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unsigned int nr_clk);
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/*
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* PLL145xx Clock Type: PLL1450x, PLL1451x, PLL1452x
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* Maximum lock time can be 150 * Pdiv cycles
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*/
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#define PLL145XX_LOCK_FACTOR (150)
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#define PLL145XX_MDIV_MASK (0x3FF)
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#define PLL145XX_PDIV_MASK (0x03F)
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#define PLL145XX_SDIV_MASK (0x007)
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#define PLL145XX_LOCKED_MASK (0x1)
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#define PLL145XX_MDIV_SHIFT (16)
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#define PLL145XX_PDIV_SHIFT (8)
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#define PLL145XX_SDIV_SHIFT (0)
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#define PLL145XX_LOCKED_SHIFT (29)
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/*
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* PLL1460X Clock Type
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* Maximum lock time can be 3000 * Pdiv cycles
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*/
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#define PLL1460X_LOCK_FACTOR (3000)
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#define PLL1460X_MDIV_MASK (0x03FF)
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#define PLL1460X_PDIV_MASK (0x003F)
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#define PLL1460X_SDIV_MASK (0x0007)
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#define PLL1460X_KDIV_MASK (0xFFFF)
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#define PLL1460X_LOCKED_MASK (0x1)
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#define PLL1460X_MDIV_SHIFT (16)
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#define PLL1460X_PDIV_SHIFT (8)
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#define PLL1460X_SDIV_SHIFT (0)
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#define PLL1460X_KDIV_SHIFT (0)
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#define PLL1460X_LOCKED_SHIFT (29)
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/*
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* PLL255xx Clock Type : PLL2551x, PLL2555x
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* Maximum lock time can be 200 * Pdiv cycles
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*/
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#define PLL255XX_LOCK_FACTOR (200)
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#define PLL255XX_MDIV_MASK (0x3FF)
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#define PLL255XX_PDIV_MASK (0x3F)
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#define PLL255XX_SDIV_MASK (0x7)
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#define PLL255XX_LOCKED_MASK (0x1)
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#define PLL255XX_MDIV_SHIFT (12)
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#define PLL255XX_PDIV_SHIFT (4)
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#define PLL255XX_SDIV_SHIFT (0)
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#define PLL255XX_LOCKED_SHIFT (29)
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/*
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* PLL2650X Clock Type
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* Maximum lock time can be 3000 * Pdiv cycles
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*/
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#define PLL2650X_LOCK_FACTOR (3000)
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#define PLL2650X_MDIV_MASK (0x01FF)
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#define PLL2650X_PDIV_MASK (0x003F)
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#define PLL2650X_SDIV_MASK (0x0007)
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#define PLL2650X_KDIV_MASK (0xFFFF)
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#define PLL2650X_LOCKED_MASK (0x1)
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#define PLL2650X_MDIV_SHIFT (12)
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#define PLL2650X_PDIV_SHIFT (4)
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#define PLL2650X_SDIV_SHIFT (0)
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#define PLL2650X_KDIV_SHIFT (0)
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#define PLL2650X_LOCKED_SHIFT (29)
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enum pll_type {
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pll_1450x = 0,
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pll_1451x,
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pll_1452x,
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pll_1460x,
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pll_2551x,
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pll_2555x,
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pll_2650x,
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};
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struct samsung_pll_rate_table {
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long rate;
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unsigned int pdiv;
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unsigned int mdiv;
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unsigned int sdiv;
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unsigned int kdiv;
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};
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#define PLL_BYPASS BIT(0)
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#define CHK_ON_CHANGING BIT(7)
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/*
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* struct samsung_composite_pll: information about composite-pll clocks
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* @id: id of the clock for binding with device tree.
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* @name: name of this pll clock.
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* @type: type of this pll clock.
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* @lock_reg: register for locking pll.
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* @con_reg: configuration register for pll.
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* @enable_reg: it can be different whether pll can be gated or only bypassed.
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* @enable_bit: bit index for en/disable pll.
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* @sel_reg: composite-pll has ctrl-mux. when disabled, it is set by 0.
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* @sel_bit: bit index for ctrl-mux.
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* @stat_reg: when sel_reg is set, status register must be checked.
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* @stat_bit: bit index for status register.
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* @rate_table: available pll output ratio table.
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* @alias: support alias for this clock.
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*/
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struct samsung_composite_pll {
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struct clk_hw hw;
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unsigned int id;
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const char *name;
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enum pll_type type;
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void __iomem *lock_reg;
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void __iomem *con_reg;
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void __iomem *enable_reg;
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unsigned int enable_bit;
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void __iomem *sel_reg;
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unsigned int sel_bit;
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void __iomem *stat_reg;
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unsigned int stat_bit;
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const struct samsung_pll_rate_table *rate_table;
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unsigned int rate_count;
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unsigned int pll_flag;
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u8 flag;
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const char *alias;
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};
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#define PLL(_id, cname, _type, lock, con, en, enbit, sel, selbit, stat, statbit, rtable, pf, f, a) \
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{ \
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.id = _id, \
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.name = cname, \
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.type = _type, \
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.lock_reg = lock, \
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.con_reg = con, \
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.enable_reg = en, \
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.enable_bit = enbit, \
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.sel_reg = sel, \
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.sel_bit = selbit, \
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.stat_reg = stat, \
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.stat_bit = statbit, \
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.rate_table = rtable, \
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.rate_count = 0, \
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.pll_flag = pf, \
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.flag = f, \
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.alias = a, \
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}
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extern void samsung_register_comp_pll(
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struct samsung_clk_provider *ctx,
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struct samsung_composite_pll *pll_list,
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unsigned int nr_pll);
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#define PNAME(x) static const char *x[]
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/*
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* struct samsung_composite_mux: information about composite-mux clocks
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* @id: id of the clock for binding with device tree.
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* @name: name of this mux clock.
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* @parents: array of parent clocks.
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* @num_parents: number of parent clocks.
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* @sel_reg: register for mux selection.
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* @sel_bit: bit index for sel_reg.
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* @sel_width: different by number of parent clocks.
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* @stat_reg: status must be checked when changing parent.
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* @stat_bit: bit index for status register.
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* @stat_width: different by number of parent clocks.
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* @flag: optional flag for clock.
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* @alias: optional name. recommend no more than 15 characters.
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*/
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struct samsung_composite_mux {
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struct clk_hw hw;
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unsigned int id;
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const char *name;
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const char **parents;
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unsigned int num_parents;
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void __iomem *sel_reg;
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unsigned int sel_bit;
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unsigned int sel_width;
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void __iomem *stat_reg;
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unsigned int stat_bit;
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unsigned int stat_width;
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unsigned int flag;
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const char *alias;
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spinlock_t *lock;
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};
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#define MUX(_id, cname, pnames, sel, selbit, selwid, stat, statbit, statwid, f, a) \
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{ \
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.id = _id, \
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.name = cname, \
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.parents = pnames, \
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.num_parents = ARRAY_SIZE(pnames), \
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.sel_reg = sel, \
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.sel_bit = selbit, \
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.sel_width = selwid, \
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.stat_reg = stat, \
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.stat_bit = statbit, \
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.stat_width = statwid, \
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.flag = f, \
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.alias = a, \
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}
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extern void samsung_register_comp_mux(
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struct samsung_clk_provider *ctx,
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struct samsung_composite_mux *mux_list,
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unsigned int nr_mux);
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/*
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* struct samsung_composite_divider: information about composite-divider clocks
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* @id: id of the clock for binding with device tree.
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* @name: name of this divider clock.
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* @parent_name: name of parent clock.
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* @rate_reg: register for ratio selection.
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* @rate_bit: bit index for rate_reg.
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* @rate_width: can be different by bit index.
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* @stat_reg: status must be checked when changing ratio.
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* @stat_bit: bit index for status register.
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* @stat_width: can be different by bit index.
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* @flag: flag for clock.
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* @alias: optional name. recommend no more than 15 characters.
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*/
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struct samsung_composite_divider {
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struct clk_hw hw;
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unsigned int id;
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const char *name;
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const char *parent_name;
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void __iomem *rate_reg;
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unsigned int rate_bit;
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unsigned int rate_width;
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void __iomem *stat_reg;
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unsigned int stat_bit;
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unsigned int stat_width;
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unsigned int flag;
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const char *alias;
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spinlock_t *lock;
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};
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#define DIV(_id, cname, pname, rate, ratebit, ratewid, stat, statbit, statwid, f, a) \
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{ \
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.id = _id, \
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.name = cname, \
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.parent_name = pname, \
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.rate_reg = rate, \
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.rate_bit = ratebit, \
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.rate_width = ratewid, \
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.stat_reg = stat, \
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.stat_bit = statbit, \
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.stat_width = statwid, \
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.flag = f, \
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.alias = a, \
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}
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extern void samsung_register_comp_divider(struct samsung_clk_provider *ctx,
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struct samsung_composite_divider *div_list, unsigned int nr_div);
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#define CLK_GATE_ENABLE BIT(20)
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#define CLK_ON_CHANGING BIT(7)
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/*
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* struct samsung_gate: information about gate clocks
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* @id: id of the clock for binding with device tree.
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* @name:
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* @parent_name:
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* @reg:
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* @bit:
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* @flag:
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* @alias:
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*/
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struct samsung_gate {
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unsigned int id;
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const char *name;
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const char *parent_name;
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void __iomem *reg;
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u8 bit;
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unsigned int flag;
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const char *alias;
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};
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#define GATE(_id, cname, pname, r, b, f, a) \
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{ \
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.id = _id, \
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.name = cname, \
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.parent_name = pname, \
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.reg = r, \
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.bit = b, \
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.flag = f, \
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.alias = a, \
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}
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extern void __init samsung_register_gate(
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struct samsung_clk_provider *ctx,
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struct samsung_gate *gate_list,
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unsigned int nr_gate);
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struct clk_samsung_usermux {
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struct clk_hw hw;
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void __iomem *sel_reg;
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u8 sel_bit;
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void __iomem *stat_reg;
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u8 stat_bit;
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u8 flag;
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spinlock_t *lock;
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};
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/*
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* struct samsung_composite_usermux: information about usermux clocks
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* @id: id of the clock for binding with device tree.
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* @name: name of this usermux clock.
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* @parent_name: name of parent clock.
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* @sel_reg: register for usermux selection.
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* @sel_bit: bit index for sel_reg.
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* @stat_reg: status must be checked when changing parent.
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* @stat_bit: bit index for status register.
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* @flag: optional flag for clock.
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* @alias: optional name. recommend no more than 15 characters.
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*/
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struct samsung_usermux {
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unsigned int id;
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const char *name;
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const char *parent_name;
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void __iomem *sel_reg;
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u8 sel_bit;
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void __iomem *stat_reg;
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u8 stat_bit;
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u8 flag;
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const char *alias;
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};
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#define USERMUX(_id, cname, pname, sel, selbit, stat, statbit, f, a) \
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{ \
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.id = _id, \
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.name = cname, \
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.parent_name = pname, \
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.sel_reg = sel, \
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.sel_bit = selbit, \
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.stat_reg = stat, \
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.stat_bit = statbit, \
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.flag = f, \
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.alias = a, \
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}
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extern void __init samsung_register_usermux(
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struct samsung_clk_provider *ctx,
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struct samsung_usermux *list,
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unsigned int nr_usermux);
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#define VCLK_DFS BIT(1)
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#define VCLK_DFS_SWITCH BIT(2)
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#define VCLK_GATE BIT(3)
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#define VCLK_QCH_EN BIT(4)
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#define VCLK_QCH_DIS BIT(5)
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#define VCLK_QACTIVE BIT(6)
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/*
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* struct init_vclk: initial information for virtual clocks
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* @id: id of the clock for binding with device tree.
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* @calid: id of the clock for calling cal.
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* @name: name of this virtual clock.
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* @flags: optional flag for clock.
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* @vclk_flags: optional flag for only virtual clock.
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* @alias: optional name. recommend no more than 15 characters.
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*/
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struct init_vclk{
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unsigned int id;
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unsigned int calid;
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const char *name;
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const char *parent;
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u8 flags;
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u8 vclk_flags;
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const char *alias;
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u32 addr;
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u32 mask;
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u32 val;
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};
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struct samsung_vclk {
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struct clk_hw hw;
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unsigned int id;
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u8 flags;
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spinlock_t *lock;
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void __iomem *addr;
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u32 mask;
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u32 val;
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};
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#define VCLK(_id, _calid, _name, f, vf, a) \
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{ \
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.id = _id, \
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.calid = _calid, \
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.name = _name, \
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.flags = f, \
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.vclk_flags = vf, \
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.alias = a, \
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}
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#define HWACG_VCLK(_id, _calid, _name, _parent, f, vf, a) \
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{ \
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.id = _id, \
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.calid = _calid, \
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.name = _name, \
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.parent = _parent, \
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.flags = f, \
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.vclk_flags = vf, \
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.alias = a, \
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}
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#define HWACG_VCLK_QACTIVE(_id, _name, _parent, f, vf, a, _addr, _mask, _val) \
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{ \
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.id = _id, \
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.name = _name, \
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.parent = _parent, \
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.flags = f, \
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.vclk_flags = vf, \
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.alias = a, \
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.addr = _addr, \
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.mask = _mask, \
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.val = _val, \
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}
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extern void __init samsung_register_vclk(struct samsung_clk_provider *ctx,
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struct init_vclk *list, unsigned int nr_vclk);
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extern struct samsung_clk_provider *__init samsung_clk_init(
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struct device_node *np, void __iomem *base,
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unsigned long nr_clks);
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extern void __init samsung_clk_of_add_provider(struct device_node *np,
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struct samsung_clk_provider *ctx);
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extern void __init samsung_register_of_fixed_ext(
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struct samsung_clk_provider *ctx,
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struct samsung_fixed_rate *fixed_rate_clk,
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unsigned int nr_fixed_rate_clk,
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struct of_device_id *clk_matches);
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extern void samsung_clk_save(void __iomem *base,
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struct samsung_clk_reg_dump *rd,
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unsigned int num_regs);
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extern void samsung_clk_restore(void __iomem *base,
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const struct samsung_clk_reg_dump *rd,
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unsigned int num_regs);
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extern struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
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const unsigned long *rdump,
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unsigned long nr_rdump);
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#endif /* __SAMSUNG_CLK_COMPOSITE_H */
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