441 lines
12 KiB
C
Executable File
441 lines
12 KiB
C
Executable File
/*
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* s2mu106_charger.h - Header of S2MU106 Charger Driver
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*
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* Copyright (C) 2016 Samsung Electronics Co.Ltd
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef S2MU106_CHARGER_H
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#define S2MU106_CHARGER_H
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#include <linux/mfd/samsung/s2mu106.h>
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#if defined(CONFIG_MUIC_NOTIFIER)
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#include <linux/muic/muic.h>
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#include <linux/muic/muic_notifier.h>
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#endif /* CONFIG_MUIC_NOTIFIER */
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#include "../common/include/sec_charging_common.h"
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extern bool mfc_fw_update;
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/* define function if need */
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#define ENABLE_MIVR 0
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/* define IRQ function if need */
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#define EN_BAT_DET_IRQ 1
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#define EN_CHG1_IRQ_CHGIN 0
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/* Test debug log enable */
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#define EN_TEST_READ 1
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#define HEALTH_DEBOUNCE_CNT 1
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#define MINVAL(a, b) ((a <= b) ? a : b)
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#define MASK(width, shift) (((0x1 << (width)) - 1) << shift)
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#define ENABLE 1
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#define DISABLE 0
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#define S2MU106_CHG_INT1 0x01
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#define S2MU106_CHG_INT2 0x02
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#define S2MU106_CHG_INT3 0x03
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#define S2MU106_CHG_INT1M 0x08
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#define S2MU106_CHG_INT2M 0x09
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#define S2MU106_CHG_INT3M 0x0A
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#define S2MU106_CHG_STATUS0 0x0E
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#define S2MU106_CHG_STATUS1 0x0F
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#define S2MU106_CHG_STATUS2 0x10
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#define S2MU106_CHG_STATUS3 0x11
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#define S2MU106_CHG_STATUS4 0x12
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#define S2MU106_CHG_STATUS5 0x13
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#define S2MU106_CHG_CTRL0 0x18
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#define S2MU106_CHG_CTRL1 0x19
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#define S2MU106_CHG_CTRL2 0x1A
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#define S2MU106_CHG_CTRL3 0x1B
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#define S2MU106_CHG_CTRL4 0x1C
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#define S2MU106_CHG_CTRL5 0x1D
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#define S2MU106_CHG_CTRL6 0x1E
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#define S2MU106_CHG_CTRL7 0x1F
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#define S2MU106_CHG_CTRL8 0x20
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#define S2MU106_CHG_CTRL9 0x21
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#define S2MU106_CHG_CTRL10 0x22
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#define S2MU106_CHG_CTRL11 0x23
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#define S2MU106_CHG_CTRL12 0x24
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#define S2MU106_CHG_CTRL13 0x25
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#define S2MU106_CHG_CTRL14 0x26
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#define S2MU106_CHG_CTRL15 0x27
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#define S2MU106_CHG_CTRL16 0x28
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#define S2MU106_CHG_CTRL17 0x29
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#define S2MU106_CHG_CTRL18 0x2A
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#define S2MU106_CHG_CTRL19 0x2B
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#define S2MU106_CHG_CTRL20 0x2C
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#define S2MU106_CHG_CTRL21 0x2D
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#define S2MU106_CHG_CTRL22 0x2E
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#define S2MU106_CHG_CTRL23 0x2F
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#define S2MU106_CHG_CTRL24 0x30
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/* S2MU106_CHG_STATUS0 */
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#define WCIN_STATUS_SHIFT 4
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#define WCIN_STATUS_WIDTH 3
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#define WCIN_STATUS_MASK MASK(WCIN_STATUS_WIDTH, WCIN_STATUS_SHIFT)
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#define CHGIN_STATUS_SHIFT 0
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#define CHGIN_STATUS_WIDTH 3
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#define CHGIN_STATUS_MASK MASK(CHGIN_STATUS_WIDTH, CHGIN_STATUS_SHIFT)
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/* S2MU106_CHG_STATUS1 */
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#define CHG_FAULT_STATUS_SHIFT 4
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#define CHG_FAULT_STATUS_WIDTH 4
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#define CHG_FAULT_STATUS_MASK MASK(CHG_FAULT_STATUS_WIDTH,\
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CHG_FAULT_STATUS_SHIFT)
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#define CHG_STATUS_NORMAL 0
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#define CHG_STATUS_WD_SUSPEND 1
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#define CHG_STATUS_WD_RST 2
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#define CHG_STATUS_TSD 3
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#define CHG_STATUS_TFB 4
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#define CHG_STATUS_TO_PRE_CHARGE 6
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#define CHG_STATUS_TO_FAST_CHARGE 7
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#define CHG_CV_STATUS_SHIFT 3
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#define CHG_CV_STATUS_MASK BIT(CHG_Restart_STATUS_SHIFT)
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#define CHG_Restart_STATUS_SHIFT 2
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#define CHG_Restart_STATUS_MASK BIT(CHG_Restart_STATUS_SHIFT)
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#define TOP_OFF_STATUS_SHIFT 1
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#define TOP_OFF_STATUS_MASK BIT(TOP_OFF_STATUS_SHIFT)
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#define DONE_STATUS_SHIFT 0
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#define DONE_STATUS_MASK BIT(DONE_STATUS_SHIFT)
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/* S2MU106_CHG_STATUS2 */
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#define OTG_STATUS_SHIFT 6
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#define OTG_STATUS_WIDTH 2
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#define OTG_STATUS_MASK MASK(OTG_STATUS_WIDTH, OTG_STATUS_SHIFT)
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#define TX_STATUS_SHIFT 4
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#define TX_STATUS_WIDTH 2
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#define TX_STATUS_MASK MASK(TX_STATUS_WIDTH, TX_STATUS_SHIFT)
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/* S2MU106_CHG_STATUS3 */
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#define BAT_STATUS_SHIFT 1
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#define BAT_STATUS_WIDTH 3
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#define BAT_STATUS_MASK MASK(BAT_STATUS_WIDTH, BAT_STATUS_SHIFT)
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#define DET_BAT_STATUS_SHIFT 0
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#define DET_BAT_STATUS_MASK BIT(DET_BAT_STATUS_SHIFT)
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/* S2MU106_CHG_STATUS5 */
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#define ICR_STATUS_SHIFT 2
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#define ICR_STATUS_MASK BIT(ICR_STATUS_SHIFT)
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#define IVR_STATUS_SHIFT 3
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#define IVR_STATUS_MASK BIT(IVR_STATUS_SHIFT)
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#define IVR_M_SHIFT 1
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#define IVR_M_MASK BIT(IVR_M_SHIFT)
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#define IVR_STATUS 0x08
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/* S2MU106_CHG_CTRL0 */
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#define REG_MODE_SHIFT 0
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#define REG_MODE_WIDTH 4
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#define REG_MODE_MASK MASK(REG_MODE_WIDTH, REG_MODE_SHIFT)
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#define CHARGER_OFF_MODE 0
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#define BUCK_MODE 1
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#define BST_MODE 2
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#define CHG_MODE 3
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#define OTG_BST_MODE 6
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/* S2MU106_CHG_CTRL1, S2MU106_CHG_CTRL2 */
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#define INPUT_CURRENT_LIMIT_SHIFT 0
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#define INPUT_CURRENT_LIMIT_WIDTH 7
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#define INPUT_CURRENT_LIMIT_MASK MASK(INPUT_CURRENT_LIMIT_WIDTH,\
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INPUT_CURRENT_LIMIT_SHIFT)
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/* S2MU106_CHG_CTRL3 */
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#define SEL_PRIO_WCIN_SHIFT 6
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#define SEL_PRIO_WCIN_SHIFT_MASK BIT(SEL_PRIO_WCIN_SHIFT)
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#define OTG_OCP_SW_ON_SHIFT 5
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#define OTG_OCP_SW_ON_MASK BIT(OTG_OCP_SW_ON_SHIFT)
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#define OTG_OCP_SW_OFF_SHIFT 4
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#define OTG_OCP_SW_OFF_MASK BIT(OTG_OCP_SW_OFF_SHIFT)
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#define SET_OTG_OCP_SHIFT 2
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#define SET_OTG_OCP_WIDTH 2
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#define SET_OTG_OCP_MASK MASK(SET_OTG_OCP_WIDTH, SET_OTG_OCP_SHIFT)
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#define SET_TX_OCP_SHIFT 0
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#define SET_TX_OCP_WIDTH 2
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#define SET_TX_OCP_MASK MASK(SET_TX_OCP_WIDTH, SET_TX_OCP_SHIFT)
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/* S2MU106_CHG_CTRL5 */
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#define SET_VF_VBAT_SHIFT 0
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#define SET_VF_VBAT_WIDTH 7
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#define SET_VF_VBAT_MASK MASK(SET_VF_VBAT_WIDTH, SET_VF_VBAT_SHIFT)
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#define SET_CHGIN_IVR_SHIFT 2
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#define SET_CHGIN_IVR_WIDTH 2
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#define SET_CHGIN_IVR_MASK MASK(SET_CHGIN_IVR_WIDTH,\
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SET_CHGIN_IVR_SHIFT)
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#define SET_WCIN_IVR_SHIFT 2
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#define SET_WCIN_IVR_WIDTH 2
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#define SET_WCIN_IVR_MASK MASK(SET_WCIN_IVR_WIDTH,\
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SET_WCIN_IVR_SHIFT)
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/* S2MU106_CHG_CTRL6 */
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#define COOL_CHARGING_CURRENT_SHIFT 0
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#define COOL_CHARGING_CURRENT_WIDTH 6
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#define COOL_CHARGING_CURRENT_MASK MASK(COOL_CHARGING_CURRENT_WIDTH,\
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COOL_CHARGING_CURRENT_SHIFT)
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/* S2MU106_CHG_CTRL7 */
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#define FAST_CHARGING_CURRENT_SHIFT 0
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#define FAST_CHARGING_CURRENT_WIDTH 6
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#define FAST_CHARGING_CURRENT_MASK MASK(FAST_CHARGING_CURRENT_WIDTH,\
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FAST_CHARGING_CURRENT_SHIFT)
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/* S2MU106_CHG_CTRL8 */
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#define SET_VSYS_SHIFT 0
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#define SET_VSYS_WIDTH 3
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#define SET_VSYS_MASK MASK(SET_VSYS_WIDTH, SET_VSYS_SHIFT)
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#define EN_JIG_REG_AP_SHIFT 7
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#define EN_JIG_REG_AP_WIDTH 1
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#define EN_JIG_REG_AP_MASK MASK(EN_JIG_REG_AP_WIDTH, EN_JIG_REG_AP_SHIFT)
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/* S2MU106_CHG_CTRL9 */
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#define SET_BAT_OCP_SHIFT 0
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#define SET_BAT_OCP_WIDTH 3
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#define SET_BAT_OCP_MASK MASK(SET_BAT_OCP_WIDTH, SET_BAT_OCP_SHIFT)
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#define BAT_OCP_QBATOFF_MASK 0x10
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/* S2MU106_CHG_CTRL10 */
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#define FIRST_TOPOFF_CURRENT_SHIFT 4
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#define FIRST_TOPOFF_CURRENT_WIDTH 4
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#define FIRST_TOPOFF_CURRENT_MASK MASK(FIRST_TOPOFF_CURRENT_WIDTH,\
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FIRST_TOPOFF_CURRENT_SHIFT)
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#define SECOND_TOPOFF_CURRENT_SHIFT 0
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#define SECOND_TOPOFF_CURRENT_WIDTH 4
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#define SECOND_TOPOFF_CURRENT_MASK MASK(SECOND_TOPOFF_CURRENT_WIDTH,\
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SECOND_TOPOFF_CURRENT_SHIFT)
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/* S2MU106_CHG_CTRL11 */
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#define SET_VF_BOOST_SHIFT 0
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#define SET_VF_BOOST_WIDTH 8
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#define SET_VF_BOOST_MASK MASK(SET_VF_BOOST_WIDTH, SET_VF_BOOST_SHIFT)
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/* S2MU106_CHG_CTRL12 */
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#define WDT_TIME_SHIFT 1
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#define WDT_TIME_WIDTH 3
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#define WDT_TIME_MASK MASK(WDT_TIME_WIDTH, WDT_TIME_SHIFT)
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#define SET_EN_WDT_SHIFT 4
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#define SET_EN_WDT_MASK BIT(SET_EN_WDT_SHIFT)
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#define SET_EN_WDT_AP_RESET_SHIFT 5
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#define SET_EN_WDT_AP_RESET_MASK BIT(SET_EN_WDT_AP_RESET_SHIFT)
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#define WDT_CLR_SHIFT 0
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#define WDT_CLR_MASK BIT(WDT_CLR_SHIFT)
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/* S2MU106_CHG_CTRL13 */
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#define SET_TIME_FC_CHG_SHIFT 3
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#define SET_TIME_FC_CHG_WIDTH 3
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#define SET_TIME_FC_CHG_MASK MASK(SET_TIME_FC_CHG_WIDTH, SET_TIME_FC_CHG_SHIFT)
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/* S2MU106_CHG_CTRL14 */
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#define TOP_OFF_TIME_SHIFT 0
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#define TOP_OFF_TIME_WIDTH 3
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#define TOP_OFF_TIME_MASK MASK(TOP_OFF_TIME_WIDTH, TOP_OFF_TIME_SHIFT)
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#define REDUCE_CURRENT_STEP 25
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#define MINIMUM_INPUT_CURRENT 300
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#define SLOW_CHARGING_CURRENT_STANDARD 400
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#define FAKE_BAT_LEVEL 50
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ssize_t s2mu106_chg_show_attrs(struct device *dev,
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struct device_attribute *attr, char *buf);
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ssize_t s2mu106_chg_store_attrs(struct device *dev,
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struct device_attribute *attr, const char *buf, size_t count);
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#define S2MU106_CHARGER_ATTR(_name) \
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{ \
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.attr = {.name = #_name, .mode = 0664}, \
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.show = s2mu106_chg_show_attrs, \
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.store = s2mu106_chg_store_attrs, \
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}
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enum {
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CHG_REG = 0,
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CHG_DATA,
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CHG_REGS,
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};
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enum {
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S2MU106_TOPOFF_TIMER_5m = 0x1,
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S2MU106_TOPOFF_TIMER_10m = 0x2,
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S2MU106_TOPOFF_TIMER_30m = 0x3,
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S2MU106_TOPOFF_TIMER_50m = 0x4,
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S2MU106_TOPOFF_TIMER_70m = 0x5,
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S2MU106_TOPOFF_TIMER_90m = 0x6,
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S2MU106_TOPOFF_TIMER_DIS = 0x7,
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};
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enum {
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S2MU106_WDT_TIMER_40s = 0x1,
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S2MU106_WDT_TIMER_50s = 0x2,
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S2MU106_WDT_TIMER_60s = 0x3,
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S2MU106_WDT_TIMER_70s = 0x4,
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S2MU106_WDT_TIMER_80s = 0x5,
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S2MU106_WDT_TIMER_90s = 0x6,
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S2MU106_WDT_TIMER_100s = 0x7,
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};
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enum {
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S2MU106_FC_CHG_TIMER_4hr = 0x1,
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S2MU106_FC_CHG_TIMER_6hr = 0x2,
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S2MU106_FC_CHG_TIMER_8hr = 0x3,
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S2MU106_FC_CHG_TIMER_10hr = 0x4,
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S2MU106_FC_CHG_TIMER_12hr = 0x5,
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S2MU106_FC_CHG_TIMER_14hr = 0x6,
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S2MU106_FC_CHG_TIMER_16hr = 0x7,
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};
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enum {
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S2MU106_SET_OTG_TX_OCP_500mA = 0x0,
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S2MU106_SET_OTG_TX_OCP_900mA = 0x1,
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S2MU106_SET_OTG_TX_OCP_1200mA = 0x2,
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S2MU106_SET_OTG_TX_OCP_1500mA = 0x3,
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};
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enum {
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S2MU106_SET_BAT_OCP_3500mA = 0x0,
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S2MU106_SET_BAT_OCP_4000mA = 0x1,
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S2MU106_SET_BAT_OCP_4500mA = 0x2,
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S2MU106_SET_BAT_OCP_5000mA = 0x3,
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S2MU106_SET_BAT_OCP_5500mA = 0x4,
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S2MU106_SET_BAT_OCP_6000mA = 0x5,
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S2MU106_SET_BAT_OCP_6500mA = 0x6,
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S2MU106_SET_BAT_OCP_7000mA = 0x7,
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};
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typedef struct s2mu106_charger_platform_data {
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int chg_float_voltage;
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char *charger_name;
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char *fuelgauge_name;
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char *wireless_charger_name;
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bool chg_eoc_dualpath;
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bool chg_ocp_disable;
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int mrstbtmr_factory;
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bool always_vssh_ldo_en;
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int recharge_vcell;
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uint32_t is_1MHz_switching:1;
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int chg_switching_freq;
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int slow_charging_current;
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int wireless_cc_cv;
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bool block_otg_psk_mode_en;
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bool reduce_async_debounce_time;
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} s2mu106_charger_platform_data_t;
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struct s2mu106_charger_data {
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struct i2c_client *i2c;
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struct device *dev;
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struct s2mu106_platform_data *s2mu106_pdata;
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struct delayed_work otg_vbus_work;
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struct delayed_work ivr_work;
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struct wake_lock ivr_wake_lock;
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struct delayed_work wc_current_work;
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struct wake_lock wc_current_wake_lock;
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struct delayed_work pmeter_3lv_work;
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struct delayed_work pmeter_2lv_work;
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struct workqueue_struct *charger_wqueue;
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struct power_supply *psy_chg;
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struct power_supply_desc psy_chg_desc;
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struct power_supply *psy_otg;
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struct power_supply_desc psy_otg_desc;
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struct power_supply *psy_bat;
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struct power_supply *psy_fg;
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s2mu106_charger_platform_data_t *pdata;
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int dev_id;
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int input_current;
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int charging_current;
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int topoff_current;
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int cable_type;
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bool is_charging;
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unsigned int charge_mode;
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struct mutex charger_mutex;
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bool ovp;
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bool otg_on;
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int unhealth_cnt;
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int status;
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int health;
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/* s2mu106 */
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int irq_det_bat;
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int irq_chg;
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int irq_chgin;
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int irq_chg_fault;
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int irq_tx;
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int irq_otg;
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int irq_vbus;
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int irq_rst;
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int irq_done;
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int irq_sys;
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int irq_event;
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int irq_bat;
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int irq_ivr;
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int irq_ivr_enabled;
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int ivr_on;
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bool slow_charging;
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int wc_current;
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int wc_pre_current;
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/* efficiency 9V charging */
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unsigned char reg_0x9E;
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#if defined(CONFIG_MUIC_NOTIFIER)
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struct notifier_block cable_check;
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#endif
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bool uno_on;
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struct mutex regmode_mutex;
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u8 read_reg;
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};
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#endif /*S2MU106_CHARGER_H*/
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