53 lines
1.4 KiB
C
Executable File
53 lines
1.4 KiB
C
Executable File
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_SPINLOCK_H
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#define _ASM_X86_SPINLOCK_H
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#include <linux/jump_label.h>
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#include <linux/atomic.h>
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#include <asm/page.h>
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#include <asm/processor.h>
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#include <linux/compiler.h>
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#include <asm/paravirt.h>
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#include <asm/bitops.h>
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/*
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* Your basic SMP spinlocks, allowing only a single CPU anywhere
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*
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* Simple spin lock operations. There are two variants, one clears IRQ's
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* on the local processor, one does not.
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*
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* These are fair FIFO ticket locks, which support up to 2^16 CPUs.
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*
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* (the type definitions are in asm/spinlock_types.h)
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*/
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/* How long a lock should spin before we consider blocking */
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#define SPIN_THRESHOLD (1 << 15)
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#include <asm/qspinlock.h>
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/*
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* Read-write spinlocks, allowing multiple readers
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* but only one writer.
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*
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* NOTE! it is quite common to have readers in interrupts
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* but no interrupt writers. For those circumstances we
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* can "mix" irq-safe locks - any writer needs to get a
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* irq-safe write-lock, but readers can get non-irqsafe
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* read-locks.
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*
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* On x86, we implement read-write locks using the generic qrwlock with
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* x86 specific optimization.
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*/
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#include <asm/qrwlock.h>
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#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
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#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
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#define arch_spin_relax(lock) cpu_relax()
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#define arch_read_relax(lock) cpu_relax()
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#define arch_write_relax(lock) cpu_relax()
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#endif /* _ASM_X86_SPINLOCK_H */
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