804 lines
21 KiB
Plaintext
Executable File
804 lines
21 KiB
Plaintext
Executable File
/*
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* Copyright (c) 2017 MediaTek Inc.
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* Author: John Crispin <john@phrozen.org>
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* Sean Wang <sean.wang@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt2701-clk.h>
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#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
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#include <dt-bindings/power/mt2701-power.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/mt2701-resets.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "mediatek,mt7623";
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interrupt-parent = <&sysirq>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpu_opp_table: opp_table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-98000000 {
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opp-hz = /bits/ 64 <98000000>;
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opp-microvolt = <1050000>;
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};
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opp-198000000 {
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opp-hz = /bits/ 64 <198000000>;
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opp-microvolt = <1050000>;
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};
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opp-398000000 {
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opp-hz = /bits/ 64 <398000000>;
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opp-microvolt = <1050000>;
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};
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opp-598000000 {
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opp-hz = /bits/ 64 <598000000>;
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opp-microvolt = <1050000>;
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};
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opp-747500000 {
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opp-hz = /bits/ 64 <747500000>;
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opp-microvolt = <1050000>;
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};
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opp-1040000000 {
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opp-hz = /bits/ 64 <1040000000>;
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opp-microvolt = <1150000>;
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};
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opp-1196000000 {
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opp-hz = /bits/ 64 <1196000000>;
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opp-microvolt = <1200000>;
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};
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opp-1300000000 {
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opp-hz = /bits/ 64 <1300000000>;
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opp-microvolt = <1300000>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "mediatek,mt6589-smp";
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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clocks = <&infracfg CLK_INFRA_CPUSEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cpu_opp_table>;
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#cooling-cells = <2>;
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cooling-min-level = <0>;
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cooling-max-level = <7>;
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clock-frequency = <1300000000>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x1>;
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operating-points-v2 = <&cpu_opp_table>;
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#cooling-cells = <2>;
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clock-frequency = <1300000000>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x2>;
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operating-points-v2 = <&cpu_opp_table>;
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#cooling-cells = <2>;
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clock-frequency = <1300000000>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x3>;
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operating-points-v2 = <&cpu_opp_table>;
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#cooling-cells = <2>;
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clock-frequency = <1300000000>;
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};
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};
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system_clk: dummy13m {
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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#clock-cells = <0>;
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};
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rtc32k: oscillator@1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32000>;
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clock-output-names = "rtc32k";
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};
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clk26m: oscillator@0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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clock-output-names = "clk26m";
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};
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thermal-zones {
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cpu_thermal: cpu_thermal {
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polling-delay-passive = <1000>;
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polling-delay = <1000>;
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thermal-sensors = <&thermal 0>;
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trips {
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cpu_passive: cpu_passive {
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temperature = <47000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_active: cpu_active {
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temperature = <67000>;
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hysteresis = <2000>;
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type = "active";
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};
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cpu_hot: cpu_hot {
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temperature = <87000>;
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hysteresis = <2000>;
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type = "hot";
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};
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cpu_crit {
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temperature = <107000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_passive>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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map1 {
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trip = <&cpu_active>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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map2 {
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trip = <&cpu_hot>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <13000000>;
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arm,cpu-registers-not-fw-configured;
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};
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topckgen: syscon@10000000 {
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compatible = "mediatek,mt7623-topckgen",
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"mediatek,mt2701-topckgen",
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"syscon";
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reg = <0 0x10000000 0 0x1000>;
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#clock-cells = <1>;
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};
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infracfg: syscon@10001000 {
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compatible = "mediatek,mt7623-infracfg",
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"mediatek,mt2701-infracfg",
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"syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pericfg: syscon@10003000 {
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compatible = "mediatek,mt7623-pericfg",
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"mediatek,mt2701-pericfg",
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"syscon";
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reg = <0 0x10003000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pio: pinctrl@10005000 {
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compatible = "mediatek,mt7623-pinctrl",
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"mediatek,mt2701-pinctrl";
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reg = <0 0x1000b000 0 0x1000>;
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mediatek,pctl-regmap = <&syscfg_pctl_a>;
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pins-are-numbered;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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};
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syscfg_pctl_a: syscfg@10005000 {
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compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
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reg = <0 0x10005000 0 0x1000>;
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};
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scpsys: scpsys@10006000 {
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compatible = "mediatek,mt7623-scpsys",
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"mediatek,mt2701-scpsys",
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"syscon";
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#power-domain-cells = <1>;
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reg = <0 0x10006000 0 0x1000>;
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infracfg = <&infracfg>;
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clocks = <&topckgen CLK_TOP_MM_SEL>,
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<&topckgen CLK_TOP_MFG_SEL>,
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<&topckgen CLK_TOP_ETHIF_SEL>;
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clock-names = "mm", "mfg", "ethif";
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};
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watchdog: watchdog@10007000 {
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compatible = "mediatek,mt7623-wdt",
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"mediatek,mt6589-wdt";
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reg = <0 0x10007000 0 0x100>;
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};
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timer: timer@10008000 {
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compatible = "mediatek,mt7623-timer",
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"mediatek,mt6577-timer";
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reg = <0 0x10008000 0 0x80>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&system_clk>, <&rtc32k>;
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clock-names = "system-clk", "rtc-clk";
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};
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pwrap: pwrap@1000d000 {
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compatible = "mediatek,mt7623-pwrap",
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"mediatek,mt2701-pwrap";
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reg = <0 0x1000d000 0 0x1000>;
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reg-names = "pwrap";
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
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reset-names = "pwrap";
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clocks = <&infracfg CLK_INFRA_PMICSPI>,
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<&infracfg CLK_INFRA_PMICWRAP>;
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clock-names = "spi", "wrap";
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};
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cir: cir@10013000 {
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compatible = "mediatek,mt7623-cir";
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reg = <0 0x10013000 0 0x1000>;
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_IRRX>;
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clock-names = "clk";
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status = "disabled";
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};
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sysirq: interrupt-controller@10200100 {
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compatible = "mediatek,mt7623-sysirq",
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"mediatek,mt6577-sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10200100 0 0x1c>;
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};
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efuse: efuse@10206000 {
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compatible = "mediatek,mt7623-efuse",
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"mediatek,mt8173-efuse";
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reg = <0 0x10206000 0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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thermal_calibration_data: calib@424 {
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reg = <0x424 0xc>;
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};
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};
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apmixedsys: syscon@10209000 {
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compatible = "mediatek,mt7623-apmixedsys",
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"mediatek,mt2701-apmixedsys",
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"syscon";
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reg = <0 0x10209000 0 0x1000>;
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#clock-cells = <1>;
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};
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rng: rng@1020f000 {
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compatible = "mediatek,mt7623-rng";
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reg = <0 0x1020f000 0 0x1000>;
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clocks = <&infracfg CLK_INFRA_TRNG>;
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clock-names = "rng";
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};
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gic: interrupt-controller@10211000 {
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compatible = "arm,cortex-a7-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10211000 0 0x1000>,
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<0 0x10212000 0 0x2000>,
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<0 0x10214000 0 0x2000>,
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<0 0x10216000 0 0x2000>;
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};
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auxadc: adc@11001000 {
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compatible = "mediatek,mt7623-auxadc",
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"mediatek,mt2701-auxadc";
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reg = <0 0x11001000 0 0x1000>;
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clocks = <&pericfg CLK_PERI_AUXADC>;
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clock-names = "main";
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#io-channel-cells = <1>;
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt7623-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11002000 0 0x400>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART0_SEL>,
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<&pericfg CLK_PERI_UART0>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart1: serial@11003000 {
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compatible = "mediatek,mt7623-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11003000 0 0x400>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART1_SEL>,
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<&pericfg CLK_PERI_UART1>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,mt7623-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11004000 0 0x400>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART2_SEL>,
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<&pericfg CLK_PERI_UART2>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart3: serial@11005000 {
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compatible = "mediatek,mt7623-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11005000 0 0x400>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART3_SEL>,
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<&pericfg CLK_PERI_UART3>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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pwm: pwm@11006000 {
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compatible = "mediatek,mt7623-pwm";
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reg = <0 0x11006000 0 0x1000>;
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#pwm-cells = <2>;
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clocks = <&topckgen CLK_TOP_PWM_SEL>,
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<&pericfg CLK_PERI_PWM>,
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<&pericfg CLK_PERI_PWM1>,
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<&pericfg CLK_PERI_PWM2>,
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<&pericfg CLK_PERI_PWM3>,
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<&pericfg CLK_PERI_PWM4>,
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<&pericfg CLK_PERI_PWM5>;
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clock-names = "top", "main", "pwm1", "pwm2",
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"pwm3", "pwm4", "pwm5";
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status = "disabled";
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};
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i2c0: i2c@11007000 {
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compatible = "mediatek,mt7623-i2c",
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"mediatek,mt6577-i2c";
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reg = <0 0x11007000 0 0x70>,
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<0 0x11000200 0 0x80>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C0>,
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<&pericfg CLK_PERI_AP_DMA>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@11008000 {
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compatible = "mediatek,mt7623-i2c",
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"mediatek,mt6577-i2c";
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reg = <0 0x11008000 0 0x70>,
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<0 0x11000280 0 0x80>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C1>,
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<&pericfg CLK_PERI_AP_DMA>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@11009000 {
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compatible = "mediatek,mt7623-i2c",
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"mediatek,mt6577-i2c";
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reg = <0 0x11009000 0 0x70>,
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<0 0x11000300 0 0x80>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C2>,
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<&pericfg CLK_PERI_AP_DMA>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi0: spi@1100a000 {
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compatible = "mediatek,mt7623-spi",
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"mediatek,mt2701-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x1100a000 0 0x100>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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<&topckgen CLK_TOP_SPI0_SEL>,
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<&pericfg CLK_PERI_SPI0>;
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clock-names = "parent-clk", "sel-clk", "spi-clk";
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status = "disabled";
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};
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thermal: thermal@1100b000 {
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#thermal-sensor-cells = <1>;
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compatible = "mediatek,mt7623-thermal",
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"mediatek,mt2701-thermal";
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reg = <0 0x1100b000 0 0x1000>;
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interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
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clock-names = "therm", "auxadc";
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resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
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reset-names = "therm";
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mediatek,auxadc = <&auxadc>;
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mediatek,apmixedsys = <&apmixedsys>;
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nvmem-cells = <&thermal_calibration_data>;
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nvmem-cell-names = "calibration-data";
|
|
};
|
|
|
|
nandc: nfi@1100d000 {
|
|
compatible = "mediatek,mt7623-nfc",
|
|
"mediatek,mt2701-nfc";
|
|
reg = <0 0x1100d000 0 0x1000>;
|
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
|
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
|
|
clocks = <&pericfg CLK_PERI_NFI>,
|
|
<&pericfg CLK_PERI_NFI_PAD>;
|
|
clock-names = "nfi_clk", "pad_clk";
|
|
status = "disabled";
|
|
ecc-engine = <&bch>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
bch: ecc@1100e000 {
|
|
compatible = "mediatek,mt7623-ecc",
|
|
"mediatek,mt2701-ecc";
|
|
reg = <0 0x1100e000 0 0x1000>;
|
|
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&pericfg CLK_PERI_NFI_ECC>;
|
|
clock-names = "nfiecc_clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@11016000 {
|
|
compatible = "mediatek,mt7623-spi",
|
|
"mediatek,mt2701-spi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0 0x11016000 0 0x100>;
|
|
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
|
|
<&topckgen CLK_TOP_SPI1_SEL>,
|
|
<&pericfg CLK_PERI_SPI1>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@11017000 {
|
|
compatible = "mediatek,mt7623-spi",
|
|
"mediatek,mt2701-spi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0 0x11017000 0 0x1000>;
|
|
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
|
|
<&topckgen CLK_TOP_SPI2_SEL>,
|
|
<&pericfg CLK_PERI_SPI2>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
afe: audio-controller@11220000 {
|
|
compatible = "mediatek,mt7623-audio",
|
|
"mediatek,mt2701-audio";
|
|
reg = <0 0x11220000 0 0x2000>,
|
|
<0 0x112a0000 0 0x20000>;
|
|
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
|
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
|
|
|
|
clocks = <&infracfg CLK_INFRA_AUDIO>,
|
|
<&topckgen CLK_TOP_AUD_MUX1_SEL>,
|
|
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
|
|
<&topckgen CLK_TOP_AUD_MUX1_DIV>,
|
|
<&topckgen CLK_TOP_AUD_MUX2_DIV>,
|
|
<&topckgen CLK_TOP_AUD_48K_TIMING>,
|
|
<&topckgen CLK_TOP_AUD_44K_TIMING>,
|
|
<&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
|
|
<&topckgen CLK_TOP_APLL_SEL>,
|
|
<&topckgen CLK_TOP_AUD1PLL_98M>,
|
|
<&topckgen CLK_TOP_AUD2PLL_90M>,
|
|
<&topckgen CLK_TOP_HADDS2PLL_98M>,
|
|
<&topckgen CLK_TOP_HADDS2PLL_294M>,
|
|
<&topckgen CLK_TOP_AUDPLL>,
|
|
<&topckgen CLK_TOP_AUDPLL_D4>,
|
|
<&topckgen CLK_TOP_AUDPLL_D8>,
|
|
<&topckgen CLK_TOP_AUDPLL_D16>,
|
|
<&topckgen CLK_TOP_AUDPLL_D24>,
|
|
<&topckgen CLK_TOP_AUDINTBUS_SEL>,
|
|
<&clk26m>,
|
|
<&topckgen CLK_TOP_SYSPLL1_D4>,
|
|
<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
|
|
<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
|
|
<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
|
|
<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
|
|
<&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
|
|
<&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
|
|
<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
|
|
<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
|
|
<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
|
|
<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
|
|
<&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
|
|
<&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
|
|
<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
|
|
<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
|
|
<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
|
|
<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
|
|
<&topckgen CLK_TOP_AUD_I2S5_MCLK>,
|
|
<&topckgen CLK_TOP_AUD_I2S6_MCLK>,
|
|
<&topckgen CLK_TOP_ASM_M_SEL>,
|
|
<&topckgen CLK_TOP_ASM_H_SEL>,
|
|
<&topckgen CLK_TOP_UNIVPLL2_D4>,
|
|
<&topckgen CLK_TOP_UNIVPLL2_D2>,
|
|
<&topckgen CLK_TOP_SYSPLL_D5>;
|
|
|
|
clock-names = "infra_sys_audio_clk",
|
|
"top_audio_mux1_sel",
|
|
"top_audio_mux2_sel",
|
|
"top_audio_mux1_div",
|
|
"top_audio_mux2_div",
|
|
"top_audio_48k_timing",
|
|
"top_audio_44k_timing",
|
|
"top_audpll_mux_sel",
|
|
"top_apll_sel",
|
|
"top_aud1_pll_98M",
|
|
"top_aud2_pll_90M",
|
|
"top_hadds2_pll_98M",
|
|
"top_hadds2_pll_294M",
|
|
"top_audpll",
|
|
"top_audpll_d4",
|
|
"top_audpll_d8",
|
|
"top_audpll_d16",
|
|
"top_audpll_d24",
|
|
"top_audintbus_sel",
|
|
"clk_26m",
|
|
"top_syspll1_d4",
|
|
"top_aud_k1_src_sel",
|
|
"top_aud_k2_src_sel",
|
|
"top_aud_k3_src_sel",
|
|
"top_aud_k4_src_sel",
|
|
"top_aud_k5_src_sel",
|
|
"top_aud_k6_src_sel",
|
|
"top_aud_k1_src_div",
|
|
"top_aud_k2_src_div",
|
|
"top_aud_k3_src_div",
|
|
"top_aud_k4_src_div",
|
|
"top_aud_k5_src_div",
|
|
"top_aud_k6_src_div",
|
|
"top_aud_i2s1_mclk",
|
|
"top_aud_i2s2_mclk",
|
|
"top_aud_i2s3_mclk",
|
|
"top_aud_i2s4_mclk",
|
|
"top_aud_i2s5_mclk",
|
|
"top_aud_i2s6_mclk",
|
|
"top_asm_m_sel",
|
|
"top_asm_h_sel",
|
|
"top_univpll2_d4",
|
|
"top_univpll2_d2",
|
|
"top_syspll_d5";
|
|
};
|
|
|
|
mmc0: mmc@11230000 {
|
|
compatible = "mediatek,mt7623-mmc",
|
|
"mediatek,mt8135-mmc";
|
|
reg = <0 0x11230000 0 0x1000>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&pericfg CLK_PERI_MSDC30_0>,
|
|
<&topckgen CLK_TOP_MSDC30_0_SEL>;
|
|
clock-names = "source", "hclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc1: mmc@11240000 {
|
|
compatible = "mediatek,mt7623-mmc",
|
|
"mediatek,mt8135-mmc";
|
|
reg = <0 0x11240000 0 0x1000>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&pericfg CLK_PERI_MSDC30_1>,
|
|
<&topckgen CLK_TOP_MSDC30_1_SEL>;
|
|
clock-names = "source", "hclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
hifsys: syscon@1a000000 {
|
|
compatible = "mediatek,mt7623-hifsys",
|
|
"mediatek,mt2701-hifsys",
|
|
"syscon";
|
|
reg = <0 0x1a000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
usb1: usb@1a1c0000 {
|
|
compatible = "mediatek,mt7623-xhci",
|
|
"mediatek,mt8173-xhci";
|
|
reg = <0 0x1a1c0000 0 0x1000>,
|
|
<0 0x1a1c4700 0 0x0100>;
|
|
reg-names = "mac", "ippc";
|
|
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
|
|
<&topckgen CLK_TOP_ETHIF_SEL>;
|
|
clock-names = "sys_ck", "free_ck";
|
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
|
|
phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
u3phy1: usb-phy@1a1c4000 {
|
|
compatible = "mediatek,mt7623-u3phy",
|
|
"mediatek,mt2701-u3phy";
|
|
reg = <0 0x1a1c4000 0 0x0700>;
|
|
clocks = <&clk26m>;
|
|
clock-names = "u3phya_ref";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
u2port0: usb-phy@1a1c4800 {
|
|
reg = <0 0x1a1c4800 0 0x0100>;
|
|
#phy-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
u3port0: usb-phy@1a1c4900 {
|
|
reg = <0 0x1a1c4900 0 0x0700>;
|
|
#phy-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
usb2: usb@1a240000 {
|
|
compatible = "mediatek,mt7623-xhci",
|
|
"mediatek,mt8173-xhci";
|
|
reg = <0 0x1a240000 0 0x1000>,
|
|
<0 0x1a244700 0 0x0100>;
|
|
reg-names = "mac", "ippc";
|
|
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
|
|
<&topckgen CLK_TOP_ETHIF_SEL>;
|
|
clock-names = "sys_ck", "free_ck";
|
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
|
|
phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
u3phy2: usb-phy@1a244000 {
|
|
compatible = "mediatek,mt7623-u3phy",
|
|
"mediatek,mt2701-u3phy";
|
|
reg = <0 0x1a244000 0 0x0700>;
|
|
clocks = <&clk26m>;
|
|
clock-names = "u3phya_ref";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
u2port1: usb-phy@1a244800 {
|
|
reg = <0 0x1a244800 0 0x0100>;
|
|
#phy-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
u3port1: usb-phy@1a244900 {
|
|
reg = <0 0x1a244900 0 0x0700>;
|
|
#phy-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
ethsys: syscon@1b000000 {
|
|
compatible = "mediatek,mt7623-ethsys",
|
|
"mediatek,mt2701-ethsys",
|
|
"syscon";
|
|
reg = <0 0x1b000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
eth: ethernet@1b100000 {
|
|
compatible = "mediatek,mt7623-eth",
|
|
"mediatek,mt2701-eth",
|
|
"syscon";
|
|
reg = <0 0x1b100000 0 0x20000>;
|
|
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
|
|
<ðsys CLK_ETHSYS_ESW>,
|
|
<ðsys CLK_ETHSYS_GP1>,
|
|
<ðsys CLK_ETHSYS_GP2>,
|
|
<&apmixedsys CLK_APMIXED_TRGPLL>;
|
|
clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
|
|
resets = <ðsys MT2701_ETHSYS_FE_RST>,
|
|
<ðsys MT2701_ETHSYS_GMAC_RST>,
|
|
<ðsys MT2701_ETHSYS_PPE_RST>;
|
|
reset-names = "fe", "gmac", "ppe";
|
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
|
|
mediatek,ethsys = <ðsys>;
|
|
mediatek,pctl = <&syscfg_pctl_a>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
crypto: crypto@1b240000 {
|
|
compatible = "mediatek,mt7623-crypto";
|
|
reg = <0 0x1b240000 0 0x20000>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
|
|
<ðsys CLK_ETHSYS_CRYPTO>;
|
|
clock-names = "ethif","cryp";
|
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
|
|
status = "disabled";
|
|
};
|
|
};
|