227 lines
7.9 KiB
C
Executable File
227 lines
7.9 KiB
C
Executable File
/* arch/arm64/mach-exynos/include/mach/apm-exynos.h
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*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* APM register definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_REGS_APM_H
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#define __ASM_ARCH_REGS_APM_H __FILE__
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#include <linux/regmap.h>
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#include <linux/types.h>
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#include <linux/file.h>
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#include <linux/fs.h>
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/* Margin related variables */
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#define MARGIN_0MV (0)
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#define MARGIN_6_25MV (1)
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#define MARGIN_12_5MV (2)
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#define MARGIN_18_75MV (3)
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#define MARGIN_25MV (4)
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#define MARGIN_31_25MV (5)
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#define MARGIN_37_5MV (6)
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#define MARGIN_43_75MV (7)
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#define MARGIN_50MV (8)
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#define MARGIN_56_25MV (9)
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#define MARGIN_62_5MV (0xA)
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#define MARGIN_68_75MV (0xB)
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#define MARGIN_75MV (0xC)
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#define MARGIN_81_25MV (0xD)
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#define MARGIN_87_5MV (0xE)
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#define MARGIN_93_75MV (0xF)
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/* PERIOD related variables */
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#define PERIOD_1MS (0)
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#define PERIOD_5MS (1)
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/* APM Protocol related variables */
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/* Notifier variables */
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#define APM_READY (0x0001)
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#define APM_SLEEP (0x0002)
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#define APM_TIMEOUT (0x0003)
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#define CL_ENABLE (0x0004)
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#define CL_DISABLE (0x0005)
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/* Shift variables */
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#define CL_DVFS_SHIFT (29)
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#define COMMAND_SHIFT (27)
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#define PM_SECTION_SHIFT (26)
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#define MASK_SHIFT (25)
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#define INIT_MODE_SHIFT (22)
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#define ASV_MODE_SHIFT (21)
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#define CL_ALL_STOP_SHIFT (30)
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#define CL_ALL_START_SHIFT (31)
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#define MULTI_BYTE_SHIFT (16)
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#define CL_DOMAIN_SHIFT (14)
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#define MULTI_BYTE_CNT_SHIFT (16)
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#define ATLAS_SHIFT (0)
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#define APOLLO_SHIFT (4)
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#define G3D_SHIFT (8)
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#define MIF_SHIFT (12)
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#define PERIOD_SHIFT (16)
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#define BYTE_SHIFT (8)
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#define BYTE_MASK (0xFF)
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#define WRITE_MODE (0)
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#define READ_MODE (1)
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#define NONE (2)
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#define TX_INTERRUPT_ENABLE (1)
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#define MASK (1)
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#define BYTE_4 (4)
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#define INIT_SET (1)
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#define ASV_SET (1)
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#define DEBUG_COUNT (10)
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/* Mask variables */
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#define CL_DVFS_MASK (1)
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#define COMMAND_MASK (0x3)
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#define MULTI_BYTE_MASK (0xF)
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#define CL_DVFS (CL_DVFS_MASK << CL_DVFS_SHIFT)
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#define CL_DVFS_OFF (0)
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#define COMMAND (COMMAND_MASK << COMMAND_SHIFT)
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#define MULTI_BYTE (MULTI_BYTE_MASK << MULTI_BYTE_SHIFT)
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/* Error variable */
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#define APM_RET_SUCESS (0xa)
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#define APM_GPIO_ERR (0xFFFFFFFF)
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#define PMIC_NO_ACK_ERR (0xEEEEEEEE)
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#define ERR_TIMEOUT (1)
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#define ERR_RETRY (2)
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#define ERR_OUT (3)
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#define RETRY_ERR (-0xFF)
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/* apm related variables */
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#define MSG_LEN (5)
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#define G3D_LV_OFFSET (0)
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#define MBOX_LEN (4)
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#define TIMEOUT (500) /* timeout 500 msec */
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#define TX (0)
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#define RX (1)
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#define HSI2C_MODE (0)
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#define APM_MODE (1)
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#define APM_TIMOUT (2)
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#define CL_ON (1)
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#define CL_OFF (0)
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#define APM_OFF (0)
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#define APM_ON (1)
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#define APM_WFI_TIMEOUT (2)
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#define EXYNOS_PMU_CORTEXM3_APM_CONFIGURATION (0x2500)
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#define EXYNOS_PMU_CORTEXM3_APM_STATUS (0x2504)
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#define EXYNOS_PMU_CORTEXM3_APM_OPTION (0x2508)
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#define EXYNOS_PMU_CORTEXM3_APM_DURATION0 (0x2510)
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#define EXYNOS_PMU_CORTEXM3_APM_DURATION1 (0x2514)
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#define EXYNOS_PMU_CORTEXM3_APM_DURATION2 (0x2518)
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#define EXYNOS_PMU_CORTEXM3_APM_DURATION3 (0x251C)
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/* CORTEX M3 */
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#define ENABLE_APM (0x1 << 15)
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#define APM_STATUS_MASK (0x1)
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#define STANDBYWFI (28)
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#define STANDBYWFI_MASK (0x1)
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#define APM_LOCAL_PWR_CFG_RUN (0x1 << 0)
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#define APM_LOCAL_PWR_CFG_RESET (~(0x1 << 0))
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struct apm_ops {
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int (*apm_update_bits) (unsigned int type, unsigned int reg,
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unsigned int mask, unsigned int value);
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int (*apm_write) (unsigned int type, unsigned int reg, unsigned int value);
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int (*apm_bulk_write) (unsigned int type, unsigned char reg,
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unsigned char *buf, unsigned int count);
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int (*apm_read) (unsigned int type, unsigned int reg, unsigned int *val);
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int (*apm_bulk_read) (unsigned int type, unsigned char reg,
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unsigned char *buf, unsigned int count);
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};
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struct cl_ops {
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void (*apm_reset) (void);
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void (*apm_power_up) (void);
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void (*apm_power_down) (void);
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int (*cl_dvfs_setup) (unsigned int atlas_cl_limit, unsigned int apollo_cl_limit,
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unsigned int g3d_cl_limit, unsigned int mif_cl_limit, unsigned int cl_period);
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int (*cl_dvfs_start) (unsigned int cl_domain);
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int (*cl_dvfs_stop) (unsigned int cl_domain, unsigned int level);
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int (*cl_dvfs_enable) (void);
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int (*cl_dvfs_disable) (void);
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int (*g3d_power_on) (void);
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int (*g3d_power_down) (void);
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int (*enter_wfi) (void);
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};
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struct debug_data {
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u32 buf[DEBUG_COUNT][6];
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s64 time[DEBUG_COUNT];
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char* name[DEBUG_COUNT];
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unsigned int cnt;
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#ifdef CONFIG_EXYNOS_APM_VOLTAGE_DEBUG
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u32 vol[DEBUG_COUNT][4];
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u32 atl_value;
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u32 apo_value;
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u32 g3d_value;
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u32 mif_value;
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#endif
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};
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struct cl_init_data {
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u32 atlas_margin;
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u32 apollo_margin;
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u32 g3d_margin;
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u32 mif_margin;
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u32 period;
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u32 cl_status;
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u32 apm_status;
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};
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extern void cl_dvfs_lock(void);
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extern void cl_dvfs_unlock(void);
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extern int cm3_status_open(struct inode *inode, struct file *file);
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extern struct apm_ops exynos_apm_function_ops;
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extern int register_apm_notifier(struct notifier_block *nb);
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extern int unregister_apm_notifier(struct notifier_block *nb);
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extern int apm_notifier_call_chain(unsigned long val);
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extern void exynos_apm_reset_release(void);
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extern void exynos_apm_power_up(void);
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extern void exynos_apm_power_down(void);
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extern int exynos_cl_dvfs_setup(unsigned int atlas_cl_limit, unsigned int apollo_cl_limit, unsigned int g3d_cl_limit,
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unsigned int mif_cl_limit, unsigned int cl_period);
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extern int exynos_cl_dvfs_start(unsigned int cl_domain);
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extern int exynos_cl_dvfs_stop(unsigned int cl_domain, unsigned int level);
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extern int exynos_cl_dvfs_mode_enable(void);
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extern int exynos_cl_dvfs_mode_disable(void);
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extern int exynos_g3d_power_on_noti_apm(void);
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extern int exynos_g3d_power_down_noti_apm(void);
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extern int exynos_apm_enter_wfi(void);
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extern int exynos_apm_update_bits(unsigned int type, unsigned int reg, unsigned int mask, unsigned int value);
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extern int exynos_apm_write(unsigned int type, unsigned int address, unsigned int value);
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extern int exynos_apm_bulk_write(unsigned int type, unsigned char reg, unsigned char *buf, unsigned int count);
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extern int exynos_apm_read(unsigned int type, unsigned int reg, unsigned int *val);
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extern int exynos_apm_bulk_read(unsigned int type, unsigned char reg, unsigned char *buf, unsigned int count);
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#define exynos7890_cl_dvfs_start(a) exynos7420_cl_dvfs_start(a)
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#define exynos7890_cl_dvfs_stop(a, b) exynos7420_cl_dvfs_stop(a, b)
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#define exynos7890_cl_dvfs_mode_enable() exynos7420_cl_dvfs_mode_enable()
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#define exynos7890_cl_dvfs_mode_disable() exynos7420_cl_dvfs_mode_disable()
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#define exynos7890_g3d_power_on_noti_apm() exynos7420_g3d_power_on_noti_apm()
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#define exynos7890_g3d_power_down_noti_apm() exynos7420_g3d_power_down_noti_apm()
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#define exynos7890_apm_enter_wfi() exynos7420_apm_enter_wfi()
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#define exynos7890_apm_update_bits(a, b, c, d) exynos7420_apm_update_bits(a, b, c, d)
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#define exynos7890_apm_write(a, b, c) exynos7420_apm_write(a, b, c)
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#define exynos7890_apm_bulk_write(a, b, c, d) exynos7420_apm_bulk_write(a, b, c, d)
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#define exynos7890_apm_read(a, b, c) exynos7420_apm_read(a, b, c)
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#define exynos7890_apm_bulk_read(a, b, c, d) exynos7420_apm_bulk_read(a, b, c, d)
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unsigned int exynos_cortexm3_pmu_read(unsigned int offset);
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void exynos_cortexm3_pmu_write(unsigned int val, unsigned int offset);
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unsigned int exynos_mailbox_reg_read(unsigned int offset);
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void exynos_mailbox_reg_write(unsigned int val, unsigned int offset);
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#endif
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