760 lines
22 KiB
C
Executable File
760 lines
22 KiB
C
Executable File
/*
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* AD7190 AD7192 AD7193 AD7195 SPI ADC driver
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*
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* Copyright 2011-2015 Analog Devices Inc.
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*
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* Licensed under the GPL-2.
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*/
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/sysfs.h>
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#include <linux/spi/spi.h>
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#include <linux/regulator/consumer.h>
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#include <linux/err.h>
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#include <linux/sched.h>
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#include <linux/delay.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/trigger.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/triggered_buffer.h>
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#include <linux/iio/adc/ad_sigma_delta.h>
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#include "ad7192.h"
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/* Registers */
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#define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
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#define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
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#define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
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#define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
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#define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
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#define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
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#define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
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#define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */
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/* (AD7792)/24-bit (AD7192)) */
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#define AD7192_REG_FULLSALE 7 /* Full-Scale Register */
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/* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
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/* Communications Register Bit Designations (AD7192_REG_COMM) */
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#define AD7192_COMM_WEN BIT(7) /* Write Enable */
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#define AD7192_COMM_WRITE 0 /* Write Operation */
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#define AD7192_COMM_READ BIT(6) /* Read Operation */
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#define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
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#define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */
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/* Status Register Bit Designations (AD7192_REG_STAT) */
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#define AD7192_STAT_RDY BIT(7) /* Ready */
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#define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */
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#define AD7192_STAT_NOREF BIT(5) /* Error no external reference */
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#define AD7192_STAT_PARITY BIT(4) /* Parity */
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#define AD7192_STAT_CH3 BIT(2) /* Channel 3 */
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#define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
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#define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
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/* Mode Register Bit Designations (AD7192_REG_MODE) */
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#define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */
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#define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */
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#define AD7192_MODE_DAT_STA BIT(20) /* Status Register transmission */
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#define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */
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#define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */
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#define AD7192_MODE_ACX BIT(14) /* AC excitation enable(AD7195 only)*/
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#define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */
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#define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/
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#define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */
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#define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */
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#define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */
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/* Mode Register: AD7192_MODE_SEL options */
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#define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */
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#define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
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#define AD7192_MODE_IDLE 2 /* Idle Mode */
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#define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
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#define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
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#define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
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#define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
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#define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
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/* Mode Register: AD7192_MODE_CLKSRC options */
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#define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/
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/* from MCLK1 to MCLK2 */
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#define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
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#define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */
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/* available at the MCLK2 pin */
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#define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/
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/* at the MCLK2 pin */
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/* Configuration Register Bit Designations (AD7192_REG_CONF) */
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#define AD7192_CONF_CHOP BIT(23) /* CHOP enable */
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#define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */
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#define AD7192_CONF_CHAN(x) ((x) << 8) /* Channel select */
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#define AD7192_CONF_CHAN_MASK (0x7FF << 8) /* Channel select mask */
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#define AD7192_CONF_BURN BIT(7) /* Burnout current enable */
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#define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */
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#define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */
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#define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */
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#define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */
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#define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */
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#define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
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#define AD7192_CH_TEMP BIT(2) /* Temp Sensor */
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#define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */
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#define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */
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#define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */
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#define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */
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#define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */
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#define AD7193_CH_AIN1P_AIN2M 0x000 /* AIN1(+) - AIN2(-) */
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#define AD7193_CH_AIN3P_AIN4M 0x001 /* AIN3(+) - AIN4(-) */
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#define AD7193_CH_AIN5P_AIN6M 0x002 /* AIN5(+) - AIN6(-) */
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#define AD7193_CH_AIN7P_AIN8M 0x004 /* AIN7(+) - AIN8(-) */
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#define AD7193_CH_TEMP 0x100 /* Temp senseor */
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#define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */
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#define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */
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#define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */
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#define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */
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#define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */
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#define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */
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#define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */
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#define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */
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#define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */
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#define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */
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/* ID Register Bit Designations (AD7192_REG_ID) */
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#define ID_AD7190 0x4
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#define ID_AD7192 0x0
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#define ID_AD7193 0x2
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#define ID_AD7195 0x6
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#define AD7192_ID_MASK 0x0F
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/* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
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#define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */
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#define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */
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#define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */
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#define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */
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#define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */
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#define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
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#define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */
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#define AD7192_EXT_FREQ_MHZ_MIN 2457600
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#define AD7192_EXT_FREQ_MHZ_MAX 5120000
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#define AD7192_INT_FREQ_MHZ 4915200
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/* NOTE:
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* The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
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* In order to avoid contentions on the SPI bus, it's therefore necessary
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* to use spi bus locking.
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*
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* The DOUT/RDY output must also be wired to an interrupt capable GPIO.
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*/
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struct ad7192_state {
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struct regulator *avdd;
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struct regulator *dvdd;
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u16 int_vref_mv;
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u32 mclk;
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u32 f_order;
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u32 mode;
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u32 conf;
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u32 scale_avail[8][2];
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u8 gpocon;
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u8 devid;
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struct ad_sigma_delta sd;
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};
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static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd)
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{
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return container_of(sd, struct ad7192_state, sd);
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}
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static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
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{
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struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
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st->conf &= ~AD7192_CONF_CHAN_MASK;
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st->conf |= AD7192_CONF_CHAN(channel);
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return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
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}
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static int ad7192_set_mode(struct ad_sigma_delta *sd,
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enum ad_sigma_delta_mode mode)
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{
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struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
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st->mode &= ~AD7192_MODE_SEL_MASK;
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st->mode |= AD7192_MODE_SEL(mode);
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return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
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}
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static const struct ad_sigma_delta_info ad7192_sigma_delta_info = {
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.set_channel = ad7192_set_channel,
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.set_mode = ad7192_set_mode,
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.has_registers = true,
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.addr_shift = 3,
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.read_mask = BIT(6),
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};
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static const struct ad_sd_calib_data ad7192_calib_arr[8] = {
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{AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
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{AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
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{AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
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{AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
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{AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
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{AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
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{AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
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{AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
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};
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static int ad7192_calibrate_all(struct ad7192_state *st)
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{
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return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,
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ARRAY_SIZE(ad7192_calib_arr));
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}
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static inline bool ad7192_valid_external_frequency(u32 freq)
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{
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return (freq >= AD7192_EXT_FREQ_MHZ_MIN &&
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freq <= AD7192_EXT_FREQ_MHZ_MAX);
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}
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static int ad7192_setup(struct ad7192_state *st,
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const struct ad7192_platform_data *pdata)
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{
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struct iio_dev *indio_dev = spi_get_drvdata(st->sd.spi);
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unsigned long long scale_uv;
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int i, ret, id;
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/* reset the serial interface */
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ret = ad_sd_reset(&st->sd, 48);
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if (ret < 0)
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goto out;
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usleep_range(500, 1000); /* Wait for at least 500us */
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/* write/read test for device presence */
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ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);
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if (ret)
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goto out;
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id &= AD7192_ID_MASK;
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if (id != st->devid)
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dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X)\n",
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id);
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switch (pdata->clock_source_sel) {
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case AD7192_CLK_INT:
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case AD7192_CLK_INT_CO:
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st->mclk = AD7192_INT_FREQ_MHZ;
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break;
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case AD7192_CLK_EXT_MCLK1_2:
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case AD7192_CLK_EXT_MCLK2:
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if (ad7192_valid_external_frequency(pdata->ext_clk_hz)) {
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st->mclk = pdata->ext_clk_hz;
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break;
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}
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dev_err(&st->sd.spi->dev, "Invalid frequency setting %u\n",
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pdata->ext_clk_hz);
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ret = -EINVAL;
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goto out;
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default:
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ret = -EINVAL;
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goto out;
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}
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st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |
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AD7192_MODE_CLKSRC(pdata->clock_source_sel) |
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AD7192_MODE_RATE(480);
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st->conf = AD7192_CONF_GAIN(0);
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if (pdata->rej60_en)
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st->mode |= AD7192_MODE_REJ60;
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if (pdata->sinc3_en)
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st->mode |= AD7192_MODE_SINC3;
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if (pdata->refin2_en && (st->devid != ID_AD7195))
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st->conf |= AD7192_CONF_REFSEL;
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if (pdata->chop_en) {
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st->conf |= AD7192_CONF_CHOP;
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if (pdata->sinc3_en)
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st->f_order = 3; /* SINC 3rd order */
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else
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st->f_order = 4; /* SINC 4th order */
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} else {
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st->f_order = 1;
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}
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if (pdata->buf_en)
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st->conf |= AD7192_CONF_BUF;
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if (pdata->unipolar_en)
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st->conf |= AD7192_CONF_UNIPOLAR;
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if (pdata->burnout_curr_en)
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st->conf |= AD7192_CONF_BURN;
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ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
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if (ret)
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goto out;
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ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
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if (ret)
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goto out;
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ret = ad7192_calibrate_all(st);
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if (ret)
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goto out;
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/* Populate available ADC input ranges */
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for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
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scale_uv = ((u64)st->int_vref_mv * 100000000)
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>> (indio_dev->channels[0].scan_type.realbits -
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((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));
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scale_uv >>= i;
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st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
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st->scale_avail[i][0] = scale_uv;
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}
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return 0;
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out:
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dev_err(&st->sd.spi->dev, "setup failed\n");
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return ret;
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}
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static ssize_t
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ad7192_show_scale_available(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct iio_dev *indio_dev = dev_to_iio_dev(dev);
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struct ad7192_state *st = iio_priv(indio_dev);
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int i, len = 0;
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for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
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len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0],
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st->scale_avail[i][1]);
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len += sprintf(buf + len, "\n");
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return len;
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}
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static IIO_DEVICE_ATTR_NAMED(in_v_m_v_scale_available,
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in_voltage-voltage_scale_available,
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0444, ad7192_show_scale_available, NULL, 0);
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static IIO_DEVICE_ATTR(in_voltage_scale_available, 0444,
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ad7192_show_scale_available, NULL, 0);
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static ssize_t ad7192_show_ac_excitation(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct iio_dev *indio_dev = dev_to_iio_dev(dev);
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struct ad7192_state *st = iio_priv(indio_dev);
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return sprintf(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX));
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}
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static ssize_t ad7192_show_bridge_switch(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct iio_dev *indio_dev = dev_to_iio_dev(dev);
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struct ad7192_state *st = iio_priv(indio_dev);
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return sprintf(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW));
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}
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static ssize_t ad7192_set(struct device *dev,
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struct device_attribute *attr,
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const char *buf,
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size_t len)
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{
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struct iio_dev *indio_dev = dev_to_iio_dev(dev);
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struct ad7192_state *st = iio_priv(indio_dev);
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struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
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int ret;
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bool val;
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ret = strtobool(buf, &val);
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if (ret < 0)
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return ret;
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ret = iio_device_claim_direct_mode(indio_dev);
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if (ret)
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return ret;
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switch ((u32)this_attr->address) {
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case AD7192_REG_GPOCON:
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if (val)
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st->gpocon |= AD7192_GPOCON_BPDSW;
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else
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st->gpocon &= ~AD7192_GPOCON_BPDSW;
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ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);
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break;
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case AD7192_REG_MODE:
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if (val)
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st->mode |= AD7192_MODE_ACX;
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else
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st->mode &= ~AD7192_MODE_ACX;
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ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
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break;
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default:
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ret = -EINVAL;
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}
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iio_device_release_direct_mode(indio_dev);
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return ret ? ret : len;
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|
}
|
|
|
|
static IIO_DEVICE_ATTR(bridge_switch_en, 0644,
|
|
ad7192_show_bridge_switch, ad7192_set,
|
|
AD7192_REG_GPOCON);
|
|
|
|
static IIO_DEVICE_ATTR(ac_excitation_en, 0644,
|
|
ad7192_show_ac_excitation, ad7192_set,
|
|
AD7192_REG_MODE);
|
|
|
|
static struct attribute *ad7192_attributes[] = {
|
|
&iio_dev_attr_in_v_m_v_scale_available.dev_attr.attr,
|
|
&iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
|
|
&iio_dev_attr_bridge_switch_en.dev_attr.attr,
|
|
&iio_dev_attr_ac_excitation_en.dev_attr.attr,
|
|
NULL
|
|
};
|
|
|
|
static const struct attribute_group ad7192_attribute_group = {
|
|
.attrs = ad7192_attributes,
|
|
};
|
|
|
|
static struct attribute *ad7195_attributes[] = {
|
|
&iio_dev_attr_in_v_m_v_scale_available.dev_attr.attr,
|
|
&iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
|
|
&iio_dev_attr_bridge_switch_en.dev_attr.attr,
|
|
NULL
|
|
};
|
|
|
|
static const struct attribute_group ad7195_attribute_group = {
|
|
.attrs = ad7195_attributes,
|
|
};
|
|
|
|
static unsigned int ad7192_get_temp_scale(bool unipolar)
|
|
{
|
|
return unipolar ? 2815 * 2 : 2815;
|
|
}
|
|
|
|
static int ad7192_read_raw(struct iio_dev *indio_dev,
|
|
struct iio_chan_spec const *chan,
|
|
int *val,
|
|
int *val2,
|
|
long m)
|
|
{
|
|
struct ad7192_state *st = iio_priv(indio_dev);
|
|
bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR);
|
|
|
|
switch (m) {
|
|
case IIO_CHAN_INFO_RAW:
|
|
return ad_sigma_delta_single_conversion(indio_dev, chan, val);
|
|
case IIO_CHAN_INFO_SCALE:
|
|
switch (chan->type) {
|
|
case IIO_VOLTAGE:
|
|
mutex_lock(&indio_dev->mlock);
|
|
*val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0];
|
|
*val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1];
|
|
mutex_unlock(&indio_dev->mlock);
|
|
return IIO_VAL_INT_PLUS_NANO;
|
|
case IIO_TEMP:
|
|
*val = 0;
|
|
*val2 = 1000000000 / ad7192_get_temp_scale(unipolar);
|
|
return IIO_VAL_INT_PLUS_NANO;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
case IIO_CHAN_INFO_OFFSET:
|
|
if (!unipolar)
|
|
*val = -(1 << (chan->scan_type.realbits - 1));
|
|
else
|
|
*val = 0;
|
|
/* Kelvin to Celsius */
|
|
if (chan->type == IIO_TEMP)
|
|
*val -= 273 * ad7192_get_temp_scale(unipolar);
|
|
return IIO_VAL_INT;
|
|
case IIO_CHAN_INFO_SAMP_FREQ:
|
|
*val = st->mclk /
|
|
(st->f_order * 1024 * AD7192_MODE_RATE(st->mode));
|
|
return IIO_VAL_INT;
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int ad7192_write_raw(struct iio_dev *indio_dev,
|
|
struct iio_chan_spec const *chan,
|
|
int val,
|
|
int val2,
|
|
long mask)
|
|
{
|
|
struct ad7192_state *st = iio_priv(indio_dev);
|
|
int ret, i, div;
|
|
unsigned int tmp;
|
|
|
|
ret = iio_device_claim_direct_mode(indio_dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
switch (mask) {
|
|
case IIO_CHAN_INFO_SCALE:
|
|
ret = -EINVAL;
|
|
for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
|
|
if (val2 == st->scale_avail[i][1]) {
|
|
ret = 0;
|
|
tmp = st->conf;
|
|
st->conf &= ~AD7192_CONF_GAIN(-1);
|
|
st->conf |= AD7192_CONF_GAIN(i);
|
|
if (tmp == st->conf)
|
|
break;
|
|
ad_sd_write_reg(&st->sd, AD7192_REG_CONF,
|
|
3, st->conf);
|
|
ad7192_calibrate_all(st);
|
|
break;
|
|
}
|
|
break;
|
|
case IIO_CHAN_INFO_SAMP_FREQ:
|
|
if (!val) {
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
div = st->mclk / (val * st->f_order * 1024);
|
|
if (div < 1 || div > 1023) {
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
st->mode &= ~AD7192_MODE_RATE(-1);
|
|
st->mode |= AD7192_MODE_RATE(div);
|
|
ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
}
|
|
|
|
iio_device_release_direct_mode(indio_dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
|
|
struct iio_chan_spec const *chan,
|
|
long mask)
|
|
{
|
|
switch (mask) {
|
|
case IIO_CHAN_INFO_SCALE:
|
|
return IIO_VAL_INT_PLUS_NANO;
|
|
case IIO_CHAN_INFO_SAMP_FREQ:
|
|
return IIO_VAL_INT;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static const struct iio_info ad7192_info = {
|
|
.read_raw = ad7192_read_raw,
|
|
.write_raw = ad7192_write_raw,
|
|
.write_raw_get_fmt = ad7192_write_raw_get_fmt,
|
|
.attrs = &ad7192_attribute_group,
|
|
.validate_trigger = ad_sd_validate_trigger,
|
|
.driver_module = THIS_MODULE,
|
|
};
|
|
|
|
static const struct iio_info ad7195_info = {
|
|
.read_raw = ad7192_read_raw,
|
|
.write_raw = ad7192_write_raw,
|
|
.write_raw_get_fmt = ad7192_write_raw_get_fmt,
|
|
.attrs = &ad7195_attribute_group,
|
|
.validate_trigger = ad_sd_validate_trigger,
|
|
.driver_module = THIS_MODULE,
|
|
};
|
|
|
|
static const struct iio_chan_spec ad7192_channels[] = {
|
|
AD_SD_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M, 24, 32, 0),
|
|
AD_SD_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M, 24, 32, 0),
|
|
AD_SD_TEMP_CHANNEL(2, AD7192_CH_TEMP, 24, 32, 0),
|
|
AD_SD_SHORTED_CHANNEL(3, 2, AD7192_CH_AIN2P_AIN2M, 24, 32, 0),
|
|
AD_SD_CHANNEL(4, 1, AD7192_CH_AIN1, 24, 32, 0),
|
|
AD_SD_CHANNEL(5, 2, AD7192_CH_AIN2, 24, 32, 0),
|
|
AD_SD_CHANNEL(6, 3, AD7192_CH_AIN3, 24, 32, 0),
|
|
AD_SD_CHANNEL(7, 4, AD7192_CH_AIN4, 24, 32, 0),
|
|
IIO_CHAN_SOFT_TIMESTAMP(8),
|
|
};
|
|
|
|
static const struct iio_chan_spec ad7193_channels[] = {
|
|
AD_SD_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M, 24, 32, 0),
|
|
AD_SD_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M, 24, 32, 0),
|
|
AD_SD_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M, 24, 32, 0),
|
|
AD_SD_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M, 24, 32, 0),
|
|
AD_SD_TEMP_CHANNEL(4, AD7193_CH_TEMP, 24, 32, 0),
|
|
AD_SD_SHORTED_CHANNEL(5, 2, AD7193_CH_AIN2P_AIN2M, 24, 32, 0),
|
|
AD_SD_CHANNEL(6, 1, AD7193_CH_AIN1, 24, 32, 0),
|
|
AD_SD_CHANNEL(7, 2, AD7193_CH_AIN2, 24, 32, 0),
|
|
AD_SD_CHANNEL(8, 3, AD7193_CH_AIN3, 24, 32, 0),
|
|
AD_SD_CHANNEL(9, 4, AD7193_CH_AIN4, 24, 32, 0),
|
|
AD_SD_CHANNEL(10, 5, AD7193_CH_AIN5, 24, 32, 0),
|
|
AD_SD_CHANNEL(11, 6, AD7193_CH_AIN6, 24, 32, 0),
|
|
AD_SD_CHANNEL(12, 7, AD7193_CH_AIN7, 24, 32, 0),
|
|
AD_SD_CHANNEL(13, 8, AD7193_CH_AIN8, 24, 32, 0),
|
|
IIO_CHAN_SOFT_TIMESTAMP(14),
|
|
};
|
|
|
|
static int ad7192_probe(struct spi_device *spi)
|
|
{
|
|
const struct ad7192_platform_data *pdata = dev_get_platdata(&spi->dev);
|
|
struct ad7192_state *st;
|
|
struct iio_dev *indio_dev;
|
|
int ret, voltage_uv = 0;
|
|
|
|
if (!pdata) {
|
|
dev_err(&spi->dev, "no platform data?\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (!spi->irq) {
|
|
dev_err(&spi->dev, "no IRQ?\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
|
|
if (!indio_dev)
|
|
return -ENOMEM;
|
|
|
|
st = iio_priv(indio_dev);
|
|
|
|
st->avdd = devm_regulator_get(&spi->dev, "avdd");
|
|
if (IS_ERR(st->avdd))
|
|
return PTR_ERR(st->avdd);
|
|
|
|
ret = regulator_enable(st->avdd);
|
|
if (ret) {
|
|
dev_err(&spi->dev, "Failed to enable specified AVdd supply\n");
|
|
return ret;
|
|
}
|
|
|
|
st->dvdd = devm_regulator_get(&spi->dev, "dvdd");
|
|
if (IS_ERR(st->dvdd)) {
|
|
ret = PTR_ERR(st->dvdd);
|
|
goto error_disable_avdd;
|
|
}
|
|
|
|
ret = regulator_enable(st->dvdd);
|
|
if (ret) {
|
|
dev_err(&spi->dev, "Failed to enable specified DVdd supply\n");
|
|
goto error_disable_avdd;
|
|
}
|
|
|
|
voltage_uv = regulator_get_voltage(st->avdd);
|
|
|
|
if (pdata->vref_mv)
|
|
st->int_vref_mv = pdata->vref_mv;
|
|
else if (voltage_uv)
|
|
st->int_vref_mv = voltage_uv / 1000;
|
|
else
|
|
dev_warn(&spi->dev, "reference voltage undefined\n");
|
|
|
|
spi_set_drvdata(spi, indio_dev);
|
|
st->devid = spi_get_device_id(spi)->driver_data;
|
|
indio_dev->dev.parent = &spi->dev;
|
|
indio_dev->name = spi_get_device_id(spi)->name;
|
|
indio_dev->modes = INDIO_DIRECT_MODE;
|
|
|
|
switch (st->devid) {
|
|
case ID_AD7193:
|
|
indio_dev->channels = ad7193_channels;
|
|
indio_dev->num_channels = ARRAY_SIZE(ad7193_channels);
|
|
break;
|
|
default:
|
|
indio_dev->channels = ad7192_channels;
|
|
indio_dev->num_channels = ARRAY_SIZE(ad7192_channels);
|
|
break;
|
|
}
|
|
|
|
if (st->devid == ID_AD7195)
|
|
indio_dev->info = &ad7195_info;
|
|
else
|
|
indio_dev->info = &ad7192_info;
|
|
|
|
ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info);
|
|
|
|
ret = ad_sd_setup_buffer_and_trigger(indio_dev);
|
|
if (ret)
|
|
goto error_disable_dvdd;
|
|
|
|
ret = ad7192_setup(st, pdata);
|
|
if (ret)
|
|
goto error_remove_trigger;
|
|
|
|
ret = iio_device_register(indio_dev);
|
|
if (ret < 0)
|
|
goto error_remove_trigger;
|
|
return 0;
|
|
|
|
error_remove_trigger:
|
|
ad_sd_cleanup_buffer_and_trigger(indio_dev);
|
|
error_disable_dvdd:
|
|
regulator_disable(st->dvdd);
|
|
error_disable_avdd:
|
|
regulator_disable(st->avdd);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int ad7192_remove(struct spi_device *spi)
|
|
{
|
|
struct iio_dev *indio_dev = spi_get_drvdata(spi);
|
|
struct ad7192_state *st = iio_priv(indio_dev);
|
|
|
|
iio_device_unregister(indio_dev);
|
|
ad_sd_cleanup_buffer_and_trigger(indio_dev);
|
|
|
|
regulator_disable(st->dvdd);
|
|
regulator_disable(st->avdd);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct spi_device_id ad7192_id[] = {
|
|
{"ad7190", ID_AD7190},
|
|
{"ad7192", ID_AD7192},
|
|
{"ad7193", ID_AD7193},
|
|
{"ad7195", ID_AD7195},
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(spi, ad7192_id);
|
|
|
|
static struct spi_driver ad7192_driver = {
|
|
.driver = {
|
|
.name = "ad7192",
|
|
},
|
|
.probe = ad7192_probe,
|
|
.remove = ad7192_remove,
|
|
.id_table = ad7192_id,
|
|
};
|
|
module_spi_driver(ad7192_driver);
|
|
|
|
MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
|
|
MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7193, AD7195 ADC");
|
|
MODULE_LICENSE("GPL v2");
|