204 lines
6.0 KiB
C
Executable File
204 lines
6.0 KiB
C
Executable File
/*
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* Copyright (C) 2012-2017 ARM Limited or its affiliates.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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/* \file ssi_driver.h
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* ARM CryptoCell Linux Crypto Driver
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*/
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#ifndef __SSI_DRIVER_H__
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#define __SSI_DRIVER_H__
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#include "ssi_config.h"
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#ifdef COMP_IN_WQ
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#include <linux/workqueue.h>
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#else
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#include <linux/interrupt.h>
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#endif
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#include <linux/dma-mapping.h>
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#include <crypto/algapi.h>
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#include <crypto/internal/skcipher.h>
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#include <crypto/aes.h>
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#include <crypto/sha.h>
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#include <crypto/aead.h>
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#include <crypto/authenc.h>
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#include <crypto/hash.h>
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#include <linux/version.h>
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#include <linux/clk.h>
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/* Registers definitions from shared/hw/ree_include */
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#include "dx_reg_base_host.h"
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#include "dx_host.h"
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#include "cc_regs.h"
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#include "dx_reg_common.h"
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#include "cc_hal.h"
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#define CC_SUPPORT_SHA DX_DEV_SHA_MAX
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#include "cc_crypto_ctx.h"
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#include "ssi_sysfs.h"
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#include "hash_defs.h"
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#include "cc_hw_queue_defs.h"
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#include "ssi_sram_mgr.h"
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#define DRV_MODULE_VERSION "3.0"
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#define SSI_DEV_NAME_STR "cc715ree"
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#define CC_COHERENT_CACHE_PARAMS 0xEEE
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#define SSI_CC_HAS_AES_CCM 1
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#define SSI_CC_HAS_AES_GCM 1
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#define SSI_CC_HAS_AES_XTS 1
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#define SSI_CC_HAS_AES_ESSIV 1
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#define SSI_CC_HAS_AES_BITLOCKER 1
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#define SSI_CC_HAS_AES_CTS 1
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#define SSI_CC_HAS_MULTI2 0
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#define SSI_CC_HAS_CMAC 1
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#define SSI_AXI_IRQ_MASK ((1 << DX_AXIM_CFG_BRESPMASK_BIT_SHIFT) | (1 << DX_AXIM_CFG_RRESPMASK_BIT_SHIFT) | \
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(1 << DX_AXIM_CFG_INFLTMASK_BIT_SHIFT) | (1 << DX_AXIM_CFG_COMPMASK_BIT_SHIFT))
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#define SSI_AXI_ERR_IRQ_MASK (1 << DX_HOST_IRR_AXI_ERR_INT_BIT_SHIFT)
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#define SSI_COMP_IRQ_MASK (1 << DX_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT)
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/* TEE FIPS status interrupt */
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#define SSI_GPR0_IRQ_MASK (1 << DX_HOST_IRR_GPR0_BIT_SHIFT)
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#define SSI_CRA_PRIO 3000
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#define MIN_HW_QUEUE_SIZE 50 /* Minimum size required for proper function */
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#define MAX_REQUEST_QUEUE_SIZE 4096
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#define MAX_MLLI_BUFF_SIZE 2080
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#define MAX_ICV_NENTS_SUPPORTED 2
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/* Definitions for HW descriptors DIN/DOUT fields */
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#define NS_BIT 1
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#define AXI_ID 0
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/* AXI_ID is not actually the AXI ID of the transaction but the value of AXI_ID
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* field in the HW descriptor. The DMA engine +8 that value.
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*/
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/* Logging macros */
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#define SSI_LOG(level, format, ...) \
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printk(level "cc715ree::%s: " format, __func__, ##__VA_ARGS__)
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#define SSI_LOG_ERR(format, ...) SSI_LOG(KERN_ERR, format, ##__VA_ARGS__)
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#define SSI_LOG_WARNING(format, ...) SSI_LOG(KERN_WARNING, format, ##__VA_ARGS__)
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#define SSI_LOG_NOTICE(format, ...) SSI_LOG(KERN_NOTICE, format, ##__VA_ARGS__)
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#define SSI_LOG_INFO(format, ...) SSI_LOG(KERN_INFO, format, ##__VA_ARGS__)
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#ifdef CC_DEBUG
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#define SSI_LOG_DEBUG(format, ...) SSI_LOG(KERN_DEBUG, format, ##__VA_ARGS__)
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#else /* Debug log messages are removed at compile time for non-DEBUG config. */
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#define SSI_LOG_DEBUG(format, ...) do {} while (0)
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#endif
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#define MIN(a, b) (((a) < (b)) ? (a) : (b))
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#define MAX(a, b) (((a) > (b)) ? (a) : (b))
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#define SSI_MAX_IVGEN_DMA_ADDRESSES 3
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struct ssi_crypto_req {
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void (*user_cb)(struct device *dev, void *req, void __iomem *cc_base);
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void *user_arg;
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dma_addr_t ivgen_dma_addr[SSI_MAX_IVGEN_DMA_ADDRESSES];
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/* For the first 'ivgen_dma_addr_len' addresses of this array,
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* generated IV would be placed in it by send_request().
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* Same generated IV for all addresses!
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*/
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unsigned int ivgen_dma_addr_len; /* Amount of 'ivgen_dma_addr' elements to be filled. */
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unsigned int ivgen_size; /* The generated IV size required, 8/16 B allowed. */
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struct completion seq_compl; /* request completion */
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};
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/**
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* struct ssi_drvdata - driver private data context
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* @cc_base: virt address of the CC registers
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* @irq: device IRQ number
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* @irq_mask: Interrupt mask shadow (1 for masked interrupts)
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* @fw_ver: SeP loaded firmware version
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*/
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struct ssi_drvdata {
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struct resource *res_mem;
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struct resource *res_irq;
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void __iomem *cc_base;
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unsigned int irq;
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u32 irq_mask;
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u32 fw_ver;
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/* Calibration time of start/stop
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* monitor descriptors
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*/
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u32 monitor_null_cycles;
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struct platform_device *plat_dev;
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ssi_sram_addr_t mlli_sram_addr;
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struct completion icache_setup_completion;
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void *buff_mgr_handle;
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void *hash_handle;
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void *aead_handle;
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void *blkcipher_handle;
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void *request_mgr_handle;
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void *fips_handle;
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void *ivgen_handle;
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void *sram_mgr_handle;
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u32 inflight_counter;
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struct clk *clk;
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bool coherent;
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};
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struct ssi_crypto_alg {
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struct list_head entry;
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int cipher_mode;
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int flow_mode; /* Note: currently, refers to the cipher mode only. */
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int auth_mode;
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struct ssi_drvdata *drvdata;
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struct crypto_alg crypto_alg;
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struct aead_alg aead_alg;
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};
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struct ssi_alg_template {
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char name[CRYPTO_MAX_ALG_NAME];
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char driver_name[CRYPTO_MAX_ALG_NAME];
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unsigned int blocksize;
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u32 type;
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union {
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struct ablkcipher_alg ablkcipher;
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struct aead_alg aead;
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struct blkcipher_alg blkcipher;
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struct cipher_alg cipher;
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struct compress_alg compress;
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} template_u;
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int cipher_mode;
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int flow_mode; /* Note: currently, refers to the cipher mode only. */
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int auth_mode;
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struct ssi_drvdata *drvdata;
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};
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struct async_gen_req_ctx {
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dma_addr_t iv_dma_addr;
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enum drv_crypto_direction op_type;
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};
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#ifdef DX_DUMP_BYTES
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void dump_byte_array(const char *name, const u8 *the_array, unsigned long size);
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#else
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#define dump_byte_array(name, array, size) do { \
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} while (0);
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#endif
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int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe);
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void fini_cc_regs(struct ssi_drvdata *drvdata);
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int cc_clk_on(struct ssi_drvdata *drvdata);
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void cc_clk_off(struct ssi_drvdata *drvdata);
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#endif /*__SSI_DRIVER_H__*/
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