715 lines
17 KiB
C
Executable File
715 lines
17 KiB
C
Executable File
/*
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* linux/arch/arm/mach-exynos/exynos-coresight.c
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*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/cpu.h>
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#include <linux/cpu_pm.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/kallsyms.h>
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#include <linux/of.h>
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#include <linux/io.h>
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#include <linux/debug-snapshot.h>
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#include <asm/core_regs.h>
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#include <asm/cputype.h>
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#include <asm/smp_plat.h>
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#include <soc/samsung/exynos-pmu.h>
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#define CS_READ(base, offset) __raw_readl(base + offset)
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#define CS_READQ(base, offset) __raw_readq(base + offset)
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#define CS_WRITE(val, base, offset) __raw_writel(val, base + offset)
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#define SYS_READ(reg, val) asm volatile("mrs %0, " #reg : "=r" (val))
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#define SYS_WRITE(reg, val) asm volatile("msr " #reg ", %0" :: "r" (val))
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#define DBG_UNLOCK(base) \
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do { isb(); __raw_writel(OSLOCK_MAGIC, base + DBGLAR); }while(0)
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#define DBG_LOCK(base) \
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do { __raw_writel(0x1, base + DBGLAR); isb(); }while(0)
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#define DBG_REG_MAX_SIZE (8)
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#define DBG_BW_REG_MAX_SIZE (30)
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#define OS_LOCK_FLAG (DBG_REG_MAX_SIZE - 1)
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#define ITERATION CONFIG_PC_ITERATION
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#define CORE_CNT CONFIG_NR_CPUS
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#define MAX_CPU (8)
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#define MSB_PADDING (0xFFFFFF0000000000)
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#define MSB_MASKING (0x0000FF0000000000)
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#define MIDR_ARCH_MASK (0xfffff)
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struct cs_dbg_cpu {
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void __iomem *base;
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ssize_t reg[DBG_REG_MAX_SIZE];
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};
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struct cs_dbg {
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u32 arch;
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u8 nr_wp;
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u8 nr_bp;
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ssize_t bw_reg[DBG_BW_REG_MAX_SIZE];
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struct cs_dbg_cpu cpu[MAX_CPU];
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};
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bool FLAG_T32_EN = false;
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static struct cs_dbg dbg;
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extern struct atomic_notifier_head hardlockup_notifier_list;
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static inline void get_arm_arch_version(int cpu)
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{
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dbg.arch = CS_READ(dbg.cpu[0].base, MIDR);
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dbg.arch = dbg.arch & MIDR_ARCH_MASK;
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}
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static inline void dbg_os_lock(void __iomem *base)
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{
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switch (dbg.arch) {
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case ARMV8_PROCESSOR:
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CS_WRITE(0x1, base, DBGOSLAR);
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break;
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default:
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break;
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}
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isb();
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}
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static inline void dbg_os_unlock(void __iomem *base)
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{
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isb();
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switch (dbg.arch) {
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case ARMV8_PROCESSOR:
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CS_WRITE(0x0, base, DBGOSLAR);
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break;
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default:
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break;
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}
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}
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#ifdef CONFIG_EXYNOS_CORESIGHT_PC_INFO
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struct exynos_cs_pcsr {
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unsigned long pc;
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int ns;
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int el;
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};
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static struct exynos_cs_pcsr exynos_cs_pc[CORE_CNT][ITERATION];
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static inline u32 linear_phycpu(unsigned int cpu)
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{
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u32 mpidr = cpu_logical_map(cpu);
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unsigned int lvl = (mpidr & MPIDR_MT_BITMASK) ? 1 : 0;
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return ((MPIDR_AFFINITY_LEVEL(mpidr, (1 + lvl)) << 2)
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| MPIDR_AFFINITY_LEVEL(mpidr, lvl));
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}
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static inline int exynos_cs_get_cpu_part_num(int cpu)
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{
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u32 midr = CS_READ(dbg.cpu[cpu].base, MIDR);
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return MIDR_PARTNUM(midr);
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}
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static inline bool have_pc_offset(void __iomem *base)
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{
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return !(CS_READ(base, DBGDEVID1) & 0xf);
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}
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static int exynos_cs_unlock(int unlock)
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{
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void __iomem *base;
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int cpu;
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for (cpu = 4; cpu <= 7; cpu++) {
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base = dbg.cpu[cpu].base;
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#ifdef CONFIG_EXYNOS_PMU
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if (!exynos_cpu.power_state(cpu))
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continue;
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#endif
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if (unlock) {
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do {
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DBG_UNLOCK(base);
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isb();
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} while (readl(base + DBGLSR) != 0x1);
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do {
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dbg_os_unlock(base);
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isb();
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} while ((readl(base + DBGOSLSR) & 0x2) != 0x0);
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} else {
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dbg_os_lock(base);
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DBG_LOCK(base);
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}
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}
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return 0;
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}
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static int exynos_cs_get_pc(int cpu, int iter)
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{
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void __iomem *base = dbg.cpu[cpu].base;
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unsigned long val = 0, valHi = 0;
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int ns = -1, el = -1;
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if (!base)
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return -ENOMEM;
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switch (exynos_cs_get_cpu_part_num(cpu)) {
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case ARM_CPU_PART_MEERKAT:
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val = CS_READ(base, DBGPCSRlo);
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valHi = CS_READ(base, DBGPCSRhi);
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val |= (valHi << 32L);
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if (have_pc_offset(base))
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val -= 0x8;
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if (MSB_MASKING == (MSB_MASKING & val))
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val |= MSB_PADDING;
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break;
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case ARM_CPU_PART_MONGOOSE:
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case ARM_CPU_PART_CORTEX_A53:
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case ARM_CPU_PART_CORTEX_A57:
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case ARM_CPU_PART_CORTEX_A73:
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DBG_UNLOCK(base);
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dbg_os_unlock(base);
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val = CS_READ(base, DBGPCSRlo);
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valHi = CS_READ(base, DBGPCSRhi);
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val |= (valHi << 32L);
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if (have_pc_offset(base))
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val -= 0x8;
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if (MSB_MASKING == (MSB_MASKING & val))
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val |= MSB_PADDING;
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dbg_os_lock(base);
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DBG_LOCK(base);
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break;
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case ARM_CPU_PART_ANANKE:
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val = CS_READ(base + PMU_OFFSET, PMUPCSRlo);
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valHi = CS_READ(base + PMU_OFFSET, PMUPCSRhi);
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ns = (valHi >> 31L) & 0x1;
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el = (valHi >> 29L) & 0x3;
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val |= (valHi << 32L);
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if (MSB_MASKING == (MSB_MASKING & val))
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val |= MSB_PADDING;
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break;
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default:
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break;
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}
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exynos_cs_pc[cpu][iter].pc = val;
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exynos_cs_pc[cpu][iter].ns = ns;
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exynos_cs_pc[cpu][iter].el = el;
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return 0;
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}
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static int exynos_cs_lockup_handler(struct notifier_block *nb,
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unsigned long l, void *core)
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{
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unsigned long val, iter;
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char buf[KSYM_SYMBOL_LEN];
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unsigned int *cpu = (unsigned int *)core;
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pr_err("CPU[%d] saved pc value\n", *cpu);
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/* If big cluster is Meerkat */
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if (exynos_cs_get_cpu_part_num(*cpu) == ARM_CPU_PART_MEERKAT)
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exynos_cs_unlock(true);
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for (iter = 0; iter < ITERATION; iter++) {
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#ifdef CONFIG_EXYNOS_PMU
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if (!exynos_cpu.power_state(*cpu))
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continue;
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#endif
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val = exynos_cs_get_pc(*cpu, iter);
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if (val < 0)
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continue;
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val = exynos_cs_pc[*cpu][iter].pc;
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sprint_symbol(buf, val);
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pr_err(" 0x%016zx : %s\n", val, buf);
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}
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return 0;
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}
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static int exynos_cs_panic_handler(struct notifier_block *np,
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unsigned long l, void *msg)
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{
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unsigned long flags, val;
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unsigned int cpu, iter;
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char buf[KSYM_SYMBOL_LEN];
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if (num_online_cpus() <= 1)
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return 0;
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local_irq_save(flags);
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/* If big cluster is Meerkat */
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if (exynos_cs_get_cpu_part_num(4) == ARM_CPU_PART_MEERKAT)
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exynos_cs_unlock(true);
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for (iter = 0; iter < ITERATION; iter++) {
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for (cpu = 0; cpu < CORE_CNT; cpu++) {
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exynos_cs_pc[cpu][iter].pc = 0;
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#ifdef CONFIG_EXYNOS_PMU
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if (!exynos_cpu.power_state(cpu))
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continue;
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#endif
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if (exynos_cs_get_pc(cpu, iter) < 0)
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continue;
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}
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}
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local_irq_restore(flags);
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for (cpu = 0; cpu < CORE_CNT; cpu++) {
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pr_err("CPU[%d] saved pc value\n", cpu);
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for (iter = 0; iter < ITERATION; iter++) {
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val = exynos_cs_pc[cpu][iter].pc;
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if (!val)
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continue;
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sprint_symbol(buf, val);
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pr_err(" 0x%016zx : %s\n", val, buf);
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}
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}
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return 0;
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}
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static struct notifier_block exynos_cs_lockup_nb = {
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.notifier_call = exynos_cs_lockup_handler,
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};
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static struct notifier_block exynos_cs_panic_nb = {
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.notifier_call = exynos_cs_panic_handler,
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};
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#endif
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#ifdef CONFIG_EXYNOS_CORESIGHT_MAINTAIN_DBG_REG
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static DEFINE_SPINLOCK(debug_lock);
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/* save debug resgisters when suspending */
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static void debug_save_bw_reg(int cpu)
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{
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int i, idx = 0;
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pr_debug("%s: cpu %d\n", __func__, cpu);
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for (i = 0; i < CORE_CNT; i++) {
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if (!dbg.cpu[i].reg[OS_LOCK_FLAG])
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return;
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}
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switch (dbg.arch) {
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case DEBUG_ARCH_V8:
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SYS_READ(DBGBVR0_EL1, dbg.bw_reg[idx++]); /* DBGBVR */
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SYS_READ(DBGBVR1_EL1, dbg.bw_reg[idx++]);
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SYS_READ(DBGBVR2_EL1, dbg.bw_reg[idx++]);
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SYS_READ(DBGBVR3_EL1, dbg.bw_reg[idx++]);
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SYS_READ(DBGBVR4_EL1, dbg.bw_reg[idx++]);
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SYS_READ(DBGBVR5_EL1, dbg.bw_reg[idx++]);
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SYS_READ(DBGBCR0_EL1, dbg.bw_reg[idx++]); /* DBGDCR */
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SYS_READ(DBGBCR1_EL1, dbg.bw_reg[idx++]);
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SYS_READ(DBGBCR2_EL1, dbg.bw_reg[idx++]);
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SYS_READ(DBGBCR3_EL1, dbg.bw_reg[idx++]);
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SYS_READ(DBGBCR4_EL1, dbg.bw_reg[idx++]);
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SYS_READ(DBGBCR5_EL1, dbg.bw_reg[idx++]);
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SYS_READ(DBGWVR0_EL1, dbg.bw_reg[idx++]); /* DBGWVR */
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SYS_READ(DBGWVR1_EL1, dbg.bw_reg[idx++]);
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SYS_READ(DBGWVR2_EL1, dbg.bw_reg[idx++]);
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SYS_READ(DBGWVR3_EL1, dbg.bw_reg[idx++]);
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SYS_READ(DBGWCR0_EL1, dbg.bw_reg[idx++]); /* DBGDCR */
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SYS_READ(DBGWCR1_EL1, dbg.bw_reg[idx++]);
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SYS_READ(DBGWCR2_EL1, dbg.bw_reg[idx++]);
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SYS_READ(DBGWCR3_EL1, dbg.bw_reg[idx++]);
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break;
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default:
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break;
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}
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}
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static void debug_suspend_cpu(int cpu)
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{
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int idx = 0;
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struct cs_dbg_cpu *cpudata = &dbg.cpu[cpu];
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void __iomem *base = cpudata->base;
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pr_debug("%s: cpu %d\n", __func__, cpu);
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if (!FLAG_T32_EN)
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return;
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DBG_UNLOCK(base);
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spin_lock(&debug_lock);
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dbg_os_lock(base);
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cpudata->reg[OS_LOCK_FLAG] = 1;
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debug_save_bw_reg(cpu);
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spin_unlock(&debug_lock);
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switch (dbg.arch) {
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case DEBUG_ARCH_V8:
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SYS_READ(MDSCR_EL1, cpudata->reg[idx++]); /* DBGDSCR */
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SYS_READ(OSECCR_EL1, cpudata->reg[idx++]); /* DBGECCR */
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SYS_READ(DBGDTRTX_EL0, cpudata->reg[idx++]); /* DBGDTRTX */
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SYS_READ(DBGDTRRX_EL0, cpudata->reg[idx++]); /* DBGDTRRX */
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SYS_READ(DBGCLAIMCLR_EL1, cpudata->reg[idx++]); /* DBGCLAIMCLR */
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break;
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default:
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break;
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}
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DBG_LOCK(base);
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pr_debug("%s: cpu %d done\n", __func__, cpu);
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}
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/* restore debug registers when resuming */
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static void debug_restore_bw_reg(int cpu)
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{
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int core = 0, idx = 0;
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struct cs_dbg_cpu *cpudata = &dbg.cpu[cpu];
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void __iomem *a_base = NULL;
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pr_debug("%s: cpu %d\n", __func__, cpu);
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/* If debugger is not connected, do not accecs some registers. */
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if (!(cpudata->reg[0] & (1<<14))) {
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return;
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}
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for (core = 0; core < CORE_CNT; core++) {
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if (!dbg.cpu[core].reg[OS_LOCK_FLAG]) {
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a_base = dbg.cpu[core].base;
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break;
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}
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}
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switch (dbg.arch) {
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case DEBUG_ARCH_V8:
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if (core < CORE_CNT) {
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SYS_WRITE(DBGBVR0_EL1, CS_READQ(a_base, DBGBVRn(0)));
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SYS_WRITE(DBGBVR1_EL1, CS_READQ(a_base, DBGBVRn(1)));
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SYS_WRITE(DBGBVR2_EL1, CS_READQ(a_base, DBGBVRn(2)));
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SYS_WRITE(DBGBVR3_EL1, CS_READQ(a_base, DBGBVRn(3)));
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SYS_WRITE(DBGBVR4_EL1, CS_READQ(a_base, DBGBVRn(4)));
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SYS_WRITE(DBGBVR5_EL1, CS_READQ(a_base, DBGBVRn(5)));
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SYS_WRITE(DBGBCR0_EL1, CS_READ(a_base, DBGBCRn(0)));
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SYS_WRITE(DBGBCR1_EL1, CS_READ(a_base, DBGBCRn(1)));
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SYS_WRITE(DBGBCR2_EL1, CS_READ(a_base, DBGBCRn(2)));
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SYS_WRITE(DBGBCR3_EL1, CS_READ(a_base, DBGBCRn(3)));
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SYS_WRITE(DBGBCR4_EL1, CS_READ(a_base, DBGBCRn(4)));
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SYS_WRITE(DBGBCR5_EL1, CS_READ(a_base, DBGBCRn(5)));
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SYS_WRITE(DBGWVR0_EL1, CS_READQ(a_base, DBGWVRn(0)));
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SYS_WRITE(DBGWVR1_EL1, CS_READQ(a_base, DBGWVRn(1)));
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SYS_WRITE(DBGWVR2_EL1, CS_READQ(a_base, DBGWVRn(2)));
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SYS_WRITE(DBGWVR3_EL1, CS_READQ(a_base, DBGWVRn(3)));
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SYS_WRITE(DBGWCR0_EL1, CS_READ(a_base, DBGWCRn(0)));
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SYS_WRITE(DBGWCR1_EL1, CS_READ(a_base, DBGWCRn(1)));
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SYS_WRITE(DBGWCR2_EL1, CS_READ(a_base, DBGWCRn(2)));
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SYS_WRITE(DBGWCR3_EL1, CS_READ(a_base, DBGWCRn(3)));
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} else {
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SYS_WRITE(DBGBVR0_EL1, dbg.bw_reg[idx++]);
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SYS_WRITE(DBGBVR1_EL1, dbg.bw_reg[idx++]);
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SYS_WRITE(DBGBVR2_EL1, dbg.bw_reg[idx++]);
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SYS_WRITE(DBGBVR3_EL1, dbg.bw_reg[idx++]);
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SYS_WRITE(DBGBVR4_EL1, dbg.bw_reg[idx++]);
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SYS_WRITE(DBGBVR5_EL1, dbg.bw_reg[idx++]);
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SYS_WRITE(DBGBCR0_EL1, dbg.bw_reg[idx++]);
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SYS_WRITE(DBGBCR1_EL1, dbg.bw_reg[idx++]);
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SYS_WRITE(DBGBCR2_EL1, dbg.bw_reg[idx++]);
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SYS_WRITE(DBGBCR3_EL1, dbg.bw_reg[idx++]);
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SYS_WRITE(DBGBCR4_EL1, dbg.bw_reg[idx++]);
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SYS_WRITE(DBGBCR5_EL1, dbg.bw_reg[idx++]);
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SYS_WRITE(DBGWVR0_EL1, dbg.bw_reg[idx++]);
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SYS_WRITE(DBGWVR1_EL1, dbg.bw_reg[idx++]);
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SYS_WRITE(DBGWVR2_EL1, dbg.bw_reg[idx++]);
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SYS_WRITE(DBGWVR3_EL1, dbg.bw_reg[idx++]);
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SYS_WRITE(DBGWCR0_EL1, dbg.bw_reg[idx++]);
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SYS_WRITE(DBGWCR1_EL1, dbg.bw_reg[idx++]);
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SYS_WRITE(DBGWCR2_EL1, dbg.bw_reg[idx++]);
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SYS_WRITE(DBGWCR3_EL1, dbg.bw_reg[idx++]);
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}
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break;
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default:
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break;
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}
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pr_debug("%s: cpu %d\n", __func__, cpu);
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}
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static void debug_resume_cpu(int cpu)
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{
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int idx = 0;
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struct cs_dbg_cpu *cpudata = &dbg.cpu[cpu];
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void __iomem *base = cpudata->base;
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pr_debug("%s: cpu %d\n", __func__, cpu);
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if (!FLAG_T32_EN && !cpudata->reg[OS_LOCK_FLAG])
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return;
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DBG_UNLOCK(base);
|
|
dbg_os_lock(base);
|
|
|
|
switch (dbg.arch) {
|
|
case DEBUG_ARCH_V8:
|
|
SYS_WRITE(MDSCR_EL1, cpudata->reg[idx++]); /* DBGDSCR */
|
|
SYS_WRITE(OSECCR_EL1, cpudata->reg[idx++]); /* DBGECCR */
|
|
SYS_WRITE(DBGDTRTX_EL0, cpudata->reg[idx++]); /* DBGDTRTX */
|
|
SYS_WRITE(DBGDTRRX_EL0, cpudata->reg[idx++]); /* DBGDTRRX */
|
|
SYS_WRITE(DBGCLAIMSET_EL1, cpudata->reg[idx++]); /* DBGCLAIMSET */
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
spin_lock(&debug_lock);
|
|
debug_restore_bw_reg(cpu);
|
|
dbg_os_unlock(base);
|
|
cpudata->reg[OS_LOCK_FLAG] = 0;
|
|
spin_unlock(&debug_lock);
|
|
DBG_LOCK(base);
|
|
|
|
pr_debug("%s: %d done\n", __func__, cpu);
|
|
}
|
|
|
|
static inline bool dbg_arch_supported(u8 arch)
|
|
{
|
|
switch (arch) {
|
|
case DEBUG_ARCH_V8:
|
|
break;
|
|
default:
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
static inline void get_dbg_arch_info(void)
|
|
{
|
|
u32 dbgdidr = CS_READ(dbg.cpu[0].base, ID_AA64DFR0_EL1);
|
|
|
|
dbg.arch = dbgdidr & 0xf;
|
|
dbg.nr_bp = ((dbgdidr >> 12) & 0xf) + 1;
|
|
dbg.nr_wp = ((dbgdidr >> 20) & 0xf) + 1;
|
|
}
|
|
|
|
static int exynos_cs_pm_notifier(struct notifier_block *self,
|
|
unsigned long cmd, void *v)
|
|
{
|
|
int cpu = raw_smp_processor_id();
|
|
|
|
switch (cmd) {
|
|
case CPU_PM_ENTER:
|
|
debug_suspend_cpu(cpu);
|
|
break;
|
|
case CPU_PM_ENTER_FAILED:
|
|
case CPU_PM_EXIT:
|
|
debug_resume_cpu(cpu);
|
|
break;
|
|
case CPU_CLUSTER_PM_ENTER:
|
|
break;
|
|
case CPU_CLUSTER_PM_ENTER_FAILED:
|
|
case CPU_CLUSTER_PM_EXIT:
|
|
break;
|
|
}
|
|
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static int __cpuinit exynos_cs_cpu_notifier(struct notifier_block *nfb,
|
|
unsigned long action, void *hcpu)
|
|
{
|
|
int cpu = (unsigned long)hcpu;
|
|
|
|
switch (action & ~CPU_TASKS_FROZEN) {
|
|
case CPU_STARTING:
|
|
case CPU_DOWN_FAILED:
|
|
debug_resume_cpu(cpu);
|
|
break;
|
|
case CPU_DYING:
|
|
debug_suspend_cpu(cpu);
|
|
break;
|
|
}
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static struct notifier_block __cpuinitdata exynos_cs_pm_notifier_block = {
|
|
.notifier_call = exynos_cs_pm_notifier,
|
|
};
|
|
|
|
static struct notifier_block __cpuinitdata exynos_cs_cpu_notifier_block = {
|
|
.notifier_call = exynos_cs_cpu_notifier,
|
|
};
|
|
|
|
static int __init exynos_cs_debug_init(void)
|
|
{
|
|
int ret = 0;
|
|
|
|
get_dbg_arch_info();
|
|
if (!dbg_arch_supported(dbg.arch)) {
|
|
pr_err("%s: DBG archtecture is not supported.\n", __func__);
|
|
ret = -EPERM;
|
|
goto err;
|
|
}
|
|
|
|
ret = cpu_pm_register_notifier(&exynos_cs_pm_notifier_block);
|
|
if (ret < 0)
|
|
goto err;
|
|
|
|
ret = register_cpu_notifier(&exynos_cs_cpu_notifier_block);
|
|
if (ret < 0)
|
|
goto err;
|
|
|
|
pr_info("exynos-coresight debug enable: arch: %x:%d bp:%d, wp:%d\n",
|
|
dbg.arch, dbg.arch, dbg.nr_bp, dbg.nr_wp);
|
|
err:
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
static const struct of_device_id of_exynos_cs_matches[] __initconst= {
|
|
{.compatible = "exynos,coresight"},
|
|
{},
|
|
};
|
|
|
|
static int exynos_cs_init_dt(void)
|
|
{
|
|
struct device_node *np = NULL;
|
|
unsigned int offset, sj_offset, val, cs_reg_base;
|
|
int ret = 0, i = 0, cpu;
|
|
void __iomem *sj_base;
|
|
|
|
np = of_find_matching_node(NULL, of_exynos_cs_matches);
|
|
|
|
if (of_property_read_u32(np, "base", &cs_reg_base))
|
|
return -EINVAL;
|
|
|
|
if (of_property_read_u32(np, "sj-offset", &sj_offset))
|
|
sj_offset = CS_SJTAG_OFFSET;
|
|
|
|
sj_base = ioremap(cs_reg_base + sj_offset, SZ_8);
|
|
if (!sj_base) {
|
|
pr_err("%s: Failed ioremap sj-offset.\n", __func__);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
val = __raw_readl(sj_base + SJTAG_STATUS);
|
|
iounmap(sj_base);
|
|
|
|
if (val & SJTAG_SOFT_LOCK)
|
|
return -EIO;
|
|
|
|
if (dbg_snapshot_get_sjtag_status() == true)
|
|
return -EIO;
|
|
|
|
while ((np = of_find_node_by_type(np, "cs"))) {
|
|
ret = of_property_read_u32(np, "dbg-offset", &offset);
|
|
if (ret)
|
|
return -EINVAL;
|
|
cpu = linear_phycpu(i);
|
|
dbg.cpu[cpu].base = ioremap(cs_reg_base + offset, SZ_256K);
|
|
if (!dbg.cpu[cpu].base) {
|
|
pr_err("%s: Failed ioremap (%d).\n", __func__, i);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
i++;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int __init exynos_cs_init(void)
|
|
{
|
|
int ret = 0;
|
|
|
|
ret = exynos_cs_init_dt();
|
|
if (ret < 0) {
|
|
pr_info("[Exynos Coresight] Failed get DT(%d).\n", ret);
|
|
goto err;
|
|
}
|
|
|
|
get_arm_arch_version(0);
|
|
|
|
#ifdef CONFIG_EXYNOS_CORESIGHT_PC_INFO
|
|
atomic_notifier_chain_register(&hardlockup_notifier_list,
|
|
&exynos_cs_lockup_nb);
|
|
atomic_notifier_chain_register(&panic_notifier_list,
|
|
&exynos_cs_panic_nb);
|
|
pr_info("[Exynos Coresight] Success Init.\n");
|
|
#endif
|
|
#ifdef CONFIG_EXYNOS_CORESIGHT_MAINTAIN_DBG_REG
|
|
ret = exynos_cs_debug_init();
|
|
if (ret < 0)
|
|
goto err;
|
|
#endif
|
|
err:
|
|
return ret;
|
|
}
|
|
subsys_initcall(exynos_cs_init);
|
|
|
|
static struct bus_type ecs_subsys = {
|
|
.name = "exynos-cs",
|
|
.dev_name = "exynos-cs",
|
|
};
|
|
|
|
static ssize_t ecs_enable_show(struct kobject *kobj,
|
|
struct kobj_attribute *attr, char *buf)
|
|
{
|
|
return scnprintf(buf, 10, "%sable\n", FLAG_T32_EN ? "en" : "dis");
|
|
}
|
|
|
|
static ssize_t ecs_enable_store(struct kobject *kobj,
|
|
struct kobj_attribute *attr,
|
|
const char *buf, size_t count)
|
|
{
|
|
int en;
|
|
|
|
if( sscanf(buf, "%1d", &en) != 1)
|
|
return -EINVAL;
|
|
|
|
if (en)
|
|
FLAG_T32_EN = true;
|
|
else
|
|
FLAG_T32_EN = false;
|
|
|
|
return count;
|
|
}
|
|
|
|
static struct kobj_attribute ecs_enable_attr =
|
|
__ATTR(enabled, 0644, ecs_enable_show, ecs_enable_store);
|
|
|
|
static struct attribute *ecs_sysfs_attrs[] = {
|
|
&ecs_enable_attr.attr,
|
|
NULL,
|
|
};
|
|
|
|
static struct attribute_group ecs_sysfs_group = {
|
|
.attrs = ecs_sysfs_attrs,
|
|
};
|
|
|
|
static const struct attribute_group *ecs_sysfs_groups[] = {
|
|
&ecs_sysfs_group,
|
|
NULL,
|
|
};
|
|
|
|
static int __init exynos_cs_sysfs_init(void)
|
|
{
|
|
int ret = 0;
|
|
|
|
ret = subsys_system_register(&ecs_subsys, ecs_sysfs_groups);
|
|
if (ret)
|
|
pr_err("fail to register exynos-coresight subsys\n");
|
|
|
|
return ret;
|
|
}
|
|
late_initcall(exynos_cs_sysfs_init);
|