271 lines
8.6 KiB
C
Executable File
271 lines
8.6 KiB
C
Executable File
/*
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* Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
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*
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* Copyright (C) 2012-2014 Samsung Electronics Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef _DW_MMC_EXYNOS_H_
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#define _DW_MMC_EXYNOS_H_
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#include <crypto/fmp.h>
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#define NUM_PINS(x) (x + 2)
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#define MAX_TUNING_RETRIES 7
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#define MAX_TUNING_LOOP (MAX_TUNING_RETRIES * 8 * 2)
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/* Each descriptor can transfer up to 4KB of data in chained mode */
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#define DW_MCI_DESC_DATA_LENGTH 0x1000
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/* Tuning Phase */
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#define TUNING_PHASE_0 0
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#define TUNING_PHASE_1 1
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#define TUNING_PHASE_2 2
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#define TUNING_PHASE_3 3
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#define TUNING_PHASE_4 4
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#define TUNING_PHASE_5 5
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#define TUNING_PHASE_6 6
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#define TUNING_PHASE_7 7
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#define TUNING_PHASE_8 8
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#define TUNING_PHASE_9 9
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#define TUNING_PHASE_10 10
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#define TUNING_PHASE_11 11
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#define TUNING_PHASE_12 12
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#define TUNING_PHASE_13 13
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#define TUNING_PHASE_14 14
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#define TUNING_PHASE_15 15
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/* Exynos implementation specific driver private data */
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struct dw_mci_exynos_priv_data {
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u8 ctrl_type;
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u8 ciu_div;
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u32 sdr_timing;
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u32 ddr_timing;
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u32 sdr_hs_timing;
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u32 tuned_sample;
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u32 cur_speed;
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u32 dqs_delay;
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u32 saved_dqs_en;
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u32 saved_strobe_ctrl;
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u32 hs200_timing;
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u32 hs400_timing;
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u32 hs400_ulp_timing;
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u32 hs400_tx_t_fastlimit;
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u32 hs400_tx_t_initval;
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u32 hs400_ulp_tx_t_fastlimit;
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u32 hs400_ulp_tx_t_initval;
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u32 sdr104_timing;
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u32 sdr50_timing;
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u32 *ref_clk;
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u32 delay_line;
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u32 tx_delay_line;
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struct pinctrl *pinctrl;
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u32 clk_drive_number;
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u32 clk_drive_tuning;
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struct pinctrl_state *clk_drive_base;
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struct pinctrl_state *clk_drive_str[6];
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int cd_gpio;
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int sec_sd_slot_type;
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#define SEC_NO_DET_SD_SLOT 0 /* No detect GPIO SD slot case */
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#define SEC_HOTPLUG_SD_SLOT 1 /* detect GPIO SD slot without Tray */
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#define SEC_HYBRID_SD_SLOT 2 /* detect GPIO SD slot with Tray */
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u32 caps;
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u32 ctrl_flag;
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u32 ctrl_windows;
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u32 ignore_phase;
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u32 selclk_drv;
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u32 voltage_int_extra;
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enum smu_id fmp;
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enum smu_id smu;
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#define DW_MMC_EXYNOS_BYPASS_FOR_ALL_PASS BIT(0)
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#define DW_MMC_EXYNOS_ENABLE_SHIFT BIT(1)
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};
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#define phase6_en BIT(6)
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#define phase7_en BIT(7)
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extern int dw_mci_exynos_request_status(void);
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extern void dw_mci_reg_dump(struct dw_mci *host);
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/*****************/
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/* SFR addresses */
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/*****************/
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#define SFR_OFFSET 0x0004
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/*
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* Registers to support idmac 64-bit address mode
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*/
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#define SDMMC_DBADDRL 0x0088
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#define SDMMC_DBADDRU (SDMMC_DBADDRL + SFR_OFFSET)
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#define SDMMC_IDSTS64 (SDMMC_DBADDRU + SFR_OFFSET)
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#define SDMMC_IDINTEN64 (SDMMC_IDSTS64 + SFR_OFFSET)
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#define SDMMC_DSCADDRL (SDMMC_IDINTEN64 + SFR_OFFSET)
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#define SDMMC_DSCADDRU (SDMMC_DSCADDRL + SFR_OFFSET)
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#define SDMMC_BUFADDRL (SDMMC_DSCADDRU + SFR_OFFSET)
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#define SDMMC_BUFADDRU (SDMMC_BUFADDRL + SFR_OFFSET)
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#if defined(CONFIG_MMC_DW_64BIT_DESC)
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#define SDMMC_AXI_BURST_LEN 0x00b4
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#define SDMMC_SECTOR_NUM_INC 0x01F8
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#define SDMMC_CLKSEL (SDMMC_BUFADDRU + SFR_OFFSET) /* specific to Samsung Exynos */
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#else
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#define SDMMC_CLKSEL (SDMMC_BUFADDR + SFR_OFFSET) /* specific to Samsung Exynos */
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#define SDMMC_AXI_BURST_LEN 0xffff /*not used */
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#define SDMMC_SECTOR_NUM_INC 0xffff /*not used */
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#endif
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#define SDMMC_CDTHRCTL 0x100
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#define SDMMC_DATA(x) (x)
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/* Extended Register's Offset */
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#define SDMMC_HS400_ENABLE_SHIFT 0x110
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#define SDMMC_HS400_DQS_EN 0x180
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#define SDMMC_HS400_ASYNC_FIFO_CTRL 0x184
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#define SDMMC_HS400_DLINE_CTRL 0x188
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/* Protector Register */
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#define SDMMC_EMMCP_BASE 0x0
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#define SDMMC_MPSTAT (SDMMC_EMMCP_BASE + 0x0008)
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#define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010)
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#define SDMMC_MPENCKEY (SDMMC_EMMCP_BASE + 0x0020)
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#define SDMMC_MPSBEGIN0 (SDMMC_EMMCP_BASE + 0x0200)
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#define SDMMC_MPSEND0 (SDMMC_EMMCP_BASE + 0x0204)
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#define SDMMC_MPSLUN0 (SDMMC_EMMCP_BASE + 0x0208)
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#define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C)
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#define SDMMC_MPSBEGIN1 (SDMMC_EMMCP_BASE + 0x0210)
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#define SDMMC_MPSEND1 (SDMMC_EMMCP_BASE + 0x0214)
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#define SDMMC_MPSCTRL1 (SDMMC_EMMCP_BASE + 0x021C)
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#define SDMMC_FORCE_CLK_STOP 0x0b0
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/* CLKSEL register defines */
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#define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0)
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#define SDMMC_CLKSEL_CCLK_FINE_SAMPLE(x) (((x) & 0xF) << 0)
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#define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16)
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#define SDMMC_CLKSEL_CCLK_FINE_DRIVE(x) (((x) & 3) << 22)
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#define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24)
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#define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7)
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#define SDMMC_CLKSEL_GET_DIV(x) (((x) >> 24) & 0x7)
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#define SDMMC_CLKSEL_GET_DIVRATIO(x) ((((x) >> 24) & 0x7) + 1)
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#define SDMMC_CLKSEL_UP_SAMPLE(x, y) (((x) & ~SDMMC_CLKSEL_CCLK_SAMPLE(7)) |\
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SDMMC_CLKSEL_CCLK_SAMPLE(y))
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#define SDMMC_CLKSEL_TIMING(div, f_drv, drv, sample) \
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(SDMMC_CLKSEL_CCLK_DIVIDER(div) | \
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SDMMC_CLKSEL_CCLK_FINE_DRIVE(f_drv) | \
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SDMMC_CLKSEL_CCLK_DRIVE(drv) | \
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SDMMC_CLKSEL_CCLK_SAMPLE(sample))
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#define SDMMC_CLKSEL_TIMING_MASK SDMMC_CLKSEL_TIMING(0x7, 0x7, 0x7, 0x7)
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#define SDMMC_CLKSEL_WAKEUP_INT BIT(11)
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/* RCLK_EN register defines */
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#define DATA_STROBE_EN BIT(0)
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#define AXI_NON_BLOCKING_WR BIT(7)
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/* SDMMC_DDR200_RDDQS_EN */
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#define DWMCI_TXDT_CRC_TIMER_FASTLIMIT(x) (((x) & 0xFF) << 16)
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#define DWMCI_TXDT_CRC_TIMER_INITVAL(x) (((x) & 0xFF) << 8)
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#define DWMCI_TXDT_CRC_TIMER_SET(x, y) (DWMCI_TXDT_CRC_TIMER_FASTLIMIT(x) | \
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DWMCI_TXDT_CRC_TIMER_INITVAL(y))
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#define DWMCI_AXI_NON_BLOCKING_WRITE BIT(7)
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#define DWMCI_RESP_RCLK_MODE BIT(5)
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#define DWMCI_BUSY_CHK_CLK_STOP_EN BIT(2)
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#define DWMCI_RXDATA_START_BIT_SEL BIT(1)
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#define DWMCI_RDDQS_EN BIT(0)
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#define DWMCI_DDR200_RDDQS_EN_DEF (DWMCI_TXDT_CRC_TIMER_FASTLIMIT(0x13) | \
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DWMCI_TXDT_CRC_TIMER_INITVAL(0x15))
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/* SDMMC_SECTOR_NUM_INC */
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#define DWMCI_BURST_LENGTH_MASK (0xF)
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#define DWMCI_BURST_LENGTH_CTRL(x) (((x)&DWMCI_BURST_LENGTH_MASK) | \
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(((x)&DWMCI_BURST_LENGTH_MASK)<<16))
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/* SDMMC_SECTOR_NUM_INC */
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#define DWMCI_SECTOR_SIZE_MASK (0x1FFF)
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#define DWMCI_SECTOR_SIZE_CTRL(x) ((x)&DWMCI_SECTOR_SIZE_MASK)
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/* SDMMC_DDR200_ENABLE_SHIFT */
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#define DWMCI_ENABLE_SHIFT_MASK (0x3)
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#define DWMCI_ENABLE_SHIFT(x) ((x) & DWMCI_ENABLE_SHIFT_MASK)
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/* SDMMC_DDR200_ASYNC_FIFO_CTRL */
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#define DWMCI_ASYNC_FIFO_RESET BIT(0)
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/* SDMMC_DDR200_DLINE_CTRL */
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#define DWMCI_WD_DQS_DELAY_CTRL(x) (((x) & 0x3FF) << 20)
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#define DWMCI_FIFO_CLK_DELAY_CTRL(x) (((x) & 0x3) << 16)
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#define DWMCI_RD_DQS_DELAY_CTRL(x) ((x) & 0x3FF)
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#define DWMCI_DDR200_DLINE_CTRL_SET(x, y, z) (DWMCI_WD_DQS_DELAY_CTRL(x) | \
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DWMCI_FIFO_CLK_DELAY_CTRL(y) | \
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DWMCI_RD_DQS_DELAY_CTRL(z))
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#define DWMCI_DDR200_DLINE_CTRL_DEF (DWMCI_FIFO_CLK_DELAY_CTRL(0x2) | \
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DWMCI_RD_DQS_DELAY_CTRL(0x40))
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/* DLINE_CTRL register defines */
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#define DQS_CTRL_RD_DELAY(x, y) (((x) & ~0x3FF) | ((y) & 0x3FF))
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#define DQS_CTRL_GET_RD_DELAY(x) ((x) & 0x3FF)
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/* Block number in eMMC */
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#define SDMMC_BLOCK_NUM 0xFFFFFFFF
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/* SMU control defines */
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#define DWMCI_MPSCTRL_SECURE_READ_BIT BIT(7)
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#define DWMCI_MPSCTRL_SECURE_WRITE_BIT BIT(6)
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#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT BIT(5)
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#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4)
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#define DWMCI_MPSCTRL_USE_FUSE_KEY BIT(3)
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#define DWMCI_MPSCTRL_ECB_MODE BIT(2)
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#define DWMCI_MPSCTRL_ENCRYPTION BIT(1)
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#define DWMCI_MPSCTRL_VALID BIT(0)
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#define DWMCI_MPSCTRL_BYPASS (DWMCI_MPSCTRL_SECURE_READ_BIT |\
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DWMCI_MPSCTRL_SECURE_WRITE_BIT |\
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DWMCI_MPSCTRL_NON_SECURE_READ_BIT |\
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DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT |\
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DWMCI_MPSCTRL_VALID)
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/* Maximum number of Ending sector */
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#define SDMMC_ENDING_SEC_NR_MAX 0xFFFFFFFF
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/* Fixed clock divider */
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#define EXYNOS4210_FIXED_CIU_CLK_DIV 2
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#define EXYNOS4412_FIXED_CIU_CLK_DIV 4
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#define HS400_FIXED_CIU_CLK_DIV 1
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/* Minimal required clock frequency for cclkin, unit: HZ */
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#define EXYNOS_CCLKIN_MIN 25000000
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/* FMP SECURITY bits */
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#define DWMCI_MPSECURITY_PROTBYTZPC BIT(31)
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#define DWMCI_MPSECURITY_MMC_SFR_PROT_ON BIT(29)
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#define DWMCI_MPSECURITY_FMP_ENC_ON BIT(28)
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#define DWMCI_MPSECURITY_DESCTYPE(type) ((type & 0x3) << 19)
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/* HWACG Control */
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#define MMC_HWACG_CONTROL BIT(4)
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#define HWACG_Q_ACTIVE_EN 1
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#define HWACG_Q_ACTIVE_DIS 0
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/* Phase 7 Mux Control */
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#define sample_path_sel_en(dev, reg) ({\
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u32 __ret = 0;\
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__ret = __raw_readl((dev)->regs + SDMMC_##reg);\
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__ret &= ~(0x1 << 31);\
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__raw_writel(((__ret) | (0x1 << 31)), (dev)->regs + SDMMC_##reg);\
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})
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#define sample_path_sel_dis(dev, reg) ({\
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u32 __ret = 0;\
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__ret = __raw_readl((dev)->regs + SDMMC_##reg);\
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__ret &= ~(0x1 << 31);\
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__raw_writel((__ret), (dev)->regs + SDMMC_##reg);\
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})
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#endif /* _DW_MMC_EXYNOS_H_ */
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