139 lines
5.3 KiB
C
Executable File
139 lines
5.3 KiB
C
Executable File
/****************************************************************************
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*
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* Copyright (c) 2014 - 2016 Samsung Electronics Co., Ltd. All rights reserved
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*
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****************************************************************************/
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#ifndef PANIC_RECORD_R4_DEFS_H__
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#define PANIC_RECORD_R4_DEFS_H__
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/*
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* R4 Panic Record Definitions.
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*
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* This record is used to pass summary information about the context of
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* Maxwell R4 firmware panics to the host.
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*
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* The record location, relative to shared DRAM memory, is defined by the
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* R4_PANIC_RECORD_OFFSET field in the firmware header [see SC-505846-SW].
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*
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* Notes:-
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* - The host panic handler should _not_ expect the R4 record to be
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* written prior to a panic indication from Maxwell, and it may never
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* be written at all. The checksum should indicate a valid record.
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*
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* N.B. Defined in this standalone header for inclusion in .s and .c.
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*/
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/*
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* The current version of the PANIC_RECORD_R4 structure defined below.
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* Written to version field by firmware, checked by host.
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* This also serves as a rudimentary endianess check.
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*/
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#define PANIC_RECORD_R4_VERSION_1 1
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/*
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* Total number of R4 registers saved.
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*/
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#define PANIC_RECORD_R4_REGISTER_COUNT 18
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/*
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* Number of panic info arguments.
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*/
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#define PANIC_RECORD_R4_INFO_COUNT 4
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/*
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* Checksum seed to prevent false match on all zeros or ones.
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*/
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#define PANIC_RECORD_R4_CKSUM_SEED 0xa5a5a5a5
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/*****************************************************************************
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* R4 Panic Record 32bit field indices.
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*****************************************************************************/
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/*
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* Version of this structure.
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*/
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#define PANIC_RECORD_R4_VERSION_INDEX 0
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/*
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* Clock counters at time of the R4 panic.
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*
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* The 1M clock is generally the most useful but there is period
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* after IP wake-up when it is not monotonic. The 32K count
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* is included in-case of a panic during wake-up.
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*/
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#define PANIC_RECORD_R4_TIMESTAMP_1M_INDEX (PANIC_RECORD_R4_VERSION_INDEX + 1)
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#define PANIC_RECORD_R4_TIMESTAMP_32K_INDEX (PANIC_RECORD_R4_TIMESTAMP_1M_INDEX + 1)
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/*
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* Snapshot of main r4 CPU registers.
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*/
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#define PANIC_RECORD_R4_REGISTERS_INDEX (PANIC_RECORD_R4_TIMESTAMP_32K_INDEX + 1)
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/*
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* Panic info.
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*
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* 1st field is key/index of panic_string.
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*/
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#define PANIC_RECORD_R4_INFO_INDEX (PANIC_RECORD_R4_REGISTERS_INDEX + PANIC_RECORD_R4_REGISTER_COUNT)
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/*
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* 32bit XOR of all the fields above + PANIC_RECORD_R4_CKSUM_SEED
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*
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* Written by firmware on panic, checked by host.
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*/
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#define PANIC_RECORD_R4_CKSUM_INDEX (PANIC_RECORD_R4_INFO_INDEX + PANIC_RECORD_R4_INFO_COUNT)
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/*
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* Length of the r4 panic record (uint32s).
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*/
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#define PANIC_RECORD_R4_LEN (PANIC_RECORD_R4_CKSUM_INDEX + 1)
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/*****************************************************************************
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* R4 uint32 Register indices relative to PANIC_RECORD_R4_REGISTERS_INDEX
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*****************************************************************************/
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#define PANIC_RECORD_R4_REGISTER_R0 0
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#define PANIC_RECORD_R4_REGISTER_R1 1
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#define PANIC_RECORD_R4_REGISTER_R2 2
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#define PANIC_RECORD_R4_REGISTER_R3 3
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#define PANIC_RECORD_R4_REGISTER_R4 4
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#define PANIC_RECORD_R4_REGISTER_R5 5
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#define PANIC_RECORD_R4_REGISTER_R6 6
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#define PANIC_RECORD_R4_REGISTER_R7 7
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#define PANIC_RECORD_R4_REGISTER_R8 8
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#define PANIC_RECORD_R4_REGISTER_R9 9
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#define PANIC_RECORD_R4_REGISTER_R10 10
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#define PANIC_RECORD_R4_REGISTER_R11 11
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#define PANIC_RECORD_R4_REGISTER_R12 12
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#define PANIC_RECORD_R4_REGISTER_SP 13
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#define PANIC_RECORD_R4_REGISTER_LR 14
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#define PANIC_RECORD_R4_REGISTER_SPSR 15
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#define PANIC_RECORD_R4_REGISTER_PC 16
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#define PANIC_RECORD_R4_REGISTER_CPSR 17
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/*****************************************************************************
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* R4 Register octet offsets relative to PANIC_RECORD_R4_REGISTERS_INDEX
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*****************************************************************************/
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#define PANIC_RECORD_R4_REGISTER_OFFSET_R0 (PANIC_RECORD_R4_REGISTER_R0 * 4)
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#define PANIC_RECORD_R4_REGISTER_OFFSET_R1 (PANIC_RECORD_R4_REGISTER_R1 * 4)
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#define PANIC_RECORD_R4_REGISTER_OFFSET_R2 (PANIC_RECORD_R4_REGISTER_R2 * 4)
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#define PANIC_RECORD_R4_REGISTER_OFFSET_R3 (PANIC_RECORD_R4_REGISTER_R3 * 4)
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#define PANIC_RECORD_R4_REGISTER_OFFSET_R4 (PANIC_RECORD_R4_REGISTER_R4 * 4)
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#define PANIC_RECORD_R4_REGISTER_OFFSET_R5 (PANIC_RECORD_R4_REGISTER_R5 * 4)
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#define PANIC_RECORD_R4_REGISTER_OFFSET_R6 (PANIC_RECORD_R4_REGISTER_R6 * 4)
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#define PANIC_RECORD_R4_REGISTER_OFFSET_R7 (PANIC_RECORD_R4_REGISTER_R7 * 4)
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#define PANIC_RECORD_R4_REGISTER_OFFSET_R8 (PANIC_RECORD_R4_REGISTER_R8 * 4)
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#define PANIC_RECORD_R4_REGISTER_OFFSET_R9 (PANIC_RECORD_R4_REGISTER_R9 * 4)
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#define PANIC_RECORD_R4_REGISTER_OFFSET_R10 (PANIC_RECORD_R4_REGISTER_R10 * 4)
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#define PANIC_RECORD_R4_REGISTER_OFFSET_R11 (PANIC_RECORD_R4_REGISTER_R11 * 4)
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#define PANIC_RECORD_R4_REGISTER_OFFSET_R12 (PANIC_RECORD_R4_REGISTER_R12 * 4)
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#define PANIC_RECORD_R4_REGISTER_OFFSET_SP (PANIC_RECORD_R4_REGISTER_SP * 4)
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#define PANIC_RECORD_R4_REGISTER_OFFSET_LR (PANIC_RECORD_R4_REGISTER_LR * 4)
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#define PANIC_RECORD_R4_REGISTER_OFFSET_SPSR (PANIC_RECORD_R4_REGISTER_SPSR * 4)
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#define PANIC_RECORD_R4_REGISTER_OFFSET_PC (PANIC_RECORD_R4_REGISTER_PC * 4)
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#define PANIC_RECORD_R4_REGISTER_OFFSET_CPSR (PANIC_RECORD_R4_REGISTER_CPSR * 4)
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#endif /* PANIC_RECORD_R4_DEFS_H__ */
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