225 lines
9.8 KiB
C
Executable File
225 lines
9.8 KiB
C
Executable File
/****************************************************************************
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*
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* Copyright (c) 2014 - 2019 Samsung Electronics Co., Ltd. All rights reserved
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*
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****************************************************************************/
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#ifndef __MIF_REG_3830_H
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#define __MIF_REG_3830_H
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/****************************************************************************
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* This header uses values from Nacho Exynos 3830 User Manual
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* A copy can be found in http://cognidox/SC-508880-SP
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****************************************************************************/
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/*********************************/
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/* PLATFORM register definitions */
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/*********************************/
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#define NUM_MBOX_PLAT 8
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#define NUM_SEMAPHORE 12
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#define MAILBOX_WLBT_BASE 0x0000
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#define MAILBOX_WLBT_REG(r) (MAILBOX_WLBT_BASE + (r))
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#define MCUCTRL 0x000 /* MCU Controller Register */
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/* R0 [31:16] - Int FROM R4/M4 */
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#define INTGR0 0x008 /* Interrupt Generation Register 0 (r/w) */
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#define INTCR0 0x00C /* Interrupt Clear Register 0 (w) */
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#define INTMR0 0x010 /* Interrupt Mask Register 0 (r/w) */
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#define INTSR0 0x014 /* Interrupt Status Register 0 (r) */
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#define INTMSR0 0x018 /* Interrupt Mask Status Register 0 (r) */
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/* R1 [15:0] - Int TO R4/M4 */
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#define INTGR1 0x01c /* Interrupt Generation Register 1 */
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#define INTCR1 0x020 /* Interrupt Clear Register 1 */
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#define INTMR1 0x024 /* Interrupt Mask Register 1 */
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#define INTSR1 0x028 /* Interrupt Status Register 1 */
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#define INTMSR1 0x02c /* Interrupt Mask Status Register 1 */
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#define MIF_INIT 0x04c /* MIF_init */
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#define IS_VERSION 0x050 /* Version Information Register */
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#define ISSR_BASE 0x080 /* IS_Shared_Register Base address */
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#define ISSR(r) (ISSR_BASE + (4 * (r)))
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#define SEMAPHORE_BASE 0x180 /* IS_Shared_Register Base address */
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#define SEMAPHORE(r) (SEMAPHORE_BASE + (4 * (r)))
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#define SEMA0CON 0x1c0
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#define SEMA0STATE 0x1c8
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#define SEMA1CON 0x1e0
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#define SEMA1STATE 0x1e8
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#define WLBT_PBUS_BASE 0x14C00000
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// CBUS : APM_BUS
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// PBUS : CFG_BUS
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/* New WLBT SFRs for MEM config */
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#define WLBT_PBUS_D_TZPC_SFR (WLBT_PBUS_BASE + 0x10000)
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#define WLBT_PBUS_BAAW_DBUS (WLBT_PBUS_BASE + 0x20000)
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#define WLBT_PBUS_BAAW_CBUS (WLBT_PBUS_BASE + 0x30000)
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#define WLBT_PBUS_SMAPPER (WLBT_PBUS_BASE + 0x40000)
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#define WLBT_PBUS_SYSREG (WLBT_PBUS_BASE + 0x50000)
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#define WLBT_PBUS_BOOT (WLBT_PBUS_BASE + 0x60000)
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#define VGPIO_TX_MONITOR 0x1700
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#define VGPIO_TX_MON_BIT29 BIT(29)
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/* Exynos 3830 UM - TODO */
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#define WLBT_CONFIGURATION 0x3100
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#define LOCAL_PWR_CFG BIT(0) /* Control power state 0: Power down 1: Power on */
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/* Exynos 3830 UM - TODO */
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#define WLBT_STATUS 0x3104
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#define WLBT_STATUS_BIT0 BIT(0) /* Status 0 : Power down 1 : Power on */
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/* Exynos 3830 UM - TODO */
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#define WLBT_STATES 0x3108 /* STATES [7:0] States index for debugging
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* 0x00 : Reset
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* 0x10 : Power up
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* 0x80 : Power down
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* */
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#define WLBT_OPTION 0x310C
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#define WLBT_OPTION_DATA BIT(3)
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/* Exynos 3830 UM - TODO */
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#define WLBT_CTRL_NS 0x3110 /* WLBT Control SFR non-secure */
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#define WLBT_ACTIVE_CLR BIT(6) /* WLBT_ACTIVE_REQ is clear internally on WAKEUP */
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#define WLBT_ACTIVE_EN BIT(5) /* Enable of WIFI_ACTIVE_REQ */
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/* Exynos 3830 UM - TODO */
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#define WLBT_CTRL_S 0x3114 /* WLBT Control SFR secure */
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#define WLBT_START BIT(3) /* CP control enable 0: Disable 1: Enable */
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/* Exynos 3830 UM - TODO */
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#define WLBT_OUT 0x3120
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#define SWEEPER_BYPASS BIT(13) /* SWEEPER bypass mode control(WLBT2AP path) If
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* this bit is set to 1, SWEEPER is bypass mode.
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*/
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#define SWEEPER_PND_CLR_REQ BIT(7) /* SWEEPER_CLEAN Request. SWPPER is the IP
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* that can clean up hung transaction in the Long hop
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* async Bus Interface, when <SUBSYS> get hung
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* state. 0: Normal 1: SWEEPER CLEAN Requested
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*/
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/* Exynos 3830 UM - Exynos3830_12_PMU.docx 1.10.566 */
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#define WLBT_IN 0x3124
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/* TODO: nacho does not have BUS_READY */
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#define BUS_READY BIT(4) /* BUS ready indication signal when reset released. 0:
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* Normal 1: BUS ready state */
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#define PWRDOWN_IND BIT(2) /* PWRDOWN state indication 0: Normal 1: In the
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* power down state */
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#define SWEEPER_PND_CLR_ACK BIT(0) /* SWEEPER_CLEAN ACK signal. SWPPER is the IP
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* that can clean up hung transaction in the Long hop
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* async Bus Interface, when <SUBSYS> get hung
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* state. 0: Normal 1: SWEEPER CLEAN
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* Acknowledged */
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/* Exynos 3830 UM - Exynos3830_12_PMU.docx Page 38 */
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#define WLBT_INT_EN 0x3144
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#define PWR_REQ_F BIT(3)
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#define TCXO_REQ_F BIT(5)
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/* Exynos 3830 UM - TODO */
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#define WLBT_STAT 0x0058
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#define WLBT_PWRDN_DONE BIT(0) /* Check WLBT power-down status.*/
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#define WLBT_ACCESS_MIF BIT(4) /* Check whether WLBT accesses MIF domain */
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/* Exynos 3830 UM - TODO */
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#define WLBT_DEBUG 0x005C
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/* Exynos 3830 UM - TODO */
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#define MIF_CTRL 0x3810
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#define TCXO_EN BIT(0) /* XCLKREQ enable 0: Disable 1: Enable */
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/* Exynos 3830 UM - TODO */
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#define TOP_OUT 0x3920
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#define PWRRGTON_CP BIT(1) /* XPWRRTON_CP contr */
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#define WAKEUP_INT_TYPE 0x3948
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#define RESETREQ_WLBT BIT(25) /* Interrupt type 0:Edge, 1:Level */
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/* Exynos 3830 UM - TODO */
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#define TCXO_BUF_CTRL 0x3B78
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#define TCXO_BUF_BIAS_EN_WLBT BIT(0)
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/* New WLBT SFRs for MEM config */
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/* end address is exclusive so the ENDx register should be set to the first
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* address that is not accessible through that BAAW.
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*
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* Another very important point to note here is we are using BAAW0 to expose
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* 16MB region, so other BAAWs can be used for other purposes
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*/
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#define WLBT_DBUS_BAAW_0_START 0x80000000 // Start of DRAM for WLBT R7
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#define WLBT_DBUS_BAAW_0_END 0x80C00000 // 12 MB
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#define WLBT_DBUS_BAAW_1_START 0xC0000000
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#define WLBT_DBUS_BAAW_1_END 0xDFFFFFFF
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/* #define WLBT_DBUS_BAAW_2_START 0x80800000
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#define WLBT_DBUS_BAAW_2_END WLBT_DBUS_BAAW_3_START
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#define WLBT_DBUS_BAAW_3_START 0x80C00000
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#define WLBT_DBUS_BAAW_3_END WLBT_DBUS_BAAW_4_START
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#define WLBT_DBUS_BAAW_4_START 0x81000000
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#define WLBT_DBUS_BAAW_4_END 0x813FFFFF */
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#define WLBT_BAAW_CON_INIT_DONE (1 << 31)
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#define WLBT_BAAW_CON_EN_WRITE (1 << 1)
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#define WLBT_BAAW_CON_EN_READ (1 << 0)
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#define WLBT_BAAW_ACCESS_CTRL (WLBT_BAAW_CON_INIT_DONE | WLBT_BAAW_CON_EN_WRITE | WLBT_BAAW_CON_EN_READ)
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/* ref Confluence Maxwell152+Memory+Map */
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#define WLBT_CBUS_BAAW_0_START 0xA0000000 // CP2WLBT MBOX
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#define WLBT_CBUS_BAAW_0_END 0xA000FFFF//WLBT_CBUS_BAAW_1_START
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#define WLBT_CBUS_BAAW_1_START 0xA0010000 // MAILBOX_GNSS2WLBT
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#define WLBT_CBUS_BAAW_1_END 0xA00CFFFF//WLBT_CBUS_BAAW_6_START // TODO
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#define WLBT_CBUS_BAAW_2_START 0xA0020000 // MAILBOX_APM2WLBT
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#define WLBT_CBUS_BAAW_2_END WLBT_CBUS_BAAW_3_START
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#define WLBT_CBUS_BAAW_3_START 0xA0030000 // MAILBOX_AP2WLBT
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#define WLBT_CBUS_BAAW_3_END WLBT_CBUS_BAAW_4_START
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#define WLBT_CBUS_BAAW_4_START 0xA0040000 // MAILBOX_WLBT2ABOX
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#define WLBT_CBUS_BAAW_4_END WLBT_CBUS_BAAW_5_START
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#define WLBT_CBUS_BAAW_5_START 0xA0050000 // MAILBOX_WLBT2CHUB
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#define WLBT_CBUS_BAAW_5_END WLBT_CBUS_BAAW_6_START
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#define WLBT_CBUS_BAAW_6_START 0xA0060000 // GPIO_CMGP
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#define WLBT_CBUS_BAAW_6_END WLBT_CBUS_BAAW_7_START
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#define WLBT_CBUS_BAAW_7_START 0xA0070000 // ADC_CMGP_AP
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#define WLBT_CBUS_BAAW_7_END WLBT_CBUS_BAAW_8_START
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#define WLBT_CBUS_BAAW_8_START 0xA0080000 // ADC_CMGP_CP
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#define WLBT_CBUS_BAAW_8_END WLBT_CBUS_BAAW_9_START
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#define WLBT_CBUS_BAAW_9_START 0xA0090000 // SYSREG_CMGP2WLBT
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#define WLBT_CBUS_BAAW_9_END WLBT_CBUS_BAAW_A_START
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#define WLBT_CBUS_BAAW_A_START 0xA00A0000 // USI_CMGP00
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#define WLBT_CBUS_BAAW_A_END WLBT_CBUS_BAAW_B_START
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#define WLBT_CBUS_BAAW_B_START 0xA00B0000 // reserved
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#define WLBT_CBUS_BAAW_B_END WLBT_CBUS_BAAW_C_START
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#define WLBT_CBUS_BAAW_C_START 0xA00C0000 // USI_CMGP01
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#define WLBT_CBUS_BAAW_C_END WLBT_CBUS_BAAW_D_START
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#define WLBT_CBUS_BAAW_D_START 0xA00D0000 // CHUB_SRAM
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#define WLBT_CBUS_BAAW_D_END 0xA010FFFF
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#define WLBT_PBUS_MBOX_CP2WLBT_BASE 0x11950000
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#define WLBT_PBUS_MBOX_GNSS2WLBT_BASE 0x119A0000
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#define WLBT_PBUS_MBOX_APM2WLBT_BASE 0x119B0000
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#define WLBT_PBUS_MBOX_AP2WLBT_BASE 0x119C0000
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#define WLBT_PBUS_MBOX_WLBT2ABOX_BASE 0x119D0000
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#define WLBT_PBUS_MBOX_WLBT2CHUB_BASE 0x119E0000
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#define WLBT_PBUS_GPIO_CMGP_BASE 0x11C30000
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#define WLBT_PBUS_ADC_CMGP_AP_BASE 0x11C40000
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#define WLBT_PBUS_ADC_CMGP_CP_BASE 0x11C50000
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#define WLBT_PBUS_SYSREG_CMGP2WLBT_BASE 0x11C60000
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#define WLBT_PBUS_USI_CMG00_BASE 0x11C70000
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#define WLBT_PBUS_USI_CMG01_BASE 0x11D20000
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#define WLBT_PBUS_CHUB_BASE 0x10E00000 /* TODO: confirm correct address */
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/* CHIP_VERSION_ID SFR (remap block) 0x14c50410
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*/
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#define CHIP_VERSION_ID_OFFSET 0x410
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#define CHIP_VERSION_ID_VER_MASK 0xFFFFFFFF /* [00:31] Version ID */
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#define CHIP_VERSION_ID_IP_PMU 0x0000F000 /* [12:15] PMU ROM Rev */
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#define CHIP_VERSION_ID_IP_MINOR 0x000F0000 /* [16:19] Minor Rev */
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#define CHIP_VERSION_ID_IP_MAJOR 0x00F00000 /* [20:23] Major Rev */
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#define CHIP_VERSION_ID_IP_PMU_SHIFT 12
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#define CHIP_VERSION_ID_IP_MINOR_SHIFT 16
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#define CHIP_VERSION_ID_IP_MAJOR_SHIFT 20
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/* TZASC (TrustZone Address Space Controller) configuration for Katmai onwards */
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#define EXYNOS_SET_CONN_TZPC 0
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#define SMC_CMD_CONN_IF (0x82000710)
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#endif /* __MIF_REG_3830_H */
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