312 lines
9.2 KiB
C
Executable File
312 lines
9.2 KiB
C
Executable File
/*
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* s2mpu09-irq.c - Interrupt controller support for S2MPU09
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*
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* Copyright (C) 2016 Samsung Electronics Co.Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/err.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/gpio.h>
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#include <linux/mfd/samsung/s2mpu09.h>
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#include <linux/mfd/samsung/s2mpu09-regulator.h>
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static const u8 s2mpu09_mask_reg[] = {
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/* TODO: Need to check other INTMASK */
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[PMIC_INT1] = S2MPU09_PMIC_REG_INT1M,
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[PMIC_INT2] = S2MPU09_PMIC_REG_INT2M,
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[PMIC_INT3] = S2MPU09_PMIC_REG_INT3M,
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[PMIC_INT4] = S2MPU09_PMIC_REG_INT4M,
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[PMIC_INT5] = S2MPU09_PMIC_REG_INT5M,
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};
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static struct i2c_client *get_i2c(struct s2mpu09_dev *s2mpu09,
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enum s2mpu09_irq_source src)
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{
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switch (src) {
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case PMIC_INT1 ... PMIC_INT5:
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return s2mpu09->pmic;
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default:
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return ERR_PTR(-EINVAL);
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}
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}
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struct s2mpu09_irq_data {
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int mask;
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enum s2mpu09_irq_source group;
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};
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#define DECLARE_IRQ(idx, _group, _mask) \
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[(idx)] = { .group = (_group), .mask = (_mask) }
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static const struct s2mpu09_irq_data s2mpu09_irqs[] = {
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_PWRONR_INT1, PMIC_INT1, 1 << 1),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_PWRONF_INT1, PMIC_INT1, 1 << 0),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_JIGONBF_INT1, PMIC_INT1, 1 << 2),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_JIGONBR_INT1, PMIC_INT1, 1 << 3),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_ACOKF_INT1, PMIC_INT1, 1 << 4),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_ACOKR_INT1, PMIC_INT1, 1 << 5),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_PWRON1S_INT1, PMIC_INT1, 1 << 6),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_MRB_INT1, PMIC_INT1, 1 << 7),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_RTC60S_INT2, PMIC_INT2, 1 << 0),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_RTCA1_INT2, PMIC_INT2, 1 << 1),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_RTCA0_INT2, PMIC_INT2, 1 << 2),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_SMPL_INT2, PMIC_INT2, 1 << 3),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_RTC1S_INT2, PMIC_INT2, 1 << 4),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_WTSR_INT2, PMIC_INT2, 1 << 5),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_WTSRB_INT2, PMIC_INT2, 1 << 7),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_120C_INT3, PMIC_INT3, 1 << 0),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_140C_INT3, PMIC_INT3, 1 << 1),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_TSD_INT3, PMIC_INT3, 1 << 2),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_OCPB1_INT3, PMIC_INT3, 1 << 6),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_OCPB2_INT3, PMIC_INT3, 1 << 7),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_OCPB3_INT4, PMIC_INT4, 1 << 0),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_OCPB4_INT4, PMIC_INT4, 1 << 1),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_OCPB5_INT4, PMIC_INT4, 1 << 2),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_OCPB6_INT4, PMIC_INT4, 1 << 3),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_OCPB7_INT4, PMIC_INT4, 1 << 4),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_OCPB8_INT4, PMIC_INT4, 1 << 5),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_OCPB9_INT4, PMIC_INT4, 1 << 6),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_OCPB10_INT4, PMIC_INT4, 1 << 7),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_SCLDO2_INT5, PMIC_INT5, 1 << 0),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_SCLDO18_INT5, PMIC_INT5, 1 << 1),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_SCLDO19_INT5, PMIC_INT5, 1 << 2),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_SCLDO33_INT5, PMIC_INT5, 1 << 3),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_SCLDO34_INT5, PMIC_INT5, 1 << 4),
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DECLARE_IRQ(S2MPU09_PMIC_IRQ_SCLDO35_INT5, PMIC_INT5, 1 << 5),
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};
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static void s2mpu09_irq_lock(struct irq_data *data)
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{
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struct s2mpu09_dev *s2mpu09 = irq_get_chip_data(data->irq);
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mutex_lock(&s2mpu09->irqlock);
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}
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static void s2mpu09_irq_sync_unlock(struct irq_data *data)
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{
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struct s2mpu09_dev *s2mpu09 = irq_get_chip_data(data->irq);
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int i;
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for (i = 0; i < S2MPU09_IRQ_GROUP_NR; i++) {
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u8 mask_reg = s2mpu09_mask_reg[i];
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struct i2c_client *i2c = get_i2c(s2mpu09, i);
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if (mask_reg == S2MPU09_REG_INVALID ||
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IS_ERR_OR_NULL(i2c))
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continue;
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s2mpu09->irq_masks_cache[i] = s2mpu09->irq_masks_cur[i];
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s2mpu09_write_reg(i2c, s2mpu09_mask_reg[i],
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s2mpu09->irq_masks_cur[i]);
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}
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mutex_unlock(&s2mpu09->irqlock);
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}
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static const inline struct s2mpu09_irq_data *
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irq_to_s2mpu09_irq(struct s2mpu09_dev *s2mpu09, int irq)
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{
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return &s2mpu09_irqs[irq - s2mpu09->irq_base];
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}
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static void s2mpu09_irq_mask(struct irq_data *data)
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{
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struct s2mpu09_dev *s2mpu09 = irq_get_chip_data(data->irq);
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const struct s2mpu09_irq_data *irq_data =
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irq_to_s2mpu09_irq(s2mpu09, data->irq);
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if (irq_data->group >= S2MPU09_IRQ_GROUP_NR)
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return;
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s2mpu09->irq_masks_cur[irq_data->group] |= irq_data->mask;
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}
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static void s2mpu09_irq_unmask(struct irq_data *data)
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{
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struct s2mpu09_dev *s2mpu09 = irq_get_chip_data(data->irq);
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const struct s2mpu09_irq_data *irq_data =
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irq_to_s2mpu09_irq(s2mpu09, data->irq);
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if (irq_data->group >= S2MPU09_IRQ_GROUP_NR)
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return;
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s2mpu09->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
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}
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static struct irq_chip s2mpu09_irq_chip = {
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.name = MFD_DEV_NAME,
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.irq_bus_lock = s2mpu09_irq_lock,
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.irq_bus_sync_unlock = s2mpu09_irq_sync_unlock,
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.irq_mask = s2mpu09_irq_mask,
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.irq_unmask = s2mpu09_irq_unmask,
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};
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static irqreturn_t s2mpu09_irq_thread(int irq, void *data)
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{
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struct s2mpu09_dev *s2mpu09 = data;
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u8 irq_reg[S2MPU09_IRQ_GROUP_NR] = {0};
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u8 irq_src;
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int i, ret;
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//pr_debug("%s: irq gpio pre-state(0x%02x)\n", __func__,
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pr_err("%s: irq gpio pre-state(0x%02x)\n", __func__,
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gpio_get_value(s2mpu09->irq_gpio));
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ret = s2mpu09_read_reg(s2mpu09->i2c,
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S2MPU09_PMIC_REG_INTSRC, &irq_src);
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pr_err("%s: interrupt source(0x%02x)\n", __func__, irq_src);
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if (ret) {
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pr_err("%s:%s Failed to read interrupt source: %d\n",
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MFD_DEV_NAME, __func__, ret);
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return IRQ_NONE;
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}
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pr_info("%s: interrupt source(0x%02x)\n", __func__, irq_src);
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if (irq_src & S2MPU09_IRQSRC_PMIC) {
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/* PMIC_INT */
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ret = s2mpu09_bulk_read(s2mpu09->pmic, S2MPU09_PMIC_REG_INT1,
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S2MPU09_NUM_IRQ_PMIC_REGS, &irq_reg[PMIC_INT1]);
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if (ret) {
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pr_err("%s:%s Failed to read pmic interrupt: %d\n",
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MFD_DEV_NAME, __func__, ret);
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return IRQ_NONE;
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}
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pr_info("%s: pmic interrupt(0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x)\n",
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__func__, irq_reg[PMIC_INT1], irq_reg[PMIC_INT2], irq_reg[PMIC_INT3],
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irq_reg[PMIC_INT4], irq_reg[PMIC_INT5]);
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}
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/* Apply masking */
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for (i = 0; i < S2MPU09_IRQ_GROUP_NR; i++)
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irq_reg[i] &= ~s2mpu09->irq_masks_cur[i];
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/* Report */
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for (i = 0; i < S2MPU09_IRQ_NR; i++) {
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if (irq_reg[s2mpu09_irqs[i].group] & s2mpu09_irqs[i].mask)
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handle_nested_irq(s2mpu09->irq_base + i);
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}
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return IRQ_HANDLED;
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}
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int s2mpu09_irq_init(struct s2mpu09_dev *s2mpu09)
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{
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int i;
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int ret;
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u8 i2c_data;
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int cur_irq;
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if (!s2mpu09->irq_gpio) {
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dev_warn(s2mpu09->dev, "No interrupt specified.\n");
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s2mpu09->irq_base = 0;
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return 0;
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}
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if (!s2mpu09->irq_base) {
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dev_err(s2mpu09->dev, "No interrupt base specified.\n");
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return 0;
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}
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mutex_init(&s2mpu09->irqlock);
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s2mpu09->irq = gpio_to_irq(s2mpu09->irq_gpio);
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pr_info("%s:%s irq=%d, irq->gpio=%d\n", MFD_DEV_NAME, __func__,
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s2mpu09->irq, s2mpu09->irq_gpio);
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ret = gpio_request(s2mpu09->irq_gpio, "pmic_irq");
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if (ret) {
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dev_err(s2mpu09->dev, "%s: failed requesting gpio %d\n",
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__func__, s2mpu09->irq_gpio);
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return ret;
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}
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gpio_direction_input(s2mpu09->irq_gpio);
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gpio_free(s2mpu09->irq_gpio);
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/* Mask individual interrupt sources */
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for (i = 0; i < S2MPU09_IRQ_GROUP_NR; i++) {
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struct i2c_client *i2c;
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s2mpu09->irq_masks_cur[i] = 0xff;
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s2mpu09->irq_masks_cache[i] = 0xff;
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i2c = get_i2c(s2mpu09, i);
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if (IS_ERR_OR_NULL(i2c))
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continue;
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if (s2mpu09_mask_reg[i] == S2MPU09_REG_INVALID)
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continue;
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s2mpu09_write_reg(i2c, s2mpu09_mask_reg[i], 0xff);
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}
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/* Register with genirq */
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for (i = 0; i < S2MPU09_IRQ_NR; i++) {
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cur_irq = i + s2mpu09->irq_base;
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irq_set_chip_data(cur_irq, s2mpu09);
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irq_set_chip_and_handler(cur_irq, &s2mpu09_irq_chip,
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handle_level_irq);
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irq_set_nested_thread(cur_irq, 1);
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#ifdef CONFIG_ARM
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set_irq_flags(cur_irq, IRQF_VALID);
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#else
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irq_set_noprobe(cur_irq);
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#endif
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}
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s2mpu09_write_reg(s2mpu09->i2c, S2MPU09_PMIC_REG_INTSRC_MASK, 0xff);
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/* Unmask s2mpu09 interrupt */
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ret = s2mpu09_read_reg(s2mpu09->i2c, S2MPU09_PMIC_REG_INTSRC_MASK,
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&i2c_data);
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if (ret) {
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pr_err("%s:%s fail to read intsrc mask reg\n",
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MFD_DEV_NAME, __func__);
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return ret;
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}
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i2c_data &= ~(S2MPU09_IRQSRC_PMIC); /* Unmask pmic interrupt */
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s2mpu09_write_reg(s2mpu09->i2c, S2MPU09_PMIC_REG_INTSRC_MASK,
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i2c_data);
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pr_info("%s:%s s2mpu09_PMIC_REG_INTSRC_MASK=0x%02x\n",
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MFD_DEV_NAME, __func__, i2c_data);
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ret = request_threaded_irq(s2mpu09->irq, NULL, s2mpu09_irq_thread,
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IRQF_TRIGGER_LOW | IRQF_ONESHOT,
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"s2mpu09-irq", s2mpu09);
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if (ret) {
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dev_err(s2mpu09->dev, "Failed to request IRQ %d: %d\n",
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s2mpu09->irq, ret);
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return ret;
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}
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return 0;
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}
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void s2mpu09_irq_exit(struct s2mpu09_dev *s2mpu09)
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{
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if (s2mpu09->irq)
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free_irq(s2mpu09->irq, s2mpu09);
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}
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