523 lines
16 KiB
C
Executable File
523 lines
16 KiB
C
Executable File
/*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Data structure definition for Exynos IOMMU driver
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _EXYNOS_IOMMU_H_
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#define _EXYNOS_IOMMU_H_
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/list.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/genalloc.h>
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#include <linux/iommu.h>
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#include <linux/irq.h>
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#include <linux/clk.h>
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#include <linux/exynos_iovmm.h>
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#include "exynos-iommu-log.h"
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typedef u32 sysmmu_iova_t;
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typedef u32 sysmmu_pte_t;
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#define IOVM_NUM_PAGES(vmsize) (vmsize / PAGE_SIZE)
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#define IOVM_BITMAP_SIZE(vmsize) \
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((IOVM_NUM_PAGES(vmsize) + BITS_PER_BYTE) / BITS_PER_BYTE)
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#define SECT_ORDER 20
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#define LPAGE_ORDER 16
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#define SPAGE_ORDER 12
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#define SECT_SIZE (1 << SECT_ORDER)
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#define LPAGE_SIZE (1 << LPAGE_ORDER)
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#define SPAGE_SIZE (1 << SPAGE_ORDER)
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#define SECT_MASK (~(SECT_SIZE - 1))
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#define LPAGE_MASK (~(LPAGE_SIZE - 1))
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#define SPAGE_MASK (~(SPAGE_SIZE - 1))
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#define SECT_ENT_MASK ~((SECT_SIZE >> PG_ENT_SHIFT) - 1)
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#define LPAGE_ENT_MASK ~((LPAGE_SIZE >> PG_ENT_SHIFT) - 1)
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#define SPAGE_ENT_MASK ~((SPAGE_SIZE >> PG_ENT_SHIFT) - 1)
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#define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
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#define PGBASE_TO_PHYS(pgent) ((phys_addr_t)(pgent) << PG_ENT_SHIFT)
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#define NUM_LV1ENTRIES 4096
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#define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE)
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#define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t))
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#define lv1ent_offset(iova) ((iova) >> SECT_ORDER)
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#define lv2ent_offset(iova) ((iova & ~SECT_MASK) >> SPAGE_ORDER)
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#define PG_ENT_SHIFT 4
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#define lv1ent_fault(sent) ((*(sent) & 7) == 0)
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#define lv1ent_page(sent) ((*(sent) & 7) == 1)
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#define FLPD_FLAG_MASK 7
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#define SLPD_FLAG_MASK 3
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#define SECT_FLAG 2
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#define SLPD_FLAG 1
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#define LPAGE_FLAG 1
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#define SPAGE_FLAG 2
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#define ENT_TO_PHYS(ent) (phys_addr_t)(*(ent))
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#define section_phys(sent) PGBASE_TO_PHYS(ENT_TO_PHYS(sent) & SECT_ENT_MASK)
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#define section_offs(iova) ((iova) & (SECT_SIZE - 1))
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#define lpage_phys(pent) PGBASE_TO_PHYS(ENT_TO_PHYS(pent) & LPAGE_ENT_MASK)
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#define lpage_offs(iova) ((iova) & (LPAGE_SIZE - 1))
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#define spage_phys(pent) PGBASE_TO_PHYS(ENT_TO_PHYS(pent) & SPAGE_ENT_MASK)
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#define spage_offs(iova) ((iova) & (SPAGE_SIZE - 1))
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#define lv1ent_section(sent) ((*(sent) & FLPD_FLAG_MASK) == SECT_FLAG)
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#define lv2table_base(sent) ((phys_addr_t)(*(sent) & ~0x3F) << PG_ENT_SHIFT)
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#define lv2ent_fault(pent) ((*(pent) & SLPD_FLAG_MASK) == 0)
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#define lv2ent_small(pent) ((*(pent) & SLPD_FLAG_MASK) == SPAGE_FLAG)
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#define lv2ent_large(pent) ((*(pent) & SLPD_FLAG_MASK) == LPAGE_FLAG)
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#define mk_lv1ent_sect(pa) ((sysmmu_pte_t) ((pa) >> PG_ENT_SHIFT) | 2)
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#define mk_lv1ent_page(pa) ((sysmmu_pte_t) ((pa) >> PG_ENT_SHIFT) | 1)
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#define mk_lv2ent_lpage(pa) ((sysmmu_pte_t) ((pa) >> PG_ENT_SHIFT) | 1)
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#define mk_lv2ent_spage(pa) ((sysmmu_pte_t) ((pa) >> PG_ENT_SHIFT) | 2)
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#define set_lv1ent_shareable(sent) (*(sent) |= (1 << 6))
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#define set_lv2ent_shareable(sent) (*(sent) |= (1 << 4))
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#define mk_lv2ent_pfnmap(pent) (*(pent) |= (1 << 5)) /* unused field */
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#define lv2ent_pfnmap(pent) ((*(pent) & (1 << 5)) == (1 << 5))
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#define SYSMMU_BLOCK_POLLING_COUNT 4096
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#define REG_MMU_CTRL 0x000
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#define REG_MMU_CFG 0x004
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#define REG_MMU_STATUS 0x008
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#define REG_MMU_VERSION 0x034
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#define CTRL_ENABLE 0x5
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#define CTRL_BLOCK 0x7
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#define CTRL_DISABLE 0x0
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#define CTRL_BLOCK_DISABLE 0x3
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#define CFG_MASK 0x301F1F8C /* Bit 29-28, 20-16, 12-7, 3-2 */
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#define CFG_ACGEN (1 << 24)
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#define CFG_FLPDCACHE (1 << 20)
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#define CFG_QOS_OVRRIDE (1 << 11)
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#define CFG_QOS(n) (((n) & 0xF) << 7)
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#define MMU_WAY_CFG_MASK_PREFETCH (1 << 1)
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#define MMU_WAY_CFG_MASK_PREFETCH_DIR (3 << 2)
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#define MMU_WAY_CFG_MASK_MATCH_METHOD (1 << 4)
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#define MMU_WAY_CFG_MASK_FETCH_SIZE (7 << 5)
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#define MMU_WAY_CFG_MASK_TARGET_CH (3 << 8)
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#define MMU_WAY_CFG_ID_MATCHING (1 << 4)
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#define MMU_WAY_CFG_ADDR_MATCHING (0 << 4)
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#define MMU_WAY_CFG_PRIVATE_ENABLE (1 << 0)
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#define MMU_PUBLIC_WAY_MASK (MMU_WAY_CFG_MASK_PREFETCH | \
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MMU_WAY_CFG_MASK_PREFETCH_DIR | MMU_WAY_CFG_MASK_FETCH_SIZE)
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#define MMU_PRIVATE_WAY_MASK (MMU_PUBLIC_WAY_MASK | \
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MMU_WAY_CFG_MASK_MATCH_METHOD | MMU_WAY_CFG_MASK_TARGET_CH)
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#define REG_PT_BASE_PPN 0x00C
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#define REG_MMU_FLUSH 0x010
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#define REG_MMU_FLUSH_ENTRY 0x014
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#define REG_MMU_FLUSH_RANGE 0x018
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#define REG_FLUSH_RANGE_START 0x020
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#define REG_FLUSH_RANGE_END 0x024
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#define REG_MMU_CAPA 0x030
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#define REG_MMU_CAPA_1 0x038
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#define REG_INT_STATUS 0x060
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#define REG_INT_CLEAR 0x064
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#define REG_FAULT_AR_ADDR 0x070
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#define REG_FAULT_AR_TRANS_INFO 0x078
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#define REG_FAULT_AW_ADDR 0x080
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#define REG_FAULT_AW_TRANS_INFO 0x088
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#define REG_L2TLB_CFG 0x200
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/* For SysMMU v7.x */
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#define REG_MMU_CAPA0_V7 0x870
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#define REG_MMU_CAPA1_V7 0x874
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#define REG_PUBLIC_WAY_CFG 0x120
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#define REG_PRIVATE_WAY_CFG(n) (0x200 + ((n) * 0x10))
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#define REG_PRIVATE_ADDR_START(n) (0x204 + ((n) * 0x10))
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#define REG_PRIVATE_ADDR_END(n) (0x208 + ((n) * 0x10))
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#define REG_PRIVATE_ID(n) (0x20C + ((n) * 0x10))
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#define REG_FAULT_ADDR 0x070
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#define REG_FAULT_TRANS_INFO 0x078
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#define REG_TLB_READ 0x1000
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#define REG_TLB_VPN 0x1004
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#define REG_TLB_PPN 0x1008
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#define REG_TLB_ATTR 0x100C
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#define REG_SBB_READ 0x1100
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#define REG_SBB_VPN 0x1104
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#define REG_SBB_LINK 0x1108
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#define REG_SBB_ATTR 0x110C
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/* For SysMMU v7.1 */
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#define MMU_CAPA1_EXIST(reg) ((reg >> 11) & 0x1)
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#define MMU_CAPA1_TYPE(reg) ((reg >> 28) & 0xF)
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#define MMU_CAPA1_NUM_TLB(reg) ((reg >> 4) & 0xFF)
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#define MMU_CAPA1_NUM_PORT(reg) ((reg) & 0xF)
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#define MMU_TLB_INFO(n) (0x2000 + ((n) * 0x20))
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#define MMU_CAPA1_NUM_TLB_SET(reg) ((reg >> 16) & 0xFF)
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#define MMU_CAPA1_NUM_TLB_WAY(reg) ((reg) & 0xFF)
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#define REG_MMU_TLB_CFG(n) (0x2000 + ((n) * 0x20) + 0x4)
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#define REG_MMU_TLB_MATCH_CFG(n) (0x2000 + ((n) * 0x20) + 0x8)
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#define REG_MMU_TLB_MATCH_SVA(n) (0x2000 + ((n) * 0x20) + 0xC)
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#define REG_MMU_TLB_MATCH_EVA(n) (0x2000 + ((n) * 0x20) + 0x10)
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#define REG_MMU_TLB_MATCH_ID(n) (0x2000 + ((n) * 0x20) + 0x14)
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#define REG_CAPA1_TLB_READ 0x8000
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#define REG_CAPA1_TLB_VPN 0x8004
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#define REG_CAPA1_TLB_PPN 0x8008
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#define REG_CAPA1_TLB_ATTR 0x800C
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#define REG_CAPA1_SBB_READ 0x8020
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#define REG_CAPA1_SBB_VPN 0x8024
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#define REG_CAPA1_SBB_LINK 0x8028
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#define REG_CAPA1_SBB_ATTR 0x802C
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#define REG_SLOT_RSV(n) (0x4000 + ((n) * 0x20))
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#define MMU_CAPA1_SET_TLB_READ_ENTRY(tid, set, way, line) \
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((set) | ((way) << 8) | ((line) << 16) | ((tid) << 20))
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#define MMU_TLB_CFG_MASK(reg) ((reg) & ((0x7 << 5) | (0x3 << 2) | (0x1 << 1)))
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#define MMU_TLB_MATCH_CFG_MASK(reg) ((reg) & ((0xFFFF << 16) | (0x3 << 8)))
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#define MMU_CAPA_NUM_SBB_ENTRY(reg) ((reg >> 12) & 0xF)
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#define MMU_CAPA_NUM_TLB_SET(reg) ((reg >> 8) & 0xF)
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#define MMU_CAPA_NUM_TLB_WAY(reg) ((reg) & 0xFF)
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#define MMU_SET_TLB_READ_ENTRY(set, way, line) \
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((set) | ((way) << 8) | ((line) << 16))
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#define MMU_TLB_ENTRY_VALID(reg) ((reg) >> 28)
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#define MMU_SBB_ENTRY_VALID(reg) ((reg) >> 28)
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#define MMU_VADDR_FROM_TLB(reg, idx) ((((reg) & 0xFFFFC) | ((idx) & 0x3)) << 12)
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#define MMU_PADDR_FROM_TLB(reg) (((reg) & 0xFFFFFF) << 12)
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#define MMU_VADDR_FROM_SBB(reg) (((reg) & 0xFFFFF) << 12)
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#define MMU_PADDR_FROM_SBB(reg) (((reg) & 0x3FFFFFF) << 10)
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#define MMU_FAULT_INFO_READ_REQUEST 0
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#define MMU_FAULT_INFO_WRITE_REQUEST 1
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#define MMU_IS_READ_FAULT(reg) \
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((((reg) >> 20) & 0x1) == MMU_FAULT_INFO_READ_REQUEST)
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#define MMU_HAVE_PB(reg) (!!((reg >> 20) & 0xF))
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#define MMU_IS_TLB_CONFIGURABLE(reg) (!!((reg >> 16) & 0xFF))
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#define MMU_MASK_LINE_SIZE 0x7
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#define MMU_DEFAULT_LINE_SIZE (0x2 << 4)
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#define MMU_MAJ_VER(val) ((val) >> 11)
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#define MMU_MIN_VER(val) ((val >> 4) & 0x7F)
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#define MMU_REV_VER(val) ((val) & 0xF)
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#define MMU_RAW_VER(reg) (((reg) >> 17) & 0x7FFF) /* upper 15 bits */
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#define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 11) | \
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(((min) & 0x7F) << 4))
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#define DEFAULT_QOS_VALUE -1
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#define SYSMMU_FAULT_BITS 4
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#define SYSMMU_FAULT_SHIFT 16
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#define SYSMMU_FAULT_MASK ((1 << SYSMMU_FAULT_BITS) - 1)
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#define SYSMMU_FAULT_FLAG(id) (((id) & SYSMMU_FAULT_MASK) << SYSMMU_FAULT_SHIFT)
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#define SYSMMU_FAULT_ID(fg) (((fg) >> SYSMMU_FAULT_SHIFT) & SYSMMU_FAULT_MASK)
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#define SYSMMU_FAULT_PTW_ACCESS 0
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#define SYSMMU_FAULT_PAGE_FAULT 1
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#define SYSMMU_FAULT_TLB_MULTIHIT 2
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#define SYSMMU_FAULT_ACCESS 3
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#define SYSMMU_FAULT_SECURITY 4
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#define SYSMMU_FAULT_UNKNOWN 5
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#define SYSMMU_FAULTS_NUM (SYSMMU_FAULT_UNKNOWN + 1)
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/*
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* This structure exynos specific generalization of struct iommu_domain.
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* It contains list of all master devices represented by owner, which has
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* been attached to this domain and page tables of IO address space defined by
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* it. It is usually referenced by 'domain' pointer.
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*/
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struct exynos_iommu_domain {
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struct iommu_domain domain; /* generic domain data structure */
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sysmmu_pte_t *pgtable; /* lv1 page table, 16KB */
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spinlock_t pgtablelock; /* lock for modifying page table */
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struct list_head clients_list; /* list of exynos_iommu_owner.client */
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atomic_t *lv2entcnt; /* free lv2 entry counter for each section */
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spinlock_t lock; /* lock for modifying clients_list */
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struct exynos_iommu_event_log log;
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};
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/*
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* This structure is attached to dev.archdata.iommu of the master device
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* on device add, contains a list of SYSMMU controllers defined by device tree,
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* which are bound to given master device. It is usually referenced by 'owner'
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* pointer.
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*/
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struct exynos_iommu_owner {
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struct exynos_iommu_owner *next;
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struct list_head sysmmu_list; /* list of sysmmu_drvdata */
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spinlock_t lock; /* lock for modifying sysmmu_list */
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struct iommu_domain *domain; /* domain of owner */
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struct device *master; /* master device */
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struct list_head client; /* node for owner clients_list */
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struct exynos_iovmm *vmm_data;
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iommu_fault_handler_t fault_handler;
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void *token;
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};
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struct tlb_priv_addr {
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unsigned int cfg;
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};
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struct tlb_priv_id {
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unsigned int cfg;
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unsigned int id;
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};
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struct tlb_port_cfg {
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unsigned int cfg;
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unsigned int id;
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};
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/*
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* flags[7:4] specifies TLB matching types.
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* 0x1 : TLB way dedication
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* 0x2 : TLB port dedication
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*/
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#define TLB_TYPE_MASK(x) ((x) & (0xF << 4))
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#define TLB_TYPE_WAY (0x1 << 4)
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#define TLB_TYPE_PORT (0x2 << 4)
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#define IS_TLB_WAY_TYPE(data) (TLB_TYPE_MASK((data)->tlb_props.flags) \
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== TLB_TYPE_WAY)
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#define IS_TLB_PORT_TYPE(data) (TLB_TYPE_MASK((data)->tlb_props.flags) \
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== TLB_TYPE_PORT)
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#define TLB_WAY_PRIVATE_ID (1 << 0)
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#define TLB_WAY_PRIVATE_ADDR (1 << 1)
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#define TLB_WAY_PUBLIC (1 << 2)
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struct tlb_way_props {
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int priv_id_cnt;
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int priv_addr_cnt;
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unsigned int public_cfg;
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struct tlb_priv_id *priv_id_cfg;
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struct tlb_priv_addr *priv_addr_cfg;
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};
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struct tlb_port_props {
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int port_id_cnt;
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int slot_cnt;
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struct tlb_port_cfg *port_cfg;
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unsigned int *slot_cfg;
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};
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struct tlb_props {
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int flags;
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union {
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struct tlb_way_props way_props;
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struct tlb_port_props port_props;
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};
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};
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enum {
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SYSMMU_USE_RUNTIME_ACTIVE = 0,
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SYSMMU_STATE_DISABLED,
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SYSMMU_STATE_ENABLED,
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};
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/*
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* This structure hold all data of a single SYSMMU controller, this includes
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* hw resources like registers and clocks, pointers and list nodes to connect
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* it to all other structures, internal state and parameters read from device
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* tree. It is usually referenced by 'data' pointer.
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*/
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struct sysmmu_drvdata {
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struct sysmmu_drvdata *next;
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struct device *sysmmu; /* SYSMMU controller device */
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void __iomem *sfrbase; /* our registers */
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struct clk *clk; /* SYSMMU's clock */
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struct iommu_device iommu; /* IOMMU core handle */
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int activations; /* number of calls to sysmmu_enable */
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int runtime_active; /* Runtime PM activated count from master */
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spinlock_t lock; /* lock for modyfying state */
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phys_addr_t pgtable; /* assigned page table structure */
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int version; /* our version */
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int qos;
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int securebase;
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struct atomic_notifier_head fault_notifiers;
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struct tlb_props tlb_props;
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bool is_suspended;
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bool hold_rpm_on_boot;
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struct exynos_iommu_event_log log;
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int no_rpm_control;
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};
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struct exynos_vm_region {
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struct list_head node;
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u32 start;
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u32 size;
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u32 section_off;
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u32 dummy_size;
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};
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struct exynos_iovmm {
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struct iommu_domain *domain; /* iommu domain for this iovmm */
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size_t iovm_size; /* iovm bitmap size per plane */
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u32 iova_start; /* iovm start address per plane */
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unsigned long *vm_map; /* iovm biatmap per plane */
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struct list_head regions_list; /* list of exynos_vm_region */
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spinlock_t vmlist_lock; /* lock for updating regions_list */
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spinlock_t bitmap_lock; /* lock for manipulating bitmaps */
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struct device *dev; /* peripheral device that has this iovmm */
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size_t allocated_size;
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int num_areas;
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unsigned int num_map;
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unsigned int num_unmap;
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const char *domain_name;
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struct iommu_group *group;
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struct exynos_iommu_event_log log;
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};
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void exynos_sysmmu_tlb_invalidate(struct iommu_domain *domain, dma_addr_t start,
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size_t size);
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int exynos_iommu_map_userptr(struct iommu_domain *dom, unsigned long addr,
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dma_addr_t iova, size_t size, int prot);
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void exynos_iommu_unmap_userptr(struct iommu_domain *dom,
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dma_addr_t iova, size_t size);
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int exynos_iommu_add_fault_handler(struct device *dev,
|
|
iommu_fault_handler_t handler, void *token);
|
|
|
|
static inline bool get_sysmmu_runtime_active(struct sysmmu_drvdata *data)
|
|
{
|
|
return ++data->runtime_active == 1 && !data->no_rpm_control;
|
|
}
|
|
|
|
static inline bool put_sysmmu_runtime_active(struct sysmmu_drvdata *data)
|
|
{
|
|
BUG_ON(data->runtime_active < 1);
|
|
return --data->runtime_active == 0 && !data->no_rpm_control;
|
|
}
|
|
|
|
static inline bool is_sysmmu_runtime_active(struct sysmmu_drvdata *data)
|
|
{
|
|
return data->runtime_active > 0 && !data->no_rpm_control;
|
|
}
|
|
|
|
static inline bool is_runtime_active_or_enabled(struct sysmmu_drvdata *data)
|
|
{
|
|
return is_sysmmu_runtime_active(data) ||
|
|
data->no_rpm_control == SYSMMU_STATE_ENABLED;
|
|
}
|
|
|
|
static inline bool set_sysmmu_active(struct sysmmu_drvdata *data)
|
|
{
|
|
/* return true if the System MMU was not active previously
|
|
and it needs to be initialized */
|
|
return ++data->activations == 1;
|
|
}
|
|
|
|
static inline bool set_sysmmu_inactive(struct sysmmu_drvdata *data)
|
|
{
|
|
/* return true if the System MMU is needed to be disabled */
|
|
BUG_ON(data->activations < 1);
|
|
return --data->activations == 0;
|
|
}
|
|
|
|
static inline bool is_sysmmu_active(struct sysmmu_drvdata *data)
|
|
{
|
|
return !data->is_suspended && data->activations > 0;
|
|
}
|
|
|
|
static inline void __raw_sysmmu_enable(void __iomem *sfrbase)
|
|
{
|
|
__raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL);
|
|
}
|
|
|
|
#define sysmmu_unblock __raw_sysmmu_enable
|
|
|
|
void dump_sysmmu_tlb_pb(void __iomem *sfrbase);
|
|
|
|
static inline bool sysmmu_block(void __iomem *sfrbase)
|
|
{
|
|
int i = SYSMMU_BLOCK_POLLING_COUNT;
|
|
|
|
__raw_writel(CTRL_BLOCK, sfrbase + REG_MMU_CTRL);
|
|
while ((i > 0) && !(__raw_readl(sfrbase + REG_MMU_STATUS) & 1))
|
|
--i;
|
|
|
|
if (!(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) {
|
|
/*
|
|
* TODO: dump_sysmmu_tlb_pb(sfrbase);
|
|
*/
|
|
panic("Failed to block System MMU!");
|
|
sysmmu_unblock(sfrbase);
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
static inline sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova)
|
|
{
|
|
return (sysmmu_pte_t *)(phys_to_virt(lv2table_base(sent))) +
|
|
lv2ent_offset(iova);
|
|
}
|
|
|
|
static inline sysmmu_pte_t *section_entry(
|
|
sysmmu_pte_t *pgtable, sysmmu_iova_t iova)
|
|
{
|
|
return (sysmmu_pte_t *)(pgtable + lv1ent_offset(iova));
|
|
}
|
|
|
|
static inline struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom)
|
|
{
|
|
return container_of(dom, struct exynos_iommu_domain, domain);
|
|
}
|
|
|
|
#if defined(CONFIG_EXYNOS_IOVMM)
|
|
static inline struct exynos_iovmm *exynos_get_iovmm(struct device *dev)
|
|
{
|
|
if (!dev->archdata.iommu) {
|
|
dev_err(dev, "%s: System MMU is not configured\n", __func__);
|
|
return NULL;
|
|
}
|
|
|
|
return ((struct exynos_iommu_owner *)dev->archdata.iommu)->vmm_data;
|
|
}
|
|
|
|
struct exynos_vm_region *find_iovm_region(struct exynos_iovmm *vmm,
|
|
dma_addr_t iova);
|
|
|
|
struct exynos_iovmm *exynos_create_single_iovmm(const char *name,
|
|
unsigned int start, unsigned int end);
|
|
#else
|
|
static inline struct exynos_iovmm *exynos_get_iovmm(struct device *dev)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
struct exynos_vm_region *find_iovm_region(struct exynos_iovmm *vmm,
|
|
dma_addr_t iova)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
static inline struct exynos_iovmm *exynos_create_single_iovmm(const char *name,
|
|
unsigned int start, unsigned int end);
|
|
{
|
|
return NULL;
|
|
}
|
|
#endif /* CONFIG_EXYNOS_IOVMM */
|
|
|
|
#endif /* _EXYNOS_IOMMU_H_ */
|