693 lines
20 KiB
C
Executable File
693 lines
20 KiB
C
Executable File
/* linux/drivers/iommu/exynos_iommu-reg.h
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*
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* Copyright (c) 2017 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "exynos-iommu.h"
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#include <dt-bindings/sysmmu/sysmmu.h>
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#ifdef CONFIG_SEC_DEBUG_AUTO_COMMENT
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#include <linux/sec_debug.h>
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#endif
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#define is_secure_info_fail(x) ((((x) >> 16) & 0xffff) == 0xdead)
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static inline u32 __secure_info_read(unsigned int addr)
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{
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u32 ret;
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ret = exynos_smc(SMC_DRM_SEC_SMMU_INFO, (unsigned long)addr,
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0, SEC_SMMU_SFR_READ);
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if (is_secure_info_fail(ret))
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pr_err("Invalid value returned, %#x\n", ret);
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return ret;
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}
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static inline void __sysmmu_tlb_invalidate_all(void __iomem *sfrbase)
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{
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writel(0x1, sfrbase + REG_MMU_FLUSH);
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}
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static inline void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *drvdata,
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dma_addr_t iova, size_t size)
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{
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void * __iomem sfrbase = drvdata->sfrbase;
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__raw_writel(iova, sfrbase + REG_FLUSH_RANGE_START);
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__raw_writel(size - 1 + iova, sfrbase + REG_FLUSH_RANGE_END);
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writel(0x1, sfrbase + REG_MMU_FLUSH_RANGE);
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SYSMMU_EVENT_LOG_TLB_INV_RANGE(SYSMMU_DRVDATA_TO_LOG(drvdata),
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iova, iova + size);
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}
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static inline void __sysmmu_set_ptbase(struct sysmmu_drvdata *drvdata,
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phys_addr_t pfn_pgtable)
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{
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void * __iomem sfrbase = drvdata->sfrbase;
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writel_relaxed(pfn_pgtable, sfrbase + REG_PT_BASE_PPN);
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__sysmmu_tlb_invalidate_all(sfrbase);
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SYSMMU_EVENT_LOG_TLB_INV_ALL(
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SYSMMU_DRVDATA_TO_LOG(drvdata));
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}
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static inline unsigned int dump_tlb_entry_way_type(void __iomem *sfrbase,
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int idx_way, int idx_set)
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{
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if (MMU_TLB_ENTRY_VALID(__raw_readl(sfrbase + REG_TLB_ATTR))) {
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pr_auto(ASL4, "[%02d][%02d] VPN: %#010x, PPN: %#010x, ATTR: %#010x\n",
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idx_way, idx_set,
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__raw_readl(sfrbase + REG_TLB_VPN),
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__raw_readl(sfrbase + REG_TLB_PPN),
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__raw_readl(sfrbase + REG_TLB_ATTR));
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return 1;
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}
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return 0;
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}
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static inline void sysmmu_tlb_compare(phys_addr_t pgtable,
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int idx_sub, u32 vpn, u32 ppn)
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{
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sysmmu_pte_t *entry;
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unsigned long vaddr = MMU_VADDR_FROM_TLB((unsigned long)vpn, idx_sub);
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unsigned long paddr = MMU_PADDR_FROM_TLB((unsigned long)ppn);
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unsigned long phys = 0;
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if (!pgtable)
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return;
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entry = section_entry(phys_to_virt(pgtable), vaddr);
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if (lv1ent_section(entry)) {
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phys = section_phys(entry);
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} else if (lv1ent_page(entry)) {
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entry = page_entry(entry, vaddr);
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if (lv2ent_large(entry))
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phys = lpage_phys(entry);
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else if (lv2ent_small(entry))
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phys = spage_phys(entry);
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} else {
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pr_auto(ASL4, ">> Invalid address detected! entry: %#lx",
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(unsigned long)*entry);
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return;
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}
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if (paddr != phys) {
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pr_auto(ASL4, ">> TLB mismatch detected!\n");
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pr_auto(ASL4, " TLB: %#010lx, PT entry: %#010lx\n", paddr, phys);
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}
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}
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static inline unsigned int dump_tlb_entry_port_type(void __iomem *sfrbase,
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phys_addr_t pgtable, int idx_way, int idx_set, int idx_sub)
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{
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if (MMU_TLB_ENTRY_VALID(__raw_readl(sfrbase + REG_CAPA1_TLB_ATTR))) {
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u32 vpn, ppn, attr;
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vpn = __raw_readl(sfrbase + REG_CAPA1_TLB_VPN);
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ppn = __raw_readl(sfrbase + REG_CAPA1_TLB_PPN);
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attr = __raw_readl(sfrbase + REG_CAPA1_TLB_ATTR);
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pr_auto(ASL4, "[%02d][%02d] VPN: %#010x, PPN: %#010x, ATTR: %#010x\n",
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idx_way, idx_set, vpn, ppn, attr);
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sysmmu_tlb_compare(pgtable, idx_sub, vpn, ppn);
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return 1;
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}
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return 0;
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}
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#define MMU_NUM_TLB_SUBLINE 4
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static inline void dump_sysmmu_tlb_way(struct sysmmu_drvdata *drvdata)
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{
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int i, j, k;
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u32 capa;
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unsigned int cnt;
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void __iomem *sfrbase = drvdata->sfrbase;
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capa = __raw_readl(sfrbase + REG_MMU_CAPA0_V7);
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pr_auto(ASL4, "TLB has %d way, %d set. SBB has %d entries.\n",
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MMU_CAPA_NUM_TLB_WAY(capa),
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(1 << MMU_CAPA_NUM_TLB_SET(capa)),
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(1 << MMU_CAPA_NUM_SBB_ENTRY(capa)));
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pr_auto(ASL4, "------------- TLB[WAY][SET][ENTRY] -------------\n");
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for (i = 0, cnt = 0; i < MMU_CAPA_NUM_TLB_WAY(capa); i++) {
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for (j = 0; j < (1 << MMU_CAPA_NUM_TLB_SET(capa)); j++) {
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for (k = 0; k < MMU_NUM_TLB_SUBLINE; k++) {
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__raw_writel(MMU_SET_TLB_READ_ENTRY(j, i, k),
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sfrbase + REG_TLB_READ);
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cnt += dump_tlb_entry_way_type(sfrbase, i, j);
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}
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}
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}
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if (!cnt)
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pr_auto(ASL4, ">> No Valid TLB Entries\n");
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pr_auto(ASL4, "--- SBB(Second-Level Page Table Base Address Buffer ---\n");
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for (i = 0, cnt = 0; i < (1 << MMU_CAPA_NUM_SBB_ENTRY(capa)); i++) {
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__raw_writel(i, sfrbase + REG_SBB_READ);
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if (MMU_SBB_ENTRY_VALID(__raw_readl(sfrbase + REG_SBB_VPN))) {
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pr_auto(ASL4, "[%02d] VPN: %#010x, PPN: %#010x, ATTR: %#010x\n",
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i, __raw_readl(sfrbase + REG_SBB_VPN),
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__raw_readl(sfrbase + REG_SBB_LINK),
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__raw_readl(sfrbase + REG_SBB_ATTR));
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cnt++;
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}
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}
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if (!cnt)
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pr_auto(ASL4, ">> No Valid SBB Entries\n");
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}
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static inline void sysmmu_sbb_compare(u32 sbb_vpn, u32 sbb_link,
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phys_addr_t pgtable)
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{
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sysmmu_pte_t *entry;
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unsigned long vaddr = MMU_VADDR_FROM_SBB((unsigned long)sbb_vpn);
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unsigned long paddr = MMU_PADDR_FROM_SBB((unsigned long)sbb_link);
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unsigned long phys = 0;
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if (!pgtable)
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return;
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entry = section_entry(phys_to_virt(pgtable), vaddr);
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if (lv1ent_page(entry)) {
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phys = lv2table_base(entry);
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if (paddr != phys) {
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pr_auto(ASL4, ">> SBB mismatch detected!\n");
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pr_auto(ASL4, " entry addr: %lx / SBB addr %lx\n",
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paddr, phys);
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}
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} else {
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pr_auto(ASL4, ">> Invalid address detected! entry: %#lx",
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(unsigned long)*entry);
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}
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}
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static inline void dump_sysmmu_tlb_port(struct sysmmu_drvdata *drvdata,
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phys_addr_t pgtable)
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{
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int t, i, j, k;
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u32 capa0, capa1, info;
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u32 sbb_vpn, sbb_link;
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unsigned int cnt;
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int num_tlb, num_port, num_sbb;
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void __iomem *sfrbase = drvdata->sfrbase;
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capa0 = __raw_readl(sfrbase + REG_MMU_CAPA0_V7);
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capa1 = __raw_readl(sfrbase + REG_MMU_CAPA1_V7);
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num_tlb = MMU_CAPA1_NUM_TLB(capa1);
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num_port = MMU_CAPA1_NUM_PORT(capa1);
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num_sbb = 1 << MMU_CAPA_NUM_SBB_ENTRY(capa0);
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pr_crit("SysMMU has %d TLBs, %d ports, %d sbb entries\n",
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num_tlb, num_port, num_sbb);
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for (t = 0; t < num_tlb; t++) {
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int num_set, num_way;
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info = __raw_readl(sfrbase + MMU_TLB_INFO(t));
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num_way = MMU_CAPA1_NUM_TLB_WAY(info);
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num_set = MMU_CAPA1_NUM_TLB_SET(info);
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pr_crit("TLB.%d has %d way, %d set.\n", t, num_way, num_set);
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pr_crit("------------- TLB[WAY][SET][ENTRY] -------------\n");
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for (i = 0, cnt = 0; i < num_way; i++) {
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for (j = 0; j < num_set; j++) {
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for (k = 0; k < MMU_NUM_TLB_SUBLINE; k++) {
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__raw_writel(MMU_CAPA1_SET_TLB_READ_ENTRY(t, j, i, k),
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sfrbase + REG_CAPA1_TLB_READ);
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cnt += dump_tlb_entry_port_type(
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sfrbase, pgtable, i, j, k);
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}
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}
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}
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}
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if (!cnt)
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pr_auto(ASL4, ">> No Valid TLB Entries\n");
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pr_crit("--- SBB(Second-Level Page Table Base Address Buffer) ---\n");
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for (i = 0, cnt = 0; i < num_sbb; i++) {
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__raw_writel(i, sfrbase + REG_CAPA1_SBB_READ);
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if (MMU_SBB_ENTRY_VALID(__raw_readl(sfrbase + REG_CAPA1_SBB_VPN))) {
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sbb_vpn = __raw_readl(sfrbase + REG_CAPA1_SBB_VPN);
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sbb_link = __raw_readl(sfrbase + REG_CAPA1_SBB_LINK);
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pr_crit("[%02d] VPN: %#010x, PPN: %#010x, ATTR: %#010x\n",
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i, sbb_vpn, sbb_link,
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__raw_readl(sfrbase + REG_CAPA1_SBB_ATTR));
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sysmmu_sbb_compare(sbb_vpn, sbb_link, pgtable);
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cnt++;
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}
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}
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if (!cnt)
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pr_auto(ASL4, ">> No Valid SBB Entries\n");
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}
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static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
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"PTW ACCESS FAULT",
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"PAGE FAULT",
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"L1TLB MULTI-HIT FAULT",
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"ACCESS FAULT",
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"SECURITY FAULT",
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"UNKNOWN FAULT"
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};
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static inline void dump_sysmmu_status(struct sysmmu_drvdata *drvdata,
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phys_addr_t pgtable)
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{
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int info;
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pgd_t *pgd;
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pud_t *pud;
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pmd_t *pmd;
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pte_t *pte;
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phys_addr_t phys;
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void __iomem *sfrbase = drvdata->sfrbase;
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pgd = pgd_offset_k((unsigned long)sfrbase);
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if (!pgd) {
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pr_auto(ASL4, "Invalid virtual address %p\n", sfrbase);
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return;
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}
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pud = pud_offset(pgd, (unsigned long)sfrbase);
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if (!pud) {
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pr_auto(ASL4, "Invalid virtual address %p\n", sfrbase);
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return;
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}
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pmd = pmd_offset(pud, (unsigned long)sfrbase);
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if (!pmd) {
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pr_auto(ASL4, "Invalid virtual address %p\n", sfrbase);
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return;
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}
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pte = pte_offset_kernel(pmd, (unsigned long)sfrbase);
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if (!pte) {
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pr_auto(ASL4, "Invalid virtual address %p\n", sfrbase);
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return;
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}
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info = MMU_RAW_VER(__raw_readl(sfrbase + REG_MMU_VERSION));
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phys = pte_pfn(*pte) << PAGE_SHIFT;
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pr_auto(ASL4, "ADDR: %pa(VA: %p), MMU_CTRL: %#010x, PT_BASE: %#010x\n",
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&phys, sfrbase,
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__raw_readl(sfrbase + REG_MMU_CTRL),
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__raw_readl(sfrbase + REG_PT_BASE_PPN));
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pr_auto(ASL4, "VERSION %d.%d.%d, MMU_CFG: %#010x, MMU_STATUS: %#010x\n",
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MMU_MAJ_VER(info), MMU_MIN_VER(info), MMU_REV_VER(info),
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__raw_readl(sfrbase + REG_MMU_CFG),
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__raw_readl(sfrbase + REG_MMU_STATUS));
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if (IS_TLB_WAY_TYPE(drvdata))
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dump_sysmmu_tlb_way(drvdata);
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else if(IS_TLB_PORT_TYPE(drvdata))
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dump_sysmmu_tlb_port(drvdata, pgtable);
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}
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static inline void show_secure_fault_information(struct sysmmu_drvdata *drvdata,
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int flags, unsigned long fault_addr)
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{
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unsigned int info;
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phys_addr_t pgtable;
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int fault_id = SYSMMU_FAULT_ID(flags);
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unsigned int sfrbase = drvdata->securebase;
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const char *port_name = NULL;
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#ifdef CONFIG_SEC_DEBUG_EXTRA_INFO
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char temp_buf[SZ_128];
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#endif
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pgtable = __secure_info_read(sfrbase + REG_PT_BASE_PPN);
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pgtable <<= PAGE_SHIFT;
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info = __secure_info_read(sfrbase + REG_FAULT_TRANS_INFO);
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of_property_read_string(drvdata->sysmmu->of_node,
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"port-name", &port_name);
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pr_auto_once(4);
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pr_auto(ASL4, "----------------------------------------------------------\n");
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pr_auto(ASL4, "From [%s], SysMMU %s %s at %#010lx (page table @ %pa)\n",
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port_name ? port_name : dev_name(drvdata->sysmmu),
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(flags & IOMMU_FAULT_WRITE) ? "WRITE" : "READ",
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sysmmu_fault_name[fault_id], fault_addr, &pgtable);
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#ifdef CONFIG_SEC_DEBUG_EXTRA_INFO
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snprintf(temp_buf, SZ_128, "%s %s %s at %#010lx (%pa)",
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port_name ? port_name : dev_name(drvdata->sysmmu),
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(flags & IOMMU_FAULT_WRITE) ? "WRITE" : "READ",
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sysmmu_fault_name[fault_id], fault_addr, &pgtable);
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sec_debug_set_extra_info_sysmmu(temp_buf);
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#endif
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if (fault_id == SYSMMU_FAULT_UNKNOWN) {
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pr_auto(ASL4, "The fault is not caused by this System MMU.\n");
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pr_auto(ASL4, "Please check IRQ and SFR base address.\n");
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goto finish;
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}
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pr_auto(ASL4, "AxID: %#x, AxLEN: %#x\n", info & 0xFFFF, (info >> 16) & 0xF);
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if (fault_id == SYSMMU_FAULT_PTW_ACCESS)
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pr_auto(ASL4, "System MMU has failed to access page table\n");
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if (!pfn_valid(pgtable >> PAGE_SHIFT)) {
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pr_auto(ASL4, "Page table base is not in a valid memory region\n");
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} else {
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sysmmu_pte_t *ent;
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ent = section_entry(phys_to_virt(pgtable), fault_addr);
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pr_auto(ASL4, "Lv1 entry: %#010x\n", *ent);
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if (lv1ent_page(ent)) {
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ent = page_entry(ent, fault_addr);
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pr_auto(ASL4, "Lv2 entry: %#010x\n", *ent);
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}
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}
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info = MMU_RAW_VER(__secure_info_read(sfrbase + REG_MMU_VERSION));
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pr_auto(ASL4, "ADDR: %#x, MMU_CTRL: %#010x, PT_BASE: %#010x\n",
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sfrbase,
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__secure_info_read(sfrbase + REG_MMU_CTRL),
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__secure_info_read(sfrbase + REG_PT_BASE_PPN));
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pr_auto(ASL4, "VERSION %d.%d.%d, MMU_CFG: %#010x, MMU_STATUS: %#010x\n",
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MMU_MAJ_VER(info), MMU_MIN_VER(info), MMU_REV_VER(info),
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__secure_info_read(sfrbase + REG_MMU_CFG),
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__secure_info_read(sfrbase + REG_MMU_STATUS));
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finish:
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pr_auto(ASL4, "----------------------------------------------------------\n");
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pr_auto_disable(4);
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}
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static inline int show_fault_information(struct sysmmu_drvdata *drvdata,
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int flags, unsigned long fault_addr)
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{
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unsigned int info;
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phys_addr_t pgtable;
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int fault_id = SYSMMU_FAULT_ID(flags);
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const char *port_name = NULL;
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static int ptw_count = 0;
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#ifdef CONFIG_SEC_DEBUG_EXTRA_INFO
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char temp_buf[SZ_128];
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#endif
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pgtable = __raw_readl(drvdata->sfrbase + REG_PT_BASE_PPN);
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pgtable <<= PAGE_SHIFT;
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info = __raw_readl(drvdata->sfrbase + REG_FAULT_TRANS_INFO);
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of_property_read_string(drvdata->sysmmu->of_node,
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"port-name", &port_name);
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pr_auto_once(4);
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pr_auto(ASL4, "----------------------------------------------------------\n");
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pr_auto(ASL4, "From [%s], SysMMU %s %s at %#010lx (page table @ %pa)\n",
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port_name ? port_name : dev_name(drvdata->sysmmu),
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(flags & IOMMU_FAULT_WRITE) ? "WRITE" : "READ",
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sysmmu_fault_name[fault_id], fault_addr, &pgtable);
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#ifdef CONFIG_SEC_DEBUG_EXTRA_INFO
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snprintf(temp_buf, SZ_128, "%s %s %s at %#010lx (%pa)",
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port_name ? port_name : dev_name(drvdata->sysmmu),
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(flags & IOMMU_FAULT_WRITE) ? "WRITE" : "READ",
|
|
sysmmu_fault_name[fault_id], fault_addr, &pgtable);
|
|
sec_debug_set_extra_info_sysmmu(temp_buf);
|
|
#endif
|
|
|
|
if (fault_id == SYSMMU_FAULT_UNKNOWN) {
|
|
pr_auto(ASL4, "The fault is not caused by this System MMU.\n");
|
|
pr_auto(ASL4, "Please check IRQ and SFR base address.\n");
|
|
goto finish;
|
|
}
|
|
|
|
pr_auto(ASL4, "AxID: %#x, AxLEN: %#x\n", info & 0xFFFF, (info >> 16) & 0xF);
|
|
|
|
if (pgtable != drvdata->pgtable)
|
|
pr_auto(ASL4, "Page table base of driver: %pa\n",
|
|
&drvdata->pgtable);
|
|
|
|
if (!pfn_valid(pgtable >> PAGE_SHIFT)) {
|
|
pr_auto(ASL4, "Page table base is not in a valid memory region\n");
|
|
pgtable = 0;
|
|
} else {
|
|
sysmmu_pte_t *ent;
|
|
ent = section_entry(phys_to_virt(pgtable), fault_addr);
|
|
pr_auto(ASL4, "Lv1 entry: %#010x\n", *ent);
|
|
|
|
if (lv1ent_page(ent)) {
|
|
ent = page_entry(ent, fault_addr);
|
|
pr_auto(ASL4, "Lv2 entry: %#010x\n", *ent);
|
|
}
|
|
}
|
|
|
|
if (fault_id == SYSMMU_FAULT_PTW_ACCESS) {
|
|
ptw_count++;
|
|
pr_auto(ASL4, "System MMU has failed to access page table, %d\n", ptw_count);
|
|
pgtable = 0;
|
|
|
|
if (ptw_count > 3)
|
|
panic("Unrecoverable System MMU PTW fault");
|
|
|
|
writel(0x1, drvdata->sfrbase + REG_INT_CLEAR);
|
|
|
|
return -EAGAIN;
|
|
}
|
|
|
|
dump_sysmmu_status(drvdata, pgtable);
|
|
|
|
finish:
|
|
pr_auto(ASL4, "----------------------------------------------------------\n");
|
|
pr_auto_disable(4);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline void __sysmmu_disable_nocount(struct sysmmu_drvdata *drvdata)
|
|
{
|
|
writel_relaxed(0, drvdata->sfrbase + REG_MMU_CFG);
|
|
writel_relaxed(CTRL_BLOCK_DISABLE, drvdata->sfrbase + REG_MMU_CTRL);
|
|
BUG_ON(readl_relaxed(drvdata->sfrbase + REG_MMU_CTRL) != CTRL_BLOCK_DISABLE);
|
|
|
|
clk_disable(drvdata->clk);
|
|
|
|
SYSMMU_EVENT_LOG_DISABLE(SYSMMU_DRVDATA_TO_LOG(drvdata));
|
|
}
|
|
|
|
static inline void __sysmmu_set_public_way(struct sysmmu_drvdata *drvdata,
|
|
unsigned int public_cfg)
|
|
{
|
|
u32 cfg = __raw_readl(drvdata->sfrbase + REG_PUBLIC_WAY_CFG);
|
|
cfg &= ~MMU_PUBLIC_WAY_MASK;
|
|
cfg |= public_cfg;
|
|
|
|
writel_relaxed(cfg, drvdata->sfrbase + REG_PUBLIC_WAY_CFG);
|
|
|
|
dev_dbg(drvdata->sysmmu, "public_cfg : %#x\n", cfg);
|
|
}
|
|
|
|
static inline void __sysmmu_set_private_way_id(struct sysmmu_drvdata *drvdata,
|
|
unsigned int way_idx)
|
|
{
|
|
struct tlb_priv_id *priv_cfg = drvdata->tlb_props.way_props.priv_id_cfg;
|
|
u32 cfg = __raw_readl(drvdata->sfrbase + REG_PRIVATE_WAY_CFG(way_idx));
|
|
|
|
cfg &= ~MMU_PRIVATE_WAY_MASK;
|
|
cfg |= MMU_WAY_CFG_ID_MATCHING | MMU_WAY_CFG_PRIVATE_ENABLE |
|
|
priv_cfg[way_idx].cfg;
|
|
|
|
writel_relaxed(cfg, drvdata->sfrbase + REG_PRIVATE_WAY_CFG(way_idx));
|
|
writel_relaxed(priv_cfg[way_idx].id,
|
|
drvdata->sfrbase + REG_PRIVATE_ID(way_idx));
|
|
|
|
dev_dbg(drvdata->sysmmu, "priv ID way[%d] cfg : %#x, id : %#x\n",
|
|
way_idx, cfg, priv_cfg[way_idx].id);
|
|
}
|
|
|
|
static inline void __sysmmu_set_private_way_addr(struct sysmmu_drvdata *drvdata,
|
|
unsigned int priv_addr_idx)
|
|
{
|
|
struct tlb_priv_addr *priv_cfg =
|
|
drvdata->tlb_props.way_props.priv_addr_cfg;
|
|
unsigned int way_idx =
|
|
drvdata->tlb_props.way_props.priv_id_cnt + priv_addr_idx;
|
|
u32 cfg = __raw_readl(drvdata->sfrbase + REG_PRIVATE_WAY_CFG(way_idx));
|
|
|
|
cfg &= ~MMU_PRIVATE_WAY_MASK;
|
|
cfg |= MMU_WAY_CFG_ADDR_MATCHING | MMU_WAY_CFG_PRIVATE_ENABLE |
|
|
priv_cfg[priv_addr_idx].cfg;
|
|
|
|
writel_relaxed(cfg, drvdata->sfrbase + REG_PRIVATE_WAY_CFG(way_idx));
|
|
|
|
dev_dbg(drvdata->sysmmu, "priv ADDR way[%d] cfg : %#x\n", way_idx, cfg);
|
|
}
|
|
|
|
static inline void __sysmmu_set_tlb_way_type(struct sysmmu_drvdata *drvdata)
|
|
{
|
|
u32 cfg = __raw_readl(drvdata->sfrbase + REG_MMU_CAPA0_V7);
|
|
u32 tlb_way_num = MMU_CAPA_NUM_TLB_WAY(cfg);
|
|
u32 set_cnt = 0;
|
|
struct tlb_props *tlb_props = &drvdata->tlb_props;
|
|
unsigned int i;
|
|
int priv_id_cnt = tlb_props->way_props.priv_id_cnt;
|
|
int priv_addr_cnt = tlb_props->way_props.priv_addr_cnt;
|
|
|
|
if (tlb_props->flags & TLB_WAY_PUBLIC)
|
|
__sysmmu_set_public_way(drvdata,
|
|
tlb_props->way_props.public_cfg);
|
|
|
|
if (tlb_props->flags & TLB_WAY_PRIVATE_ID) {
|
|
for (i = 0; i < priv_id_cnt &&
|
|
set_cnt < tlb_way_num; i++, set_cnt++)
|
|
__sysmmu_set_private_way_id(drvdata, i);
|
|
}
|
|
|
|
if (tlb_props->flags & TLB_WAY_PRIVATE_ADDR) {
|
|
for (i = 0; i < priv_addr_cnt &&
|
|
set_cnt < tlb_way_num; i++, set_cnt++)
|
|
__sysmmu_set_private_way_addr(drvdata, i);
|
|
}
|
|
|
|
if (priv_id_cnt + priv_addr_cnt > tlb_way_num) {
|
|
dev_warn(drvdata->sysmmu,
|
|
"Too many values than TLB way count %d,"
|
|
" so ignored!\n", tlb_way_num);
|
|
dev_warn(drvdata->sysmmu,
|
|
"Number of private way id/addr = %d/%d\n",
|
|
priv_id_cnt, priv_addr_cnt);
|
|
}
|
|
}
|
|
|
|
static inline void __sysmmu_set_tlb_port(struct sysmmu_drvdata *drvdata,
|
|
unsigned int port_idx)
|
|
{
|
|
struct tlb_port_cfg *port_cfg = drvdata->tlb_props.port_props.port_cfg;
|
|
|
|
writel_relaxed(MMU_TLB_CFG_MASK(port_cfg[port_idx].cfg),
|
|
drvdata->sfrbase + REG_MMU_TLB_CFG(port_idx));
|
|
|
|
/* port_idx 0 is default port. */
|
|
if (port_idx == 0) {
|
|
dev_dbg(drvdata->sysmmu, "port[%d] cfg : %#x for common\n",
|
|
port_idx,
|
|
MMU_TLB_CFG_MASK(port_cfg[port_idx].cfg));
|
|
return;
|
|
}
|
|
|
|
writel_relaxed(MMU_TLB_MATCH_CFG_MASK(port_cfg[port_idx].cfg),
|
|
drvdata->sfrbase + REG_MMU_TLB_MATCH_CFG(port_idx));
|
|
writel_relaxed(port_cfg[port_idx].id,
|
|
drvdata->sfrbase + REG_MMU_TLB_MATCH_ID(port_idx));
|
|
|
|
dev_dbg(drvdata->sysmmu, "port[%d] cfg : %#x, match : %#x, id : %#x\n",
|
|
port_idx,
|
|
MMU_TLB_CFG_MASK(port_cfg[port_idx].cfg),
|
|
MMU_TLB_MATCH_CFG_MASK(port_cfg[port_idx].cfg),
|
|
port_cfg[port_idx].id);
|
|
}
|
|
|
|
static inline void __sysmmu_set_tlb_port_type(struct sysmmu_drvdata *drvdata)
|
|
{
|
|
u32 cfg = __raw_readl(drvdata->sfrbase + REG_MMU_CAPA1_V7);
|
|
u32 tlb_num = MMU_CAPA1_NUM_TLB(cfg);
|
|
struct tlb_props *tlb_props = &drvdata->tlb_props;
|
|
unsigned int i;
|
|
int port_id_cnt = tlb_props->port_props.port_id_cnt;
|
|
int slot_cnt = tlb_props->port_props.slot_cnt;
|
|
|
|
if (port_id_cnt > tlb_num) {
|
|
dev_warn(drvdata->sysmmu,
|
|
"Too many values %d than TLB count %d,"
|
|
" so ignored!\n", port_id_cnt, tlb_num);
|
|
port_id_cnt = tlb_num;
|
|
}
|
|
|
|
for (i = 0; i < port_id_cnt; i++)
|
|
__sysmmu_set_tlb_port(drvdata, i);
|
|
|
|
for (i = 0; i < slot_cnt; i++)
|
|
writel_relaxed(tlb_props->port_props.slot_cfg[i],
|
|
drvdata->sfrbase + REG_SLOT_RSV(i));
|
|
}
|
|
|
|
static inline void __sysmmu_init_config(struct sysmmu_drvdata *drvdata)
|
|
{
|
|
unsigned long cfg = 0;
|
|
|
|
if (IS_TLB_WAY_TYPE(drvdata))
|
|
__sysmmu_set_tlb_way_type(drvdata);
|
|
else if (IS_TLB_PORT_TYPE(drvdata))
|
|
__sysmmu_set_tlb_port_type(drvdata);
|
|
|
|
if (drvdata->qos != DEFAULT_QOS_VALUE)
|
|
cfg |= CFG_QOS_OVRRIDE | CFG_QOS(drvdata->qos);
|
|
|
|
cfg |= __raw_readl(drvdata->sfrbase + REG_MMU_CFG) & ~CFG_MASK;
|
|
writel_relaxed(cfg, drvdata->sfrbase + REG_MMU_CFG);
|
|
}
|
|
|
|
static inline void __sysmmu_enable_nocount(struct sysmmu_drvdata *drvdata)
|
|
{
|
|
clk_enable(drvdata->clk);
|
|
|
|
__sysmmu_init_config(drvdata);
|
|
|
|
__sysmmu_set_ptbase(drvdata, drvdata->pgtable / PAGE_SIZE);
|
|
|
|
writel(CTRL_ENABLE, drvdata->sfrbase + REG_MMU_CTRL);
|
|
|
|
SYSMMU_EVENT_LOG_ENABLE(SYSMMU_DRVDATA_TO_LOG(drvdata));
|
|
}
|
|
|
|
static inline u32 __sysmmu_get_intr_status(struct sysmmu_drvdata *drvdata,
|
|
bool is_secure)
|
|
{
|
|
if (is_secure)
|
|
return __secure_info_read(drvdata->securebase + REG_INT_STATUS);
|
|
else
|
|
return __raw_readl(drvdata->sfrbase + REG_INT_STATUS);
|
|
}
|
|
|
|
static inline u32 __sysmmu_get_fault_address(struct sysmmu_drvdata *drvdata,
|
|
bool is_secure)
|
|
{
|
|
if (is_secure)
|
|
return __secure_info_read(drvdata->securebase + REG_FAULT_ADDR);
|
|
else
|
|
return __raw_readl(drvdata->sfrbase + REG_FAULT_ADDR);
|
|
}
|
|
|
|
static inline u32 __sysmmu_get_fault_trans_info(struct sysmmu_drvdata *drvdata,
|
|
bool is_secure)
|
|
{
|
|
if (is_secure)
|
|
return __secure_info_read(
|
|
drvdata->securebase + REG_FAULT_TRANS_INFO);
|
|
else
|
|
return __raw_readl(drvdata->sfrbase + REG_FAULT_TRANS_INFO);
|
|
}
|
|
|
|
static inline u32 __sysmmu_get_hw_version(struct sysmmu_drvdata *data)
|
|
{
|
|
return MMU_RAW_VER(__raw_readl(data->sfrbase + REG_MMU_VERSION));
|
|
}
|
|
|
|
static inline bool __sysmmu_has_capa1(struct sysmmu_drvdata *data)
|
|
{
|
|
return MMU_CAPA1_EXIST(__raw_readl(data->sfrbase + REG_MMU_CAPA0_V7));
|
|
}
|
|
|
|
static inline u32 __sysmmu_get_capa_type(struct sysmmu_drvdata *data)
|
|
{
|
|
return MMU_CAPA1_TYPE(__raw_readl(data->sfrbase + REG_MMU_CAPA1_V7));
|
|
}
|