187 lines
5.1 KiB
C
Executable File
187 lines
5.1 KiB
C
Executable File
/*
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* Copyright 2014 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __CORESIGHT_REGS_H
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#define __CORESIGHT_REGS_H
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#include <linux/kernel.h>
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#include <linux/types.h>
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#define OSLOCK_MAGIC (0xc5acce55)
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/* Defines are used by core-sight */
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#define CS_SJTAG_OFFSET (0x8000)
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#define SJTAG_STATUS (0x4)
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#define SJTAG_SOFT_LOCK (1<<2)
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/* DBG Registers */
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#define DBGWFAR (0x018) /* RW */
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#define DBGVCR (0x01c) /* RW */
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#define DBGECR (0x024) /* RW or RAZ */
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#define DBGDSCCR (0x028) /* RW or RAZ */
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#define DBGDSMCR (0x02c) /* RW or RAZ */
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#define DBGDTRRX (0x080) /* RW */
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#define DBGITR (0x084) /* RW */
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#define DBGDSCR (0x088) /* RW */
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#define DBGDTRTX (0x08c) /* RW */
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#define DBGDRCR (0x090) /* WO */
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#define DBGEACR (0x094) /* RW */
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#define DBGECCR (0x098) /* RW */
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#define DBGPCSRlo (0x0a0) /* RO */
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#define DBGCIDSR (0x0a4) /* RO */
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#define DBGVIDSR (0x0a8) /* RO */
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#define DBGPCSRhi (0x0ac) /* RO */
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#define DBGBXVR0 (0x250) /* RW */
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#define DBGBXVR1 (0x254) /* RW */
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#define DBGOSLAR (0x300) /* WO */
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#define DBGOSLSR (0x304) /* RO */
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#define DBGPRCR (0x310) /* RW */
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#define DBGPRSR (0x314) /* RO, OSLSR in ARMv8 */
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#define DBGITOCTRL (0xef8) /* WO */
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#define DBGITISR (0xefc) /* RO */
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#define DBGITCTRL (0xf00) /* RW */
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#define DBGCLAIMSET (0xfa0) /* RW */
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#define DBGCLAIMCLR (0xfa4) /* RW */
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#define DBGLAR (0xfb0) /* WO */
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#define DBGLSR (0xfb4) /* RO */
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#define DBGAUTHSTATUS (0xfb8) /* RO */
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#define DBGDEVID2 (0xfc0) /* RO */
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#define DBGDEVID1 (0xfc4) /* RO, PC offset */
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#define DBGDEVID0 (0xfc8) /* RO */
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#define DBGDEVTYPE (0xfcc) /* RO */
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#define MIDR (0xd00) /* RO */
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#define ID_AA64DFR0_EL1 (0xd28)
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/* DBG breakpoint registers (All RW) */
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#define DBGBVRn(n) (0x400 + (n * 0x10)) /* 64bit */
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#define DBGBCRn(n) (0x408 + (n * 0x10))
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/* DBG watchpoint registers (All RW) */
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#define DBGWVRn(n) (0x800 + (n * 0x10)) /* 64bit */
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#define DBGWCRn(n) (0x808 + (n * 0x10))
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/* DIDR or ID_AA64DFR0_EL1 bit */
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#define DEBUG_ARCH_V8 (0x6)
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/* MIDR bit */
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#define ARMV8_PROCESSOR (0xf << 16)
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#define ARMV8_CORTEXA53 (0xd03)
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#define ARMV8_CORTEXA57 (0xd07)
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/* TMC(ETB/ETF/ETR) registers */
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#define TMCRSZ (0x004)
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#define TMCSTS (0x00c)
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#define TMCRRD (0x010)
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#define TMCRRP (0x014)
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#define TMCRWP (0x018)
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#define TMCTGR (0x01c)
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#define TMCCTL (0x020)
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#define TMCRWD (0x024)
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#define TMCMODE (0x028)
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#define TMCLBUFLEVEL (0x02c)
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#define TMCCBUFLEVEL (0x030)
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#define TMCBUFWM (0x034)
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#define TMCRRPHI (0x038)
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#define TMCRWPHI (0x03c)
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#define TMCAXICTL (0x110)
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#define TMCDBALO (0x118)
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#define TMCDBAHI (0x11c)
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#define TMCFFSR (0x300)
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#define TMCFFCR (0x304)
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#define TMCPSCR (0x308)
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/* Coresight manager register */
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#define ITCTRL (0xf00)
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#define CLAIMSET (0xfa0)
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#define CLAIMCLR (0xfa4)
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#define LAR (0xfb0)
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#define LSR (0xfb4)
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#define AUTHSTATUS (0xfb8)
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/* FUNNEL configuration register */
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#define FUNCTRL (0x0)
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#define FUNPRIORCTRL (0x4)
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#define DBG_OFFSET (0x0)
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#define CTI_OFFSET (0x10000)
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#define PMU_OFFSET (0x20000)
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#define ETM_OFFSET (0x30000)
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#define PMUPCSRlo (0x200)
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#define PMUPCSRhi (0x204)
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/* ETM registers */
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#define ETMCTLR (0x004)
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#define ETMPROCSELR (0x008)
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#define ETMSTATUS (0x00c)
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#define ETMCONFIG (0x010)
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#define ETMAUXCTLR (0x018)
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#define ETMEVENTCTL0R (0x020)
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#define ETMEVENTCTL1R (0x024)
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#define ETMSTALLCTLR (0x02c)
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#define ETMTSCTLR (0x030)
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#define ETMSYNCPR (0x034)
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#define ETMCCCCTLR (0x038)
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#define ETMBBCTLR (0x03c)
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#define ETMTRACEIDR (0x040)
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#define ETMQCTRLR (0x044)
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#define ETMVICTLR (0x080)
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#define ETMVIIECTLR (0x084)
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#define ETMVISSCTLR (0x088)
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#define ETMVIPCSSCTLR (0x08c)
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#define ETMVDCTLR (0x0a0)
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#define ETMVDSACCTLR (0x0a4)
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#define ETMVDARCCTLR (0x0a8)
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#define ETMSEQEVR(n) (0x100 + (n * 4))
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#define ETMSEQRSTEVR (0x118)
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#define ETMSEQSTR (0x11c)
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#define ETMEXTINSELR (0x120)
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#define ETMCNTRLDVR(n) (0x140 + (n * 4))
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#define ETMCNTCTLR(n) (0x150 + (n * 4))
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#define ETMCNTVR(n) (0x160 + (n * 4))
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#define ETMIDR8 (0x180)
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#define ETMIDR9 (0x184)
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#define ETMID10 (0x188)
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#define ETMID11 (0x18c)
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#define ETMID12 (0x190)
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#define ETMID13 (0x194)
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#define ETMID0 (0x1e0)
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#define ETMID1 (0x1e4)
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#define ETMID2 (0x1e8)
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#define ETMID3 (0x1ec)
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#define ETMID4 (0x1f0)
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#define ETMID5 (0x1f4)
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#define ETMID6 (0x1f8)
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#define ETMID7 (0x1fc)
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#define ETMRSCTLR(n) (0x200 + (n * 4))
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#define ETMSSCCR(n) (0x280 + (n * 4))
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#define ETMSSCSR(n) (0x2a0 + (n * 4))
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#define ETMSSPCICR(n) (0x2c0 + (n * 4))
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#define ETMOSLAR (0x300)
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#define ETMOSLSR (0x304)
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#define ETMPDCR (0x310)
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#define ETMPDSR (0x314)
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#define ETMACVR(n) (0x400 + (n * 4))
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#define ETMACAT(n) (0x480 + (n * 4))
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#define ETMDVCVR(n) (0x500 + (n * 4))
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#define ETMDVCMR(n) (0x580 + (n * 4))
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#define ETMCIDCVR(n) (0x600 + (n * 4))
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#define ETMVMIDCVR(n) (0x640 + (n * 4))
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#define ETMCCIDCCTLR0 (0x680)
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#define ETMCCIDCCTLR1 (0x684)
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#define ETMVMIDCCTLR0 (0x688)
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#define ETMVMIDCCTLR1 (0x68c)
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#ifdef CONFIG_EXYNOS_CORESIGHT_ETM
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extern void exynos_trace_stop(void);
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#else
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#define exynos_trace_stop() do { } while(0)
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#endif
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#endif
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