/** * core.c - DesignWare USB3 DRD Controller Core file * * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com * * Authors: Felipe Balbi , * Sebastian Andrzej Siewior * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 of * the License as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "core.h" #include "otg.h" #include "gadget.h" #include "io.h" #include "debug.h" #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ /* for BC1.2 spec */ int dwc3_set_vbus_current(int state) { struct power_supply *psy; union power_supply_propval pval = {0}; psy = power_supply_get_by_name("battery"); if (!psy) { pr_err("%s: fail to get battery power_supply\n", __func__); return -1; } pval.intval = state; power_supply_set_property(psy, (enum power_supply_property)POWER_SUPPLY_EXT_PROP_USB_CONFIGURE, &pval); power_supply_put(psy); return 0; } static void dwc3_exynos_set_vbus_current_work(struct work_struct *w) { struct dwc3 *dwc = container_of(w, struct dwc3, set_vbus_current_work); struct otg_notify *o_notify = get_otg_notify(); switch (dwc->vbus_current) { case USB_CURRENT_SUSPENDED: /* set vbus current for suspend state is called in usb_notify. */ send_otg_notify(o_notify, NOTIFY_EVENT_USBD_SUSPEND, 1); goto skip; case USB_CURRENT_UNCONFIGURED: send_otg_notify(o_notify, NOTIFY_EVENT_USBD_UNCONFIGURE, 1); break; case USB_CURRENT_HIGH_SPEED: case USB_CURRENT_SUPER_SPEED: send_otg_notify(o_notify, NOTIFY_EVENT_USBD_CONFIGURE, 1); break; default: break; } dwc3_set_vbus_current(dwc->vbus_current); skip: return; } /* -------------------------------------------------------------------------- */ /** * dwc3_get_dr_mode - Validates and sets dr_mode * @dwc: pointer to our context structure */ /* Remove warning - Check later! static int dwc3_get_dr_mode(struct dwc3 *dwc) { enum usb_dr_mode mode; struct device *dev = dwc->dev; unsigned int hw_mode; if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) dwc->dr_mode = USB_DR_MODE_OTG; mode = dwc->dr_mode; hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); switch (hw_mode) { case DWC3_GHWPARAMS0_MODE_GADGET: if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { dev_err(dev, "Controller does not support host mode.\n"); return -EINVAL; } mode = USB_DR_MODE_PERIPHERAL; break; case DWC3_GHWPARAMS0_MODE_HOST: if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { dev_err(dev, "Controller does not support device mode.\n"); return -EINVAL; } mode = USB_DR_MODE_HOST; break; default: if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) mode = USB_DR_MODE_HOST; else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) mode = USB_DR_MODE_PERIPHERAL; } if (mode != dwc->dr_mode) { dev_warn(dev, "Configuration mismatch. dr_mode forced to %s\n", mode == USB_DR_MODE_HOST ? "host" : "gadget"); dwc->dr_mode = mode; } return 0; } */ void dwc3_event_buffers_cleanup(struct dwc3 *dwc); int dwc3_event_buffers_setup(struct dwc3 *dwc); static void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) { u32 reg; reg = dwc3_readl(dwc->regs, DWC3_GCTL); reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); reg |= DWC3_GCTL_PRTCAPDIR(mode); dwc3_writel(dwc->regs, DWC3_GCTL, reg); } /* static void __dwc3_set_mode(struct work_struct *work) { struct dwc3 *dwc = work_to_dwc(work); unsigned long flags; int ret; if (!dwc->desired_dr_role) return; if (dwc->desired_dr_role == dwc->current_dr_role) return; if (dwc->dr_mode != USB_DR_MODE_OTG) return; if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG) return; switch (dwc->current_dr_role) { case DWC3_GCTL_PRTCAP_HOST: dwc3_host_exit(dwc); break; case DWC3_GCTL_PRTCAP_DEVICE: dwc3_gadget_exit(dwc); dwc3_event_buffers_cleanup(dwc); break; default: break; } spin_lock_irqsave(&dwc->lock, flags); dwc3_set_prtcap(dwc, dwc->desired_dr_role); dwc->current_dr_role = dwc->desired_dr_role; spin_unlock_irqrestore(&dwc->lock, flags); switch (dwc->desired_dr_role) { case DWC3_GCTL_PRTCAP_HOST: ret = dwc3_host_init(dwc); if (ret) { dev_err(dwc->dev, "failed to initialize host\n"); } else { if (dwc->usb2_phy) otg_set_vbus(dwc->usb2_phy->otg, true); if (dwc->usb2_generic_phy) phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); } break; case DWC3_GCTL_PRTCAP_DEVICE: dwc3_event_buffers_setup(dwc); if (dwc->usb2_phy) otg_set_vbus(dwc->usb2_phy->otg, false); if (dwc->usb2_generic_phy) phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); ret = dwc3_gadget_init(dwc); if (ret) dev_err(dwc->dev, "failed to initialize peripheral\n"); break; default: break; } } void dwc3_set_mode(struct dwc3 *dwc, u32 mode) { unsigned long flags; spin_lock_irqsave(&dwc->lock, flags); dwc->desired_dr_role = mode; spin_unlock_irqrestore(&dwc->lock, flags); queue_work(system_freezable_wq, &dwc->drd_work); } */ void dwc3_set_mode(struct dwc3 *dwc, u32 mode) { u32 reg; reg = dwc3_readl(dwc->regs, DWC3_GCTL); reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); reg |= DWC3_GCTL_PRTCAPDIR(mode); dwc3_writel(dwc->regs, DWC3_GCTL, reg); } void dwc3_core_config(struct dwc3 *dwc) { u32 reg; /* AHB bus configuration */ reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); reg |= (DWC3_GSBUSCFG0_INCRBRSTEN | DWC3_GSBUSCFG0_INCR16BRSTEN); /** * AXI Bus' cache type configuration for DMA transfer. * By below setting, cache type was set to Cacheable/Modifiable. * From DWC USB3.0 Link version 2.20A, this cache type could be set. */ if (dwc->revision >= DWC3_REVISION_220A) reg |= (DWC3_GSBUSCFG0_DESWRREQINFO | DWC3_GSBUSCFG0_DATWRREQINFO | DWC3_GSBUSCFG0_DESRDREQINFO | DWC3_GSBUSCFG0_DATRDREQINFO); dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg); reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG1); reg |= (DWC3_GSBUSCFG1_BREQLIMIT(3)); dwc3_writel(dwc->regs, DWC3_GSBUSCFG1, reg); /* * WORKAROUND: * For ss bulk-in data packet, when the host detects * a DPP error or the internal buffer becomes full, * it retries with an ACK TP Retry=1. Under the following * conditions, the Retry=1 is falsely carried over to the next * DWC3_GUCTL_USBHSTINAUTORETRYEN should be set to a one * regardless of revision * - There is only single active asynchronous SS EP at the time. * - The active asynchronous EP is a Bulk IN EP. * - The burst with the correctly Retry=1 ACK TP and * the next burst belong to the same transfer. */ reg = dwc3_readl(dwc->regs, DWC3_GUCTL); reg |= (DWC3_GUCTL_USBHSTINAUTORETRYEN); if (dwc->adj_sof_accuracy) { reg &= ~DWC3_GUCTL_REFCLKPER_MASK; /* fix ITP interval time to 125us */ reg |= DWC3_GUCTL_REFCLKPER(0x14); } if (dwc->dis_u2_freeclk_exists_quirk) { reg &= ~DWC3_GUCTL_REFCLKPER_MASK; /* fix ITP interval time to 125us */ reg |= DWC3_GUCTL_REFCLKPER(0xF); } if (dwc->sparse_transfer_control) reg |= DWC3_GUCTL_SPRSCTRLTRANSEN; dwc3_writel(dwc->regs, DWC3_GUCTL, reg); if (dwc->revision >= DWC3_REVISION_190A && dwc->revision <= DWC3_REVISION_210A) { reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); reg &= ~(DWC3_GRXTHRCFG_USBRXPKTCNT_MASK | DWC3_GRXTHRCFG_USBMAXRXBURSTSIZE_MASK); reg |= (DWC3_GRXTHRCFG_USBRXPKTCNTSEL | DWC3_GRXTHRCFG_USBRXPKTCNT(3) | DWC3_GRXTHRCFG_USBMAXRXBURSTSIZE(3)); dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); } /* * WORKAROUND: DWC3 revisions 2.10a and earlier have a bug * The delay of the entry to a low power state such that * for applications where the link stays in a non-U0 state * for a short duration(< 1 microsecond), * the local PHY does not enter the low power state prior * to receiving a potential LFPS wakeup. * This causes the PHY CDR (Clock and Data Recovery) operation * to be unstable for some Synopsys PHYs. * The proposal now is to change the default and the recommended value * for GUSB3PIPECTL[21:19] in the RTL from 3'b100 to a minimum of 3'b001 */ if (dwc->revision <= DWC3_REVISION_210A) { reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); reg &= ~(DWC3_GUSB3PIPECTL_DEP1P2P3_MASK); reg |= (DWC3_GUSB3PIPECTL_DEP1P2P3_EN); dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); } if (dwc->revision >= DWC3_REVISION_250A) { reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); } if (dwc->revision >= DWC3_REVISION_250A) { reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); } if (dwc->revision >= DWC3_REVISION_250A) { reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); } if (dwc->revision >= DWC3_REVISION_250A) { reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); } reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); if (dwc->ux_exit_in_px_quirk) reg |= DWC3_GUSB3PIPECTL_UX_EXIT_PX; if (dwc->elastic_buf_mode_quirk) reg |= DWC3_ELASTIC_BUFFER_MODE; dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); if (dwc->revision > DWC3_USB31_REVISION_120A) { reg = dwc3_readl(dwc->regs, DWC3_LLUCTL); reg |= (DWC3_PENDING_HP_TIMER_US(0xb) | DWC3_EN_US_HP_TIMER); dwc3_writel(dwc->regs, DWC3_LLUCTL, reg); reg = dwc3_readl(dwc->regs, DWC3_LSKIPFREQ); reg |= (DWC3_PM_ENTRY_TIMER_US(0x9) | DWC3_PM_LC_TIMER_US(0x5) | DWC3_EN_PM_TIMER_US); dwc3_writel(dwc->regs, DWC3_LSKIPFREQ, reg); } /* * WORKAROUND: DWC3 revisions 2.10a and earlier have a bug * Race Condition in PORTSC Write Followed by Read * If the software quickly does a read to the PORTSC, * some fields (port status change related fields * like OCC, etc.) may not have correct value * due to the current way of handling these bits. * After clearing the status register (for example, OCC) bit * by writing PORTSC tregister, software can insert some delay * (for example, 5 mac2_clk -> UTMI clock = 60 MHz -> * (16.66 ns x 5 = 84ns)) before reading the PORTSC to check status. */ if (dwc->revision <= DWC3_REVISION_210A) { reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); reg |= (DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT)); dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); } } u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) { struct dwc3 *dwc = dep->dwc; u32 reg; dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, DWC3_GDBGFIFOSPACE_NUM(dep->number) | DWC3_GDBGFIFOSPACE_TYPE(type)); reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); } /** * dwc3_core_soft_reset - Issues core soft reset and PHY reset * @dwc: pointer to our context structure */ static int dwc3_core_soft_reset(struct dwc3 *dwc) { u32 reg; int retries = 1000; int ret; ret = phy_power_on(dwc->usb3_generic_phy); if (ret < 0) return ret; ret = phy_power_on(dwc->usb2_generic_phy); if (ret < 0) goto err_usb3phy_power; usb_phy_init(dwc->usb2_phy); usb_phy_init(dwc->usb3_phy); ret = phy_init(dwc->usb2_generic_phy); if (ret < 0) goto err_usb2phy_power; ret = phy_init(dwc->usb3_generic_phy); if (ret < 0) goto err_usb2phy_init; /* * We're resetting only the device side because, if we're in host mode, * XHCI driver will reset the host block. If dwc3 was configured for * host-only mode, then we can return early. */ if (dwc->dr_mode == USB_DR_MODE_HOST) return 0; reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg |= DWC3_DCTL_CSFTRST; dwc3_writel(dwc->regs, DWC3_DCTL, reg); do { reg = dwc3_readl(dwc->regs, DWC3_DCTL); if (!(reg & DWC3_DCTL_CSFTRST)) return 0; udelay(1); } while (--retries); phy_exit(dwc->usb3_generic_phy); phy_exit(dwc->usb2_generic_phy); return -ETIMEDOUT; err_usb2phy_init: phy_exit(dwc->usb2_generic_phy); err_usb2phy_power: phy_power_off(dwc->usb2_generic_phy); err_usb3phy_power: phy_power_off(dwc->usb3_generic_phy); return ret; } /** * dwc3_soft_reset - Issue soft reset * @dwc: Pointer to our controller context structure */ int dwc3_soft_reset(struct dwc3 *dwc) { unsigned long timeout; u32 reg; timeout = jiffies + msecs_to_jiffies(500); dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); do { reg = dwc3_readl(dwc->regs, DWC3_DCTL); if (!(reg & DWC3_DCTL_CSFTRST)) break; if (time_after(jiffies, timeout)) { dev_err(dwc->dev, "Reset Timed Out\n"); return -ETIMEDOUT; } cpu_relax(); } while (true); return 0; } /* * dwc3_frame_length_adjustment - Adjusts frame length if required * @dwc3: Pointer to our controller context structure */ static void dwc3_frame_length_adjustment(struct dwc3 *dwc) { u32 reg; u32 dft; if (dwc->revision < DWC3_REVISION_250A) return; if (dwc->fladj == 0) return; reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); dft = reg & DWC3_GFLADJ_30MHZ_MASK; /*if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj, * "request value same as default, ignoring\n")) { */ if(dft != dwc->fladj) { reg &= ~DWC3_GFLADJ_30MHZ_MASK; reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); } } /** * dwc3_free_one_event_buffer - Frees one event buffer * @dwc: Pointer to our controller context structure * @evt: Pointer to event buffer to be freed */ static void dwc3_free_one_event_buffer(struct dwc3 *dwc, struct dwc3_event_buffer *evt) { dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); } /** * dwc3_alloc_one_event_buffer - Allocates one event buffer structure * @dwc: Pointer to our controller context structure * @length: size of the event buffer * * Returns a pointer to the allocated event buffer structure on success * otherwise ERR_PTR(errno). */ static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length) { struct dwc3_event_buffer *evt; evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); if (!evt) return ERR_PTR(-ENOMEM); evt->dwc = dwc; evt->length = length; evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); if (!evt->cache) return ERR_PTR(-ENOMEM); evt->buf = dma_alloc_coherent(dwc->sysdev, length, &evt->dma, GFP_KERNEL); if (!evt->buf) return ERR_PTR(-ENOMEM); return evt; } /** * dwc3_free_event_buffers - frees all allocated event buffers * @dwc: Pointer to our controller context structure */ static void dwc3_free_event_buffers(struct dwc3 *dwc) { struct dwc3_event_buffer *evt; evt = dwc->ev_buf; if (evt) dwc3_free_one_event_buffer(dwc, evt); } /** * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length * @dwc: pointer to our controller context structure * @length: size of event buffer * * Returns 0 on success otherwise negative errno. In the error case, dwc * may contain some buffers allocated but not all which were requested. */ static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) { struct dwc3_event_buffer *evt; evt = dwc3_alloc_one_event_buffer(dwc, length); if (IS_ERR(evt)) { dev_err(dwc->dev, "can't allocate event buffer\n"); return PTR_ERR(evt); } dwc->ev_buf = evt; return 0; } /** * dwc3_event_buffers_setup - setup our allocated event buffers * @dwc: pointer to our controller context structure * * Returns 0 on success otherwise negative errno. */ int dwc3_event_buffers_setup(struct dwc3 *dwc) { struct dwc3_event_buffer *evt; evt = dwc->ev_buf; evt->lpos = 0; dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), lower_32_bits(evt->dma)); dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), upper_32_bits(evt->dma)); dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_SIZE(evt->length)); dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); return 0; } void dwc3_event_buffers_cleanup(struct dwc3 *dwc) { struct dwc3_event_buffer *evt; u32 left = 0; evt = dwc->ev_buf; evt->lpos = 0; dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK | DWC3_GEVNTSIZ_SIZE(0)); left = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); left &= DWC3_GEVNTCOUNT_MASK; while (left > 0) { dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4); left -= 4; } } static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) { if (!dwc->has_hibernation) return 0; if (!dwc->nr_scratch) return 0; dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); if (!dwc->scratchbuf) return -ENOMEM; return 0; } static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) { dma_addr_t scratch_addr; u32 param; int ret; if (!dwc->has_hibernation) return 0; if (!dwc->nr_scratch) return 0; /* should never fall here */ if (!WARN_ON(dwc->scratchbuf)) return 0; scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); if (dma_mapping_error(dwc->sysdev, scratch_addr)) { dev_err(dwc->sysdev, "failed to map scratch buffer\n"); ret = -EFAULT; goto err0; } dwc->scratch_addr = scratch_addr; param = lower_32_bits(scratch_addr); ret = dwc3_send_gadget_generic_command(dwc, DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); if (ret < 0) goto err1; param = upper_32_bits(scratch_addr); ret = dwc3_send_gadget_generic_command(dwc, DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); if (ret < 0) goto err1; return 0; err1: dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); err0: return ret; } static void dwc3_free_scratch_buffers(struct dwc3 *dwc) { if (!dwc->has_hibernation) return; if (!dwc->nr_scratch) return; /* should never fall here */ if (!WARN_ON(dwc->scratchbuf)) return; dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); kfree(dwc->scratchbuf); } static void dwc3_core_num_eps(struct dwc3 *dwc) { struct dwc3_hwparams *parms = &dwc->hwparams; dwc->num_eps = DWC3_NUM_EPS(parms); } static void dwc3_cache_hwparams(struct dwc3 *dwc) { struct dwc3_hwparams *parms = &dwc->hwparams; parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); } /** * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core * @dwc: Pointer to our controller context structure * * Returns 0 on success. The USB PHY interfaces are configured but not * initialized. The PHY interfaces and the PHYs get initialized together with * the core in dwc3_core_init. */ int dwc3_phy_setup(struct dwc3 *dwc) { u32 reg; int ret; reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); if (dwc->ux_exit_in_px_quirk) reg |= DWC3_GUSB3PIPECTL_UX_EXIT_PX; else reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; /* * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY * to '0' during coreConsultant configuration. So default value * will be '0' when the core is reset. Application needs to set it * to '1' after the core initialization is completed. */ if (dwc->revision > DWC3_REVISION_194A) reg |= DWC3_GUSB3PIPECTL_SUSPHY; if (dwc->u2ss_inp3_quirk) reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; if (dwc->dis_rxdet_inp3_quirk) reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; if (dwc->u1u2_exitfail_to_recov_quirk) reg |= DWC3_GUSB3PIPECTL_U1U2EXITFAIL_TO_RECOV; if (dwc->req_p1p2p3_quirk) reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; if (dwc->del_p1p2p3_quirk) reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; if (dwc->del_phy_power_chg_quirk) reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; if (dwc->lfps_filter_quirk) reg |= DWC3_GUSB3PIPECTL_LFPSFILT; if (dwc->rx_detect_poll_quirk) reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; if (dwc->tx_de_emphasis_quirk) reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); if (dwc->dis_u3_susphy_quirk) reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; if (dwc->dis_del_phy_power_chg_quirk) reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); /* Select the HS PHY interface */ switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: if (dwc->hsphy_interface && !strncmp(dwc->hsphy_interface, "utmi", 4)) { reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; break; } else if (dwc->hsphy_interface && !strncmp(dwc->hsphy_interface, "ulpi", 4)) { reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); } else { /* Relying on default value. */ if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) break; } /* FALLTHROUGH */ case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: ret = dwc3_ulpi_init(dwc); if (ret) return ret; /* FALLTHROUGH */ default: break; } switch (dwc->hsphy_mode) { case USBPHY_INTERFACE_MODE_UTMI: reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); break; case USBPHY_INTERFACE_MODE_UTMIW: reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); break; default: break; } /* * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to * '0' during coreConsultant configuration. So default value will * be '0' when the core is reset. Application needs to set it to * '1' after the core initialization is completed. */ if (dwc->revision > DWC3_REVISION_194A) reg |= DWC3_GUSB2PHYCFG_SUSPHY; if (dwc->dis_u2_susphy_quirk) reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; if (dwc->dis_enblslpm_quirk) reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; if (dwc->dis_u2_freeclk_exists_quirk) reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; if (dwc->adj_sof_accuracy) reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); return 0; } void dwc3_core_exit(struct dwc3 *dwc) { dwc3_event_buffers_cleanup(dwc); usb_phy_shutdown(dwc->usb2_phy); usb_phy_shutdown(dwc->usb3_phy); phy_exit(dwc->usb2_generic_phy); phy_exit(dwc->usb3_generic_phy); usb_phy_set_suspend(dwc->usb2_phy, 1); usb_phy_set_suspend(dwc->usb3_phy, 1); phy_power_off(dwc->usb2_generic_phy); phy_power_off(dwc->usb3_generic_phy); dwc->link_state = DWC3_LINK_STATE_SS_DIS; } static bool dwc3_core_is_valid(struct dwc3 *dwc) { u32 reg; reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); /* This should read as U3 followed by revision number */ if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) { /* Detected DWC_usb3 IP */ dwc->revision = reg; } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) { /* Detected DWC_usb31 IP */ dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); dwc->revision |= DWC3_REVISION_IS_DWC31; } else { return false; } return true; } static void dwc3_core_setup_global_control(struct dwc3 *dwc) { u32 hwparams4 = dwc->hwparams.hwparams4; u32 reg; reg = dwc3_readl(dwc->regs, DWC3_GCTL); reg &= ~DWC3_GCTL_SCALEDOWN_MASK; switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { case DWC3_GHWPARAMS1_EN_PWROPT_CLK: /** * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an * issue which would cause xHCI compliance tests to fail. * * Because of that we cannot enable clock gating on such * configurations. * * Refers to: * * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based * SOF/ITP Mode Used */ if ((dwc->dr_mode == USB_DR_MODE_HOST || dwc->dr_mode == USB_DR_MODE_OTG) && (dwc->revision >= DWC3_REVISION_210A && dwc->revision <= DWC3_REVISION_250A)) reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; else reg &= ~DWC3_GCTL_DSBLCLKGTNG; break; case DWC3_GHWPARAMS1_EN_PWROPT_HIB: /* enable hibernation here */ dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); /* * REVISIT Enabling this bit so that host-mode hibernation * will work. Device-mode hibernation is not yet implemented. */ reg |= DWC3_GCTL_GBLHIBERNATIONEN; break; default: /* nothing */ break; } /* check if current dwc3 is on simulation board */ if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { dev_info(dwc->dev, "Running with FPGA optmizations\n"); dwc->is_fpga = true; } WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, "disable_scramble cannot be used on non-FPGA builds\n"); if (dwc->disable_scramble_quirk && dwc->is_fpga) reg |= DWC3_GCTL_DISSCRAMBLE; else reg &= ~DWC3_GCTL_DISSCRAMBLE; if (dwc->u2exit_lfps_quirk) reg |= DWC3_GCTL_U2EXIT_LFPS; /* * WORKAROUND: DWC3 revisions <1.90a have a bug * where the device can fail to connect at SuperSpeed * and falls back to high-speed mode which causes * the device to enter a Connect/Disconnect loop */ if (dwc->revision < DWC3_REVISION_190A) reg |= DWC3_GCTL_U2RSTECN; if (dwc->adj_sof_accuracy) { reg &= ~DWC3_GCTL_SOFITPSYNC; reg |= DWC3_GCTL_DSBLCLKGTNG; } dwc3_writel(dwc->regs, DWC3_GCTL, reg); } static int dwc3_core_get_phy(struct dwc3 *dwc); /** * dwc3_core_init - Low-level initialization of DWC3 Core * @dwc: Pointer to our controller context structure * * Returns 0 on success otherwise negative errno. */ int dwc3_core_init(struct dwc3 *dwc) { u32 reg; struct dwc3_otg *dotg = dwc->dotg; int ret; if (!dwc3_core_is_valid(dwc)) { dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); ret = -ENODEV; goto err0; } /* * Write Linux Version Code to our GUID register so it's easy to figure * out which kernel version a bug was found. */ dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); /* Handle USB2.0-only core configuration */ if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { if (dwc->maximum_speed == USB_SPEED_SUPER) dwc->maximum_speed = USB_SPEED_HIGH; } ret = dwc3_core_get_phy(dwc); if (ret) goto err0; /* Adjust SOF accuracy only for revisions >= 2.50a */ if (dwc->revision < DWC3_REVISION_250A) dwc->adj_sof_accuracy = 0; ret = dwc3_core_soft_reset(dwc); if (ret) goto err0; ret = dwc3_phy_setup(dwc); if (ret) goto err0; if (dotg) { phy_tune(dwc->usb2_generic_phy, dotg->otg.state); phy_tune(dwc->usb3_generic_phy, dotg->otg.state); } else { phy_tune(dwc->usb2_generic_phy, 0); phy_tune(dwc->usb3_generic_phy, 0); } dwc3_core_setup_global_control(dwc); dwc3_core_num_eps(dwc); dwc->suspend_clk_freq = 50000000; dev_info(dwc->dev, "%s: max speed:%d, hibernation:%d, nr_scratch:%d\n", __func__, dwc->maximum_speed, dwc->has_hibernation, dwc->nr_scratch); ret = dwc3_setup_scratch_buffers(dwc); if (ret) goto err1; /* Adjust Frame Length */ dwc3_frame_length_adjustment(dwc); usb_phy_set_suspend(dwc->usb2_phy, 0); usb_phy_set_suspend(dwc->usb3_phy, 0); ret = dwc3_event_buffers_setup(dwc); if (ret) { dev_err(dwc->dev, "failed to setup event buffers\n"); goto err2; } /* * ENDXFER polling is available on version 3.10a and later of * the DWC_usb3 controller. It is NOT available in the * DWC_usb31 controller. */ if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) { reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); reg |= DWC3_GUCTL2_RST_ACTBITLATER; dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); } if (dwc->revision >= DWC3_REVISION_250A) { reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); /* * Enable hardware control of sending remote wakeup * in HS when the device is in the L1 state. */ if (dwc->revision >= DWC3_REVISION_290A) reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; if (dwc->dis_tx_ipgap_linecheck_quirk) reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); } dwc3_core_config(dwc); if (dwc->adj_sof_accuracy) { reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); reg &= ~DWC3_GFLADJ_REFCLK_240MHZDECR_PLS1; reg &= ~DWC3_GFLADJ_REFCLK_240MHZ_DECR_MASK; reg |= DWC3_GFLADJ_REFCLK_240MHZ_DECR(0xA); reg |= DWC3_GFLADJ_REFCLK_LPM_SEL; reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK; reg |= DWC3_GFLADJ_REFCLK_FLADJ(0x7F0); dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); } dwc->link_state = DWC3_LINK_STATE_U0; return 0; err2: phy_power_off(dwc->usb3_generic_phy); phy_power_off(dwc->usb2_generic_phy); usb_phy_set_suspend(dwc->usb2_phy, 1); usb_phy_set_suspend(dwc->usb3_phy, 1); err1: usb_phy_shutdown(dwc->usb2_phy); usb_phy_shutdown(dwc->usb3_phy); phy_exit(dwc->usb2_generic_phy); phy_exit(dwc->usb3_generic_phy); phy_power_off(dwc->usb2_generic_phy); phy_power_off(dwc->usb3_generic_phy); dwc->link_state = DWC3_LINK_STATE_SS_DIS; err0: return ret; } static int dwc3_core_get_phy(struct dwc3 *dwc) { struct device *dev = dwc->dev; struct device_node *node = dev->of_node; int ret; if (node) { dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); } else { dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); } if (IS_ERR(dwc->usb2_phy)) { ret = PTR_ERR(dwc->usb2_phy); if (ret == -ENXIO || ret == -ENODEV) { dwc->usb2_phy = NULL; } else if (ret == -EPROBE_DEFER) { return ret; } else { dev_err(dev, "no usb2 phy configured\n"); return ret; } } if (IS_ERR(dwc->usb3_phy)) { ret = PTR_ERR(dwc->usb3_phy); if (ret == -ENXIO || ret == -ENODEV) { dwc->usb3_phy = NULL; } else if (ret == -EPROBE_DEFER) { return ret; } else { dev_err(dev, "no usb3 phy configured\n"); return ret; } } dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); if (IS_ERR(dwc->usb2_generic_phy)) { ret = PTR_ERR(dwc->usb2_generic_phy); if (ret == -ENOSYS || ret == -ENODEV) { dwc->usb2_generic_phy = NULL; } else if (ret == -EPROBE_DEFER) { return ret; } else { dev_err(dev, "no usb2 phy configured\n"); return ret; } } dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); if (IS_ERR(dwc->usb3_generic_phy)) { ret = PTR_ERR(dwc->usb3_generic_phy); if (ret == -ENOSYS || ret == -ENODEV) { dwc->usb3_generic_phy = NULL; } else if (ret == -EPROBE_DEFER) { return ret; } else { dev_err(dev, "no usb3 phy configured\n"); return ret; } } return 0; } static int dwc3_core_init_mode(struct dwc3 *dwc) { struct device *dev = dwc->dev; int ret; switch (dwc->dr_mode) { case USB_DR_MODE_PERIPHERAL: dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); if (dwc->usb2_phy) otg_set_vbus(dwc->usb2_phy->otg, false); if (dwc->usb2_generic_phy) phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); ret = dwc3_gadget_init(dwc); if (ret) { if (ret != -EPROBE_DEFER) dev_err(dev, "failed to initialize gadget\n"); return ret; } break; case USB_DR_MODE_HOST: dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); if (dwc->usb2_phy) otg_set_vbus(dwc->usb2_phy->otg, true); if (dwc->usb2_generic_phy) phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); ret = dwc3_host_init(dwc); if (ret) { if (ret != -EPROBE_DEFER) dev_err(dev, "failed to initialize host\n"); return ret; } break; case USB_DR_MODE_OTG: ret = dwc3_otg_init(dwc); if (ret) { dev_err(dev, "failed to initialize otg\n"); return ret; } /* turn off PHYs to save power */ dwc3_core_exit(dwc); ret = dwc3_host_init(dwc); if (ret) { if (ret != -EPROBE_DEFER) dev_err(dev, "failed to initialize host\n"); dwc3_otg_exit(dwc); return ret; } ret = dwc3_gadget_init(dwc); if (ret) { if (ret != -EPROBE_DEFER) dev_err(dev, "failed to initialize gadget\n"); dwc3_host_exit(dwc); dwc3_otg_exit(dwc); return ret; } /* Now we are ready to start OTG */ ret = dwc3_otg_start(dwc); if (ret) { dev_err(dev, "failed to start otg\n"); dwc3_host_exit(dwc); dwc3_gadget_exit(dwc); dwc3_otg_exit(dwc); return ret; } /* Unblock runtime PM for OTG */ pm_runtime_put_sync(dev); /* New drd routine in Kernel 4.14 */ /* INIT_WORK(&dwc->drd_work, __dwc3_set_mode); ret = dwc3_drd_init(dwc); if (ret) { if (ret != -EPROBE_DEFER) dev_err(dev, "failed to initialize dual-role\n"); return ret; } */ break; default: dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); return -EINVAL; } return 0; } static void dwc3_core_exit_mode(struct dwc3 *dwc) { switch (dwc->dr_mode) { case USB_DR_MODE_PERIPHERAL: dwc3_gadget_exit(dwc); break; case USB_DR_MODE_HOST: dwc3_host_exit(dwc); break; case USB_DR_MODE_OTG: dwc3_drd_exit(dwc); break; default: /* do nothing */ break; } } static int dwc3_get_option(struct dwc3 *dwc) { struct device *dev = dwc->dev; struct device_node *node = dev->of_node; int value; if (!of_property_read_u32(node, "adj-sof-accuracy", &value)) { dwc->adj_sof_accuracy = value ? true : false; } else { dev_err(dev, "can't get adj-sof-accuracy from %s node", node->name); return -EINVAL; } if (!of_property_read_u32(node, "is_not_vbus_pad", &value)) { dwc->is_not_vbus_pad = value ? true : false; } else { dev_err(dev, "can't get is_not_vbus_pad from %s node", node->name); return -EINVAL; } if (!of_property_read_u32(node, "enable_sprs_transfer", &value)) { dwc->sparse_transfer_control = value ? true : false; } else { dev_err(dev, "can't get sprs-xfer-ctrl from %s node", node->name); return -EINVAL; } return 0; } static void dwc3_get_properties(struct dwc3 *dwc) { struct device *dev = dwc->dev; u8 lpm_nyet_threshold; u8 tx_de_emphasis; u8 hird_threshold; int ret; /* default to highest possible threshold */ lpm_nyet_threshold = 0xff; /* default to -3.5dB de-emphasis */ tx_de_emphasis = 1; /* * default to assert utmi_sleep_n and use maximum allowed HIRD * threshold value of 0b1100 */ hird_threshold = 12; dwc->maximum_speed = usb_get_maximum_speed(dev); dwc->dr_mode = usb_get_dr_mode(dev); dwc->suspend_clk_freq = of_usb_get_suspend_clk_freq(dev); dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); ret = dwc3_get_option(dwc); if (ret) dev_err(dev, "dwc3_get_option error occurred\n"); dwc->sysdev_is_parent = device_property_read_bool(dev, "linux,sysdev_is_parent"); if (dwc->sysdev_is_parent) dwc->sysdev = dwc->dev->parent; else dwc->sysdev = dwc->dev; dwc->has_lpm_erratum = device_property_read_bool(dev, "snps,has-lpm-erratum"); device_property_read_u8(dev, "snps,lpm-nyet-threshold", &lpm_nyet_threshold); dwc->is_utmi_l1_suspend = device_property_read_bool(dev, "snps,is-utmi-l1-suspend"); device_property_read_u8(dev, "snps,hird-threshold", &hird_threshold); dwc->usb3_lpm_capable = device_property_read_bool(dev, "snps,usb3_lpm_capable"); dwc->disable_scramble_quirk = device_property_read_bool(dev, "snps,disable_scramble_quirk"); dwc->u2exit_lfps_quirk = device_property_read_bool(dev, "snps,u2exit_lfps_quirk"); dwc->u2ss_inp3_quirk = device_property_read_bool(dev, "snps,u2ss_inp3_quirk"); dwc->req_p1p2p3_quirk = device_property_read_bool(dev, "snps,req_p1p2p3_quirk"); dwc->del_p1p2p3_quirk = device_property_read_bool(dev, "snps,del_p1p2p3_quirk"); dwc->u1u2_exitfail_to_recov_quirk = device_property_read_bool(dev, "snps,u1u2_exitfail_quirk"); dwc->ux_exit_in_px_quirk = device_property_read_bool(dev, "snps,ux_exit_in_px_quirk"); dwc->elastic_buf_mode_quirk = device_property_read_bool(dev, "snps,elastic_buf_mode_quirk"); dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, "snps,del_phy_power_chg_quirk"); dwc->lfps_filter_quirk = device_property_read_bool(dev, "snps,lfps_filter_quirk"); dwc->rx_detect_poll_quirk = device_property_read_bool(dev, "snps,rx_detect_poll_quirk"); dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, "snps,dis_u3_susphy_quirk"); dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, "snps,dis_u2_susphy_quirk"); dwc->dis_enblslpm_quirk = device_property_read_bool(dev, "snps,dis_enblslpm_quirk"); dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, "snps,dis_rxdet_inp3_quirk"); dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"); dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, "snps,dis-del-phy-power-chg-quirk"); dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, "snps,dis-tx-ipgap-linecheck-quirk"); dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, "snps,tx_de_emphasis_quirk"); device_property_read_u8(dev, "snps,tx_de_emphasis", &tx_de_emphasis); device_property_read_string(dev, "snps,hsphy_interface", &dwc->hsphy_interface); device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", &dwc->fladj); dev_info(dwc->dev, "%s: dr_mode:%d, suspend clock:%dMHz\n", __func__, dwc->dr_mode , dwc->suspend_clk_freq/1000000); dwc->lpm_nyet_threshold = lpm_nyet_threshold; dwc->tx_de_emphasis = tx_de_emphasis; dwc->hird_threshold = hird_threshold | (dwc->is_utmi_l1_suspend << 4); dwc->imod_interval = 0; } /* check whether the core supports IMOD */ bool dwc3_has_imod(struct dwc3 *dwc) { return ((dwc3_is_usb3(dwc) && dwc->revision >= DWC3_REVISION_300A) || (dwc3_is_usb31(dwc) && dwc->revision >= DWC3_USB31_REVISION_120A)); } static void dwc3_check_params(struct dwc3 *dwc) { struct device *dev = dwc->dev; /* Check for proper value of imod_interval */ if (dwc->imod_interval && !dwc3_has_imod(dwc)) { dev_warn(dwc->dev, "Interrupt moderation not supported\n"); dwc->imod_interval = 0; } /* * Workaround for STAR 9000961433 which affects only version * 3.00a of the DWC_usb3 core. This prevents the controller * interrupt from being masked while handling events. IMOD * allows us to work around this issue. Enable it for the * affected version. */ if (!dwc->imod_interval && (dwc->revision == DWC3_REVISION_300A)) dwc->imod_interval = 1; /* Check the maximum_speed parameter */ switch (dwc->maximum_speed) { case USB_SPEED_LOW: case USB_SPEED_FULL: case USB_SPEED_HIGH: case USB_SPEED_SUPER: case USB_SPEED_SUPER_PLUS: break; default: dev_err(dev, "invalid maximum_speed parameter %d\n", dwc->maximum_speed); /* fall through */ case USB_SPEED_UNKNOWN: /* default to superspeed */ dwc->maximum_speed = USB_SPEED_SUPER; /* * default to superspeed plus if we are capable. */ if (dwc3_is_usb31(dwc) && (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) dwc->maximum_speed = USB_SPEED_SUPER_PLUS; break; } } static int dwc3_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct resource *res; struct dwc3 *dwc; int ret; void __iomem *regs; pr_info("%s: +++\n", __func__); dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); if (!dwc) return -ENOMEM; dwc->dev = dev; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { dev_err(dev, "missing memory resource\n"); return -ENODEV; } dwc->xhci_resources[0].start = res->start; dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + DWC3_XHCI_REGS_END; dwc->xhci_resources[0].flags = res->flags; dwc->xhci_resources[0].name = res->name; res->start += DWC3_GLOBALS_REGS_START; /* * Request memory region but exclude xHCI regs, * since it will be requested by the xhci-plat driver. */ regs = devm_ioremap_resource(dev, res); if (IS_ERR(regs)) { ret = PTR_ERR(regs); goto err0; } dwc->regs = regs; dwc->regs_size = resource_size(res); dwc3_get_properties(dwc); ret = dma_set_mask(dwc->sysdev, DMA_BIT_MASK(36)); if (ret) { pr_err("dma set mask ret = %d\n", ret); return ret; } platform_set_drvdata(pdev, dwc); dwc3_cache_hwparams(dwc); spin_lock_init(&dwc->lock); init_completion(&dwc->disconnect); ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); if (ret) { dev_err(dwc->dev, "failed to allocate event buffers\n"); ret = -ENOMEM; goto err2; } //ret = dwc3_get_dr_mode(dwc); //if (ret) // goto err3; ret = dwc3_alloc_scratch_buffers(dwc); if (ret) goto err3; /* pm_runtime_get_sync triggers dwc3_core_init, which causes Kernel panic because dwc3_core_init is called in pm_runtime_get_sync before dwc3_alloc_event_buffers. Move the location to call pm runtime api */ pm_runtime_set_active(dev); pm_runtime_use_autosuspend(dev); pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); pm_runtime_enable(dev); ret = pm_runtime_get_sync(dev); if (ret < 0) goto err1; pm_runtime_forbid(dev); ret = dwc3_core_init(dwc); if (ret) { dev_err(dev, "failed to initialize core\n"); goto err4; } dwc3_check_params(dwc); ret = dwc3_core_init_mode(dwc); if (ret) goto err5; dwc3_debugfs_init(dwc); ret = pm_runtime_put(dev); pr_info("%s, pm_runtime_put = %d\n", __func__, ret); INIT_WORK(&dwc->set_vbus_current_work, dwc3_exynos_set_vbus_current_work); pr_info("%s: ---\n", __func__); return 0; err5: dwc3_event_buffers_cleanup(dwc); err4: dwc3_free_scratch_buffers(dwc); err3: dwc3_free_event_buffers(dwc); dwc3_ulpi_exit(dwc); err2: pm_runtime_allow(&pdev->dev); err1: pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); err0: /* * restore res->start back to its original value so that, in case the * probe is deferred, we don't end up getting error in request the * memory region the next time probe is called. */ res->start -= DWC3_GLOBALS_REGS_START; return ret; } static int dwc3_remove(struct platform_device *pdev) { struct dwc3 *dwc = platform_get_drvdata(pdev); struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); pm_runtime_get_sync(&pdev->dev); /* * restore res->start back to its original value so that, in case the * probe is deferred, we don't end up getting error in request the * memory region the next time probe is called. */ res->start -= DWC3_GLOBALS_REGS_START; dwc3_debugfs_exit(dwc); dwc3_core_exit_mode(dwc); dwc3_core_exit(dwc); dwc3_ulpi_exit(dwc); if (dwc->dr_mode != USB_DR_MODE_OTG) pm_runtime_put_sync(&pdev->dev); pm_runtime_allow(&pdev->dev); pm_runtime_disable(&pdev->dev); dwc3_free_event_buffers(dwc); dwc3_free_scratch_buffers(dwc); return 0; } #ifdef CONFIG_PM static int dwc3_suspend_common(struct dwc3 *dwc) { unsigned long flags; /* bring to full power */ pm_runtime_get_sync(dwc->dev); switch (dwc->dr_mode) { case USB_DR_MODE_PERIPHERAL: spin_lock_irqsave(&dwc->lock, flags); dwc3_gadget_suspend(dwc); spin_unlock_irqrestore(&dwc->lock, flags); break; case USB_DR_MODE_OTG: dwc3_event_buffers_cleanup(dwc); break; case USB_DR_MODE_HOST: usb_phy_shutdown(dwc->usb3_phy); usb_phy_shutdown(dwc->usb2_phy); phy_exit(dwc->usb2_generic_phy); phy_exit(dwc->usb3_generic_phy); phy_power_off(dwc->usb2_generic_phy); phy_power_off(dwc->usb3_generic_phy); default: /* do nothing */ break; } return 0; } static int dwc3_resume_common(struct dwc3 *dwc) { unsigned long flags; /* executing phy_init() twice caused 'ep0out' enable failure in resume. * don't call dwc3_core_init * ret = dwc3_core_init(dwc); */ dwc3_event_buffers_setup(dwc); switch (dwc->dr_mode) { case USB_DR_MODE_PERIPHERAL: spin_lock_irqsave(&dwc->lock, flags); dwc3_gadget_resume(dwc); spin_unlock_irqrestore(&dwc->lock, flags); break; /* Applying KC OTG and Role switch driver patch - e40c2ae, it's difficult to apply the patch because dwc3_resume func was changed in Kernel4.9 */ case USB_DR_MODE_OTG: break; case USB_DR_MODE_HOST: default: /* do nothing */ break; } return 0; } #endif /* CONFIG_PM */ #ifdef CONFIG_PM_SLEEP static int dwc3_suspend(struct device *dev) { struct dwc3 *dwc = dev_get_drvdata(dev); int ret; pr_info("[%s]\n", __func__); ret = dwc3_suspend_common(dwc); if (ret) return ret; pinctrl_pm_select_sleep_state(dev); return 0; } static int dwc3_resume(struct device *dev) { struct dwc3 *dwc = dev_get_drvdata(dev); int ret; pr_info("[%s]\n", __func__); pinctrl_pm_select_default_state(dev); ret = dwc3_resume_common(dwc); if (ret) return ret; pm_runtime_disable(dev); pm_runtime_set_active(dev); pm_runtime_enable(dev); /* Compensate usage count incremented during prepare */ pm_runtime_put_sync(dev); return 0; } #endif /* CONFIG_PM_SLEEP */ static const struct dev_pm_ops dwc3_dev_pm_ops = { SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) /*SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, dwc3_runtime_idle) */ }; #ifdef CONFIG_OF static const struct of_device_id of_dwc3_match[] = { { .compatible = "snps,dwc3" }, { .compatible = "synopsys,dwc3" }, { }, }; MODULE_DEVICE_TABLE(of, of_dwc3_match); #endif #ifdef CONFIG_ACPI #define ACPI_ID_INTEL_BSW "808622B7" static const struct acpi_device_id dwc3_acpi_match[] = { { ACPI_ID_INTEL_BSW, 0 }, { }, }; MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); #endif static struct platform_driver dwc3_driver = { .probe = dwc3_probe, .remove = dwc3_remove, .driver = { .name = "dwc3", .of_match_table = of_match_ptr(of_dwc3_match), .acpi_match_table = ACPI_PTR(dwc3_acpi_match), .pm = &dwc3_dev_pm_ops, }, }; module_platform_driver(dwc3_driver); MODULE_ALIAS("platform:dwc3"); MODULE_AUTHOR("Felipe Balbi "); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");