#ifndef __CMUCAL_QCH_H__ #define __CMUCAL_QCH_H__ #include "../cmucal.h" /*=================CMUCAL version: S5E9810================================*/ /*=================Q-channel information================================*/ enum qch_id { APBIF_GPIO_ALIVE_QCH = QCH_TYPE, APBIF_PMU_ALIVE_QCH, APBIF_RTC_QCH, APBIF_TOP_RTC_QCH, APM_CMU_APM_QCH, GREBEINTEGRATION_QCH_GREBE, GREBEINTEGRATION_QCH_DBG, INTMEM_QCH, LHM_AXI_P_APM_QCH, LHM_AXI_P_APM_CHUB_QCH, LHM_AXI_P_APM_CP_QCH, LHM_AXI_P_APM_GNSS_QCH, LHS_AXI_D_APM_QCH, LHS_AXI_G_SCAN2DRAM_QCH, LHS_AXI_LP_CHUB_QCH, LHS_AXI_P_APM2CMGP_QCH, MAILBOX_AP2CHUB_QCH, MAILBOX_AP2CP_QCH, MAILBOX_AP2CP_S_QCH, MAILBOX_AP2GNSS_QCH, MAILBOX_AP2VTS_QCH, MAILBOX_APM2AP_QCH, MAILBOX_APM2CHUB_QCH, MAILBOX_APM2CP_QCH, MAILBOX_APM2GNSS_QCH, MAILBOX_CHUB2CP_QCH, MAILBOX_GNSS2CHUB_QCH, MAILBOX_GNSS2CP_QCH, PEM_QCH, PGEN_APM_QCH, PMU_INTR_GEN_QCH, RSTNSYNC_CLK_APM_BUS_QCH, SPEEDY_APM_QCH, SPEEDY_SUB_APM_QCH, SYSREG_APM_QCH, WDT_APM_QCH, ABOX_QCH_ACLK, ABOX_QCH_BCLK_DSIF, ABOX_QCH_BCLK0, ABOX_QCH_BCLK1, ABOX_QCH_BCLK2, ABOX_QCH_BCLK3, ABOX_QCH_DUMMY, ABOX_QCH_CCLK_ASB, ABOX_QCH_CCLK_ATB, AUD_CMU_AUD_QCH, BTM_AUD_QCH, DFTMUX_AUD_QCH, DMIC_QCH, GPIO_AUD_QCH, LHM_AXI_P_AUD_QCH, LHS_ATB_AUD_QCH, LHS_AXI_D_AUD_QCH, PPMU_AUD_QCH, SYSMMU_AUD_QCH, SYSREG_AUD_QCH, TREX_AUD_QCH, WDT_AUD_QCH, BAAW_P_CHUB_QCH, BAAW_P_GNSS_QCH, BUS1_CMU_BUS1_QCH, LHM_AXI_D_APM_QCH, LHM_AXI_D_CHUB_QCH, LHM_AXI_D_GNSS_QCH, LHM_AXI_G_CSSYS_QCH, LHS_AXI_D_BUS1_QCH, LHS_AXI_P_CHUB_QCH, LHS_AXI_P_CSSYS_QCH, LHS_AXI_P_GNSS_QCH, SYSREG_BUS1_QCH, TREX_P_BUS1_QCH, BUSC_CMU_BUSC_QCH, BUSIF_CMUTOPC_QCH, BUSIF_HPMBUSC_QCH, LHM_ACEL_D0_DSPM_QCH, LHM_ACEL_D0_G2D_QCH, LHM_ACEL_D1_DSPM_QCH, LHM_ACEL_D1_G2D_QCH, LHM_ACEL_D2_DSPM_QCH, LHM_ACEL_D2_G2D_QCH, LHM_ACEL_D_FSYS0_QCH, LHM_ACEL_D_FSYS1_QCH, LHM_ACEL_D_IVA_QCH, LHM_AXI_D0_DPU_QCH, LHM_AXI_D0_ISPLP_QCH, LHM_AXI_D0_MFC_QCH, LHM_AXI_D1_DPU_QCH, LHM_AXI_D1_ISPLP_QCH, LHM_AXI_D1_MFC_QCH, LHM_AXI_D2_DPU_QCH, LHM_AXI_D_AUD_QCH, LHM_AXI_D_BUS1_QCH, LHM_AXI_D_DCF_QCH, LHM_AXI_D_DCRD_QCH, LHM_AXI_D_ISPHQ_QCH, LHM_AXI_D_ISPPRE_QCH, LHS_AXI_D_IVASC_QCH, LHS_AXI_P_AUD_QCH, LHS_AXI_P_DCF_QCH, LHS_AXI_P_DCRD_QCH, LHS_AXI_P_DPU_QCH, LHS_AXI_P_DSPM_QCH, LHS_AXI_P_FSYS0_QCH, LHS_AXI_P_FSYS1_QCH, LHS_AXI_P_G2D_QCH, LHS_AXI_P_ISPHQ_QCH, LHS_AXI_P_ISPLP_QCH, LHS_AXI_P_ISPPRE_QCH, LHS_AXI_P_IVA_QCH, LHS_AXI_P_MFC_QCH, LHS_AXI_P_MIF0_QCH, LHS_AXI_P_MIF1_QCH, LHS_AXI_P_MIF2_QCH, LHS_AXI_P_MIF3_QCH, LHS_AXI_P_PERIC0_QCH, LHS_AXI_P_PERIC1_QCH, LHS_AXI_P_PERIS_QCH, PDMA0_QCH, PGEN_LITE_BUSC_QCH, PGEN_PDMA0_QCH, PPFW_QCH, SBIC_QCH, SIREX_QCH, SPDMA_QCH, SYSREG_BUSC_QCH, TREX_D_BUSC_QCH, TREX_P_BUSC_QCH, TREX_RB_BUSC_QCH, ASYNCAHBM_CHUB_QCH, BAAW_D_CHUB_QCH, BAAW_P_APM_CHUB_QCH, BAAW_S_CHUB_QCH, CHUB_CMU_CHUB_QCH, CM4_CHUB_QCH, GPIO_CHUB_QCH, I2C_CHUB00_QCH, I2C_CHUB01_QCH, LHM_AXI_LP_CHUB_QCH, LHM_AXI_P_CHUB_QCH, LHS_AXI_D_CHUB_QCH, LHS_AXI_P_APM_CHUB_QCH, PDMA_CHUB_QCH, PWM_CHUB_QCH, SWEEPER_D_CHUB_QCH, SWEEPER_P_APM_CHUB_QCH, SYSREG_CHUB_QCH, TIMER_CHUB_QCH, USI_CHUB00_QCH, USI_CHUB01_QCH, WDT_CHUB_QCH, ADC_CMGP_QCH_S0, ADC_CMGP_QCH_S1, ADC_CMGP_QCH_ADC, CMGP_CMU_CMGP_QCH, GPIO_CMGP_QCH, I2C_CMGP00_QCH, I2C_CMGP01_QCH, I2C_CMGP02_QCH, I2C_CMGP03_QCH, LHM_AXI_P_APM2CMGP_QCH, SYSREG_CMGP_QCH, SYSREG_CMGP2CHUB_QCH, SYSREG_CMGP2CP_QCH, SYSREG_CMGP2GNSS_QCH, SYSREG_CMGP2PMU_AP_QCH, SYSREG_CMGP2PMU_CHUB_QCH, USI_CMGP00_QCH, USI_CMGP01_QCH, USI_CMGP02_QCH, USI_CMGP03_QCH, CMU_CMU_CMUREF_QCH, DFTMUX_TOP_QCH_CIS_CLK0, DFTMUX_TOP_QCH_CIS_CLK1, DFTMUX_TOP_QCH_CIS_CLK2, DFTMUX_TOP_QCH_CIS_CLK3, OTP_QCH, ACE_SLICE_G3D0_QCH, ACE_SLICE_G3D1_QCH, ACE_SLICE_G3D2_QCH, ACE_SLICE_G3D3_QCH, BAAW_CP_QCH, BDU_QCH, BUSIF_HPMCORE_QCH, CCI_QCH, CORE_CMU_CORE_QCH, LHM_ACE_D0_G3D_QCH, LHM_ACE_D1_G3D_QCH, LHM_ACE_D2_G3D_QCH, LHM_ACE_D3_G3D_QCH, LHM_ACE_D_CPUCL0_QCH, LHM_AXI_D_CP_QCH, LHM_AXI_P_CLUSTER0_QCH, LHS_ATB_T_BDU_QCH, LHS_AXI_P_APM_QCH, LHS_AXI_P_CP_QCH, LHS_AXI_P_CPUCL0_QCH, LHS_AXI_P_CPUCL1_QCH, LHS_AXI_P_G3D_QCH, PPCFW_G3D_QCH, PPFW_DP_QCH, PPFW_G3D_QCH, PPFW_IO_QCH, PPMU_CPUCL0_QCH, PPMU_CPUCL1_QCH, PPMU_G3D0_QCH, PPMU_G3D1_QCH, PPMU_G3D2_QCH, PPMU_G3D3_QCH, SYSREG_CORE_QCH, TREX_D_CORE_QCH, TREX_P0_CORE_QCH, TREX_P1_CORE_QCH, ADM_APB_G_CLUSTER0_QCH, BUSIF_HPMCPUCL0_QCH, CLUSTER0_QCH_SCLK, CLUSTER0_QCH_ATCLK, CLUSTER0_QCH_PDBGCLK, CLUSTER0_QCH_GIC, CLUSTER0_QCH_DBG_PD, CLUSTER0_QCH_PCLK, CLUSTER0_QCH_PERIPHCLK, CMU_CPUCL0_SHORTSTOP_QCH, CPUCL0_CMU_CPUCL0_QCH, CSSYS_QCH, DUMPPC_CLUSTER0_QCH, DUMPPC_CLUSTER1_QCH, LHM_ATB_T0_CLUSTER0_QCH, LHM_ATB_T0_CLUSTER1_QCH, LHM_ATB_T1_CLUSTER0_QCH, LHM_ATB_T1_CLUSTER1_QCH, LHM_ATB_T2_CLUSTER0_QCH, LHM_ATB_T2_CLUSTER1_QCH, LHM_ATB_T3_CLUSTER0_QCH, LHM_ATB_T3_CLUSTER1_QCH, LHM_ATB_T_AUD_QCH, LHM_ATB_T_BDU_QCH, LHM_AXI_P_CPUCL0_QCH, LHM_AXI_P_CSSYS_QCH, LHS_ACE_D_CLUSTER0_QCH, LHS_ATB_T0_CLUSTER0_QCH, LHS_ATB_T1_CLUSTER0_QCH, LHS_ATB_T2_CLUSTER0_QCH, LHS_ATB_T3_CLUSTER0_QCH, LHS_AXI_G_CSSYS_QCH, LHS_AXI_G_ETR_QCH, LHS_AXI_P_CLUSTER0_QCH, SECJTAG_QCH, SYSREG_CPUCL0_QCH, BUSIF_HPMCPUCL1_QCH, CLUSTER1_QCH_CPU, CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1, CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1, CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1, CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1, CLUSTER1_QCH_PCLKDBG, CMU_CPUCL1_SHORTSTOP_QCH, CPUCL1_CMU_CPUCL1_QCH, LHM_AXI_P_CPUCL1_QCH, SYSREG_CPUCL1_QCH, BTM_DCF_QCH, DCF_CMU_DCF_QCH, IS_DCF_QCH_CIP, IS_DCF_QCH_QE, IS_DCF_QCH_SYSREG, IS_DCF_QCH_PPMU, IS_DCF_QCH_SYSMMU, IS_DCF_QCH_C2SYNC_2SLV, IS_DCF_QCH_PGEN_LITE, LHM_ATB_DCPOSTDCF_QCH, LHM_ATB_ISPHQDCF_QCH, LHM_AXI_D_DCPOSTDCF_QCH, LHM_AXI_P_DCF_QCH, LHS_ATB_DCFDCPOST_QCH, LHS_ATB_DCFISPLP_QCH, LHS_AXI_D_DCF_QCH, LHS_AXI_P_DCFDCPOST_QCH, DCPOST_CMU_DCPOST_QCH, IS_DCPOST_QCH_SYSREG, IS_DCPOST_QCH_CIP2, IS_DCPOST_QCH_QE, IS_DCPOST_QCH_C2SYNC_1SLV_CLK, LHM_ATB_DCFDCPOST_QCH, LHM_ATB_DCRDDCPOST_QCH, LHM_AXI_P_DCFDCPOST_QCH, LHS_ATB_DCPOSTDCF_QCH, LHS_ATB_DCPOSTDCRD_QCH, LHS_AXI_D_DCPOSTDCF_QCH, BTM_DCRD_QCH, DCRD_CMU_DCRD_QCH, IS_DCRD_QCH_DCP, IS_DCRD_QCH_PPMU, IS_DCRD_QCH_SYSMMU, IS_DCRD_QCH_SYSREG, IS_DCRD_QCH_PGEN_LITE, IS_DCRD_QCH_DCP_C2C, IS_DCRD_QCH_DCP_DIV2, LHM_ATB_DCPOSTDCRD_QCH, LHM_AXI_P_DCRD_QCH, LHS_ATB_DCRDDCPOST_QCH, LHS_ATB_DCRDISPLP_QCH, LHS_AXI_D_DCRD_QCH, BTM_DPUD0_QCH, BTM_DPUD1_QCH, BTM_DPUD2_QCH, DPU_QCH_DPU, DPU_QCH_DPU_DMA, DPU_QCH_DPU_DPP, DPU_QCH_DPU_WB_MUX, DPU_CMU_DPU_QCH, LHM_AXI_P_DPU_QCH, LHS_AXI_D0_DPU_QCH, LHS_AXI_D1_DPU_QCH, LHS_AXI_D2_DPU_QCH, PPMU_DPUD0_QCH, PPMU_DPUD1_QCH, PPMU_DPUD2_QCH, SYSMMU_DPUD0_QCH, SYSMMU_DPUD1_QCH, SYSMMU_DPUD2_QCH, SYSREG_DPU_QCH, ADM_APB_DSPM_QCH, BTM_DSPM0_QCH, BTM_DSPM1_QCH, DSPM_CMU_DSPM_QCH, LHM_AXI_D0_DSPSDSPM_QCH, LHM_AXI_D1_DSPSDSPM_QCH, LHM_AXI_P_DSPM_QCH, LHM_AXI_P_IVADSPM_QCH, LHS_ACEL_D0_DSPM_QCH, LHS_ACEL_D1_DSPM_QCH, LHS_ACEL_D2_DSPM_QCH, LHS_AXI_P_DSPMDSPS_QCH, LHS_AXI_P_DSPMIVA_QCH, PGEN_LITE_DSPM_QCH, PPMU_DSPM0_QCH, PPMU_DSPM1_QCH, SCORE_MASTER_QCH, SYSMMU_DSPM0_QCH, SYSMMU_DSPM1_QCH, SYSREG_DSPM_QCH, DSPS_CMU_DSPS_QCH, LHM_AXI_D_IVADSPS_QCH, LHM_AXI_P_DSPMDSPS_QCH, LHS_AXI_D0_DSPSDSPM_QCH, LHS_AXI_D1_DSPSDSPM_QCH, LHS_AXI_D_DSPSIVA_QCH, SCORE_KNIGHT_QCH, SYSREG_DSPS_QCH, BTM_FSYS0_QCH, DP_LINK_QCH, DP_LINK_QCH_GTC, ETR_MIU_QCH_PCLK, ETR_MIU_QCH_ACLK, FSYS0_CMU_FSYS0_QCH, GPIO_FSYS0_QCH, LHM_AXI_G_ETR_QCH, LHM_AXI_P_FSYS0_QCH, LHS_ACEL_D_FSYS0_QCH, PGEN_LITE_FSYS0_QCH, PPMU_FSYS0_QCH, SYSREG_FSYS0_QCH, UFS_EMBD_QCH, UFS_EMBD_QCH_FMP, USB30DRD_QCH_USB30DRD_LINK, USB30DRD_QCH_USBPCS, USB30DRD_QCH_USB30DRD_CTRL, USB30DRD_QCH_USBDPPHY, USB30DRD_QCH_SOC_PLL, ADM_AHB_SSS_QCH, BTM_FSYS1_QCH, FSYS1_CMU_FSYS1_QCH, GPIO_FSYS1_QCH, LHM_AXI_P_FSYS1_QCH, LHS_ACEL_D_FSYS1_QCH, MMC_CARD_QCH, PCIE_GEN2_QCH_MSTR, PCIE_GEN2_QCH_PCS, PCIE_GEN2_QCH_PHY, PCIE_GEN2_QCH_DBI, PCIE_GEN2_QCH_APB, PCIE_GEN2_QCH_SOCPLL, PCIE_GEN3_QCH_MSTR, PCIE_GEN3_QCH_PCS, PCIE_GEN3_QCH_DBI, PCIE_GEN3_QCH_APB, PCIE_GEN3_QCH_SOCPLL, PCIE_GEN3_QCH_PHY, PCIE_IA_GEN2_QCH, PCIE_IA_GEN3_QCH, PGEN_LITE_FSYS1_QCH, PPMU_FSYS1_QCH, RTIC_QCH, SSS_QCH, SYSMMU_FSYS1_QCH, SYSREG_FSYS1_QCH, UFS_CARD_QCH, UFS_CARD_QCH_FMP, ASTC_QCH, BTM_G2DD0_QCH, BTM_G2DD1_QCH, BTM_G2DD2_QCH, G2D_QCH, G2D_CMU_G2D_QCH, JPEG_QCH, LHM_AXI_P_G2D_QCH, LHS_ACEL_D0_G2D_QCH, LHS_ACEL_D1_G2D_QCH, LHS_ACEL_D2_G2D_QCH, MSCL_QCH, PGEN100_LITE_G2D_QCH, PPMU_G2DD0_QCH, PPMU_G2DD1_QCH, PPMU_G2DD2_QCH, QE_ASTC_QCH, QE_JPEG_QCH, QE_MSCL_QCH, SYSMMU_G2DD0_QCH, SYSMMU_G2DD1_QCH, SYSMMU_G2DD2_QCH, SYSREG_G2D_QCH, BUSIF_HPMG3D_QCH, G3D_CMU_G3D_QCH, GPU_QCH, LHM_AXI_G3DSFR_QCH, LHM_AXI_P_G3D_QCH, LHS_ACE_D0_G3D_QCH, LHS_ACE_D1_G3D_QCH, LHS_ACE_D2_G3D_QCH, LHS_ACE_D3_G3D_QCH, LHS_AXI_G3DSFR_QCH, PGEN_LITE_G3D_QCH, SYSREG_G3D_QCH, BTM_ISPHQ_QCH, ISPHQ_CMU_ISPHQ_QCH, IS_ISPHQ_QCH_ISPHQ, IS_ISPHQ_QCH_SYSMMU_ISPHQ, IS_ISPHQ_QCH_PPMU_ISPHQ, IS_ISPHQ_QCH_PGEN_LITE_ISPHQ, IS_ISPHQ_QCH_ISPHQ_C2COM, LHM_ATB_ISPLPISPHQ_QCH, LHM_ATB_ISPPREISPHQ_QCH, LHM_AXI_P_ISPHQ_QCH, LHS_ATB_ISPHQDCF_QCH, LHS_ATB_ISPHQISPLP_QCH, LHS_AXI_D_ISPHQ_QCH, SYSREG_ISPHQ_QCH, BTM_ISPLP0_QCH, BTM_ISPLP1_QCH, ISPLP_CMU_ISPLP_QCH, IS_ISPLP_QCH_MC_SCALER, IS_ISPLP_QCH_ISPLP, IS_ISPLP_QCH_QE_ISPLP, IS_ISPLP_QCH_SYSMMU_ISPLP0, IS_ISPLP_QCH_PPMU_ISPLP0, IS_ISPLP_QCH_SYSMMU_ISPLP1, IS_ISPLP_QCH_PPMU_ISPLP1, IS_ISPLP_QCH_QE_VRA, IS_ISPLP_QCH_VRA, IS_ISPLP_QCH_GDC, IS_ISPLP_QCH_PGEN_LITE, IS_ISPLP_QCH_QE_GDC, IS_ISPLP_QCH_ISPLP_C2, LHM_ATB_DCFISPLP_QCH, LHM_ATB_DCRDISPLP_QCH, LHM_ATB_ISPHQISPLP_QCH, LHM_ATB_ISPPREISPLP_QCH, LHM_AXI_P_ISPLP_QCH, LHS_ATB_ISPLPISPHQ_QCH, LHS_AXI_D0_ISPLP_QCH, LHS_AXI_D1_ISPLP_QCH, SYSREG_ISPLP_QCH, BTM_ISPPRE_QCH, ISPPRE_CMU_ISPPRE_QCH, IS_ISPPRE_QCH_CSIS0, IS_ISPPRE_QCH_CSIS1, IS_ISPPRE_QCH_CSIS2, IS_ISPPRE_QCH_CSIS3, IS_ISPPRE_QCH_PPMU_ISPPRE, IS_ISPPRE_QCH_PDP_DMA, IS_ISPPRE_QCH_SYSMMU_ISPPRE, IS_ISPPRE_QCH_QE_PDP, IS_ISPPRE_QCH_QE_3AA, IS_ISPPRE_QCH_QE_3AAM, IS_ISPPRE_QCH_3AA, IS_ISPPRE_QCH_3AAM, IS_ISPPRE_QCH_PDP_CORE0, IS_ISPPRE_QCH_PDP_CORE1, IS_ISPPRE_QCH_PGEN_LITE, IS_ISPPRE_QCH_QE_PDP_STAT, IS_ISPPRE_QCH_PGEN_LITE1, LHM_AXI_P_ISPPRE_QCH, LHS_ATB_ISPPREISPHQ_QCH, LHS_ATB_ISPPREISPLP_QCH, LHS_AXI_D_ISPPRE_QCH, SYSREG_ISPPRE_QCH_SYSREG, ADM_DAP_IVA_QCH, BTM_IVA_QCH, IVA_QCH_IVA, IVA_QCH_IVA_DEBUG, IVA_CMU_IVA_QCH, IVA_INTMEM_QCH, LHM_AXI_D_DSPSIVA_QCH, LHM_AXI_D_IVASC_QCH, LHM_AXI_P_DSPMIVA_QCH, LHM_AXI_P_IVA_QCH, LHS_ACEL_D_IVA_QCH, LHS_AXI_D_IVADSPS_QCH, LHS_AXI_P_IVADSPM_QCH, PGEN_LITE_IVA_QCH, PPMU_IVA_QCH, SYSMMU_IVA_QCH, SYSREG_IVA_QCH, TREX_RB_IVA_QCH, BTM_MFCD0_QCH, BTM_MFCD1_QCH, LHM_AXI_P_MFC_QCH, LHS_AXI_D0_MFC_QCH, LHS_AXI_D1_MFC_QCH, LH_ATB_QCH_MI, LH_ATB_QCH_SI, MFC_QCH, MFC_CMU_MFC_QCH, PGEN100_LITE_MFC_QCH, PPMU_MFCD0_QCH, PPMU_MFCD1_QCH, PPMU_MFCD2_QCH, RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MI_SW_RESET_QCH, RSTNSYNC_CLK_MFC_BUSD_LH_ATB_SI_SW_RESET_QCH, RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH, RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH, SYSMMU_MFCD0_QCH, SYSMMU_MFCD1_QCH, SYSREG_MFC_QCH, WFD_QCH, APBBR_DDRPHY_QCH, APBBR_DMC_QCH, APBBR_DMCTZ_QCH, BUSIF_HPMMIF_QCH, CMU_MIF_CMUREF_QCH, DMC_QCH, LHM_AXI_P_MIF_QCH, MIF_CMU_MIF_QCH, QCH_ADAPTER_PPMUPPC_DEBUG_QCH, QCH_ADAPTER_PPMUPPC_DVFS_QCH, SYSREG_MIF_QCH, GPIO_PERIC0_QCH, LHM_AXI_P_PERIC0_QCH, PERIC0_CMU_PERIC0_QCH, PWM_QCH, SYSREG_PERIC0_QCH, UART_DBG_QCH, USI00_I2C_QCH, USI00_USI_QCH, USI01_I2C_QCH, USI01_USI_QCH, USI02_I2C_QCH, USI02_USI_QCH, USI03_I2C_QCH, USI03_USI_QCH, USI04_I2C_QCH, USI04_USI_QCH, USI05_I2C_QCH, USI05_USI_QCH, USI12_I2C_QCH, USI12_USI_QCH, USI13_I2C_QCH, USI13_USI_QCH, USI14_I2C_QCH, USI14_USI_QCH, GPIO_PERIC1_QCH, I2C_CAM0_QCH, I2C_CAM1_QCH, I2C_CAM2_QCH, I2C_CAM3_QCH, LHM_AXI_P_PERIC1_QCH, PERIC1_CMU_PERIC1_QCH, SPI_CAM0_QCH, SYSREG_PERIC1_QCH, UART_BT_QCH, USI06_I2C_QCH, USI06_USI_QCH, USI07_I2C_QCH, USI07_USI_QCH, USI08_I2C_QCH, USI08_USI_QCH, USI09_I2C_QCH, USI09_USI_QCH, USI10_I2C_QCH, USI10_USI_QCH, USI11_I2C_QCH, USI11_USI_QCH, BUSIF_TMU_QCH, GIC_QCH, LHM_AXI_P_PERIS_QCH, MCT_QCH, OTP_CON_BIRA_QCH, OTP_CON_TOP_QCH, PERIS_CMU_PERIS_QCH, SYSREG_PERIS_QCH, WDT_CLUSTER0_QCH, WDT_CLUSTER1_QCH, S2D_CMU_S2D_QCH, AHB_BUSMATRIX_QCH_SYS, ASYNCAHBM_VTS_QCH, CORTEXM4INTEGRATION_QCH_CPU, DMIC_AHB0_QCH_PCLK, DMIC_AHB1_QCH_PCLK, DMIC_IF_QCH_PCLK, DMIC_IF_QCH_DMIC_CLK, GPIO_VTS_QCH, HWACG_SYS_DMIC0_QCH, HWACG_SYS_DMIC1_QCH, MAILBOX_VTS2CHUB_QCH, SYSREG_VTS_QCH, VTS_CMU_VTS_QCH, WDT_VTS_QCH, U_DMIC_CLK_MUX_QCH, end_of_qch, num_of_qch = end_of_qch - QCH_TYPE, }; /*=================Controller Option information================================*/ enum option_id { CTRL_OPTION_BLK_APM = OPTION_TYPE, CTRL_OPTION_BLK_AUD, CTRL_OPTION_BLK_BUS1, CTRL_OPTION_BLK_BUSC, CTRL_OPTION_BLK_CHUB, CTRL_OPTION_BLK_CMGP, CTRL_OPTION_BLK_CMU, CTRL_OPTION_BLK_CORE, CTRL_OPTION_BLK_CPUCL0, CTRL_OPTION_BLK_CPUCL1, CTRL_OPTION_BLK_DCF, CTRL_OPTION_BLK_DCPOST, CTRL_OPTION_BLK_DCRD, CTRL_OPTION_BLK_DPU, CTRL_OPTION_BLK_DSPM, CTRL_OPTION_BLK_DSPS, CTRL_OPTION_BLK_FSYS0, CTRL_OPTION_BLK_FSYS1, CTRL_OPTION_BLK_G2D, CTRL_OPTION_BLK_G3D, CTRL_OPTION_BLK_ISPHQ, CTRL_OPTION_BLK_ISPLP, CTRL_OPTION_BLK_ISPPRE, CTRL_OPTION_BLK_IVA, CTRL_OPTION_BLK_MFC, CTRL_OPTION_BLK_MIF, CTRL_OPTION_BLK_PERIC0, CTRL_OPTION_BLK_PERIC1, CTRL_OPTION_BLK_PERIS, CTRL_OPTION_BLK_S2D, CTRL_OPTION_BLK_VTS, end_of_option, num_of_option = end_of_option - OPTION_TYPE, }; #endif