#ifndef __CMUCAL_VCLK_H__ #define __CMUCAL_VCLK_H__ #include "../cmucal.h" /*=================CMUCAL version: S5E9610================================*/ enum vclk_id { /* DVFS TYPE */ VCLK_VDD_CPUCL0 = DFS_VCLK_TYPE, VCLK_VDD_CPUCL1, VCLK_VDD_G3D, VCLK_VDD_INT, VCLK_VDD_CAM, VCLK_VDD_MIF, end_of_dfs_vclk, num_of_dfs_vclk = end_of_dfs_vclk - DFS_VCLK_TYPE, /* SPECIAL TYPE */ VCLK_CLKCMU_SHUB_BUS = (MASK_OF_ID & end_of_dfs_vclk) | VCLK_TYPE, VCLK_DIV_CLK_CMGP_ADC, VCLK_DIV_CLK_CMGP_USI01, VCLK_DIV_CLK_CMGP_USI03, VCLK_DIV_CLK_CMGP_USI02, VCLK_DIV_CLK_CMGP_USI00, VCLK_DIV_CLK_CMGP_USI04, VCLK_CLKCMU_FSYS_UFS_EMBD, VCLK_DIV_CLK_CMU_CMUREF, VCLK_CLKCMU_HPM, VCLK_CLKCMU_PERI_IP, VCLK_CLKCMU_MIF_BUSP, VCLK_CLKCMU_APM_BUS, VCLK_CLKCMU_CIS_CLK1, VCLK_CLKCMU_CIS_CLK3, VCLK_CLKCMU_USB_USB30DRD, VCLK_CLKCMU_CIS_CLK0, VCLK_CLKCMU_USB_DPGTC, VCLK_CLKCMU_CIS_CLK2, VCLK_CLKCMU_PERI_UART, VCLK_DIV_CLK_CLUSTER0_PCLKDBG, VCLK_DIV_CLK_CLUSTER0_ACLK, VCLK_DIV_CLK_CPUCL0_CMUREF, VCLK_DIV_CLK_CLUSTER0_CNTCLK, VCLK_DIV_CLK_CLUSTER1_CNTCLK, VCLK_DIV_CLK_CPUCL1_CMUREF, VCLK_DIV_CLK_AUD_DSIF, VCLK_DIV_CLK_AUD_UAIF0, VCLK_DIV_CLK_AUD_UAIF2, VCLK_DIV_CLK_AUD_CPU_PCLKDBG, VCLK_DIV_CLK_AUD_UAIF1, VCLK_DIV_CLK_AUD_FM, VCLK_MUX_MIF_CMUREF, VCLK_MUX_MIF1_CMUREF, VCLK_PLL_MIF1, VCLK_DIV_CLK_PERI_SPI0, VCLK_DIV_CLK_PERI_SPI2, VCLK_DIV_CLK_PERI_USI_I2C, VCLK_DIV_CLK_PERI_SPI1, VCLK_DIV_CLK_PERI_USI_USI, VCLK_DIV_CLK_SHUB_I2C, VCLK_DIV_CLK_SHUB_USI00, end_of_vclk, num_of_vclk = end_of_vclk - ((MASK_OF_ID & end_of_dfs_vclk) | VCLK_TYPE), /* COMMON TYPE */ VCLK_BLK_APM = (MASK_OF_ID & end_of_vclk) | COMMON_VCLK_TYPE, VCLK_BLK_CAM, VCLK_BLK_CMGP, VCLK_BLK_CMU, VCLK_BLK_CORE, VCLK_BLK_CPUCL0, VCLK_BLK_CPUCL1, VCLK_BLK_DISPAUD, VCLK_BLK_G2D, VCLK_BLK_G3D, VCLK_BLK_ISP, VCLK_BLK_MFC, VCLK_BLK_PERI, VCLK_BLK_SHUB, VCLK_BLK_VIPX1, VCLK_BLK_VIPX2, end_of_common_vclk, num_of_common_vclk = end_of_common_vclk - ((MASK_OF_ID & end_of_vclk) | COMMON_VCLK_TYPE), /* GATING TYPE */ VCLK_IP_APBIF_GPIO_ALIVE = (MASK_OF_ID & end_of_common_vclk) | GATE_VCLK_TYPE, VCLK_IP_APBIF_PMU_ALIVE, VCLK_IP_APBIF_RTC, VCLK_IP_APBIF_TOP_RTC, VCLK_IP_APM_CMU_APM, VCLK_IP_GREBEINTEGRATION, VCLK_IP_INTMEM, VCLK_IP_LHM_AXI_P_APM, VCLK_IP_LHM_AXI_P_APM_GNSS, VCLK_IP_LHM_AXI_P_APM_MODEM, VCLK_IP_LHM_AXI_P_APM_SHUB, VCLK_IP_LHM_AXI_P_APM_WLBT, VCLK_IP_LHS_AXI_D_APM, VCLK_IP_LHS_AXI_LP_SHUB, VCLK_IP_MAILBOX_AP2CP, VCLK_IP_MAILBOX_AP2CP_S, VCLK_IP_MAILBOX_AP2GNSS, VCLK_IP_MAILBOX_AP2SHUB, VCLK_IP_MAILBOX_AP2WLBT, VCLK_IP_MAILBOX_APM2AP, VCLK_IP_MAILBOX_APM2CP, VCLK_IP_MAILBOX_APM2GNSS, VCLK_IP_MAILBOX_APM2SHUB, VCLK_IP_MAILBOX_APM2WLBT, VCLK_IP_MAILBOX_CP2GNSS, VCLK_IP_MAILBOX_CP2SHUB, VCLK_IP_MAILBOX_CP2WLBT, VCLK_IP_MAILBOX_SHUB2GNSS, VCLK_IP_MAILBOX_SHUB2WLBT, VCLK_IP_MAILBOX_WLBT2ABOX, VCLK_IP_MAILBOX_WLBT2GNSS, VCLK_IP_PEM, VCLK_IP_PGEN_LITE_APM, VCLK_IP_PMU_INTR_GEN, VCLK_IP_SPEEDY_APM, VCLK_IP_SYSREG_APM, VCLK_IP_WDT_APM, VCLK_IP_XIU_DP_APM, VCLK_IP_BLK_CAM, VCLK_IP_BTM_CAM, VCLK_IP_CAM_CMU_CAM, VCLK_IP_LHM_AXI_P_CAM, VCLK_IP_LHS_ACEL_D_CAM, VCLK_IP_LHS_ATB_CAMISP, VCLK_IP_SYSREG_CAM, VCLK_IP_is6p10p0_CAM, VCLK_IP_ADC_CMGP, VCLK_IP_CMGP_CMU_CMGP, VCLK_IP_GPIO_CMGP, VCLK_IP_I2C_CMGP00, VCLK_IP_I2C_CMGP01, VCLK_IP_I2C_CMGP02, VCLK_IP_I2C_CMGP03, VCLK_IP_I2C_CMGP04, VCLK_IP_SYSREG_CMGP, VCLK_IP_SYSREG_CMGP2CP, VCLK_IP_SYSREG_CMGP2GNSS, VCLK_IP_SYSREG_CMGP2PMU_AP, VCLK_IP_SYSREG_CMGP2PMU_SHUB, VCLK_IP_SYSREG_CMGP2SHUB, VCLK_IP_SYSREG_CMGP2WLBT, VCLK_IP_USI_CMGP00, VCLK_IP_USI_CMGP01, VCLK_IP_USI_CMGP02, VCLK_IP_USI_CMGP03, VCLK_IP_USI_CMGP04, VCLK_IP_OTP, VCLK_IP_AD_APB_CCI_550, VCLK_IP_AD_APB_DIT, VCLK_IP_AD_APB_PDMA0, VCLK_IP_AD_APB_PGEN_PDMA, VCLK_IP_AD_APB_PPFW_MEM0, VCLK_IP_AD_APB_PPFW_MEM1, VCLK_IP_AD_APB_PPFW_PERI, VCLK_IP_AD_APB_SPDMA, VCLK_IP_AD_AXI_GIC, VCLK_IP_ASYNCSFR_WR_DMC0, VCLK_IP_ASYNCSFR_WR_DMC1, VCLK_IP_AXI_US_A40_64to128_DIT, VCLK_IP_BAAW_P_GNSS, VCLK_IP_BAAW_P_MODEM, VCLK_IP_BAAW_P_SHUB, VCLK_IP_BAAW_P_WLBT, VCLK_IP_CCI_550, VCLK_IP_CORE_CMU_CORE, VCLK_IP_DIT, VCLK_IP_GIC400_AIHWACG, VCLK_IP_LHM_ACEL_D0_ISP, VCLK_IP_LHM_ACEL_D0_MFC, VCLK_IP_LHM_ACEL_D1_ISP, VCLK_IP_LHM_ACEL_D1_MFC, VCLK_IP_LHM_ACEL_D_CAM, VCLK_IP_LHM_ACEL_D_DPU, VCLK_IP_LHM_ACEL_D_FSYS, VCLK_IP_LHM_ACEL_D_G2D, VCLK_IP_LHM_ACEL_D_USB, VCLK_IP_LHM_ACEL_D_VIPX1, VCLK_IP_LHM_ACEL_D_VIPX2, VCLK_IP_LHM_ACE_D_CPUCL0, VCLK_IP_LHM_ACE_D_CPUCL1, VCLK_IP_LHM_AXI_D0_MODEM, VCLK_IP_LHM_AXI_D1_MODEM, VCLK_IP_LHM_AXI_D_ABOX, VCLK_IP_LHM_AXI_D_APM, VCLK_IP_LHM_AXI_D_CSSYS, VCLK_IP_LHM_AXI_D_G3D, VCLK_IP_LHM_AXI_D_GNSS, VCLK_IP_LHM_AXI_D_SHUB, VCLK_IP_LHM_AXI_D_WLBT, VCLK_IP_LHS_AXI_D0_MIF_CP, VCLK_IP_LHS_AXI_D0_MIF_CPU, VCLK_IP_LHS_AXI_D0_MIF_NRT, VCLK_IP_LHS_AXI_D0_MIF_RT, VCLK_IP_LHS_AXI_D1_MIF_CP, VCLK_IP_LHS_AXI_D1_MIF_CPU, VCLK_IP_LHS_AXI_D1_MIF_NRT, VCLK_IP_LHS_AXI_D1_MIF_RT, VCLK_IP_LHS_AXI_P_APM, VCLK_IP_LHS_AXI_P_CAM, VCLK_IP_LHS_AXI_P_CPUCL0, VCLK_IP_LHS_AXI_P_CPUCL1, VCLK_IP_LHS_AXI_P_DISPAUD, VCLK_IP_LHS_AXI_P_FSYS, VCLK_IP_LHS_AXI_P_G2D, VCLK_IP_LHS_AXI_P_G3D, VCLK_IP_LHS_AXI_P_GNSS, VCLK_IP_LHS_AXI_P_ISP, VCLK_IP_LHS_AXI_P_MFC, VCLK_IP_LHS_AXI_P_MIF0, VCLK_IP_LHS_AXI_P_MIF1, VCLK_IP_LHS_AXI_P_MODEM, VCLK_IP_LHS_AXI_P_PERI, VCLK_IP_LHS_AXI_P_SHUB, VCLK_IP_LHS_AXI_P_USB, VCLK_IP_LHS_AXI_P_VIPX1, VCLK_IP_LHS_AXI_P_VIPX2, VCLK_IP_LHS_AXI_P_WLBT, VCLK_IP_PDMA_CORE, VCLK_IP_PGEN_LITE_SIREX, VCLK_IP_PGEN_PDMA, VCLK_IP_PPCFW_G3D, VCLK_IP_PPFW_CORE_MEM0, VCLK_IP_PPFW_CORE_MEM1, VCLK_IP_PPFW_CORE_PERI, VCLK_IP_PPMU_ACE_CPUCL0, VCLK_IP_PPMU_ACE_CPUCL1, VCLK_IP_SFR_APBIF_CMU_TOPC, VCLK_IP_SIREX, VCLK_IP_SPDMA_CORE, VCLK_IP_SYSREG_CORE, VCLK_IP_TREX_D_CORE, VCLK_IP_TREX_D_NRT, VCLK_IP_TREX_P_CORE, VCLK_IP_XIU_D_CORE, VCLK_IP_ADM_APB_G_CSSYS_CORE, VCLK_IP_ADS_AHB_G_CSSYS_FSYS, VCLK_IP_ADS_APB_G_CSSYS_CPUCL1, VCLK_IP_ADS_APB_G_P8Q, VCLK_IP_AD_APB_P_DUMP_PC_CPUCL0, VCLK_IP_AD_APB_P_DUMP_PC_CPUCL1, VCLK_IP_BUSIF_HPMCPUCL0, VCLK_IP_CPUCL0_CMU_CPUCL0, VCLK_IP_CSSYS_DBG, VCLK_IP_DUMP_PC_CPUCL0, VCLK_IP_DUMP_PC_CPUCL1, VCLK_IP_HPM_CPUCL0, VCLK_IP_LHM_AXI_P_CPUCL0, VCLK_IP_LHS_AXI_D_CSSYS, VCLK_IP_SECJTAG, VCLK_IP_SYSREG_CPUCL0, VCLK_IP_ADM_APB_G_CSSYS_CPUCL1, VCLK_IP_BUSIF_HPMCPUCL1, VCLK_IP_CPUCL1_CMU_CPUCL1, VCLK_IP_HPM_CPUCL1, VCLK_IP_LHM_AXI_P_CPUCL1, VCLK_IP_LHS_ACE_D_CPUCL1, VCLK_IP_SYSREG_CPUCL1, VCLK_IP_ABOX, VCLK_IP_AXI_US_32to128, VCLK_IP_BLK_DISPAUD, VCLK_IP_BTM_ABOX, VCLK_IP_BTM_DPU, VCLK_IP_DFTMUX_DISPAUD, VCLK_IP_DISPAUD_CMU_DISPAUD, VCLK_IP_DPU, VCLK_IP_GPIO_DISPAUD, VCLK_IP_LHM_AXI_P_DISPAUD, VCLK_IP_LHS_ACEL_D_DPU, VCLK_IP_LHS_AXI_D_ABOX, VCLK_IP_PERI_AXI_ASB, VCLK_IP_PPMU_ABOX, VCLK_IP_PPMU_DPU, VCLK_IP_SMMU_ABOX, VCLK_IP_SMMU_DPU, VCLK_IP_SYSREG_DISPAUD, VCLK_IP_WDT_AUD, VCLK_IP_ADM_AHB_SSS, VCLK_IP_BTM_FSYS, VCLK_IP_FSYS_CMU_FSYS, VCLK_IP_GPIO_FSYS, VCLK_IP_LHM_AXI_P_FSYS, VCLK_IP_LHS_ACEL_D_FSYS, VCLK_IP_MMC_CARD, VCLK_IP_MMC_EMBD, VCLK_IP_PGEN_LITE_FSYS, VCLK_IP_PPMU_FSYS, VCLK_IP_RTIC, VCLK_IP_SSS, VCLK_IP_SYSREG_FSYS, VCLK_IP_UFS_EMBD, VCLK_IP_XIU_D_FSYS, VCLK_IP_AS_AXI_JPEG, VCLK_IP_AS_AXI_MSCL, VCLK_IP_BLK_G2D, VCLK_IP_BTM_G2D, VCLK_IP_G2D, VCLK_IP_G2D_CMU_G2D, VCLK_IP_JPEG, VCLK_IP_LHM_AXI_P_G2D, VCLK_IP_LHS_ACEL_D_G2D, VCLK_IP_MSCL, VCLK_IP_PGEN100_LITE_G2D, VCLK_IP_PPMU_G2D, VCLK_IP_SYSMMU_G2D, VCLK_IP_SYSREG_G2D, VCLK_IP_XIU_D_MSCL, VCLK_IP_BTM_G3D, VCLK_IP_BUSIF_HPMG3D, VCLK_IP_G3D, VCLK_IP_G3D_CMU_G3D, VCLK_IP_GRAY2BIN_G3D, VCLK_IP_HPM_G3D, VCLK_IP_LHM_AXI_G3DSFR, VCLK_IP_LHM_AXI_P_G3D, VCLK_IP_LHS_AXI_D_G3D, VCLK_IP_LHS_AXI_G3DSFR, VCLK_IP_PGEN_LITE_G3D, VCLK_IP_SYSREG_G3D, VCLK_IP_BLK_ISP, VCLK_IP_BTM_ISP0, VCLK_IP_BTM_ISP1, VCLK_IP_ISP_CMU_ISP, VCLK_IP_LHM_ATB_CAMISP, VCLK_IP_LHM_AXI_P_ISP, VCLK_IP_LHS_ACEL_D0_ISP, VCLK_IP_LHS_ACEL_D1_ISP, VCLK_IP_SYSREG_ISP, VCLK_IP_is6p10p0_ISP, VCLK_IP_AS_AXI_WFD, VCLK_IP_BLK_MFC, VCLK_IP_BTM_MFCD0, VCLK_IP_BTM_MFCD1, VCLK_IP_LHM_AXI_P_MFC, VCLK_IP_LHS_ACEL_D0_MFC, VCLK_IP_LHS_ACEL_D1_MFC, VCLK_IP_LH_ATB_MFC, VCLK_IP_MFC, VCLK_IP_MFC_CMU_MFC, VCLK_IP_PGEN100_LITE_MFC, VCLK_IP_PPMU_MFCD0, VCLK_IP_PPMU_MFCD1, VCLK_IP_SYSMMU_MFCD0, VCLK_IP_SYSMMU_MFCD1, VCLK_IP_SYSREG_MFC, VCLK_IP_WFD, VCLK_IP_XIU_D_MFC, VCLK_IP_BUSIF_HPMMIF, VCLK_IP_DDR_PHY, VCLK_IP_DMC, VCLK_IP_HPM_MIF, VCLK_IP_LHM_AXI_D_MIF_CP, VCLK_IP_LHM_AXI_D_MIF_CPU, VCLK_IP_LHM_AXI_D_MIF_NRT, VCLK_IP_LHM_AXI_D_MIF_RT, VCLK_IP_LHM_AXI_P_MIF, VCLK_IP_MIF_CMU_MIF, VCLK_IP_PPMU_DMC_CPU, VCLK_IP_QE_DMC_CPU, VCLK_IP_SFRAPB_BRIDGE_DDR_PHY, VCLK_IP_SFRAPB_BRIDGE_DMC, VCLK_IP_SFRAPB_BRIDGE_DMC_PF, VCLK_IP_SFRAPB_BRIDGE_DMC_PPMPU, VCLK_IP_SFRAPB_BRIDGE_DMC_SECURE, VCLK_IP_SYSREG_MIF, VCLK_IP_BUSIF_HPMMIF1, VCLK_IP_DMC1, VCLK_IP_HPM_MIF1, VCLK_IP_LHM_AXI_D_MIF1_CP, VCLK_IP_LHM_AXI_D_MIF1_CPU, VCLK_IP_LHM_AXI_D_MIF1_NRT, VCLK_IP_LHM_AXI_D_MIF1_RT, VCLK_IP_MIF1_CMU_MIF1, VCLK_IP_AXI2AHB_MSD32_PERI, VCLK_IP_BUSIF_TMU, VCLK_IP_CAMI2C_0, VCLK_IP_CAMI2C_1, VCLK_IP_CAMI2C_2, VCLK_IP_CAMI2C_3, VCLK_IP_GPIO_PERI, VCLK_IP_I2C_0, VCLK_IP_I2C_1, VCLK_IP_I2C_2, VCLK_IP_I2C_3, VCLK_IP_I2C_4, VCLK_IP_I2C_5, VCLK_IP_I2C_6, VCLK_IP_LHM_AXI_P_PERI, VCLK_IP_MCT, VCLK_IP_OTP_CON_TOP, VCLK_IP_PERI_CMU_PERI, VCLK_IP_PWM_MOTOR, VCLK_IP_SPI_0, VCLK_IP_SPI_1, VCLK_IP_SPI_2, VCLK_IP_SYSREG_PERI, VCLK_IP_UART, VCLK_IP_USI00_I2C, VCLK_IP_USI00_USI, VCLK_IP_WDT_CLUSTER0, VCLK_IP_WDT_CLUSTER1, VCLK_IP_BAAW_D_SHUB, VCLK_IP_BAAW_P_APM_SHUB, VCLK_IP_CM4_SHUB, VCLK_IP_GPIO_SHUB, VCLK_IP_I2C_SHUB00, VCLK_IP_LHM_AXI_LP_SHUB, VCLK_IP_LHM_AXI_P_SHUB, VCLK_IP_LHS_AXI_D_SHUB, VCLK_IP_LHS_AXI_P_APM_SHUB, VCLK_IP_PDMA_SHUB, VCLK_IP_PWM_SHUB, VCLK_IP_SHUB_CMU_SHUB, VCLK_IP_SWEEPER_D_SHUB, VCLK_IP_SWEEPER_P_APM_SHUB, VCLK_IP_SYSREG_SHUB, VCLK_IP_TIMER_SHUB, VCLK_IP_USI_SHUB00, VCLK_IP_WDT_SHUB, VCLK_IP_XIU_DP_SHUB, VCLK_IP_BTM_USB, VCLK_IP_DP_LINK, VCLK_IP_LHM_AXI_P_USB, VCLK_IP_LHS_ACEL_D_USB, VCLK_IP_PGEN_LITE_USB, VCLK_IP_PPMU_USB, VCLK_IP_SYSREG_USB, VCLK_IP_USB30DRD, VCLK_IP_USB_CMU_USB, VCLK_IP_US_D_USB, VCLK_IP_BLK_VIPX1, VCLK_IP_BTM_D_VIPX1, VCLK_IP_LHM_ATB_VIPX1, VCLK_IP_LHM_AXI_P_VIPX1, VCLK_IP_LHS_ACEL_D_VIPX1, VCLK_IP_LHS_ATB_VIPX1, VCLK_IP_LHS_AXI_P_VIPX1_LOCAL, VCLK_IP_PGEN_LITE_VIPX1, VCLK_IP_PPMU_D_VIPX1, VCLK_IP_SMMU_D_VIPX1, VCLK_IP_SYSREG_VIPX1, VCLK_IP_VIPX1, VCLK_IP_VIPX1_CMU_VIPX1, VCLK_IP_XIU_D_VIPX1, VCLK_IP_BLK_VIPX2, VCLK_IP_BTM_D_VIPX2, VCLK_IP_LHM_ATB_VIPX2, VCLK_IP_LHM_AXI_P_VIPX2, VCLK_IP_LHM_AXI_P_VIPX2_LOCAL, VCLK_IP_LHS_ACEL_D_VIPX2, VCLK_IP_LHS_ATB_VIPX2, VCLK_IP_PGEN_LITE_VIPX2, VCLK_IP_PPMU_D_VIPX2, VCLK_IP_SMMU_D_VIPX2, VCLK_IP_SYSREG_VIPX2, VCLK_IP_VIPX2, VCLK_IP_VIPX2_CMU_VIPX2, end_of_gating_vclk, num_of_gating_vclk = end_of_gating_vclk - ((MASK_OF_ID & end_of_common_vclk) | GATE_VCLK_TYPE), }; #endif