#ifndef __CMUCAL_SFR_H__ #define __CMUCAL_SFR_H__ #include "../cmucal.h" /*=================CMUCAL version: S5E9610================================*/ /*====================The section of SFR Block===================*/ enum sfr_block_id { APM = SFR_BLOCK_TYPE, CAM, CMGP, TOP, CORE, CPUCL0, CPUCL1, DISPAUD, FSYS, G2D, G3D, ISP, MFC, MIF, MIF1, PERI, SHUB, USB, VIPX1, VIPX2, end_of_sfr_block, num_of_sfr_block = end_of_sfr_block - SFR_BLOCK_TYPE, }; /*====================The section of SFR===================*/ enum sfr_id { PLL_CON0_MUX_CLKCMU_APM_BUS_USER = SFR_TYPE, PLL_CON2_MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, CLK_CON_DIV_DIV_CLK_APM_BUS, CLK_CON_MUX_MUX_CLK_APM_BUS, PLL_CON0_MUX_DLL_USER, PLL_CON2_MUX_DLL_USER, CLK_CON_MUX_MUX_CLKCMU_SHUB_BUS, CLK_CON_DIV_CLKCMU_SHUB_BUS, CLK_CON_GAT_GATE_CLKCMU_SHUB_BUS, CLK_CON_GAT_CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_SHUB_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_MODEM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_SHUB_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2SHUB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2WLBT_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2SHUB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2GNSS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2GNSS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2ABOX_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_LITE_APM_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_WLBT_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2WLBT_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2GNSS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2SHUB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2WLBT_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_RCO_IPCLKPORT_CLK, QCH_CON_APBIF_GPIO_ALIVE_QCH, QCH_CON_APBIF_PMU_ALIVE_QCH, QCH_CON_APBIF_RTC_QCH, QCH_CON_APBIF_TOP_RTC_QCH, QCH_CON_APM_CMU_APM_QCH, QCH_CON_GREBEINTEGRATION_QCH_GREBE, QCH_CON_GREBEINTEGRATION_QCH_DBG, QCH_CON_INTMEM_QCH, QCH_CON_LHM_AXI_P_APM_QCH, QCH_CON_LHM_AXI_P_APM_GNSS_QCH, QCH_CON_LHM_AXI_P_APM_MODEM_QCH, QCH_CON_LHM_AXI_P_APM_SHUB_QCH, QCH_CON_LHM_AXI_P_APM_WLBT_QCH, QCH_CON_LHS_AXI_D_APM_QCH, QCH_CON_LHS_AXI_LP_SHUB_QCH, QCH_CON_MAILBOX_AP2CP_QCH, QCH_CON_MAILBOX_AP2CP_S_QCH, QCH_CON_MAILBOX_AP2GNSS_QCH, QCH_CON_MAILBOX_AP2SHUB_QCH, QCH_CON_MAILBOX_AP2WLBT_QCH, QCH_CON_MAILBOX_APM2AP_QCH, QCH_CON_MAILBOX_APM2CP_QCH, QCH_CON_MAILBOX_APM2GNSS_QCH, QCH_CON_MAILBOX_APM2SHUB_QCH, QCH_CON_MAILBOX_APM2WLBT_QCH, QCH_CON_MAILBOX_CP2GNSS_QCH, QCH_CON_MAILBOX_CP2SHUB_QCH, QCH_CON_MAILBOX_CP2WLBT_QCH, QCH_CON_MAILBOX_SHUB2GNSS_QCH, QCH_CON_MAILBOX_SHUB2WLBT_QCH, QCH_CON_MAILBOX_WLBT2ABOX_QCH, QCH_CON_MAILBOX_WLBT2GNSS_QCH, QCH_CON_PEM_QCH, QCH_CON_PGEN_LITE_APM_QCH, QCH_CON_PMU_INTR_GEN_QCH, QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH, QCH_CON_SPEEDY_APM_QCH, QCH_CON_SYSREG_APM_QCH, QCH_CON_WDT_APM_QCH, PLL_CON0_MUX_CLKCMU_CAM_BUS_USER, PLL_CON2_MUX_CLKCMU_CAM_BUS_USER, CLK_CON_DIV_DIV_CLK_CAM_BUSP, CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ATB_CAMISP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ACEL_D_CAM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_CAM_UID_RSTNSYNC_CLK_CAM_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_XIU_D_CAM, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PPMU_CAM, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PPMU_CAM, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_SMMU_CAM, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_3AA, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS0, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS2, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS3, CLK_CON_GAT_GOUT_BLK_CAM_UID_BLK_CAM_IPCLKPORT_CLK_CAM_BUSD, CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM0, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_DMA, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PAFSTAT_CORE, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_RDMA, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS0, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS2, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS3, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM1, QCH_CON_BTM_CAM_QCH, QCH_CON_CAM_CMU_CAM_QCH, QCH_CON_LHM_AXI_P_CAM_QCH, QCH_CON_LHS_ACEL_D_CAM_QCH, QCH_CON_LHS_ATB_CAMISP_QCH, QCH_CON_SYSREG_CAM_QCH, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS0, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS1, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS2, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS3, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_3AA, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PPMU, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_SMMU, QCH_CON_IS6P10P0_CAM_QCH_S_CAM0_PGEN_LITE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_RDMA, QCH_CON_IS6P10P0_CAM_QCH_S_CAM1_PGEN_LITE, CLK_CON_DIV_DIV_CLK_CMGP_USI03, CLK_CON_DIV_DIV_CLK_CMGP_USI00, CLK_CON_DIV_DIV_CLK_CMGP_I2C, CLK_CON_DIV_DIV_CLK_CMGP_USI01, CLK_CON_DIV_DIV_CLK_CMGP_USI04, CLK_CON_MUX_MUX_CLK_CMGP_USI01, CLK_CON_MUX_MUX_CLK_CMGP_I2C, CLK_CON_MUX_MUX_CLK_CMGP_USI00, CLK_CON_MUX_MUX_CLK_CMGP_USI04, CLK_CON_MUX_MUX_CLK_CMGP_USI02, CLK_CON_DIV_DIV_CLK_CMGP_USI02, CLK_CON_MUX_MUX_CLK_CMGP_USI03, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2SHUB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_PCLK, CLK_CON_MUX_MUX_CLK_CMGP_ADC, CLK_CON_DIV_DIV_CLK_CMGP_ADC, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI00_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI01_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI02_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI03_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI04_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_IPCLK, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_SHUB_IPCLKPORT_PCLK, QCH_CON_ADC_CMGP_QCH_S0, QCH_CON_ADC_CMGP_QCH_S1, DMYQCH_CON_ADC_CMGP_QCH_ADC, QCH_CON_CMGP_CMU_CMGP_QCH, QCH_CON_GPIO_CMGP_QCH, QCH_CON_I2C_CMGP00_QCH, QCH_CON_I2C_CMGP01_QCH, QCH_CON_I2C_CMGP02_QCH, QCH_CON_I2C_CMGP03_QCH, QCH_CON_I2C_CMGP04_QCH, QCH_CON_SYSREG_CMGP_QCH, QCH_CON_SYSREG_CMGP2CP_QCH, QCH_CON_SYSREG_CMGP2GNSS_QCH, QCH_CON_SYSREG_CMGP2PMU_AP_QCH, QCH_CON_SYSREG_CMGP2PMU_SHUB_QCH, QCH_CON_SYSREG_CMGP2SHUB_QCH, QCH_CON_SYSREG_CMGP2WLBT_QCH, QCH_CON_USI_CMGP00_QCH, QCH_CON_USI_CMGP01_QCH, QCH_CON_USI_CMGP02_QCH, QCH_CON_USI_CMGP03_QCH, QCH_CON_USI_CMGP04_QCH, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_DISP, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_DISP, CLK_CON_DIV_CLKCMU_DISPAUD_DISP, CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD, CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS, CLK_CON_DIV_CLKCMU_FSYS_BUS, CLK_CON_DIV_CLKCMU_G2D_MSCL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0, CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, CLK_CON_DIV_CLKCMU_PERI_BUS, CLK_CON_MUX_MUX_CLKCMU_PERI_IP, CLK_CON_GAT_GATE_CLKCMU_PERI_IP, CLK_CON_DIV_CLKCMU_PERI_IP, CLK_CON_GAT_GATE_CLKCMU_APM_BUS, CLK_CON_DIV_CLKCMU_APM_BUS, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD, CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD, CLK_CON_DIV_CLKCMU_CIS_CLK0, CLK_CON_DIV_CLKCMU_CIS_CLK1, CLK_CON_DIV_CLKCMU_CIS_CLK2, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1, CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK, CLK_CON_MUX_MUX_CMU_CMUREF, CLK_CON_MUX_MUX_CLK_CMU_CMUREF, CLK_CON_DIV_DIV_CLK_CMU_CMUREF, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, PLL_CON0_PLL_SHARED0, PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED1, PLL_LOCKTIME_PLL_SHARED1, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, CLK_CON_DIV_CLKCMU_CORE_BUS, CLK_CON_DIV_PLL_SHARED0_DIV3, CLK_CON_DIV_CLKCMU_CPUCL0_DBG, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG, CLK_CON_DIV_PLL_SHARED0_DIV2, CLK_CON_DIV_PLL_SHARED0_DIV4, CLK_CON_DIV_PLL_SHARED1_DIV2, CLK_CON_DIV_PLL_SHARED1_DIV4, CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, CLK_CON_DIV_CLKCMU_CORE_CCI, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D, CLK_CON_DIV_CLKCMU_CORE_G3D, CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, CLK_CON_DIV_CLKCMU_MIF_BUSP, CLK_CON_DIV_PLL_SHARED1_DIV3, PLL_CON0_PLL_MMC, PLL_CON3_PLL_MMC, PLL_LOCKTIME_PLL_MMC, CLK_CON_MUX_MUX_CLKCMU_FSYS_UFS_EMBD, CLK_CON_GAT_GATE_CLKCMU_FSYS_UFS_EMBD, CLK_CON_DIV_CLKCMU_FSYS_UFS_EMBD, CLK_CON_DIV_CLKCMU_CAM_BUS, CLK_CON_GAT_GATE_CLKCMU_CAM_BUS, CLK_CON_MUX_MUX_CLKCMU_CAM_BUS, CLK_CON_MUX_MUX_CLKCMU_VIPX1_BUS, CLK_CON_GAT_GATE_CLKCMU_VIPX1_BUS, CLK_CON_DIV_CLKCMU_VIPX1_BUS, CLK_CON_DIV_CLKCMU_ISP_BUS, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS, CLK_CON_GAT_GATE_CLKCMU_ISP_BUS, CLK_CON_DIV_CLKCMU_ISP_VRA, CLK_CON_MUX_MUX_CLKCMU_ISP_VRA, CLK_CON_GAT_GATE_CLKCMU_ISP_VRA, CLK_CON_DIV_CLKCMU_ISP_GDC, CLK_CON_GAT_GATE_CLKCMU_ISP_GDC, CLK_CON_MUX_MUX_CLKCMU_ISP_GDC, CLK_CON_DIV_CLKCMU_G2D_G2D, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, CLK_CON_DIV_CLKCMU_G3D_SWITCH, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_CPU, CLK_CON_DIV_CLKCMU_DISPAUD_CPU, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_CPU, CLK_CON_GAT_CLKCMU_MIF_SWITCH, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, CLK_CON_MUX_MUX_CLKCMU_USB_BUS, CLK_CON_DIV_CLKCMU_USB_BUS, CLK_CON_GAT_GATE_CLKCMU_USB_BUS, CLK_CON_MUX_MUX_CLKCMU_USB_USB30DRD, CLK_CON_DIV_CLKCMU_USB_USB30DRD, CLK_CON_GAT_GATE_CLKCMU_USB_USB30DRD, CLK_CON_MUX_MUX_CLKCMU_USB_DPGTC, CLK_CON_GAT_GATE_CLKCMU_USB_DPGTC, CLK_CON_DIV_CLKCMU_USB_DPGTC, CLK_CON_DIV_CLKCMU_DISPAUD_AUD, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_AUD, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_AUD, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, CLK_CON_GAT_GATE_CLKCMU_MFC_WFD, CLK_CON_DIV_CLKCMU_MFC_MFC, CLK_CON_DIV_CLKCMU_MFC_WFD, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, CLK_CON_MUX_MUX_CLKCMU_HPM, CLK_CON_GAT_GATE_CLKCMU_HPM, CLK_CON_DIV_CLKCMU_HPM, CLK_CON_DIV_CLKCMU_PERI_UART, CLK_CON_MUX_MUX_CLKCMU_PERI_UART, CLK_CON_GAT_GATE_CLKCMU_PERI_UART, CLK_CON_DIV_CLKCMU_OTP, CLK_CON_GAT_CLK_BLK_CMU_UID_OTP_IPCLKPORT_CLK, CLK_CON_GAT_GATE_CLKCMU_VIPX2_BUS, CLK_CON_DIV_CLKCMU_VIPX2_BUS, CLK_CON_MUX_MUX_CLKCMU_VIPX2_BUS, CLK_CON_DIV_CLKCMU_CIS_CLK3, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, CLK_CON_DIV_PLL_MMC_DIV2, DMYQCH_CON_CMU_TOP_CMUREF_QCH, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS0, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS1, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS2, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS3, DMYQCH_CON_OTP_QCH, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, PLL_CON2_MUX_CLKCMU_CORE_BUS_USER, CLK_CON_DIV_DIV_CLK_CORE_BUSP, CLK_CON_MUX_MUX_CLK_CORE_GIC, PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, PLL_CON2_MUX_CLKCMU_CORE_CCI_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM, CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC400_AIHWACG_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_DPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_CAM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_OCC_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_OCC_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_CCI_550_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK, PLL_CON0_MUX_CLKCMU_CORE_G3D_USER, PLL_CON2_MUX_CLKCMU_CORE_G3D_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_OCC_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_NRT_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_NRT_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC0_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_ISP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_FSYS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_ISP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_G2D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_SHUB_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_SHUB_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_WLBT_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0, CLK_CON_GAT_GOUT_BLK_CORE_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_ISP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_RT_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_RT_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_MFC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_MFC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_USB_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX2_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_USB_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC1_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM0_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM1_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_PERI_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_SHUB_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_550_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_CCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_LITE_SIREX_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_CCLK_P_CORE, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE, CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM0_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM1_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_PERI_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_US_A40_64TO128_DIT_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX2_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_PDMA_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PGEN_PDMA_IPCLKPORT_PCLKM, QCH_CON_BAAW_P_GNSS_QCH, QCH_CON_BAAW_P_MODEM_QCH, QCH_CON_BAAW_P_SHUB_QCH, QCH_CON_BAAW_P_WLBT_QCH, QCH_CON_CCI_550_QCH, QCH_CON_CORE_CMU_CORE_QCH, QCH_CON_DIT_QCH, QCH_CON_GIC400_AIHWACG_QCH, QCH_CON_LHM_ACEL_D0_ISP_QCH, QCH_CON_LHM_ACEL_D0_MFC_QCH, QCH_CON_LHM_ACEL_D1_ISP_QCH, QCH_CON_LHM_ACEL_D1_MFC_QCH, QCH_CON_LHM_ACEL_D_CAM_QCH, QCH_CON_LHM_ACEL_D_DPU_QCH, QCH_CON_LHM_ACEL_D_FSYS_QCH, QCH_CON_LHM_ACEL_D_G2D_QCH, QCH_CON_LHM_ACEL_D_USB_QCH, QCH_CON_LHM_ACEL_D_VIPX1_QCH, QCH_CON_LHM_ACEL_D_VIPX2_QCH, QCH_CON_LHM_ACE_D_CPUCL0_QCH, QCH_CON_LHM_ACE_D_CPUCL1_QCH, QCH_CON_LHM_AXI_D0_MODEM_QCH, QCH_CON_LHM_AXI_D1_MODEM_QCH, QCH_CON_LHM_AXI_D_ABOX_QCH, QCH_CON_LHM_AXI_D_APM_QCH, QCH_CON_LHM_AXI_D_CSSYS_QCH, QCH_CON_LHM_AXI_D_G3D_QCH, QCH_CON_LHM_AXI_D_GNSS_QCH, QCH_CON_LHM_AXI_D_SHUB_QCH, QCH_CON_LHM_AXI_D_WLBT_QCH, QCH_CON_LHS_AXI_D0_MIF_CP_QCH, QCH_CON_LHS_AXI_D0_MIF_CPU_QCH, QCH_CON_LHS_AXI_D0_MIF_NRT_QCH, QCH_CON_LHS_AXI_D0_MIF_RT_QCH, QCH_CON_LHS_AXI_D1_MIF_CP_QCH, QCH_CON_LHS_AXI_D1_MIF_CPU_QCH, QCH_CON_LHS_AXI_D1_MIF_NRT_QCH, QCH_CON_LHS_AXI_D1_MIF_RT_QCH, QCH_CON_LHS_AXI_P_APM_QCH, QCH_CON_LHS_AXI_P_CAM_QCH, QCH_CON_LHS_AXI_P_CPUCL0_QCH, QCH_CON_LHS_AXI_P_CPUCL1_QCH, QCH_CON_LHS_AXI_P_DISPAUD_QCH, QCH_CON_LHS_AXI_P_FSYS_QCH, QCH_CON_LHS_AXI_P_G2D_QCH, QCH_CON_LHS_AXI_P_G3D_QCH, QCH_CON_LHS_AXI_P_GNSS_QCH, QCH_CON_LHS_AXI_P_ISP_QCH, QCH_CON_LHS_AXI_P_MFC_QCH, QCH_CON_LHS_AXI_P_MIF0_QCH, QCH_CON_LHS_AXI_P_MIF1_QCH, QCH_CON_LHS_AXI_P_MODEM_QCH, QCH_CON_LHS_AXI_P_PERI_QCH, QCH_CON_LHS_AXI_P_SHUB_QCH, QCH_CON_LHS_AXI_P_USB_QCH, QCH_CON_LHS_AXI_P_VIPX1_QCH, QCH_CON_LHS_AXI_P_VIPX2_QCH, QCH_CON_LHS_AXI_P_WLBT_QCH, QCH_CON_PDMA_CORE_QCH, QCH_CON_PGEN_LITE_SIREX_QCH, QCH_CON_PGEN_PDMA_QCH, QCH_CON_PPCFW_G3D_QCH, QCH_CON_PPFW_CORE_MEM0_QCH, QCH_CON_PPFW_CORE_MEM1_QCH, QCH_CON_PPFW_CORE_PERI_QCH, QCH_CON_PPMU_ACE_CPUCL0_QCH, QCH_CON_PPMU_ACE_CPUCL1_QCH, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_QCH, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_OCC_QCH, QCH_CON_RSTNSYNC_CLK_CORE_CCI_OCC_QCH, QCH_CON_RSTNSYNC_CLK_CORE_G3D_OCC_QCH, QCH_CON_SFR_APBIF_CMU_TOPC_QCH, QCH_CON_SIREX_QCH, QCH_CON_SPDMA_CORE_QCH, QCH_CON_SYSREG_CORE_QCH, QCH_CON_TREX_D_CORE_QCH, QCH_CON_TREX_D_NRT_QCH, QCH_CON_TREX_P_CORE_QCH, PLL_CON0_PLL_CPUCL0, PLL_LOCKTIME_PLL_CPUCL0, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG, CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER, PLL_CON2_MUX_CLKCMU_CPUCL0_DBG_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK, CLK_CON_GAT_GATE_CLK_CLUSTER0_CPU, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CSSYS_CORE_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_CSSYS_FSYS_IPCLKPORT_HCLKS, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_P8Q_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_D_CSSYS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK, QCH_CON_BUSIF_HPMCPUCL0_QCH, DMYQCH_CON_CLUSTER0_QCH_CPU, DMYQCH_CON_CLUSTER0_QCH_DBG, QCH_CON_CLUSTER0_QCH_LHS_ACE_D_CPUCL0, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH, QCH_CON_CPUCL0_CMU_CPUCL0_QCH, DMYQCH_CON_CSSYS_DBG_QCH, QCH_CON_DUMP_PC_CPUCL0_QCH, QCH_CON_DUMP_PC_CPUCL1_QCH, QCH_CON_LHM_AXI_P_CPUCL0_QCH, QCH_CON_LHS_AXI_D_CSSYS_QCH, QCH_CON_SECJTAG_QCH, QCH_CON_SYSREG_CPUCL0_QCH, PLL_CON0_PLL_CPUCL1, PLL_LOCKTIME_PLL_CPUCL1, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK, CLK_CON_GAT_GATE_CLK_CLUSTER1_CPU, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK, DMYQCH_CON_ADM_APB_G_CSSYS_CPUCL1_QCH, QCH_CON_BUSIF_HPMCPUCL1_QCH, DMYQCH_CON_CLUSTER1_QCH_CPU, DMYQCH_CON_CLUSTER1_QCH_DBG, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH, QCH_CON_CPUCL1_CMU_CPUCL1_QCH, QCH_CON_LHM_AXI_P_CPUCL1_QCH, QCH_CON_LHS_ACE_D_CPUCL1_QCH, QCH_CON_SYSREG_CPUCL1_QCH, CLK_CON_DIV_DIV_CLK_AUD_CPU, CLK_CON_MUX_MUX_CLK_AUD_CPU, PLL_CON0_MUX_CLKCMU_DISPAUD_CPU_USER, PLL_CON2_MUX_CLKCMU_DISPAUD_CPU_USER, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, CLK_CON_DIV_DIV_CLK_AUD_UAIF0, CLK_CON_DIV_DIV_CLK_AUD_AUDIF, CLK_CON_DIV_DIV_CLK_AUD_UAIF2, CLK_CON_DIV_DIV_CLK_AUD_UAIF1, CLK_CON_MUX_MUX_CLK_AUD_UAIF0, CLK_CON_MUX_MUX_CLK_AUD_UAIF2, CLK_CON_MUX_MUX_CLK_AUD_UAIF1, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_AUD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_AUD_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK, PLL_CON0_MUX_CLKCMU_DISPAUD_DISP_USER, PLL_CON2_MUX_CLKCMU_DISPAUD_DISP_USER, CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP, PLL_CON0_PLL_AUD, PLL_CON3_PLL_AUD, PLL_LOCKTIME_PLL_AUD, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_ACEL_D_DPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_DISP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK, CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK, CLK_CON_DIV_DIV_CLK_AUD_DSIF, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, CLK_CON_MUX_MUX_CLK_AUD_FM, CLK_CON_DIV_DIV_CLK_AUD_FM, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY, PLL_CON0_MUX_CLKCMU_DISPAUD_AUD_USER, PLL_CON2_MUX_CLKCMU_DISPAUD_AUD_USER, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_DISP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_DBG, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_DSIF, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_OSC_SPDY, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_AUD, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7, CLK_CON_DIV_DIV_CLK_AUD_BUS, CLK_CON_MUX_MUX_CLK_AUD_BUS, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK, DMYQCH_CON_ABOX_QCH_CPU, QCH_CON_ABOX_QCH_S_ACLK, QCH_CON_ABOX_QCH_S_BCLK0, QCH_CON_ABOX_QCH_S_BCLK2, QCH_CON_ABOX_QCH_S_BCLK1, DMYQCH_CON_ABOX_QCH_FM, QCH_CON_ABOX_QCH_S_BCLK_DSIF, QCH_CON_BTM_ABOX_QCH, QCH_CON_BTM_DPU_QCH, QCH_CON_DISPAUD_CMU_DISPAUD_QCH, QCH_CON_DPU_QCH_S_DPP, QCH_CON_DPU_QCH_S_DMA, QCH_CON_DPU_QCH_S_DECON, QCH_CON_GPIO_DISPAUD_QCH, QCH_CON_LHM_AXI_P_DISPAUD_QCH, QCH_CON_LHS_ACEL_D_DPU_QCH, QCH_CON_LHS_AXI_D_ABOX_QCH, QCH_CON_PPMU_ABOX_QCH, QCH_CON_PPMU_DPU_QCH, QCH_CON_RSTNSYNC_CLK_AUD_CPU_CLKIN_QCH, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH, QCH_CON_SMMU_ABOX_QCH, QCH_CON_SMMU_DPU_QCH, QCH_CON_SYSREG_DISPAUD_QCH, QCH_CON_WDT_AUD_QCH, PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER, PLL_CON2_MUX_CLKCMU_FSYS_BUS_USER, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER, PLL_CON2_MUX_CLKCMU_FSYS_MMC_CARD_USER, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER, PLL_CON2_MUX_CLKCMU_FSYS_MMC_EMBD_USER, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_ACEL_D_FSYS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, PLL_CON0_MUX_CLKCMU_FSYS_UFS_EMBD_USER, PLL_CON2_MUX_CLKCMU_FSYS_UFS_EMBD_USER, CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PGEN_LITE_FSYS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, QCH_CON_ADM_AHB_SSS_QCH, QCH_CON_BTM_FSYS_QCH, QCH_CON_FSYS_CMU_FSYS_QCH, QCH_CON_GPIO_FSYS_QCH, QCH_CON_LHM_AXI_P_FSYS_QCH, QCH_CON_LHS_ACEL_D_FSYS_QCH, QCH_CON_MMC_CARD_QCH, QCH_CON_MMC_EMBD_QCH, QCH_CON_PGEN_LITE_FSYS_QCH, QCH_CON_PPMU_FSYS_QCH, QCH_CON_RTIC_QCH, QCH_CON_SSS_QCH, QCH_CON_SYSREG_FSYS_QCH, QCH_CON_UFS_EMBD_QCH_UFS, QCH_CON_UFS_EMBD_QCH_FMP, PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER, PLL_CON2_MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_DIV_DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_MSCL_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_G2D_UID_RSTNSYNC_CLK_G2D_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_FIMP_CLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_MSCL_IPCLKPORT_ACLK, PLL_CON0_MUX_CLKCMU_G2D_G2D_USER, PLL_CON2_MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKM, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKS, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKS, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKM, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D_G2D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_G2D_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_MSCL_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_PGEN100_LITE_G2D_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_MSCL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_G2D, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_PCLK, QCH_CON_BTM_G2D_QCH, QCH_CON_G2D_QCH, QCH_CON_G2D_CMU_G2D_QCH, QCH_CON_JPEG_QCH, QCH_CON_LHM_AXI_P_G2D_QCH, QCH_CON_LHS_ACEL_D_G2D_QCH, QCH_CON_MSCL_QCH, QCH_CON_PGEN100_LITE_G2D_QCH, QCH_CON_PPMU_G2D_QCH, QCH_CON_SYSMMU_G2D_QCH, QCH_CON_SYSREG_G2D_QCH, CLK_CON_DIV_DIV_CLK_G3D_BUSP, PLL_CON0_PLL_G3D, PLL_LOCKTIME_PLL_G3D, CLK_CON_MUX_MUX_CLK_G3D_BUSD, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_PCLK, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK, CLK_CON_DIV_DIV_CLK_G3D_BUSD, QCH_CON_BTM_G3D_QCH, QCH_CON_BUSIF_HPMG3D_QCH, QCH_CON_G3D_QCH, QCH_CON_G3D_CMU_G3D_QCH, QCH_CON_LHM_AXI_G3DSFR_QCH, QCH_CON_LHM_AXI_P_G3D_QCH, QCH_CON_LHS_AXI_D_G3D_QCH, QCH_CON_LHS_AXI_G3DSFR_QCH, QCH_CON_PGEN_LITE_G3D_QCH, QCH_CON_SYSREG_G3D_QCH, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_OSCCLK_IPCLKPORT_CLK, PLL_CON0_MUX_CLKCMU_ISP_BUS_USER, PLL_CON2_MUX_CLKCMU_ISP_BUS_USER, CLK_CON_DIV_DIV_CLK_ISP_BUSP, PLL_CON0_MUX_CLKCMU_ISP_VRA_USER, PLL_CON2_MUX_CLKCMU_ISP_VRA_USER, CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK, PLL_CON0_MUX_CLKCMU_ISP_GDC_USER, PLL_CON2_MUX_CLKCMU_ISP_GDC_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_GDC_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_VRA_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_AXI_P_ISP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D1_ISP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D0_ISP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_VRA, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_VRA, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_GDC, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_GDC, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP0, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP0, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP0, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_GDC, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_ISP, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_VRA, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_ATB_CAMISP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_BUSD, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_GDC, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_VRA, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP1, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_D_ISP, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_MCSC, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PGEN_LITE_ISP_PCLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_PCLK, QCH_CON_BTM_ISP0_QCH, QCH_CON_BTM_ISP1_QCH, QCH_CON_ISP_CMU_ISP_QCH, QCH_CON_LHM_ATB_CAMISP_QCH, QCH_CON_LHM_AXI_P_ISP_QCH, QCH_CON_LHS_ACEL_D0_ISP_QCH, QCH_CON_LHS_ACEL_D1_ISP_QCH, QCH_CON_SYSREG_ISP_QCH, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_ISP, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_MCSC, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_VRA, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP0, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_GDC, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PGEN_LITE_ISP, CLK_CON_DIV_DIV_CLK_MFC_BUSP, PLL_CON0_MUX_CLKCMU_MFC_WFD_USER, PLL_CON2_MUX_CLKCMU_MFC_WFD_USER, PLL_CON0_MUX_CLKCMU_MFC_MFC_USER, PLL_CON2_MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKS, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKM, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_SI, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_MI, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_PGEN100_LITE_MFC_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD0_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD1_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_WFD_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_XIU_D_MFC_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_MFC, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_WFD, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_MFC_UID_RSTNSYNC_CLK_MFC_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D0_MFC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D1_MFC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_SW_RESET_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_SW_RESET_IPCLKPORT_CLK, QCH_CON_BTM_MFCD0_QCH, QCH_CON_BTM_MFCD1_QCH, QCH_CON_LHM_AXI_P_MFC_QCH, QCH_CON_LHS_ACEL_D0_MFC_QCH, QCH_CON_LHS_ACEL_D1_MFC_QCH, QCH_CON_LH_ATB_MFC_QCH_S_SI, QCH_CON_LH_ATB_MFC_QCH_S_MI, QCH_CON_MFC_QCH, QCH_CON_MFC_CMU_MFC_QCH, QCH_CON_PGEN100_LITE_MFC_QCH, QCH_CON_PPMU_MFCD0_QCH, QCH_CON_PPMU_MFCD1_QCH, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC_MFC_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC_WFD_SW_RESET_QCH, QCH_CON_SYSMMU_MFCD0_QCH, QCH_CON_SYSMMU_MFCD1_QCH, QCH_CON_SYSREG_MFC_QCH, QCH_CON_WFD_QCH, CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X, CLK_CON_MUX_MUX_MIF_CMUREF, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK, CLK_CON_DIV_CLK_MIF_BUSD, PLL_CON0_PLL_MIF, PLL_LOCKTIME_PLL_MIF, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER, PLL_CON2_MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDR_PHY_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDR_PHY_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C, CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_ACLK, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CP_IPCLKPORT_I_CLK, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CPU_IPCLKPORT_I_CLK, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_NRT_IPCLKPORT_I_CLK, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_RT_IPCLKPORT_I_CLK, QCH_CON_BUSIF_HPMMIF_QCH, DMYQCH_CON_CMU_MIF_CMUREF_QCH, QCH_CON_DMC_QCH, QCH_CON_LHM_AXI_D_MIF_CP_QCH, QCH_CON_LHM_AXI_D_MIF_CPU_QCH, QCH_CON_LHM_AXI_D_MIF_NRT_QCH, QCH_CON_LHM_AXI_D_MIF_RT_QCH, QCH_CON_LHM_AXI_P_MIF_QCH, QCH_CON_MIF_CMU_MIF_QCH, QCH_CON_PPMU_DMC_CPU_QCH, QCH_CON_QE_DMC_CPU_QCH, QCH_CON_SFRAPB_BRIDGE_DDR_PHY_QCH, QCH_CON_SFRAPB_BRIDGE_DMC_QCH, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH, QCH_CON_SYSREG_MIF_QCH, PLL_CON0_PLL_MIF1, PLL_LOCKTIME_PLL_MIF1, CLK_CON_MUX_MUX_CLK_MIF1_DDRPHY_CLK2X, CLK_CON_DIV_CLK_MIF1_BUSD, PLL_CON0_MUX_CLKCMU_MIF1_BUSP_USER, PLL_CON2_MUX_CLKCMU_MIF1_BUSP_USER, CLK_CON_MUX_MUX_MIF1_CMUREF, CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PF, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PPMPU, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_SECURE, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_NRT_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_RT_IPCLKPORT_I_CLK, QCH_CON_BUSIF_HPMMIF1_QCH, DMYQCH_CON_CMU_MIF1_CMUREF_QCH, QCH_CON_DMC1_QCH, QCH_CON_LHM_AXI_D_MIF1_CP_QCH, QCH_CON_LHM_AXI_D_MIF1_CPU_QCH, QCH_CON_LHM_AXI_D_MIF1_NRT_QCH, QCH_CON_LHM_AXI_D_MIF1_RT_QCH, QCH_CON_MIF1_CMU_MIF1_QCH, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK, PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, PLL_CON2_MUX_CLKCMU_PERI_BUS_USER, PLL_CON0_MUX_CLKCMU_PERI_IP_USER, PLL_CON2_MUX_CLKCMU_PERI_IP_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_MOTOR_IPCLKPORT_I_PCLK_S0, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_IPCLKPORT_CLK, CLK_CON_GAT_GATE_CLK_PERI_I2C, CLK_CON_GAT_GATE_CLK_PERI_SPI0, CLK_CON_GAT_GATE_CLK_PERI_SPI1, CLK_CON_GAT_GATE_CLK_PERI_USI_USI, CLK_CON_GAT_GATE_CLK_PERI_USI_I2C, CLK_CON_GAT_GATE_CLK_PERI_SPI2, CLK_CON_DIV_DIV_CLK_PERI_I2C, CLK_CON_DIV_DIV_CLK_PERI_SPI0, CLK_CON_DIV_DIV_CLK_PERI_SPI1, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C, CLK_CON_DIV_DIV_CLK_PERI_USI_USI, CLK_CON_DIV_DIV_CLK_PERI_SPI2, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_I2C_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_0_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_1_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_I2C_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_2_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, PLL_CON2_MUX_CLKCMU_PERI_UART_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_3_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_4_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_5_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_6_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK, QCH_CON_BUSIF_TMU_QCH, QCH_CON_CAMI2C_0_QCH, QCH_CON_CAMI2C_1_QCH, QCH_CON_CAMI2C_2_QCH, QCH_CON_CAMI2C_3_QCH, QCH_CON_GPIO_PERI_QCH, QCH_CON_I2C_0_QCH, QCH_CON_I2C_1_QCH, QCH_CON_I2C_2_QCH, QCH_CON_I2C_3_QCH, QCH_CON_I2C_4_QCH, QCH_CON_I2C_5_QCH, QCH_CON_I2C_6_QCH, QCH_CON_LHM_AXI_P_PERI_QCH, QCH_CON_MCT_QCH, QCH_CON_OTP_CON_TOP_QCH, QCH_CON_PERI_CMU_PERI_QCH, QCH_CON_PWM_MOTOR_QCH, QCH_CON_SPI_0_QCH, QCH_CON_SPI_1_QCH, QCH_CON_SPI_2_QCH, QCH_CON_SYSREG_PERI_QCH, QCH_CON_UART_QCH, QCH_CON_USI00_I2C_QCH, QCH_CON_USI00_USI_QCH, QCH_CON_WDT_CLUSTER0_QCH, QCH_CON_WDT_CLUSTER1_QCH, CLK_CON_MUX_MUX_CLK_SHUB_USI00, PLL_CON0_MUX_CLKCMU_SHUB_BUS_USER, PLL_CON2_MUX_CLKCMU_SHUB_BUS_USER, CLK_CON_DIV_DIV_CLK_SHUB_USI01, CLK_CON_DIV_DIV_CLK_SHUB_I2C, CLK_CON_MUX_MUX_CLK_SHUB_USI01, CLK_CON_DIV_DIV_CLK_SHUB_USI00, CLK_CON_MUX_MUX_CLK_SHUB_I2C, CLK_CON_GAT_CLK_BLK_SHUB_UID_SHUB_CMU_SHUB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_D_SHUB_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_P_APM_SHUB_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_SHUB_UID_GPIO_SHUB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_LP_SHUB_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_P_SHUB_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_D_SHUB_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_P_APM_SHUB_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PWM_SHUB_IPCLKPORT_I_PCLK_S0, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_D_SHUB_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_P_APM_SHUB_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SYSREG_SHUB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_SHUB_UID_TIMER_SHUB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_SHUB_UID_WDT_SHUB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_BUS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_I2C_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_RTCCLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_USI00_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_SHUB_UID_CM4_SHUB_IPCLKPORT_FCLK, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PDMA_SHUB_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_SHUB_UID_XIU_DP_SHUB_IPCLKPORT_ACLK, QCH_CON_BAAW_D_SHUB_QCH, QCH_CON_BAAW_P_APM_SHUB_QCH, QCH_CON_CM4_SHUB_QCH, QCH_CON_GPIO_SHUB_QCH, QCH_CON_I2C_SHUB00_QCH, QCH_CON_LHM_AXI_LP_SHUB_QCH, QCH_CON_LHM_AXI_P_SHUB_QCH, QCH_CON_LHS_AXI_D_SHUB_QCH, QCH_CON_LHS_AXI_P_APM_SHUB_QCH, QCH_CON_PDMA_SHUB_QCH, QCH_CON_PWM_SHUB_QCH, QCH_CON_SHUB_CMU_SHUB_QCH, QCH_CON_SWEEPER_D_SHUB_QCH, QCH_CON_SWEEPER_P_APM_SHUB_QCH, QCH_CON_SYSREG_SHUB_QCH, QCH_CON_TIMER_SHUB_QCH, QCH_CON_USI_SHUB00_QCH, QCH_CON_WDT_SHUB_QCH, PLL_CON0_MUX_CLKCMU_USB_BUS_USER, PLL_CON2_MUX_CLKCMU_USB_BUS_USER, CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK, PLL_CON0_MUX_CLKCMU_USB_USB30DRD_USER, PLL_CON2_MUX_CLKCMU_USB_USB30DRD_USER, PLL_CON0_MUX_CLKCMU_USB_DPGTC_USER, PLL_CON2_MUX_CLKCMU_USB_DPGTC_USER, CLK_CON_GAT_GOUT_BLK_USB_UID_LHM_AXI_P_USB_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_BUS_CLK_EARLY, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_DP_GTC_CLK, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_USB_UID_RSTNSYNC_CLK_USB_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_20, CLK_CON_GAT_GOUT_BLK_USB_UID_PGEN_LITE_USB_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_1, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_USB_UID_US_D_USB_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_PCLK, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_0, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_USB30DRD_REF_CLK, CLK_CON_GAT_GOUT_BLK_USB_UID_LHS_ACEL_D_USB_IPCLKPORT_I_CLK, QCH_CON_BTM_USB_QCH, QCH_CON_DP_LINK_QCH_DP, QCH_CON_DP_LINK_QCH_GTC, QCH_CON_LHM_AXI_P_USB_QCH, QCH_CON_LHS_ACEL_D_USB_QCH, QCH_CON_PGEN_LITE_USB_QCH, QCH_CON_PPMU_USB_QCH, QCH_CON_SYSREG_USB_QCH, QCH_CON_USB30DRD_QCH_USB30, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_0, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_1, QCH_CON_USB30DRD_QCH_USBPHY_20CTRL, QCH_CON_USB_CMU_USB_QCH, CLK_CON_DIV_DIV_CLK_VIPX1_BUSP, PLL_CON0_MUX_CLKCMU_VIPX1_BUS_USER, PLL_CON2_MUX_CLKCMU_VIPX1_BUS_USER, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ACEL_D_VIPX1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SYSREG_VIPX1_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_VIPX1_UID_VIPX1_CMU_VIPX1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ATB_VIPX1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BLK_VIPX1_IPCLKPORT_CLK_VIPX1_BUSD, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SMMU_D_VIPX1_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_XIU_D_VIPX1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PGEN_LITE_VIPX1_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_VIPX1_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_AXI_P_VIPX1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_ATB_VIPX1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_AXI_P_VIPX1_LOCAL_IPCLKPORT_I_CLK, QCH_CON_BTM_D_VIPX1_QCH, QCH_CON_LHM_ATB_VIPX1_QCH, QCH_CON_LHM_AXI_P_VIPX1_QCH, QCH_CON_LHS_ACEL_D_VIPX1_QCH, QCH_CON_LHS_ATB_VIPX1_QCH, QCH_CON_LHS_AXI_P_VIPX1_LOCAL_QCH, QCH_CON_PGEN_LITE_VIPX1_QCH, QCH_CON_PPMU_D_VIPX1_QCH, QCH_CON_SMMU_D_VIPX1_QCH, QCH_CON_SYSREG_VIPX1_QCH, QCH_CON_VIPX1_QCH, QCH_CON_VIPX1_CMU_VIPX1_QCH, CLK_CON_DIV_DIV_CLK_VIPX2_BUSP, PLL_CON0_MUX_CLKCMU_VIPX2_BUS_USER, PLL_CON2_MUX_CLKCMU_VIPX2_BUS_USER, CLK_CON_GAT_CLK_BLK_VIPX2_UID_VIPX2_CMU_VIPX2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_ATB_VIPX2_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ACEL_D_VIPX2_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ATB_VIPX2_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_LOCAL_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PGEN_LITE_VIPX2_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SMMU_D_VIPX2_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SYSREG_VIPX2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BLK_VIPX2_IPCLKPORT_CLK_VIPX2_BUSD, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_VIPX2_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_OSCCLK_IPCLKPORT_CLK, QCH_CON_BTM_D_VIPX2_QCH, QCH_CON_LHM_ATB_VIPX2_QCH, QCH_CON_LHM_AXI_P_VIPX2_QCH, QCH_CON_LHM_AXI_P_VIPX2_LOCAL_QCH, QCH_CON_LHS_ACEL_D_VIPX2_QCH, QCH_CON_LHS_ATB_VIPX2_QCH, QCH_CON_PGEN_LITE_VIPX2_QCH, QCH_CON_PPMU_D_VIPX2_QCH, QCH_CON_SMMU_D_VIPX2_QCH, QCH_CON_SYSREG_VIPX2_QCH, QCH_CON_VIPX2_QCH, QCH_CON_VIPX2_QCH_LOCAL, QCH_CON_VIPX2_CMU_VIPX2_QCH, /*====================The section of controller option SFR===================*/ APM_CMU_APM_CONTROLLER_OPTION, CAM_CMU_CAM_CONTROLLER_OPTION, CMGP_CMU_CMGP_CONTROLLER_OPTION, CMU_CMU_TOP_CONTROLLER_OPTION, CORE_CMU_CORE_CONTROLLER_OPTION, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION, CPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTION, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION, CPUCL1_EMBEDDED_CMU_CPUCL1_CONTROLLER_OPTION, DISPAUD_CMU_DISPAUD_CONTROLLER_OPTION, FSYS_CMU_FSYS_CONTROLLER_OPTION, G2D_CMU_G2D_CONTROLLER_OPTION, G3D_CMU_G3D_CONTROLLER_OPTION, ISP_CMU_ISP_CONTROLLER_OPTION, MFC_CMU_MFC_CONTROLLER_OPTION, MIF_CMU_MIF_CONTROLLER_OPTION, MIF1_CMU_MIF1_CONTROLLER_OPTION, PERI_CMU_PERI_CONTROLLER_OPTION, SHUB_CMU_SHUB_CONTROLLER_OPTION, USB_CMU_USB_CONTROLLER_OPTION, VIPX1_CMU_VIPX1_CONTROLLER_OPTION, VIPX2_CMU_VIPX2_CONTROLLER_OPTION, end_of_sfr, num_of_sfr = end_of_sfr - SFR_TYPE, }; /*====================The section of SFR access===================*/ enum sfr_access_id { PLL_CON0_MUX_CLKCMU_APM_BUS_USER_BUSY = SFR_ACCESS_TYPE, PLL_CON0_MUX_CLKCMU_APM_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_APM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_APM_BUS_BUSY, CLK_CON_DIV_DIV_CLK_APM_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_APM_BUS_DIVRATIO, CLK_CON_MUX_MUX_CLK_APM_BUS_BUSY, CLK_CON_MUX_MUX_CLK_APM_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_APM_BUS_SELECT, PLL_CON0_MUX_DLL_USER_BUSY, PLL_CON0_MUX_DLL_USER_MUX_SEL, PLL_CON2_MUX_DLL_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_SHUB_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_SHUB_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_SHUB_BUS_SELECT, CLK_CON_DIV_CLKCMU_SHUB_BUS_BUSY, CLK_CON_DIV_CLKCMU_SHUB_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_SHUB_BUS_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_SHUB_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_SHUB_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_SHUB_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLKCMU_CMGP_BUS_CG_VAL, CLK_CON_GAT_CLKCMU_CMGP_BUS_MANUAL, CLK_CON_GAT_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_SHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_SHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_SHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_SHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_LP_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2CP_S_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2WLBT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2WLBT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2ABOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2ABOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_WLBT2ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_LITE_APM_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_LITE_APM_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PGEN_LITE_APM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_WLBT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_WLBT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_WLBT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2WLBT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2WLBT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_SHUB2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2WLBT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2WLBT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_CP2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_APBIF_GPIO_ALIVE_QCH_ENABLE, QCH_CON_APBIF_GPIO_ALIVE_QCH_CLOCK_REQ, QCH_CON_APBIF_GPIO_ALIVE_QCH_EXPIRE_VAL, QCH_CON_APBIF_GPIO_ALIVE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_APBIF_PMU_ALIVE_QCH_ENABLE, QCH_CON_APBIF_PMU_ALIVE_QCH_CLOCK_REQ, QCH_CON_APBIF_PMU_ALIVE_QCH_EXPIRE_VAL, QCH_CON_APBIF_PMU_ALIVE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_APBIF_RTC_QCH_ENABLE, QCH_CON_APBIF_RTC_QCH_CLOCK_REQ, QCH_CON_APBIF_RTC_QCH_EXPIRE_VAL, QCH_CON_APBIF_RTC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_APBIF_TOP_RTC_QCH_ENABLE, QCH_CON_APBIF_TOP_RTC_QCH_CLOCK_REQ, QCH_CON_APBIF_TOP_RTC_QCH_EXPIRE_VAL, QCH_CON_APBIF_TOP_RTC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_APM_CMU_APM_QCH_ENABLE, QCH_CON_APM_CMU_APM_QCH_CLOCK_REQ, QCH_CON_APM_CMU_APM_QCH_EXPIRE_VAL, QCH_CON_APM_CMU_APM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_GREBEINTEGRATION_QCH_GREBE_ENABLE, QCH_CON_GREBEINTEGRATION_QCH_GREBE_CLOCK_REQ, QCH_CON_GREBEINTEGRATION_QCH_GREBE_EXPIRE_VAL, QCH_CON_GREBEINTEGRATION_QCH_GREBE_IGNORE_FORCE_PM_EN, QCH_CON_GREBEINTEGRATION_QCH_DBG_ENABLE, QCH_CON_GREBEINTEGRATION_QCH_DBG_CLOCK_REQ, QCH_CON_GREBEINTEGRATION_QCH_DBG_EXPIRE_VAL, QCH_CON_GREBEINTEGRATION_QCH_DBG_IGNORE_FORCE_PM_EN, QCH_CON_INTMEM_QCH_ENABLE, QCH_CON_INTMEM_QCH_CLOCK_REQ, QCH_CON_INTMEM_QCH_EXPIRE_VAL, QCH_CON_INTMEM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_P_APM_QCH_ENABLE, QCH_CON_LHM_AXI_P_APM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_APM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_APM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_P_APM_GNSS_QCH_ENABLE, QCH_CON_LHM_AXI_P_APM_GNSS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_APM_GNSS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_APM_GNSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_P_APM_MODEM_QCH_ENABLE, QCH_CON_LHM_AXI_P_APM_MODEM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_APM_MODEM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_APM_MODEM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_P_APM_SHUB_QCH_ENABLE, QCH_CON_LHM_AXI_P_APM_SHUB_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_APM_SHUB_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_APM_SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_P_APM_WLBT_QCH_ENABLE, QCH_CON_LHM_AXI_P_APM_WLBT_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_APM_WLBT_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_APM_WLBT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_D_APM_QCH_ENABLE, QCH_CON_LHS_AXI_D_APM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_APM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_APM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_LP_SHUB_QCH_ENABLE, QCH_CON_LHS_AXI_LP_SHUB_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_LP_SHUB_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_LP_SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_AP2CP_QCH_ENABLE, QCH_CON_MAILBOX_AP2CP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP2CP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP2CP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_AP2CP_S_QCH_ENABLE, QCH_CON_MAILBOX_AP2CP_S_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP2CP_S_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP2CP_S_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_AP2GNSS_QCH_ENABLE, QCH_CON_MAILBOX_AP2GNSS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP2GNSS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP2GNSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_AP2SHUB_QCH_ENABLE, QCH_CON_MAILBOX_AP2SHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP2SHUB_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP2SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_AP2WLBT_QCH_ENABLE, QCH_CON_MAILBOX_AP2WLBT_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP2WLBT_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP2WLBT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_APM2AP_QCH_ENABLE, QCH_CON_MAILBOX_APM2AP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM2AP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM2AP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_APM2CP_QCH_ENABLE, QCH_CON_MAILBOX_APM2CP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM2CP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM2CP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_APM2GNSS_QCH_ENABLE, QCH_CON_MAILBOX_APM2GNSS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM2GNSS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM2GNSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_APM2SHUB_QCH_ENABLE, QCH_CON_MAILBOX_APM2SHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM2SHUB_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM2SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_APM2WLBT_QCH_ENABLE, QCH_CON_MAILBOX_APM2WLBT_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM2WLBT_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM2WLBT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_CP2GNSS_QCH_ENABLE, QCH_CON_MAILBOX_CP2GNSS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_CP2GNSS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_CP2GNSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_CP2SHUB_QCH_ENABLE, QCH_CON_MAILBOX_CP2SHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_CP2SHUB_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_CP2SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_CP2WLBT_QCH_ENABLE, QCH_CON_MAILBOX_CP2WLBT_QCH_CLOCK_REQ, QCH_CON_MAILBOX_CP2WLBT_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_CP2WLBT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_SHUB2GNSS_QCH_ENABLE, QCH_CON_MAILBOX_SHUB2GNSS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_SHUB2GNSS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_SHUB2GNSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_SHUB2WLBT_QCH_ENABLE, QCH_CON_MAILBOX_SHUB2WLBT_QCH_CLOCK_REQ, QCH_CON_MAILBOX_SHUB2WLBT_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_SHUB2WLBT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_WLBT2ABOX_QCH_ENABLE, QCH_CON_MAILBOX_WLBT2ABOX_QCH_CLOCK_REQ, QCH_CON_MAILBOX_WLBT2ABOX_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_WLBT2ABOX_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_WLBT2GNSS_QCH_ENABLE, QCH_CON_MAILBOX_WLBT2GNSS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_WLBT2GNSS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_WLBT2GNSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PEM_QCH_ENABLE, QCH_CON_PEM_QCH_CLOCK_REQ, QCH_CON_PEM_QCH_EXPIRE_VAL, QCH_CON_PEM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PGEN_LITE_APM_QCH_ENABLE, QCH_CON_PGEN_LITE_APM_QCH_CLOCK_REQ, QCH_CON_PGEN_LITE_APM_QCH_EXPIRE_VAL, QCH_CON_PGEN_LITE_APM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PMU_INTR_GEN_QCH_ENABLE, QCH_CON_PMU_INTR_GEN_QCH_CLOCK_REQ, QCH_CON_PMU_INTR_GEN_QCH_EXPIRE_VAL, QCH_CON_PMU_INTR_GEN_QCH_IGNORE_FORCE_PM_EN, QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SPEEDY_APM_QCH_ENABLE, QCH_CON_SPEEDY_APM_QCH_CLOCK_REQ, QCH_CON_SPEEDY_APM_QCH_EXPIRE_VAL, QCH_CON_SPEEDY_APM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_APM_QCH_ENABLE, QCH_CON_SYSREG_APM_QCH_CLOCK_REQ, QCH_CON_SYSREG_APM_QCH_EXPIRE_VAL, QCH_CON_SYSREG_APM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_WDT_APM_QCH_ENABLE, QCH_CON_WDT_APM_QCH_CLOCK_REQ, QCH_CON_WDT_APM_QCH_EXPIRE_VAL, QCH_CON_WDT_APM_QCH_IGNORE_FORCE_PM_EN, PLL_CON0_MUX_CLKCMU_CAM_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_CAM_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_CAM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CAM_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_CAM_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CAM_BUSP_DIVRATIO, CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ATB_CAMISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ATB_CAMISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ATB_CAMISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ACEL_D_CAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ACEL_D_CAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_ACEL_D_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CAM_UID_RSTNSYNC_CLK_CAM_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CAM_UID_RSTNSYNC_CLK_CAM_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CAM_UID_RSTNSYNC_CLK_CAM_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_XIU_D_CAM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_XIU_D_CAM_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_XIU_D_CAM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PPMU_CAM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PPMU_CAM_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PPMU_CAM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PPMU_CAM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PPMU_CAM_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PPMU_CAM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_SMMU_CAM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_SMMU_CAM_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_SMMU_CAM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_3AA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_3AA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_3AA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS2_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS3_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS3_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_CSIS3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_BLK_CAM_IPCLKPORT_CLK_CAM_BUSD_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BLK_CAM_IPCLKPORT_CLK_CAM_BUSD_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BLK_CAM_IPCLKPORT_CLK_CAM_BUSD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_DMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_DMA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PAFSTAT_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PAFSTAT_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_PAFSTAT_CORE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_RDMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_RDMA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_RDMA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS2_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS3_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS3_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_ACLK_GLUE_CSIS3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS6P10P0_CAM_IPCLKPORT_PCLK_PGEN_LITE_CAM1_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BTM_CAM_QCH_ENABLE, QCH_CON_BTM_CAM_QCH_CLOCK_REQ, QCH_CON_BTM_CAM_QCH_EXPIRE_VAL, QCH_CON_BTM_CAM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_CAM_CMU_CAM_QCH_ENABLE, QCH_CON_CAM_CMU_CAM_QCH_CLOCK_REQ, QCH_CON_CAM_CMU_CAM_QCH_EXPIRE_VAL, QCH_CON_CAM_CMU_CAM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_P_CAM_QCH_ENABLE, QCH_CON_LHM_AXI_P_CAM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_CAM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_CAM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_ACEL_D_CAM_QCH_ENABLE, QCH_CON_LHS_ACEL_D_CAM_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_CAM_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_CAM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_ATB_CAMISP_QCH_ENABLE, QCH_CON_LHS_ATB_CAMISP_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_CAMISP_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_CAMISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_CAM_QCH_ENABLE, QCH_CON_SYSREG_CAM_QCH_CLOCK_REQ, QCH_CON_SYSREG_CAM_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CAM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS0_ENABLE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS0_CLOCK_REQ, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS0_EXPIRE_VAL, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS0_IGNORE_FORCE_PM_EN, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS1_ENABLE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS1_CLOCK_REQ, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS1_EXPIRE_VAL, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS1_IGNORE_FORCE_PM_EN, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS2_ENABLE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS2_CLOCK_REQ, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS2_EXPIRE_VAL, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS2_IGNORE_FORCE_PM_EN, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS3_ENABLE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS3_CLOCK_REQ, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS3_EXPIRE_VAL, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_CSIS3_IGNORE_FORCE_PM_EN, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_3AA_ENABLE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_3AA_CLOCK_REQ, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_3AA_EXPIRE_VAL, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_3AA_IGNORE_FORCE_PM_EN, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PPMU_ENABLE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PPMU_CLOCK_REQ, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PPMU_EXPIRE_VAL, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PPMU_IGNORE_FORCE_PM_EN, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_SMMU_ENABLE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_SMMU_CLOCK_REQ, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_SMMU_EXPIRE_VAL, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_SMMU_IGNORE_FORCE_PM_EN, QCH_CON_IS6P10P0_CAM_QCH_S_CAM0_PGEN_LITE_ENABLE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM0_PGEN_LITE_CLOCK_REQ, QCH_CON_IS6P10P0_CAM_QCH_S_CAM0_PGEN_LITE_EXPIRE_VAL, QCH_CON_IS6P10P0_CAM_QCH_S_CAM0_PGEN_LITE_IGNORE_FORCE_PM_EN, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE_ENABLE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE_CLOCK_REQ, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE_EXPIRE_VAL, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE_IGNORE_FORCE_PM_EN, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA_ENABLE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA_CLOCK_REQ, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA_EXPIRE_VAL, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA_IGNORE_FORCE_PM_EN, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_RDMA_ENABLE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_RDMA_CLOCK_REQ, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_RDMA_EXPIRE_VAL, QCH_CON_IS6P10P0_CAM_QCH_S_CAM_RDMA_IGNORE_FORCE_PM_EN, QCH_CON_IS6P10P0_CAM_QCH_S_CAM1_PGEN_LITE_ENABLE, QCH_CON_IS6P10P0_CAM_QCH_S_CAM1_PGEN_LITE_CLOCK_REQ, QCH_CON_IS6P10P0_CAM_QCH_S_CAM1_PGEN_LITE_EXPIRE_VAL, QCH_CON_IS6P10P0_CAM_QCH_S_CAM1_PGEN_LITE_IGNORE_FORCE_PM_EN, CLK_CON_DIV_DIV_CLK_CMGP_USI03_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI03_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CMGP_USI03_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI00_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI00_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CMGP_USI00_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_I2C_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_I2C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CMGP_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI01_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI01_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CMGP_USI01_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI04_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI04_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CMGP_USI04_DIVRATIO, CLK_CON_MUX_MUX_CLK_CMGP_USI01_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI01_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CMGP_USI01_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_I2C_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_I2C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CMGP_I2C_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI00_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI00_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CMGP_USI00_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI04_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI04_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CMGP_USI04_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI02_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI02_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CMGP_USI02_SELECT, CLK_CON_DIV_DIV_CLK_CMGP_USI02_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI02_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CMGP_USI02_DIVRATIO, CLK_CON_MUX_MUX_CLK_CMGP_USI03_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI03_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CMGP_USI03_SELECT, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CMGP_ADC_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CMGP_ADC_SELECT, CLK_CON_DIV_DIV_CLK_CMGP_ADC_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CMGP_ADC_DIVRATIO, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI00_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI00_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI00_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI01_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI01_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI01_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI02_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI02_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI02_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI03_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI03_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI03_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI04_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI04_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI04_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP01_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP02_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP03_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP04_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP01_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP02_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP03_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP04_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_ADC_CMGP_QCH_S0_ENABLE, QCH_CON_ADC_CMGP_QCH_S0_CLOCK_REQ, QCH_CON_ADC_CMGP_QCH_S0_EXPIRE_VAL, QCH_CON_ADC_CMGP_QCH_S0_IGNORE_FORCE_PM_EN, QCH_CON_ADC_CMGP_QCH_S1_ENABLE, QCH_CON_ADC_CMGP_QCH_S1_CLOCK_REQ, QCH_CON_ADC_CMGP_QCH_S1_EXPIRE_VAL, QCH_CON_ADC_CMGP_QCH_S1_IGNORE_FORCE_PM_EN, DMYQCH_CON_ADC_CMGP_QCH_ADC_ENABLE, DMYQCH_CON_ADC_CMGP_QCH_ADC_CLOCK_REQ, DMYQCH_CON_ADC_CMGP_QCH_ADC_IGNORE_FORCE_PM_EN, QCH_CON_CMGP_CMU_CMGP_QCH_ENABLE, QCH_CON_CMGP_CMU_CMGP_QCH_CLOCK_REQ, QCH_CON_CMGP_CMU_CMGP_QCH_EXPIRE_VAL, QCH_CON_CMGP_CMU_CMGP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_GPIO_CMGP_QCH_ENABLE, QCH_CON_GPIO_CMGP_QCH_CLOCK_REQ, QCH_CON_GPIO_CMGP_QCH_EXPIRE_VAL, QCH_CON_GPIO_CMGP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_I2C_CMGP00_QCH_ENABLE, QCH_CON_I2C_CMGP00_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP00_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP00_QCH_IGNORE_FORCE_PM_EN, QCH_CON_I2C_CMGP01_QCH_ENABLE, QCH_CON_I2C_CMGP01_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP01_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP01_QCH_IGNORE_FORCE_PM_EN, QCH_CON_I2C_CMGP02_QCH_ENABLE, QCH_CON_I2C_CMGP02_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP02_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP02_QCH_IGNORE_FORCE_PM_EN, QCH_CON_I2C_CMGP03_QCH_ENABLE, QCH_CON_I2C_CMGP03_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP03_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP03_QCH_IGNORE_FORCE_PM_EN, QCH_CON_I2C_CMGP04_QCH_ENABLE, QCH_CON_I2C_CMGP04_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP04_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP04_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_CMGP_QCH_ENABLE, QCH_CON_SYSREG_CMGP_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_CMGP2CP_QCH_ENABLE, QCH_CON_SYSREG_CMGP2CP_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2CP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2CP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_CMGP2GNSS_QCH_ENABLE, QCH_CON_SYSREG_CMGP2GNSS_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2GNSS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2GNSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_ENABLE, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_CMGP2PMU_SHUB_QCH_ENABLE, QCH_CON_SYSREG_CMGP2PMU_SHUB_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2PMU_SHUB_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2PMU_SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_CMGP2SHUB_QCH_ENABLE, QCH_CON_SYSREG_CMGP2SHUB_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2SHUB_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_CMGP2WLBT_QCH_ENABLE, QCH_CON_SYSREG_CMGP2WLBT_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2WLBT_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2WLBT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI_CMGP00_QCH_ENABLE, QCH_CON_USI_CMGP00_QCH_CLOCK_REQ, QCH_CON_USI_CMGP00_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP00_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI_CMGP01_QCH_ENABLE, QCH_CON_USI_CMGP01_QCH_CLOCK_REQ, QCH_CON_USI_CMGP01_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP01_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI_CMGP02_QCH_ENABLE, QCH_CON_USI_CMGP02_QCH_CLOCK_REQ, QCH_CON_USI_CMGP02_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP02_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI_CMGP03_QCH_ENABLE, QCH_CON_USI_CMGP03_QCH_CLOCK_REQ, QCH_CON_USI_CMGP03_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP03_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI_CMGP04_QCH_ENABLE, QCH_CON_USI_CMGP04_QCH_CLOCK_REQ, QCH_CON_USI_CMGP04_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP04_QCH_IGNORE_FORCE_PM_EN, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_BUSY, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_SELECT, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_DISP_BUSY, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_DISP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_DISP_SELECT, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_DISP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_DISP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_DISP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_DISPAUD_DISP_BUSY, CLK_CON_DIV_CLKCMU_DISPAUD_DISP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_DISPAUD_DISP_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD_SELECT, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_FSYS_BUS_BUSY, CLK_CON_DIV_CLKCMU_FSYS_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_FSYS_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_G2D_MSCL_BUSY, CLK_CON_DIV_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_G2D_MSCL_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK_BUSY, CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_SELECT, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERI_BUS_BUSY, CLK_CON_DIV_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERI_BUS_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_PERI_IP_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERI_IP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERI_IP_SELECT, CLK_CON_GAT_GATE_CLKCMU_PERI_IP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERI_IP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERI_IP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERI_IP_BUSY, CLK_CON_DIV_CLKCMU_PERI_IP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERI_IP_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_APM_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_APM_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_APM_BUS_BUSY, CLK_CON_DIV_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_APM_BUS_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD_SELECT, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD_BUSY, CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK0_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CIS_CLK0_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK1_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CIS_CLK1_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK2_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CIS_CLK2_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_SELECT, CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD_BUSY, CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK_BUSY, CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK_DIVRATIO, CLK_CON_MUX_MUX_CMU_CMUREF_BUSY, CLK_CON_MUX_MUX_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CMU_CMUREF_SELECT, CLK_CON_MUX_MUX_CLK_CMU_CMUREF_BUSY, CLK_CON_MUX_MUX_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CMU_CMUREF_SELECT, CLK_CON_DIV_DIV_CLK_CMU_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CMU_CMUREF_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_APM_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_APM_BUS_SELECT, PLL_CON0_PLL_SHARED0_DIV_P, PLL_CON0_PLL_SHARED0_DIV_M, PLL_CON0_PLL_SHARED0_DIV_S, PLL_CON0_PLL_SHARED0_ENABLE, PLL_CON0_PLL_SHARED0_STABLE, PLL_LOCKTIME_PLL_SHARED0_PLL_LOCK_TIME, PLL_CON0_PLL_SHARED1_DIV_P, PLL_CON0_PLL_SHARED1_DIV_M, PLL_CON0_PLL_SHARED1_DIV_S, PLL_CON0_PLL_SHARED1_ENABLE, PLL_CON0_PLL_SHARED1_STABLE, PLL_LOCKTIME_PLL_SHARED1_PLL_LOCK_TIME, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CORE_BUS_BUSY, CLK_CON_DIV_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CORE_BUS_DIVRATIO, CLK_CON_DIV_PLL_SHARED0_DIV3_BUSY, CLK_CON_DIV_PLL_SHARED0_DIV3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_PLL_SHARED0_DIV3_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUSY, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_PLL_SHARED0_DIV2_BUSY, CLK_CON_DIV_PLL_SHARED0_DIV2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_PLL_SHARED0_DIV2_DIVRATIO, CLK_CON_DIV_PLL_SHARED0_DIV4_BUSY, CLK_CON_DIV_PLL_SHARED0_DIV4_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_PLL_SHARED0_DIV4_DIVRATIO, CLK_CON_DIV_PLL_SHARED1_DIV2_BUSY, CLK_CON_DIV_PLL_SHARED1_DIV2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_PLL_SHARED1_DIV2_DIVRATIO, CLK_CON_DIV_PLL_SHARED1_DIV4_BUSY, CLK_CON_DIV_PLL_SHARED1_DIV4_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_PLL_SHARED1_DIV4_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_CORE_CCI_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CORE_CCI_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CORE_CCI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CORE_CCI_BUSY, CLK_CON_DIV_CLKCMU_CORE_CCI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CORE_CCI_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CORE_G3D_BUSY, CLK_CON_DIV_CLKCMU_CORE_G3D_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CORE_G3D_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_CORE_CCI_BUSY, CLK_CON_MUX_MUX_CLKCMU_CORE_CCI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CORE_CCI_SELECT, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D_BUSY, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D_SELECT, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_BUSY, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_SELECT, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_MIF_BUSP_BUSY, CLK_CON_DIV_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_MIF_BUSP_DIVRATIO, CLK_CON_DIV_PLL_SHARED1_DIV3_BUSY, CLK_CON_DIV_PLL_SHARED1_DIV3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_PLL_SHARED1_DIV3_DIVRATIO, PLL_CON0_PLL_MMC_DIV_P, PLL_CON0_PLL_MMC_DIV_M, PLL_CON0_PLL_MMC_DIV_S, PLL_CON0_PLL_MMC_ENABLE, PLL_CON0_PLL_MMC_STABLE, PLL_CON3_PLL_MMC_DIV_K, PLL_LOCKTIME_PLL_MMC_PLL_LOCK_TIME, CLK_CON_MUX_MUX_CLKCMU_FSYS_UFS_EMBD_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_FSYS_UFS_EMBD_SELECT, CLK_CON_GAT_GATE_CLKCMU_FSYS_UFS_EMBD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_UFS_EMBD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_FSYS_UFS_EMBD_BUSY, CLK_CON_DIV_CLKCMU_FSYS_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_FSYS_UFS_EMBD_DIVRATIO, CLK_CON_DIV_CLKCMU_CAM_BUS_BUSY, CLK_CON_DIV_CLKCMU_CAM_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CAM_BUS_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_CAM_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CAM_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CAM_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CAM_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CAM_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CAM_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_VIPX1_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_VIPX1_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_VIPX1_BUS_SELECT, CLK_CON_GAT_GATE_CLKCMU_VIPX1_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_VIPX1_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_VIPX1_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_VIPX1_BUS_BUSY, CLK_CON_DIV_CLKCMU_VIPX1_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_VIPX1_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_ISP_BUS_BUSY, CLK_CON_DIV_CLKCMU_ISP_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_ISP_BUS_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS_SELECT, CLK_CON_GAT_GATE_CLKCMU_ISP_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ISP_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ISP_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_ISP_VRA_BUSY, CLK_CON_DIV_CLKCMU_ISP_VRA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_ISP_VRA_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_ISP_VRA_BUSY, CLK_CON_MUX_MUX_CLKCMU_ISP_VRA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_ISP_VRA_SELECT, CLK_CON_GAT_GATE_CLKCMU_ISP_VRA_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ISP_VRA_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ISP_VRA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_ISP_GDC_BUSY, CLK_CON_DIV_CLKCMU_ISP_GDC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_ISP_GDC_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_ISP_GDC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ISP_GDC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ISP_GDC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_ISP_GDC_BUSY, CLK_CON_MUX_MUX_CLKCMU_ISP_GDC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_ISP_GDC_SELECT, CLK_CON_DIV_CLKCMU_G2D_G2D_BUSY, CLK_CON_DIV_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_G2D_G2D_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_BUSY, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_SELECT, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_SELECT, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_SELECT, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_G3D_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_G3D_SWITCH_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_SELECT, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_CPU_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_CPU_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_CPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_DISPAUD_CPU_BUSY, CLK_CON_DIV_CLKCMU_DISPAUD_CPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_DISPAUD_CPU_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_CPU_BUSY, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_CPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_CPU_SELECT, CLK_CON_GAT_CLKCMU_MIF_SWITCH_CG_VAL, CLK_CON_GAT_CLKCMU_MIF_SWITCH_MANUAL, CLK_CON_GAT_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_SELECT, CLK_CON_MUX_MUX_CLKCMU_USB_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_USB_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_USB_BUS_SELECT, CLK_CON_DIV_CLKCMU_USB_BUS_BUSY, CLK_CON_DIV_CLKCMU_USB_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_USB_BUS_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_USB_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_USB_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_USB_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_USB_USB30DRD_BUSY, CLK_CON_MUX_MUX_CLKCMU_USB_USB30DRD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_USB_USB30DRD_SELECT, CLK_CON_DIV_CLKCMU_USB_USB30DRD_BUSY, CLK_CON_DIV_CLKCMU_USB_USB30DRD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_USB_USB30DRD_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_USB_USB30DRD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_USB_USB30DRD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_USB_USB30DRD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_USB_DPGTC_BUSY, CLK_CON_MUX_MUX_CLKCMU_USB_DPGTC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_USB_DPGTC_SELECT, CLK_CON_GAT_GATE_CLKCMU_USB_DPGTC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_USB_DPGTC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_USB_DPGTC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_USB_DPGTC_BUSY, CLK_CON_DIV_CLKCMU_USB_DPGTC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_USB_DPGTC_DIVRATIO, CLK_CON_DIV_CLKCMU_DISPAUD_AUD_BUSY, CLK_CON_DIV_CLKCMU_DISPAUD_AUD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_DISPAUD_AUD_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_AUD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_AUD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DISPAUD_AUD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_AUD_BUSY, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_AUD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_DISPAUD_AUD_SELECT, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_MFC_WFD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MFC_WFD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_MFC_MFC_BUSY, CLK_CON_DIV_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_MFC_MFC_DIVRATIO, CLK_CON_DIV_CLKCMU_MFC_WFD_BUSY, CLK_CON_DIV_CLKCMU_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_MFC_WFD_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_BUSY, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_SELECT, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD_BUSY, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD_SELECT, CLK_CON_MUX_MUX_CLKCMU_HPM_BUSY, CLK_CON_MUX_MUX_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_HPM_SELECT, CLK_CON_GAT_GATE_CLKCMU_HPM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HPM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_HPM_BUSY, CLK_CON_DIV_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_HPM_DIVRATIO, CLK_CON_DIV_CLKCMU_PERI_UART_BUSY, CLK_CON_DIV_CLKCMU_PERI_UART_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERI_UART_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERI_UART_SELECT, CLK_CON_GAT_GATE_CLKCMU_PERI_UART_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERI_UART_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERI_UART_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_OTP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CMU_UID_OTP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMU_UID_OTP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMU_UID_OTP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_VIPX2_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_VIPX2_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_VIPX2_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_VIPX2_BUS_BUSY, CLK_CON_DIV_CLKCMU_VIPX2_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_VIPX2_BUS_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_VIPX2_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_VIPX2_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_VIPX2_BUS_SELECT, CLK_CON_DIV_CLKCMU_CIS_CLK3_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CIS_CLK3_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_SELECT, CLK_CON_DIV_PLL_MMC_DIV2_BUSY, CLK_CON_DIV_PLL_MMC_DIV2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_PLL_MMC_DIV2_DIVRATIO, DMYQCH_CON_CMU_TOP_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_TOP_CMUREF_QCH_CLOCK_REQ, DMYQCH_CON_CMU_TOP_CMUREF_QCH_IGNORE_FORCE_PM_EN, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS0_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS0_CLOCK_REQ, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS0_IGNORE_FORCE_PM_EN, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS1_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS1_CLOCK_REQ, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS1_IGNORE_FORCE_PM_EN, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS2_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS2_CLOCK_REQ, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS2_IGNORE_FORCE_PM_EN, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS3_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS3_CLOCK_REQ, DMYQCH_CON_DFTMUX_TOP_QCH_CLK_CSIS3_IGNORE_FORCE_PM_EN, DMYQCH_CON_OTP_QCH_ENABLE, DMYQCH_CON_OTP_QCH_CLOCK_REQ, DMYQCH_CON_OTP_QCH_IGNORE_FORCE_PM_EN, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_CORE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CORE_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_CORE_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CORE_BUSP_DIVRATIO, CLK_CON_MUX_MUX_CLK_CORE_GIC_BUSY, CLK_CON_MUX_MUX_CLK_CORE_GIC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CORE_GIC_SELECT, PLL_CON0_MUX_CLKCMU_CORE_CCI_USER_BUSY, PLL_CON0_MUX_CLKCMU_CORE_CCI_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_CORE_CCI_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC400_AIHWACG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC400_AIHWACG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC400_AIHWACG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_CAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_CAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_WLBT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DISPAUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_FSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_ACE_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_OCC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_OCC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_OCC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_OCC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_OCC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_OCC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_CCI_550_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_CCI_550_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_CCI_550_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_CORE_G3D_USER_BUSY, PLL_CON0_MUX_CLKCMU_CORE_G3D_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_CORE_G3D_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_OCC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_OCC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_OCC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_CCI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_NRT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_NRT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_NRT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_NRT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_FSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_FSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_FSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_SHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_SHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_SHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_SHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_WLBT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_WLBT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_WLBT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PDMA_CORE_IPCLKPORT_ACLK_PDMA0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SPDMA_CORE_IPCLKPORT_ACLK_PDMA1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_RT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_RT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D1_MIF_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_RT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_RT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_D0_MIF_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D0_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D1_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_USB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_USB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D_VIPX2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_USB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_USB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ASYNCSFR_WR_DMC1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_MEM1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_PERI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_PERI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPFW_CORE_PERI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_SHUB_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_SHUB_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_SHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_550_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_550_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_550_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_CCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_CCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_CCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_LITE_SIREX_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_LITE_SIREX_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_LITE_SIREX_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_CCLK_P_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_CCLK_P_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_CCLK_P_CORE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM1_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM1_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_MEM1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_PERI_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_PERI_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PPFW_PERI_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_US_A40_64TO128_DIT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_US_A40_64TO128_DIT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_US_A40_64TO128_DIT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_VIPX2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_PDMA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_PDMA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PGEN_PDMA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PGEN_PDMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PGEN_PDMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PGEN_PDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BAAW_P_GNSS_QCH_ENABLE, QCH_CON_BAAW_P_GNSS_QCH_CLOCK_REQ, QCH_CON_BAAW_P_GNSS_QCH_EXPIRE_VAL, QCH_CON_BAAW_P_GNSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_BAAW_P_MODEM_QCH_ENABLE, QCH_CON_BAAW_P_MODEM_QCH_CLOCK_REQ, QCH_CON_BAAW_P_MODEM_QCH_EXPIRE_VAL, QCH_CON_BAAW_P_MODEM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_BAAW_P_SHUB_QCH_ENABLE, QCH_CON_BAAW_P_SHUB_QCH_CLOCK_REQ, QCH_CON_BAAW_P_SHUB_QCH_EXPIRE_VAL, QCH_CON_BAAW_P_SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_BAAW_P_WLBT_QCH_ENABLE, QCH_CON_BAAW_P_WLBT_QCH_CLOCK_REQ, QCH_CON_BAAW_P_WLBT_QCH_EXPIRE_VAL, QCH_CON_BAAW_P_WLBT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_CCI_550_QCH_ENABLE, QCH_CON_CCI_550_QCH_CLOCK_REQ, QCH_CON_CCI_550_QCH_EXPIRE_VAL, QCH_CON_CCI_550_QCH_IGNORE_FORCE_PM_EN, QCH_CON_CORE_CMU_CORE_QCH_ENABLE, QCH_CON_CORE_CMU_CORE_QCH_CLOCK_REQ, QCH_CON_CORE_CMU_CORE_QCH_EXPIRE_VAL, QCH_CON_CORE_CMU_CORE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_DIT_QCH_ENABLE, QCH_CON_DIT_QCH_CLOCK_REQ, QCH_CON_DIT_QCH_EXPIRE_VAL, QCH_CON_DIT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_GIC400_AIHWACG_QCH_ENABLE, QCH_CON_GIC400_AIHWACG_QCH_CLOCK_REQ, QCH_CON_GIC400_AIHWACG_QCH_EXPIRE_VAL, QCH_CON_GIC400_AIHWACG_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_ACEL_D0_ISP_QCH_ENABLE, QCH_CON_LHM_ACEL_D0_ISP_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D0_ISP_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D0_ISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_ACEL_D0_MFC_QCH_ENABLE, QCH_CON_LHM_ACEL_D0_MFC_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D0_MFC_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D0_MFC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_ACEL_D1_ISP_QCH_ENABLE, QCH_CON_LHM_ACEL_D1_ISP_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D1_ISP_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D1_ISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_ACEL_D1_MFC_QCH_ENABLE, QCH_CON_LHM_ACEL_D1_MFC_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D1_MFC_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D1_MFC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_ACEL_D_CAM_QCH_ENABLE, QCH_CON_LHM_ACEL_D_CAM_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_CAM_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_CAM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_ACEL_D_DPU_QCH_ENABLE, QCH_CON_LHM_ACEL_D_DPU_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_DPU_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_DPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_ACEL_D_FSYS_QCH_ENABLE, QCH_CON_LHM_ACEL_D_FSYS_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_FSYS_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_FSYS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_ACEL_D_G2D_QCH_ENABLE, QCH_CON_LHM_ACEL_D_G2D_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_G2D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_G2D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_ACEL_D_USB_QCH_ENABLE, QCH_CON_LHM_ACEL_D_USB_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_USB_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_USB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_ACEL_D_VIPX1_QCH_ENABLE, QCH_CON_LHM_ACEL_D_VIPX1_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_VIPX1_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_VIPX1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_ACEL_D_VIPX2_QCH_ENABLE, QCH_CON_LHM_ACEL_D_VIPX2_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_VIPX2_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_VIPX2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_ACE_D_CPUCL0_QCH_ENABLE, QCH_CON_LHM_ACE_D_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D_CPUCL0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_ACE_D_CPUCL1_QCH_ENABLE, QCH_CON_LHM_ACE_D_CPUCL1_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D_CPUCL1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_D0_MODEM_QCH_ENABLE, QCH_CON_LHM_AXI_D0_MODEM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_MODEM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_MODEM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_D1_MODEM_QCH_ENABLE, QCH_CON_LHM_AXI_D1_MODEM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_MODEM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_MODEM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_D_ABOX_QCH_ENABLE, QCH_CON_LHM_AXI_D_ABOX_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_ABOX_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_ABOX_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_D_APM_QCH_ENABLE, QCH_CON_LHM_AXI_D_APM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_APM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_APM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_D_CSSYS_QCH_ENABLE, QCH_CON_LHM_AXI_D_CSSYS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_CSSYS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_CSSYS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_D_G3D_QCH_ENABLE, QCH_CON_LHM_AXI_D_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_G3D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_D_GNSS_QCH_ENABLE, QCH_CON_LHM_AXI_D_GNSS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_GNSS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_GNSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_D_SHUB_QCH_ENABLE, QCH_CON_LHM_AXI_D_SHUB_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_SHUB_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_D_WLBT_QCH_ENABLE, QCH_CON_LHM_AXI_D_WLBT_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_WLBT_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_WLBT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_D0_MIF_CP_QCH_ENABLE, QCH_CON_LHS_AXI_D0_MIF_CP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_MIF_CP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_MIF_CP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_D0_MIF_CPU_QCH_ENABLE, QCH_CON_LHS_AXI_D0_MIF_CPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_MIF_CPU_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_MIF_CPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_D0_MIF_NRT_QCH_ENABLE, QCH_CON_LHS_AXI_D0_MIF_NRT_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_MIF_NRT_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_MIF_NRT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_D0_MIF_RT_QCH_ENABLE, QCH_CON_LHS_AXI_D0_MIF_RT_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_MIF_RT_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_MIF_RT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_D1_MIF_CP_QCH_ENABLE, QCH_CON_LHS_AXI_D1_MIF_CP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_MIF_CP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_MIF_CP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_D1_MIF_CPU_QCH_ENABLE, QCH_CON_LHS_AXI_D1_MIF_CPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_MIF_CPU_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_MIF_CPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_D1_MIF_NRT_QCH_ENABLE, QCH_CON_LHS_AXI_D1_MIF_NRT_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_MIF_NRT_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_MIF_NRT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_D1_MIF_RT_QCH_ENABLE, QCH_CON_LHS_AXI_D1_MIF_RT_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_MIF_RT_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_MIF_RT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_P_APM_QCH_ENABLE, QCH_CON_LHS_AXI_P_APM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_APM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_APM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_P_CAM_QCH_ENABLE, QCH_CON_LHS_AXI_P_CAM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_CAM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_CAM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_P_CPUCL0_QCH_ENABLE, QCH_CON_LHS_AXI_P_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_P_CPUCL1_QCH_ENABLE, QCH_CON_LHS_AXI_P_CPUCL1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_CPUCL1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_P_DISPAUD_QCH_ENABLE, QCH_CON_LHS_AXI_P_DISPAUD_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_DISPAUD_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_DISPAUD_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_P_FSYS_QCH_ENABLE, QCH_CON_LHS_AXI_P_FSYS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_FSYS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_FSYS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_P_G2D_QCH_ENABLE, QCH_CON_LHS_AXI_P_G2D_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_G2D_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_G2D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_P_G3D_QCH_ENABLE, QCH_CON_LHS_AXI_P_G3D_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_G3D_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_G3D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_P_GNSS_QCH_ENABLE, QCH_CON_LHS_AXI_P_GNSS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_GNSS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_GNSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_P_ISP_QCH_ENABLE, QCH_CON_LHS_AXI_P_ISP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_ISP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_ISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_P_MFC_QCH_ENABLE, QCH_CON_LHS_AXI_P_MFC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MFC_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MFC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_P_MIF0_QCH_ENABLE, QCH_CON_LHS_AXI_P_MIF0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MIF0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MIF0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_P_MIF1_QCH_ENABLE, QCH_CON_LHS_AXI_P_MIF1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MIF1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MIF1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_P_MODEM_QCH_ENABLE, QCH_CON_LHS_AXI_P_MODEM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MODEM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MODEM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_P_PERI_QCH_ENABLE, QCH_CON_LHS_AXI_P_PERI_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_PERI_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_PERI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_P_SHUB_QCH_ENABLE, QCH_CON_LHS_AXI_P_SHUB_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_SHUB_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_P_USB_QCH_ENABLE, QCH_CON_LHS_AXI_P_USB_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_USB_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_USB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_P_VIPX1_QCH_ENABLE, QCH_CON_LHS_AXI_P_VIPX1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_VIPX1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_VIPX1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_P_VIPX2_QCH_ENABLE, QCH_CON_LHS_AXI_P_VIPX2_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_VIPX2_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_VIPX2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_P_WLBT_QCH_ENABLE, QCH_CON_LHS_AXI_P_WLBT_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_WLBT_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_WLBT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PDMA_CORE_QCH_ENABLE, QCH_CON_PDMA_CORE_QCH_CLOCK_REQ, QCH_CON_PDMA_CORE_QCH_EXPIRE_VAL, QCH_CON_PDMA_CORE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PGEN_LITE_SIREX_QCH_ENABLE, QCH_CON_PGEN_LITE_SIREX_QCH_CLOCK_REQ, QCH_CON_PGEN_LITE_SIREX_QCH_EXPIRE_VAL, QCH_CON_PGEN_LITE_SIREX_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PGEN_PDMA_QCH_ENABLE, QCH_CON_PGEN_PDMA_QCH_CLOCK_REQ, QCH_CON_PGEN_PDMA_QCH_EXPIRE_VAL, QCH_CON_PGEN_PDMA_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPCFW_G3D_QCH_ENABLE, QCH_CON_PPCFW_G3D_QCH_CLOCK_REQ, QCH_CON_PPCFW_G3D_QCH_EXPIRE_VAL, QCH_CON_PPCFW_G3D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPFW_CORE_MEM0_QCH_ENABLE, QCH_CON_PPFW_CORE_MEM0_QCH_CLOCK_REQ, QCH_CON_PPFW_CORE_MEM0_QCH_EXPIRE_VAL, QCH_CON_PPFW_CORE_MEM0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPFW_CORE_MEM1_QCH_ENABLE, QCH_CON_PPFW_CORE_MEM1_QCH_CLOCK_REQ, QCH_CON_PPFW_CORE_MEM1_QCH_EXPIRE_VAL, QCH_CON_PPFW_CORE_MEM1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPFW_CORE_PERI_QCH_ENABLE, QCH_CON_PPFW_CORE_PERI_QCH_CLOCK_REQ, QCH_CON_PPFW_CORE_PERI_QCH_EXPIRE_VAL, QCH_CON_PPFW_CORE_PERI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_ACE_CPUCL0_QCH_ENABLE, QCH_CON_PPMU_ACE_CPUCL0_QCH_CLOCK_REQ, QCH_CON_PPMU_ACE_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_PPMU_ACE_CPUCL0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_ACE_CPUCL1_QCH_ENABLE, QCH_CON_PPMU_ACE_CPUCL1_QCH_CLOCK_REQ, QCH_CON_PPMU_ACE_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_PPMU_ACE_CPUCL1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_G3D_OCC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_OCC_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_OCC_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_OCC_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_CORE_BUSP_OCC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_RSTNSYNC_CLK_CORE_CCI_OCC_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CORE_CCI_OCC_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CORE_CCI_OCC_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_CORE_CCI_OCC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_RSTNSYNC_CLK_CORE_G3D_OCC_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CORE_G3D_OCC_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CORE_G3D_OCC_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_CORE_G3D_OCC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SFR_APBIF_CMU_TOPC_QCH_ENABLE, QCH_CON_SFR_APBIF_CMU_TOPC_QCH_CLOCK_REQ, QCH_CON_SFR_APBIF_CMU_TOPC_QCH_EXPIRE_VAL, QCH_CON_SFR_APBIF_CMU_TOPC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SIREX_QCH_ENABLE, QCH_CON_SIREX_QCH_CLOCK_REQ, QCH_CON_SIREX_QCH_EXPIRE_VAL, QCH_CON_SIREX_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SPDMA_CORE_QCH_ENABLE, QCH_CON_SPDMA_CORE_QCH_CLOCK_REQ, QCH_CON_SPDMA_CORE_QCH_EXPIRE_VAL, QCH_CON_SPDMA_CORE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_CORE_QCH_ENABLE, QCH_CON_SYSREG_CORE_QCH_CLOCK_REQ, QCH_CON_SYSREG_CORE_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CORE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_TREX_D_CORE_QCH_ENABLE, QCH_CON_TREX_D_CORE_QCH_CLOCK_REQ, QCH_CON_TREX_D_CORE_QCH_EXPIRE_VAL, QCH_CON_TREX_D_CORE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_TREX_D_NRT_QCH_ENABLE, QCH_CON_TREX_D_NRT_QCH_CLOCK_REQ, QCH_CON_TREX_D_NRT_QCH_EXPIRE_VAL, QCH_CON_TREX_D_NRT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_TREX_P_CORE_QCH_ENABLE, QCH_CON_TREX_P_CORE_QCH_CLOCK_REQ, QCH_CON_TREX_P_CORE_QCH_EXPIRE_VAL, QCH_CON_TREX_P_CORE_QCH_IGNORE_FORCE_PM_EN, PLL_CON0_PLL_CPUCL0_DIV_P, PLL_CON0_PLL_CPUCL0_DIV_M, PLL_CON0_PLL_CPUCL0_DIV_S, PLL_CON0_PLL_CPUCL0_ENABLE, PLL_CON0_PLL_CPUCL0_STABLE, PLL_LOCKTIME_PLL_CPUCL0_PLL_LOCK_TIME, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_BUSY, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_SELECT, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_DIVRATIO, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER_BUSY, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_CPUCL0_DBG_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLK_CLUSTER0_CPU_CG_VAL, CLK_CON_GAT_GATE_CLK_CLUSTER0_CPU_MANUAL, CLK_CON_GAT_GATE_CLK_CLUSTER0_CPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CSSYS_CORE_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CSSYS_CORE_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CSSYS_CORE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_CSSYS_FSYS_IPCLKPORT_HCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_CSSYS_FSYS_IPCLKPORT_HCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_AHB_G_CSSYS_FSYS_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_P8Q_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_P8Q_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADS_APB_G_P8Q_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_D_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_D_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHS_AXI_D_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AD_APB_P_DUMP_PC_CPUCL1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_DUMP_PC_CPUCL1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BUSIF_HPMCPUCL0_QCH_ENABLE, QCH_CON_BUSIF_HPMCPUCL0_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMCPUCL0_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMCPUCL0_QCH_IGNORE_FORCE_PM_EN, DMYQCH_CON_CLUSTER0_QCH_CPU_ENABLE, DMYQCH_CON_CLUSTER0_QCH_CPU_CLOCK_REQ, DMYQCH_CON_CLUSTER0_QCH_CPU_IGNORE_FORCE_PM_EN, DMYQCH_CON_CLUSTER0_QCH_DBG_ENABLE, DMYQCH_CON_CLUSTER0_QCH_DBG_CLOCK_REQ, DMYQCH_CON_CLUSTER0_QCH_DBG_IGNORE_FORCE_PM_EN, QCH_CON_CLUSTER0_QCH_LHS_ACE_D_CPUCL0_ENABLE, QCH_CON_CLUSTER0_QCH_LHS_ACE_D_CPUCL0_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_LHS_ACE_D_CPUCL0_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_LHS_ACE_D_CPUCL0_IGNORE_FORCE_PM_EN, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_EXPIRE_VAL, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_ENABLE, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_CLOCK_REQ, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN, DMYQCH_CON_CSSYS_DBG_QCH_ENABLE, DMYQCH_CON_CSSYS_DBG_QCH_CLOCK_REQ, DMYQCH_CON_CSSYS_DBG_QCH_IGNORE_FORCE_PM_EN, QCH_CON_DUMP_PC_CPUCL0_QCH_ENABLE, QCH_CON_DUMP_PC_CPUCL0_QCH_CLOCK_REQ, QCH_CON_DUMP_PC_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_DUMP_PC_CPUCL0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_DUMP_PC_CPUCL1_QCH_ENABLE, QCH_CON_DUMP_PC_CPUCL1_QCH_CLOCK_REQ, QCH_CON_DUMP_PC_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_DUMP_PC_CPUCL1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_P_CPUCL0_QCH_ENABLE, QCH_CON_LHM_AXI_P_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_D_CSSYS_QCH_ENABLE, QCH_CON_LHS_AXI_D_CSSYS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_CSSYS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_CSSYS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SECJTAG_QCH_ENABLE, QCH_CON_SECJTAG_QCH_CLOCK_REQ, QCH_CON_SECJTAG_QCH_EXPIRE_VAL, QCH_CON_SECJTAG_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_CPUCL0_QCH_ENABLE, QCH_CON_SYSREG_CPUCL0_QCH_CLOCK_REQ, QCH_CON_SYSREG_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CPUCL0_QCH_IGNORE_FORCE_PM_EN, PLL_CON0_PLL_CPUCL1_DIV_P, PLL_CON0_PLL_CPUCL1_DIV_M, PLL_CON0_PLL_CPUCL1_DIV_S, PLL_CON0_PLL_CPUCL1_ENABLE, PLL_CON0_PLL_CPUCL1_STABLE, PLL_LOCKTIME_PLL_CPUCL1_PLL_LOCK_TIME, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_SELECT, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_BUSY, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_DIVRATIO, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_DIVRATIO, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK_DIVRATIO, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG_DIVRATIO, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_ADM_APB_G_CSSYS_CPUCL1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLK_CLUSTER1_CPU_CG_VAL, CLK_CON_GAT_GATE_CLK_CLUSTER1_CPU_MANUAL, CLK_CON_GAT_GATE_CLK_CLUSTER1_CPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHS_ACE_D_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, DMYQCH_CON_ADM_APB_G_CSSYS_CPUCL1_QCH_ENABLE, DMYQCH_CON_ADM_APB_G_CSSYS_CPUCL1_QCH_CLOCK_REQ, DMYQCH_CON_ADM_APB_G_CSSYS_CPUCL1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_BUSIF_HPMCPUCL1_QCH_ENABLE, QCH_CON_BUSIF_HPMCPUCL1_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMCPUCL1_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMCPUCL1_QCH_IGNORE_FORCE_PM_EN, DMYQCH_CON_CLUSTER1_QCH_CPU_ENABLE, DMYQCH_CON_CLUSTER1_QCH_CPU_CLOCK_REQ, DMYQCH_CON_CLUSTER1_QCH_CPU_IGNORE_FORCE_PM_EN, DMYQCH_CON_CLUSTER1_QCH_DBG_ENABLE, DMYQCH_CON_CLUSTER1_QCH_DBG_CLOCK_REQ, DMYQCH_CON_CLUSTER1_QCH_DBG_IGNORE_FORCE_PM_EN, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_EXPIRE_VAL, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_ENABLE, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_CLOCK_REQ, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_P_CPUCL1_QCH_ENABLE, QCH_CON_LHM_AXI_P_CPUCL1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_CPUCL1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_ACE_D_CPUCL1_QCH_ENABLE, QCH_CON_LHS_ACE_D_CPUCL1_QCH_CLOCK_REQ, QCH_CON_LHS_ACE_D_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_LHS_ACE_D_CPUCL1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_CPUCL1_QCH_ENABLE, QCH_CON_SYSREG_CPUCL1_QCH_CLOCK_REQ, QCH_CON_SYSREG_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CPUCL1_QCH_IGNORE_FORCE_PM_EN, CLK_CON_DIV_DIV_CLK_AUD_CPU_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_CPU_DIVRATIO, CLK_CON_MUX_MUX_CLK_AUD_CPU_BUSY, CLK_CON_MUX_MUX_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_AUD_CPU_SELECT, PLL_CON0_MUX_CLKCMU_DISPAUD_CPU_USER_BUSY, PLL_CON0_MUX_CLKCMU_DISPAUD_CPU_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_DISPAUD_CPU_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_BUSY, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_DIVRATIO, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_SELECT, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_ASB_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_AUD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_AUD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_WDT_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DFTMUX_DISPAUD_IPCLKPORT_AUD_CODEC_MCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_ABOX_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_DISPAUD_DISP_USER_BUSY, PLL_CON0_MUX_CLKCMU_DISPAUD_DISP_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_DISPAUD_DISP_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP_DIVRATIO, PLL_CON0_PLL_AUD_DIV_P, PLL_CON0_PLL_AUD_DIV_M, PLL_CON0_PLL_AUD_DIV_S, PLL_CON0_PLL_AUD_ENABLE, PLL_CON0_PLL_AUD_STABLE, PLL_CON3_PLL_AUD_DIV_K, PLL_LOCKTIME_PLL_AUD_PLL_LOCK_TIME, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_ACEL_D_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_ACEL_D_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_ACEL_D_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_DISP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_DISP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_DISP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_DISPAUD_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_PPMU_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SYSREG_DISPAUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHM_AXI_P_DISPAUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH_BUSY, CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH_SELECT, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_DISPAUD_CMU_DISPAUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_DSIF_BUSY, CLK_CON_DIV_DIV_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_DSIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY_BUSY, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY_DIVRATIO, CLK_CON_MUX_MUX_CLK_AUD_FM_BUSY, CLK_CON_MUX_MUX_CLK_AUD_FM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_AUD_FM_SELECT, CLK_CON_DIV_DIV_CLK_AUD_FM_BUSY, CLK_CON_DIV_DIV_CLK_AUD_FM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_FM_DIVRATIO, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_DISPAUD_AUD_USER_BUSY, PLL_CON0_MUX_CLKCMU_DISPAUD_AUD_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_DISPAUD_AUD_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_SMMU_DPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_DISP_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_DISP_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_DISP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_DBG_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_DBG_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_DBG_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DECON_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DPP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_DPU_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_OSC_SPDY_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_OSC_SPDY_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_OSC_SPDY_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DISPAUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_ABOX_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BTM_DPU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_AUD_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_AUD_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_BLK_DISPAUD_IPCLKPORT_CLK_DISPAUD_AUD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_ABOX_IPCLKPORT_CCLK_CA7_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_BUS_BUSY, CLK_CON_DIV_DIV_CLK_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_BUS_DIVRATIO, CLK_CON_MUX_MUX_CLK_AUD_BUS_BUSY, CLK_CON_MUX_MUX_CLK_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_AUD_BUS_SELECT, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISPAUD_UID_GPIO_DISPAUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, DMYQCH_CON_ABOX_QCH_CPU_ENABLE, DMYQCH_CON_ABOX_QCH_CPU_CLOCK_REQ, DMYQCH_CON_ABOX_QCH_CPU_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_S_ACLK_ENABLE, QCH_CON_ABOX_QCH_S_ACLK_CLOCK_REQ, QCH_CON_ABOX_QCH_S_ACLK_EXPIRE_VAL, QCH_CON_ABOX_QCH_S_ACLK_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_S_BCLK0_ENABLE, QCH_CON_ABOX_QCH_S_BCLK0_CLOCK_REQ, QCH_CON_ABOX_QCH_S_BCLK0_EXPIRE_VAL, QCH_CON_ABOX_QCH_S_BCLK0_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_S_BCLK2_ENABLE, QCH_CON_ABOX_QCH_S_BCLK2_CLOCK_REQ, QCH_CON_ABOX_QCH_S_BCLK2_EXPIRE_VAL, QCH_CON_ABOX_QCH_S_BCLK2_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_S_BCLK1_ENABLE, QCH_CON_ABOX_QCH_S_BCLK1_CLOCK_REQ, QCH_CON_ABOX_QCH_S_BCLK1_EXPIRE_VAL, QCH_CON_ABOX_QCH_S_BCLK1_IGNORE_FORCE_PM_EN, DMYQCH_CON_ABOX_QCH_FM_ENABLE, DMYQCH_CON_ABOX_QCH_FM_CLOCK_REQ, DMYQCH_CON_ABOX_QCH_FM_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_S_BCLK_DSIF_ENABLE, QCH_CON_ABOX_QCH_S_BCLK_DSIF_CLOCK_REQ, QCH_CON_ABOX_QCH_S_BCLK_DSIF_EXPIRE_VAL, QCH_CON_ABOX_QCH_S_BCLK_DSIF_IGNORE_FORCE_PM_EN, QCH_CON_BTM_ABOX_QCH_ENABLE, QCH_CON_BTM_ABOX_QCH_CLOCK_REQ, QCH_CON_BTM_ABOX_QCH_EXPIRE_VAL, QCH_CON_BTM_ABOX_QCH_IGNORE_FORCE_PM_EN, QCH_CON_BTM_DPU_QCH_ENABLE, QCH_CON_BTM_DPU_QCH_CLOCK_REQ, QCH_CON_BTM_DPU_QCH_EXPIRE_VAL, QCH_CON_BTM_DPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_DISPAUD_CMU_DISPAUD_QCH_ENABLE, QCH_CON_DISPAUD_CMU_DISPAUD_QCH_CLOCK_REQ, QCH_CON_DISPAUD_CMU_DISPAUD_QCH_EXPIRE_VAL, QCH_CON_DISPAUD_CMU_DISPAUD_QCH_IGNORE_FORCE_PM_EN, QCH_CON_DPU_QCH_S_DPP_ENABLE, QCH_CON_DPU_QCH_S_DPP_CLOCK_REQ, QCH_CON_DPU_QCH_S_DPP_EXPIRE_VAL, QCH_CON_DPU_QCH_S_DPP_IGNORE_FORCE_PM_EN, QCH_CON_DPU_QCH_S_DMA_ENABLE, QCH_CON_DPU_QCH_S_DMA_CLOCK_REQ, QCH_CON_DPU_QCH_S_DMA_EXPIRE_VAL, QCH_CON_DPU_QCH_S_DMA_IGNORE_FORCE_PM_EN, QCH_CON_DPU_QCH_S_DECON_ENABLE, QCH_CON_DPU_QCH_S_DECON_CLOCK_REQ, QCH_CON_DPU_QCH_S_DECON_EXPIRE_VAL, QCH_CON_DPU_QCH_S_DECON_IGNORE_FORCE_PM_EN, QCH_CON_GPIO_DISPAUD_QCH_ENABLE, QCH_CON_GPIO_DISPAUD_QCH_CLOCK_REQ, QCH_CON_GPIO_DISPAUD_QCH_EXPIRE_VAL, QCH_CON_GPIO_DISPAUD_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_P_DISPAUD_QCH_ENABLE, QCH_CON_LHM_AXI_P_DISPAUD_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DISPAUD_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_DISPAUD_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_ACEL_D_DPU_QCH_ENABLE, QCH_CON_LHS_ACEL_D_DPU_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_DPU_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_DPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_D_ABOX_QCH_ENABLE, QCH_CON_LHS_AXI_D_ABOX_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_ABOX_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_ABOX_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_ABOX_QCH_ENABLE, QCH_CON_PPMU_ABOX_QCH_CLOCK_REQ, QCH_CON_PPMU_ABOX_QCH_EXPIRE_VAL, QCH_CON_PPMU_ABOX_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_DPU_QCH_ENABLE, QCH_CON_PPMU_DPU_QCH_CLOCK_REQ, QCH_CON_PPMU_DPU_QCH_EXPIRE_VAL, QCH_CON_PPMU_DPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_RSTNSYNC_CLK_AUD_CPU_CLKIN_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_AUD_CPU_CLKIN_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_AUD_CPU_CLKIN_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_AUD_CPU_CLKIN_QCH_IGNORE_FORCE_PM_EN, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SMMU_ABOX_QCH_ENABLE, QCH_CON_SMMU_ABOX_QCH_CLOCK_REQ, QCH_CON_SMMU_ABOX_QCH_EXPIRE_VAL, QCH_CON_SMMU_ABOX_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SMMU_DPU_QCH_ENABLE, QCH_CON_SMMU_DPU_QCH_CLOCK_REQ, QCH_CON_SMMU_DPU_QCH_EXPIRE_VAL, QCH_CON_SMMU_DPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_DISPAUD_QCH_ENABLE, QCH_CON_SYSREG_DISPAUD_QCH_CLOCK_REQ, QCH_CON_SYSREG_DISPAUD_QCH_EXPIRE_VAL, QCH_CON_SYSREG_DISPAUD_QCH_IGNORE_FORCE_PM_EN, QCH_CON_WDT_AUD_QCH_ENABLE, QCH_CON_WDT_AUD_QCH_CLOCK_REQ, QCH_CON_WDT_AUD_QCH_EXPIRE_VAL, QCH_CON_WDT_AUD_QCH_IGNORE_FORCE_PM_EN, PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_FSYS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER_BUSY, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_FSYS_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER_BUSY, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_FSYS_MMC_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHM_AXI_P_FSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_ACEL_D_FSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_ACEL_D_FSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_LHS_ACEL_D_FSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_FSYS_UID_RSTNSYNC_CLK_FSYS_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_XIU_D_FSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_FSYS_UFS_EMBD_USER_BUSY, PLL_CON0_MUX_CLKCMU_FSYS_UFS_EMBD_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_FSYS_UFS_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_FSYS_UID_FSYS_CMU_FSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_RTIC_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_SSS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PGEN_LITE_FSYS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PGEN_LITE_FSYS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_PGEN_LITE_FSYS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_BTM_FSYS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_ADM_AHB_SSS_QCH_ENABLE, QCH_CON_ADM_AHB_SSS_QCH_CLOCK_REQ, QCH_CON_ADM_AHB_SSS_QCH_EXPIRE_VAL, QCH_CON_ADM_AHB_SSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_BTM_FSYS_QCH_ENABLE, QCH_CON_BTM_FSYS_QCH_CLOCK_REQ, QCH_CON_BTM_FSYS_QCH_EXPIRE_VAL, QCH_CON_BTM_FSYS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_FSYS_CMU_FSYS_QCH_ENABLE, QCH_CON_FSYS_CMU_FSYS_QCH_CLOCK_REQ, QCH_CON_FSYS_CMU_FSYS_QCH_EXPIRE_VAL, QCH_CON_FSYS_CMU_FSYS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_GPIO_FSYS_QCH_ENABLE, QCH_CON_GPIO_FSYS_QCH_CLOCK_REQ, QCH_CON_GPIO_FSYS_QCH_EXPIRE_VAL, QCH_CON_GPIO_FSYS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_P_FSYS_QCH_ENABLE, QCH_CON_LHM_AXI_P_FSYS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_FSYS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_FSYS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_ACEL_D_FSYS_QCH_ENABLE, QCH_CON_LHS_ACEL_D_FSYS_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_FSYS_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_FSYS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MMC_CARD_QCH_ENABLE, QCH_CON_MMC_CARD_QCH_CLOCK_REQ, QCH_CON_MMC_CARD_QCH_EXPIRE_VAL, QCH_CON_MMC_CARD_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MMC_EMBD_QCH_ENABLE, QCH_CON_MMC_EMBD_QCH_CLOCK_REQ, QCH_CON_MMC_EMBD_QCH_EXPIRE_VAL, QCH_CON_MMC_EMBD_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PGEN_LITE_FSYS_QCH_ENABLE, QCH_CON_PGEN_LITE_FSYS_QCH_CLOCK_REQ, QCH_CON_PGEN_LITE_FSYS_QCH_EXPIRE_VAL, QCH_CON_PGEN_LITE_FSYS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_FSYS_QCH_ENABLE, QCH_CON_PPMU_FSYS_QCH_CLOCK_REQ, QCH_CON_PPMU_FSYS_QCH_EXPIRE_VAL, QCH_CON_PPMU_FSYS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_RTIC_QCH_ENABLE, QCH_CON_RTIC_QCH_CLOCK_REQ, QCH_CON_RTIC_QCH_EXPIRE_VAL, QCH_CON_RTIC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SSS_QCH_ENABLE, QCH_CON_SSS_QCH_CLOCK_REQ, QCH_CON_SSS_QCH_EXPIRE_VAL, QCH_CON_SSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_FSYS_QCH_ENABLE, QCH_CON_SYSREG_FSYS_QCH_CLOCK_REQ, QCH_CON_SYSREG_FSYS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_FSYS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_UFS_EMBD_QCH_UFS_ENABLE, QCH_CON_UFS_EMBD_QCH_UFS_CLOCK_REQ, QCH_CON_UFS_EMBD_QCH_UFS_EXPIRE_VAL, QCH_CON_UFS_EMBD_QCH_UFS_IGNORE_FORCE_PM_EN, QCH_CON_UFS_EMBD_QCH_FMP_ENABLE, QCH_CON_UFS_EMBD_QCH_FMP_CLOCK_REQ, QCH_CON_UFS_EMBD_QCH_FMP_EXPIRE_VAL, QCH_CON_UFS_EMBD_QCH_FMP_IGNORE_FORCE_PM_EN, PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER_BUSY, PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_G2D_MSCL_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_G2D_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_G2D_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_G2D_BUSP_DIVRATIO, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_MSCL_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_MSCL_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_MSCL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_G2D_UID_RSTNSYNC_CLK_G2D_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G2D_UID_RSTNSYNC_CLK_G2D_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G2D_UID_RSTNSYNC_CLK_G2D_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_FIMP_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_FIMP_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_FIMP_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_MSCL_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_MSCL_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_MSCL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_BUSY, PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_G2D_G2D_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_JPEG_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_AXI_MSCL_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_G2D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_G2D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_G2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_MSCL_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_MSCL_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_MSCL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_PGEN100_LITE_G2D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PGEN100_LITE_G2D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PGEN100_LITE_G2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_MSCL_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_MSCL_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_G2D_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_G2D_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BLK_G2D_IPCLKPORT_CLK_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2D_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BTM_G2D_QCH_ENABLE, QCH_CON_BTM_G2D_QCH_CLOCK_REQ, QCH_CON_BTM_G2D_QCH_EXPIRE_VAL, QCH_CON_BTM_G2D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_G2D_QCH_ENABLE, QCH_CON_G2D_QCH_CLOCK_REQ, QCH_CON_G2D_QCH_EXPIRE_VAL, QCH_CON_G2D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_G2D_CMU_G2D_QCH_ENABLE, QCH_CON_G2D_CMU_G2D_QCH_CLOCK_REQ, QCH_CON_G2D_CMU_G2D_QCH_EXPIRE_VAL, QCH_CON_G2D_CMU_G2D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_JPEG_QCH_ENABLE, QCH_CON_JPEG_QCH_CLOCK_REQ, QCH_CON_JPEG_QCH_EXPIRE_VAL, QCH_CON_JPEG_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_P_G2D_QCH_ENABLE, QCH_CON_LHM_AXI_P_G2D_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_G2D_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_G2D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_ACEL_D_G2D_QCH_ENABLE, QCH_CON_LHS_ACEL_D_G2D_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_G2D_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_G2D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MSCL_QCH_ENABLE, QCH_CON_MSCL_QCH_CLOCK_REQ, QCH_CON_MSCL_QCH_EXPIRE_VAL, QCH_CON_MSCL_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PGEN100_LITE_G2D_QCH_ENABLE, QCH_CON_PGEN100_LITE_G2D_QCH_CLOCK_REQ, QCH_CON_PGEN100_LITE_G2D_QCH_EXPIRE_VAL, QCH_CON_PGEN100_LITE_G2D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_G2D_QCH_ENABLE, QCH_CON_PPMU_G2D_QCH_CLOCK_REQ, QCH_CON_PPMU_G2D_QCH_EXPIRE_VAL, QCH_CON_PPMU_G2D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_G2D_QCH_ENABLE, QCH_CON_SYSMMU_G2D_QCH_CLOCK_REQ, QCH_CON_SYSMMU_G2D_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_G2D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_G2D_QCH_ENABLE, QCH_CON_SYSREG_G2D_QCH_CLOCK_REQ, QCH_CON_SYSREG_G2D_QCH_EXPIRE_VAL, QCH_CON_SYSREG_G2D_QCH_IGNORE_FORCE_PM_EN, CLK_CON_DIV_DIV_CLK_G3D_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_G3D_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_G3D_BUSP_DIVRATIO, PLL_CON0_PLL_G3D_DIV_P, PLL_CON0_PLL_G3D_DIV_M, PLL_CON0_PLL_G3D_DIV_S, PLL_CON0_PLL_G3D_ENABLE, PLL_CON0_PLL_G3D_STABLE, PLL_LOCKTIME_PLL_G3D_PLL_LOCK_TIME, CLK_CON_MUX_MUX_CLK_G3D_BUSD_BUSY, CLK_CON_MUX_MUX_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_G3D_BUSD_SELECT, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_BUSY, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_PGEN_LITE_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BTM_G3D_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_D_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_G3D_BUSD_BUSY, CLK_CON_DIV_DIV_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BTM_G3D_QCH_ENABLE, QCH_CON_BTM_G3D_QCH_CLOCK_REQ, QCH_CON_BTM_G3D_QCH_EXPIRE_VAL, QCH_CON_BTM_G3D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_BUSIF_HPMG3D_QCH_ENABLE, QCH_CON_BUSIF_HPMG3D_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMG3D_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMG3D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_G3D_QCH_ENABLE, QCH_CON_G3D_QCH_CLOCK_REQ, QCH_CON_G3D_QCH_EXPIRE_VAL, QCH_CON_G3D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_G3D_CMU_G3D_QCH_ENABLE, QCH_CON_G3D_CMU_G3D_QCH_CLOCK_REQ, QCH_CON_G3D_CMU_G3D_QCH_EXPIRE_VAL, QCH_CON_G3D_CMU_G3D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_G3DSFR_QCH_ENABLE, QCH_CON_LHM_AXI_G3DSFR_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_G3DSFR_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_G3DSFR_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_P_G3D_QCH_ENABLE, QCH_CON_LHM_AXI_P_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_G3D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_D_G3D_QCH_ENABLE, QCH_CON_LHS_AXI_D_G3D_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_G3D_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_G3D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_G3DSFR_QCH_ENABLE, QCH_CON_LHS_AXI_G3DSFR_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G3DSFR_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_G3DSFR_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PGEN_LITE_G3D_QCH_ENABLE, QCH_CON_PGEN_LITE_G3D_QCH_CLOCK_REQ, QCH_CON_PGEN_LITE_G3D_QCH_EXPIRE_VAL, QCH_CON_PGEN_LITE_G3D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_G3D_QCH_ENABLE, QCH_CON_SYSREG_G3D_QCH_CLOCK_REQ, QCH_CON_SYSREG_G3D_QCH_EXPIRE_VAL, QCH_CON_SYSREG_G3D_QCH_IGNORE_FORCE_PM_EN, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_ISP_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_ISP_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_ISP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ISP_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_ISP_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ISP_BUSP_DIVRATIO, PLL_CON0_MUX_CLKCMU_ISP_VRA_USER_BUSY, PLL_CON0_MUX_CLKCMU_ISP_VRA_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_ISP_VRA_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_ISP_GDC_USER_BUSY, PLL_CON0_MUX_CLKCMU_ISP_GDC_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_ISP_GDC_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_GDC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_GDC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_VRA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_VRA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_CLK_ISP_VRA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_AXI_P_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_AXI_P_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_AXI_P_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D1_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D1_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D1_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D0_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D0_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHS_ACEL_D0_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP1_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP1_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_VRA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_VRA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_GDC_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_GDC_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCS_GDC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_GDC_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_GDC_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_ASYNCM_GDC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP0_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP0_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP0_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP0_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PCLK_PPMU_ISP0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP0_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP0_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_GDC_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_GDC_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_GDC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_ISP_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_ISP_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_ISP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_VRA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_ATB_CAMISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_ATB_CAMISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LHM_ATB_CAMISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_BUSD_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_BUSD_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_BUSD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_GDC_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_GDC_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_GDC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BLK_ISP_IPCLKPORT_CLK_ISP_VRA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP1_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP1_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_PPMU_ISP1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP1_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP1_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_SMMU_ISP1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_D_ISP_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_D_ISP_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_XIU_D_ISP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_MCSC_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_MCSC_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_ACLK_MCSC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PGEN_LITE_ISP_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PGEN_LITE_ISP_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_IS6P10P0_ISP_IPCLKPORT_PGEN_LITE_ISP_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_BTM_ISP1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BTM_ISP0_QCH_ENABLE, QCH_CON_BTM_ISP0_QCH_CLOCK_REQ, QCH_CON_BTM_ISP0_QCH_EXPIRE_VAL, QCH_CON_BTM_ISP0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_BTM_ISP1_QCH_ENABLE, QCH_CON_BTM_ISP1_QCH_CLOCK_REQ, QCH_CON_BTM_ISP1_QCH_EXPIRE_VAL, QCH_CON_BTM_ISP1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_ISP_CMU_ISP_QCH_ENABLE, QCH_CON_ISP_CMU_ISP_QCH_CLOCK_REQ, QCH_CON_ISP_CMU_ISP_QCH_EXPIRE_VAL, QCH_CON_ISP_CMU_ISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_ATB_CAMISP_QCH_ENABLE, QCH_CON_LHM_ATB_CAMISP_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_CAMISP_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_CAMISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_P_ISP_QCH_ENABLE, QCH_CON_LHM_AXI_P_ISP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_ISP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_ISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_ACEL_D0_ISP_QCH_ENABLE, QCH_CON_LHS_ACEL_D0_ISP_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D0_ISP_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D0_ISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_ACEL_D1_ISP_QCH_ENABLE, QCH_CON_LHS_ACEL_D1_ISP_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D1_ISP_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D1_ISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_ISP_QCH_ENABLE, QCH_CON_SYSREG_ISP_QCH_CLOCK_REQ, QCH_CON_SYSREG_ISP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_ISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_ISP_ENABLE, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_ISP_CLOCK_REQ, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_ISP_EXPIRE_VAL, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_ISP_IGNORE_FORCE_PM_EN, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_MCSC_ENABLE, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_MCSC_CLOCK_REQ, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_MCSC_EXPIRE_VAL, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_MCSC_IGNORE_FORCE_PM_EN, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_VRA_ENABLE, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_VRA_CLOCK_REQ, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_VRA_EXPIRE_VAL, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_VRA_IGNORE_FORCE_PM_EN, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP1_ENABLE, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP1_CLOCK_REQ, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP1_EXPIRE_VAL, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP1_IGNORE_FORCE_PM_EN, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP0_ENABLE, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP0_CLOCK_REQ, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP0_EXPIRE_VAL, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PPMU_ISP0_IGNORE_FORCE_PM_EN, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_GDC_ENABLE, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_GDC_CLOCK_REQ, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_GDC_EXPIRE_VAL, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_GDC_IGNORE_FORCE_PM_EN, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0_ENABLE, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0_CLOCK_REQ, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0_EXPIRE_VAL, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0_IGNORE_FORCE_PM_EN, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1_ENABLE, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1_CLOCK_REQ, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1_EXPIRE_VAL, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1_IGNORE_FORCE_PM_EN, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PGEN_LITE_ISP_ENABLE, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PGEN_LITE_ISP_CLOCK_REQ, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PGEN_LITE_ISP_EXPIRE_VAL, QCH_CON_IS6P10P0_ISP_QCH_S_ISP_PGEN_LITE_ISP_IGNORE_FORCE_PM_EN, CLK_CON_DIV_DIV_CLK_MFC_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MFC_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_MFC_BUSP_DIVRATIO, PLL_CON0_MUX_CLKCMU_MFC_WFD_USER_BUSY, PLL_CON0_MUX_CLKCMU_MFC_WFD_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_MFC_WFD_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_MFC_MFC_USER_BUSY, PLL_CON0_MUX_CLKCMU_MFC_MFC_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_MFC_MFC_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_SI_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_SI_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_SI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_MI_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_MI_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_MI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_PGEN100_LITE_MFC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PGEN100_LITE_MFC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PGEN100_LITE_MFC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFCD1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_WFD_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_WFD_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_WFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_XIU_D_MFC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_XIU_D_MFC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_XIU_D_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_MFC_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_MFC_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_WFD_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_WFD_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BLK_MFC_IPCLKPORT_CLK_MFC_WFD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MFC_UID_RSTNSYNC_CLK_MFC_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC_UID_RSTNSYNC_CLK_MFC_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC_UID_RSTNSYNC_CLK_MFC_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D0_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D0_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D0_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D1_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D1_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_ACEL_D1_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_MFC_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_WFD_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BTM_MFCD0_QCH_ENABLE, QCH_CON_BTM_MFCD0_QCH_CLOCK_REQ, QCH_CON_BTM_MFCD0_QCH_EXPIRE_VAL, QCH_CON_BTM_MFCD0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_BTM_MFCD1_QCH_ENABLE, QCH_CON_BTM_MFCD1_QCH_CLOCK_REQ, QCH_CON_BTM_MFCD1_QCH_EXPIRE_VAL, QCH_CON_BTM_MFCD1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_P_MFC_QCH_ENABLE, QCH_CON_LHM_AXI_P_MFC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MFC_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_MFC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_ACEL_D0_MFC_QCH_ENABLE, QCH_CON_LHS_ACEL_D0_MFC_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D0_MFC_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D0_MFC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_ACEL_D1_MFC_QCH_ENABLE, QCH_CON_LHS_ACEL_D1_MFC_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D1_MFC_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D1_MFC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_ATB_MFC_QCH_S_SI_ENABLE, QCH_CON_LH_ATB_MFC_QCH_S_SI_CLOCK_REQ, QCH_CON_LH_ATB_MFC_QCH_S_SI_EXPIRE_VAL, QCH_CON_LH_ATB_MFC_QCH_S_SI_IGNORE_FORCE_PM_EN, QCH_CON_LH_ATB_MFC_QCH_S_MI_ENABLE, QCH_CON_LH_ATB_MFC_QCH_S_MI_CLOCK_REQ, QCH_CON_LH_ATB_MFC_QCH_S_MI_EXPIRE_VAL, QCH_CON_LH_ATB_MFC_QCH_S_MI_IGNORE_FORCE_PM_EN, QCH_CON_MFC_QCH_ENABLE, QCH_CON_MFC_QCH_CLOCK_REQ, QCH_CON_MFC_QCH_EXPIRE_VAL, QCH_CON_MFC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MFC_CMU_MFC_QCH_ENABLE, QCH_CON_MFC_CMU_MFC_QCH_CLOCK_REQ, QCH_CON_MFC_CMU_MFC_QCH_EXPIRE_VAL, QCH_CON_MFC_CMU_MFC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PGEN100_LITE_MFC_QCH_ENABLE, QCH_CON_PGEN100_LITE_MFC_QCH_CLOCK_REQ, QCH_CON_PGEN100_LITE_MFC_QCH_EXPIRE_VAL, QCH_CON_PGEN100_LITE_MFC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_MFCD0_QCH_ENABLE, QCH_CON_PPMU_MFCD0_QCH_CLOCK_REQ, QCH_CON_PPMU_MFCD0_QCH_EXPIRE_VAL, QCH_CON_PPMU_MFCD0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_MFCD1_QCH_ENABLE, QCH_CON_PPMU_MFCD1_QCH_CLOCK_REQ, QCH_CON_PPMU_MFCD1_QCH_EXPIRE_VAL, QCH_CON_PPMU_MFCD1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_MI_SW_RESET_QCH_IGNORE_FORCE_PM_EN, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC_LH_ATB_MFC_SI_SW_RESET_QCH_IGNORE_FORCE_PM_EN, QCH_CON_RSTNSYNC_CLK_MFC_MFC_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC_MFC_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC_MFC_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC_MFC_SW_RESET_QCH_IGNORE_FORCE_PM_EN, QCH_CON_RSTNSYNC_CLK_MFC_WFD_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC_WFD_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC_WFD_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC_WFD_SW_RESET_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_MFCD0_QCH_ENABLE, QCH_CON_SYSMMU_MFCD0_QCH_CLOCK_REQ, QCH_CON_SYSMMU_MFCD0_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_MFCD0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_MFCD1_QCH_ENABLE, QCH_CON_SYSMMU_MFCD1_QCH_CLOCK_REQ, QCH_CON_SYSMMU_MFCD1_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_MFCD1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_MFC_QCH_ENABLE, QCH_CON_SYSREG_MFC_QCH_CLOCK_REQ, QCH_CON_SYSREG_MFC_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MFC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_WFD_QCH_ENABLE, QCH_CON_WFD_QCH_CLOCK_REQ, QCH_CON_WFD_QCH_EXPIRE_VAL, QCH_CON_WFD_QCH_IGNORE_FORCE_PM_EN, CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X_BUSY, CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_MIF_DDRPHY_CLK2X_SELECT, CLK_CON_MUX_MUX_MIF_CMUREF_BUSY, CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_MIF_CMUREF_SELECT, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLK_MIF_BUSD_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_PLL_MIF_DIV_P, PLL_CON0_PLL_MIF_DIV_M, PLL_CON0_PLL_MIF_DIV_S, PLL_CON0_PLL_MIF_ENABLE, PLL_CON0_PLL_MIF_STABLE, PLL_LOCKTIME_PLL_MIF_PLL_LOCK_TIME, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_BUSY, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_MIF_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDR_PHY_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDR_PHY_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDR_PHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDR_PHY_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDR_PHY_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDR_PHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_NRT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_NRT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_RT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_RT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_AXI_D_MIF_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BUSIF_HPMMIF_QCH_ENABLE, QCH_CON_BUSIF_HPMMIF_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMMIF_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMMIF_QCH_IGNORE_FORCE_PM_EN, DMYQCH_CON_CMU_MIF_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_MIF_CMUREF_QCH_CLOCK_REQ, DMYQCH_CON_CMU_MIF_CMUREF_QCH_IGNORE_FORCE_PM_EN, QCH_CON_DMC_QCH_ENABLE, QCH_CON_DMC_QCH_CLOCK_REQ, QCH_CON_DMC_QCH_EXPIRE_VAL, QCH_CON_DMC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_D_MIF_CP_QCH_ENABLE, QCH_CON_LHM_AXI_D_MIF_CP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_MIF_CP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_MIF_CP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_D_MIF_CPU_QCH_ENABLE, QCH_CON_LHM_AXI_D_MIF_CPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_MIF_CPU_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_MIF_CPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_D_MIF_NRT_QCH_ENABLE, QCH_CON_LHM_AXI_D_MIF_NRT_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_MIF_NRT_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_MIF_NRT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_D_MIF_RT_QCH_ENABLE, QCH_CON_LHM_AXI_D_MIF_RT_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_MIF_RT_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_MIF_RT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_P_MIF_QCH_ENABLE, QCH_CON_LHM_AXI_P_MIF_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MIF_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_MIF_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MIF_CMU_MIF_QCH_ENABLE, QCH_CON_MIF_CMU_MIF_QCH_CLOCK_REQ, QCH_CON_MIF_CMU_MIF_QCH_EXPIRE_VAL, QCH_CON_MIF_CMU_MIF_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_DMC_CPU_QCH_ENABLE, QCH_CON_PPMU_DMC_CPU_QCH_CLOCK_REQ, QCH_CON_PPMU_DMC_CPU_QCH_EXPIRE_VAL, QCH_CON_PPMU_DMC_CPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_QE_DMC_CPU_QCH_ENABLE, QCH_CON_QE_DMC_CPU_QCH_CLOCK_REQ, QCH_CON_QE_DMC_CPU_QCH_EXPIRE_VAL, QCH_CON_QE_DMC_CPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SFRAPB_BRIDGE_DDR_PHY_QCH_ENABLE, QCH_CON_SFRAPB_BRIDGE_DDR_PHY_QCH_CLOCK_REQ, QCH_CON_SFRAPB_BRIDGE_DDR_PHY_QCH_EXPIRE_VAL, QCH_CON_SFRAPB_BRIDGE_DDR_PHY_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SFRAPB_BRIDGE_DMC_QCH_ENABLE, QCH_CON_SFRAPB_BRIDGE_DMC_QCH_CLOCK_REQ, QCH_CON_SFRAPB_BRIDGE_DMC_QCH_EXPIRE_VAL, QCH_CON_SFRAPB_BRIDGE_DMC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH_ENABLE, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH_CLOCK_REQ, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH_EXPIRE_VAL, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH_ENABLE, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH_CLOCK_REQ, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH_EXPIRE_VAL, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH_ENABLE, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH_CLOCK_REQ, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH_EXPIRE_VAL, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_MIF_QCH_ENABLE, QCH_CON_SYSREG_MIF_QCH_CLOCK_REQ, QCH_CON_SYSREG_MIF_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MIF_QCH_IGNORE_FORCE_PM_EN, PLL_CON0_PLL_MIF1_DIV_P, PLL_CON0_PLL_MIF1_DIV_M, PLL_CON0_PLL_MIF1_DIV_S, PLL_CON0_PLL_MIF1_ENABLE, PLL_CON0_PLL_MIF1_STABLE, PLL_LOCKTIME_PLL_MIF1_PLL_LOCK_TIME, CLK_CON_MUX_MUX_CLK_MIF1_DDRPHY_CLK2X_BUSY, CLK_CON_MUX_MUX_CLK_MIF1_DDRPHY_CLK2X_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_MIF1_DDRPHY_CLK2X_SELECT, CLK_CON_DIV_CLK_MIF1_BUSD_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_MIF1_BUSP_USER_BUSY, PLL_CON0_MUX_CLKCMU_MIF1_BUSP_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_MIF1_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_MIF1_CMUREF_BUSY, CLK_CON_MUX_MUX_MIF1_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_MIF1_CMUREF_SELECT, CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PF_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PF_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PPMPU_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PPMPU_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_PPMPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_NRT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_NRT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_RT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_RT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_D_MIF1_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BUSIF_HPMMIF1_QCH_ENABLE, QCH_CON_BUSIF_HPMMIF1_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMMIF1_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMMIF1_QCH_IGNORE_FORCE_PM_EN, DMYQCH_CON_CMU_MIF1_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_MIF1_CMUREF_QCH_CLOCK_REQ, DMYQCH_CON_CMU_MIF1_CMUREF_QCH_IGNORE_FORCE_PM_EN, QCH_CON_DMC1_QCH_ENABLE, QCH_CON_DMC1_QCH_CLOCK_REQ, QCH_CON_DMC1_QCH_EXPIRE_VAL, QCH_CON_DMC1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_D_MIF1_CP_QCH_ENABLE, QCH_CON_LHM_AXI_D_MIF1_CP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_MIF1_CP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_MIF1_CP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_D_MIF1_CPU_QCH_ENABLE, QCH_CON_LHM_AXI_D_MIF1_CPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_MIF1_CPU_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_MIF1_CPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_D_MIF1_NRT_QCH_ENABLE, QCH_CON_LHM_AXI_D_MIF1_NRT_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_MIF1_NRT_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_MIF1_NRT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_D_MIF1_RT_QCH_ENABLE, QCH_CON_LHM_AXI_D_MIF1_RT_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_MIF1_RT_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_MIF1_RT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MIF1_CMU_MIF1_QCH_ENABLE, QCH_CON_MIF1_CMU_MIF1_QCH_CLOCK_REQ, QCH_CON_MIF1_CMU_MIF1_QCH_EXPIRE_VAL, QCH_CON_MIF1_CMU_MIF1_QCH_IGNORE_FORCE_PM_EN, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_PERI_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERI_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERI_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_PERI_IP_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERI_IP_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERI_IP_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_BUSIF_TMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_LHM_AXI_P_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_MOTOR_IPCLKPORT_I_PCLK_S0_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_MOTOR_IPCLKPORT_I_PCLK_S0_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_MOTOR_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLK_PERI_I2C_CG_VAL, CLK_CON_GAT_GATE_CLK_PERI_I2C_MANUAL, CLK_CON_GAT_GATE_CLK_PERI_I2C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLK_PERI_SPI0_CG_VAL, CLK_CON_GAT_GATE_CLK_PERI_SPI0_MANUAL, CLK_CON_GAT_GATE_CLK_PERI_SPI0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLK_PERI_SPI1_CG_VAL, CLK_CON_GAT_GATE_CLK_PERI_SPI1_MANUAL, CLK_CON_GAT_GATE_CLK_PERI_SPI1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLK_PERI_USI_USI_CG_VAL, CLK_CON_GAT_GATE_CLK_PERI_USI_USI_MANUAL, CLK_CON_GAT_GATE_CLK_PERI_USI_USI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLK_PERI_USI_I2C_CG_VAL, CLK_CON_GAT_GATE_CLK_PERI_USI_I2C_MANUAL, CLK_CON_GAT_GATE_CLK_PERI_USI_I2C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLK_PERI_SPI2_CG_VAL, CLK_CON_GAT_GATE_CLK_PERI_SPI2_MANUAL, CLK_CON_GAT_GATE_CLK_PERI_SPI2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_PERI_I2C_BUSY, CLK_CON_DIV_DIV_CLK_PERI_I2C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_PERI_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_SPI0_BUSY, CLK_CON_DIV_DIV_CLK_PERI_SPI0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_PERI_SPI0_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_SPI1_BUSY, CLK_CON_DIV_DIV_CLK_PERI_SPI1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_PERI_SPI1_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C_BUSY, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_USI_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERI_USI_USI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_PERI_USI_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_SPI2_BUSY, CLK_CON_DIV_DIV_CLK_PERI_SPI2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_PERI_SPI2_DIVRATIO, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_SPI_2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_PERI_UART_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERI_UART_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERI_UART_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_CAMI2C_3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_4_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_4_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_5_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_5_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_5_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_6_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_6_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_I2C_6_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SPI_2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BUSIF_TMU_QCH_ENABLE, QCH_CON_BUSIF_TMU_QCH_CLOCK_REQ, QCH_CON_BUSIF_TMU_QCH_EXPIRE_VAL, QCH_CON_BUSIF_TMU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_CAMI2C_0_QCH_ENABLE, QCH_CON_CAMI2C_0_QCH_CLOCK_REQ, QCH_CON_CAMI2C_0_QCH_EXPIRE_VAL, QCH_CON_CAMI2C_0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_CAMI2C_1_QCH_ENABLE, QCH_CON_CAMI2C_1_QCH_CLOCK_REQ, QCH_CON_CAMI2C_1_QCH_EXPIRE_VAL, QCH_CON_CAMI2C_1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_CAMI2C_2_QCH_ENABLE, QCH_CON_CAMI2C_2_QCH_CLOCK_REQ, QCH_CON_CAMI2C_2_QCH_EXPIRE_VAL, QCH_CON_CAMI2C_2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_CAMI2C_3_QCH_ENABLE, QCH_CON_CAMI2C_3_QCH_CLOCK_REQ, QCH_CON_CAMI2C_3_QCH_EXPIRE_VAL, QCH_CON_CAMI2C_3_QCH_IGNORE_FORCE_PM_EN, QCH_CON_GPIO_PERI_QCH_ENABLE, QCH_CON_GPIO_PERI_QCH_CLOCK_REQ, QCH_CON_GPIO_PERI_QCH_EXPIRE_VAL, QCH_CON_GPIO_PERI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_I2C_0_QCH_ENABLE, QCH_CON_I2C_0_QCH_CLOCK_REQ, QCH_CON_I2C_0_QCH_EXPIRE_VAL, QCH_CON_I2C_0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_I2C_1_QCH_ENABLE, QCH_CON_I2C_1_QCH_CLOCK_REQ, QCH_CON_I2C_1_QCH_EXPIRE_VAL, QCH_CON_I2C_1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_I2C_2_QCH_ENABLE, QCH_CON_I2C_2_QCH_CLOCK_REQ, QCH_CON_I2C_2_QCH_EXPIRE_VAL, QCH_CON_I2C_2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_I2C_3_QCH_ENABLE, QCH_CON_I2C_3_QCH_CLOCK_REQ, QCH_CON_I2C_3_QCH_EXPIRE_VAL, QCH_CON_I2C_3_QCH_IGNORE_FORCE_PM_EN, QCH_CON_I2C_4_QCH_ENABLE, QCH_CON_I2C_4_QCH_CLOCK_REQ, QCH_CON_I2C_4_QCH_EXPIRE_VAL, QCH_CON_I2C_4_QCH_IGNORE_FORCE_PM_EN, QCH_CON_I2C_5_QCH_ENABLE, QCH_CON_I2C_5_QCH_CLOCK_REQ, QCH_CON_I2C_5_QCH_EXPIRE_VAL, QCH_CON_I2C_5_QCH_IGNORE_FORCE_PM_EN, QCH_CON_I2C_6_QCH_ENABLE, QCH_CON_I2C_6_QCH_CLOCK_REQ, QCH_CON_I2C_6_QCH_EXPIRE_VAL, QCH_CON_I2C_6_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_P_PERI_QCH_ENABLE, QCH_CON_LHM_AXI_P_PERI_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_PERI_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_PERI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MCT_QCH_ENABLE, QCH_CON_MCT_QCH_CLOCK_REQ, QCH_CON_MCT_QCH_EXPIRE_VAL, QCH_CON_MCT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_OTP_CON_TOP_QCH_ENABLE, QCH_CON_OTP_CON_TOP_QCH_CLOCK_REQ, QCH_CON_OTP_CON_TOP_QCH_EXPIRE_VAL, QCH_CON_OTP_CON_TOP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PERI_CMU_PERI_QCH_ENABLE, QCH_CON_PERI_CMU_PERI_QCH_CLOCK_REQ, QCH_CON_PERI_CMU_PERI_QCH_EXPIRE_VAL, QCH_CON_PERI_CMU_PERI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PWM_MOTOR_QCH_ENABLE, QCH_CON_PWM_MOTOR_QCH_CLOCK_REQ, QCH_CON_PWM_MOTOR_QCH_EXPIRE_VAL, QCH_CON_PWM_MOTOR_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SPI_0_QCH_ENABLE, QCH_CON_SPI_0_QCH_CLOCK_REQ, QCH_CON_SPI_0_QCH_EXPIRE_VAL, QCH_CON_SPI_0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SPI_1_QCH_ENABLE, QCH_CON_SPI_1_QCH_CLOCK_REQ, QCH_CON_SPI_1_QCH_EXPIRE_VAL, QCH_CON_SPI_1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SPI_2_QCH_ENABLE, QCH_CON_SPI_2_QCH_CLOCK_REQ, QCH_CON_SPI_2_QCH_EXPIRE_VAL, QCH_CON_SPI_2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_PERI_QCH_ENABLE, QCH_CON_SYSREG_PERI_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERI_QCH_EXPIRE_VAL, QCH_CON_SYSREG_PERI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_UART_QCH_ENABLE, QCH_CON_UART_QCH_CLOCK_REQ, QCH_CON_UART_QCH_EXPIRE_VAL, QCH_CON_UART_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI00_I2C_QCH_ENABLE, QCH_CON_USI00_I2C_QCH_CLOCK_REQ, QCH_CON_USI00_I2C_QCH_EXPIRE_VAL, QCH_CON_USI00_I2C_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI00_USI_QCH_ENABLE, QCH_CON_USI00_USI_QCH_CLOCK_REQ, QCH_CON_USI00_USI_QCH_EXPIRE_VAL, QCH_CON_USI00_USI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_WDT_CLUSTER0_QCH_ENABLE, QCH_CON_WDT_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_WDT_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_WDT_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_WDT_CLUSTER1_QCH_ENABLE, QCH_CON_WDT_CLUSTER1_QCH_CLOCK_REQ, QCH_CON_WDT_CLUSTER1_QCH_EXPIRE_VAL, QCH_CON_WDT_CLUSTER1_QCH_IGNORE_FORCE_PM_EN, CLK_CON_MUX_MUX_CLK_SHUB_USI00_BUSY, CLK_CON_MUX_MUX_CLK_SHUB_USI00_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_SHUB_USI00_SELECT, PLL_CON0_MUX_CLKCMU_SHUB_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_SHUB_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_SHUB_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_SHUB_USI01_BUSY, CLK_CON_DIV_DIV_CLK_SHUB_USI01_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_SHUB_USI01_DIVRATIO, CLK_CON_DIV_DIV_CLK_SHUB_I2C_BUSY, CLK_CON_DIV_DIV_CLK_SHUB_I2C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_SHUB_I2C_DIVRATIO, CLK_CON_MUX_MUX_CLK_SHUB_USI01_BUSY, CLK_CON_MUX_MUX_CLK_SHUB_USI01_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_SHUB_USI01_SELECT, CLK_CON_DIV_DIV_CLK_SHUB_USI00_BUSY, CLK_CON_DIV_DIV_CLK_SHUB_USI00_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_SHUB_USI00_DIVRATIO, CLK_CON_MUX_MUX_CLK_SHUB_I2C_BUSY, CLK_CON_MUX_MUX_CLK_SHUB_I2C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_SHUB_I2C_SELECT, CLK_CON_GAT_CLK_BLK_SHUB_UID_SHUB_CMU_SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SHUB_UID_SHUB_CMU_SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_SHUB_UID_SHUB_CMU_SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_D_SHUB_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_D_SHUB_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_D_SHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_P_APM_SHUB_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_P_APM_SHUB_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_BAAW_P_APM_SHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SHUB_UID_GPIO_SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_GPIO_SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_GPIO_SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_LP_SHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_LP_SHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_LP_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_P_SHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_P_SHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHM_AXI_P_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_D_SHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_D_SHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_D_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_P_APM_SHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_P_APM_SHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_LHS_AXI_P_APM_SHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PWM_SHUB_IPCLKPORT_I_PCLK_S0_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PWM_SHUB_IPCLKPORT_I_PCLK_S0_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PWM_SHUB_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_D_SHUB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_D_SHUB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_D_SHUB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_P_APM_SHUB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_P_APM_SHUB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SWEEPER_P_APM_SHUB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SYSREG_SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SYSREG_SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_SYSREG_SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SHUB_UID_TIMER_SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_TIMER_SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_TIMER_SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SHUB_UID_WDT_SHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_WDT_SHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_WDT_SHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_RTCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_RTCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_RTCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_USI00_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_USI00_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_RSTNSYNC_CLK_SHUB_USI00_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SHUB_UID_CM4_SHUB_IPCLKPORT_FCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_CM4_SHUB_IPCLKPORT_FCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_CM4_SHUB_IPCLKPORT_FCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_I2C_SHUB00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PDMA_SHUB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PDMA_SHUB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_PDMA_SHUB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_USI_SHUB00_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SHUB_UID_XIU_DP_SHUB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_XIU_DP_SHUB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SHUB_UID_XIU_DP_SHUB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BAAW_D_SHUB_QCH_ENABLE, QCH_CON_BAAW_D_SHUB_QCH_CLOCK_REQ, QCH_CON_BAAW_D_SHUB_QCH_EXPIRE_VAL, QCH_CON_BAAW_D_SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_BAAW_P_APM_SHUB_QCH_ENABLE, QCH_CON_BAAW_P_APM_SHUB_QCH_CLOCK_REQ, QCH_CON_BAAW_P_APM_SHUB_QCH_EXPIRE_VAL, QCH_CON_BAAW_P_APM_SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_CM4_SHUB_QCH_ENABLE, QCH_CON_CM4_SHUB_QCH_CLOCK_REQ, QCH_CON_CM4_SHUB_QCH_EXPIRE_VAL, QCH_CON_CM4_SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_GPIO_SHUB_QCH_ENABLE, QCH_CON_GPIO_SHUB_QCH_CLOCK_REQ, QCH_CON_GPIO_SHUB_QCH_EXPIRE_VAL, QCH_CON_GPIO_SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_I2C_SHUB00_QCH_ENABLE, QCH_CON_I2C_SHUB00_QCH_CLOCK_REQ, QCH_CON_I2C_SHUB00_QCH_EXPIRE_VAL, QCH_CON_I2C_SHUB00_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_LP_SHUB_QCH_ENABLE, QCH_CON_LHM_AXI_LP_SHUB_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_LP_SHUB_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_LP_SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_P_SHUB_QCH_ENABLE, QCH_CON_LHM_AXI_P_SHUB_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_SHUB_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_D_SHUB_QCH_ENABLE, QCH_CON_LHS_AXI_D_SHUB_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_SHUB_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_P_APM_SHUB_QCH_ENABLE, QCH_CON_LHS_AXI_P_APM_SHUB_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_APM_SHUB_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_APM_SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PDMA_SHUB_QCH_ENABLE, QCH_CON_PDMA_SHUB_QCH_CLOCK_REQ, QCH_CON_PDMA_SHUB_QCH_EXPIRE_VAL, QCH_CON_PDMA_SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PWM_SHUB_QCH_ENABLE, QCH_CON_PWM_SHUB_QCH_CLOCK_REQ, QCH_CON_PWM_SHUB_QCH_EXPIRE_VAL, QCH_CON_PWM_SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SHUB_CMU_SHUB_QCH_ENABLE, QCH_CON_SHUB_CMU_SHUB_QCH_CLOCK_REQ, QCH_CON_SHUB_CMU_SHUB_QCH_EXPIRE_VAL, QCH_CON_SHUB_CMU_SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SWEEPER_D_SHUB_QCH_ENABLE, QCH_CON_SWEEPER_D_SHUB_QCH_CLOCK_REQ, QCH_CON_SWEEPER_D_SHUB_QCH_EXPIRE_VAL, QCH_CON_SWEEPER_D_SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SWEEPER_P_APM_SHUB_QCH_ENABLE, QCH_CON_SWEEPER_P_APM_SHUB_QCH_CLOCK_REQ, QCH_CON_SWEEPER_P_APM_SHUB_QCH_EXPIRE_VAL, QCH_CON_SWEEPER_P_APM_SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_SHUB_QCH_ENABLE, QCH_CON_SYSREG_SHUB_QCH_CLOCK_REQ, QCH_CON_SYSREG_SHUB_QCH_EXPIRE_VAL, QCH_CON_SYSREG_SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_TIMER_SHUB_QCH_ENABLE, QCH_CON_TIMER_SHUB_QCH_CLOCK_REQ, QCH_CON_TIMER_SHUB_QCH_EXPIRE_VAL, QCH_CON_TIMER_SHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI_SHUB00_QCH_ENABLE, QCH_CON_USI_SHUB00_QCH_CLOCK_REQ, QCH_CON_USI_SHUB00_QCH_EXPIRE_VAL, QCH_CON_USI_SHUB00_QCH_IGNORE_FORCE_PM_EN, QCH_CON_WDT_SHUB_QCH_ENABLE, QCH_CON_WDT_SHUB_QCH_CLOCK_REQ, QCH_CON_WDT_SHUB_QCH_EXPIRE_VAL, QCH_CON_WDT_SHUB_QCH_IGNORE_FORCE_PM_EN, PLL_CON0_MUX_CLKCMU_USB_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_USB_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_USB_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_USB_USB30DRD_USER_BUSY, PLL_CON0_MUX_CLKCMU_USB_USB30DRD_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_USB_USB30DRD_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_USB_DPGTC_USER_BUSY, PLL_CON0_MUX_CLKCMU_USB_DPGTC_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_USB_DPGTC_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_LHM_AXI_P_USB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_LHM_AXI_P_USB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_LHM_AXI_P_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_BUS_CLK_EARLY_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_BUS_CLK_EARLY_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_BUS_CLK_EARLY_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_DP_GTC_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_DP_GTC_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_DP_GTC_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_USB_UID_RSTNSYNC_CLK_USB_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_USB_UID_RSTNSYNC_CLK_USB_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_USB_UID_RSTNSYNC_CLK_USB_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_20_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_20_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_20_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_PGEN_LITE_USB_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PGEN_LITE_USB_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PGEN_LITE_USB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_1_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_1_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_BTM_USB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_US_D_USB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_US_D_USB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_US_D_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_DP_LINK_IPCLKPORT_DPTX_LINK_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_0_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_0_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_ACLK_PHYCTRL_30_0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_USB30DRD_REF_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_USB30DRD_REF_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB30DRD_IPCLKPORT_USB30DRD_REF_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_LHS_ACEL_D_USB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_LHS_ACEL_D_USB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_LHS_ACEL_D_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BTM_USB_QCH_ENABLE, QCH_CON_BTM_USB_QCH_CLOCK_REQ, QCH_CON_BTM_USB_QCH_EXPIRE_VAL, QCH_CON_BTM_USB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_DP_LINK_QCH_DP_ENABLE, QCH_CON_DP_LINK_QCH_DP_CLOCK_REQ, QCH_CON_DP_LINK_QCH_DP_EXPIRE_VAL, QCH_CON_DP_LINK_QCH_DP_IGNORE_FORCE_PM_EN, QCH_CON_DP_LINK_QCH_GTC_ENABLE, QCH_CON_DP_LINK_QCH_GTC_CLOCK_REQ, QCH_CON_DP_LINK_QCH_GTC_EXPIRE_VAL, QCH_CON_DP_LINK_QCH_GTC_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_P_USB_QCH_ENABLE, QCH_CON_LHM_AXI_P_USB_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_USB_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_USB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_ACEL_D_USB_QCH_ENABLE, QCH_CON_LHS_ACEL_D_USB_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_USB_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_USB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PGEN_LITE_USB_QCH_ENABLE, QCH_CON_PGEN_LITE_USB_QCH_CLOCK_REQ, QCH_CON_PGEN_LITE_USB_QCH_EXPIRE_VAL, QCH_CON_PGEN_LITE_USB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_USB_QCH_ENABLE, QCH_CON_PPMU_USB_QCH_CLOCK_REQ, QCH_CON_PPMU_USB_QCH_EXPIRE_VAL, QCH_CON_PPMU_USB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_USB_QCH_ENABLE, QCH_CON_SYSREG_USB_QCH_CLOCK_REQ, QCH_CON_SYSREG_USB_QCH_EXPIRE_VAL, QCH_CON_SYSREG_USB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USB30DRD_QCH_USB30_ENABLE, QCH_CON_USB30DRD_QCH_USB30_CLOCK_REQ, QCH_CON_USB30DRD_QCH_USB30_EXPIRE_VAL, QCH_CON_USB30DRD_QCH_USB30_IGNORE_FORCE_PM_EN, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_0_ENABLE, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_0_CLOCK_REQ, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_0_EXPIRE_VAL, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_0_IGNORE_FORCE_PM_EN, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_1_ENABLE, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_1_CLOCK_REQ, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_1_EXPIRE_VAL, QCH_CON_USB30DRD_QCH_USBPHY_30CTRL_1_IGNORE_FORCE_PM_EN, QCH_CON_USB30DRD_QCH_USBPHY_20CTRL_ENABLE, QCH_CON_USB30DRD_QCH_USBPHY_20CTRL_CLOCK_REQ, QCH_CON_USB30DRD_QCH_USBPHY_20CTRL_EXPIRE_VAL, QCH_CON_USB30DRD_QCH_USBPHY_20CTRL_IGNORE_FORCE_PM_EN, QCH_CON_USB_CMU_USB_QCH_ENABLE, QCH_CON_USB_CMU_USB_QCH_CLOCK_REQ, QCH_CON_USB_CMU_USB_QCH_EXPIRE_VAL, QCH_CON_USB_CMU_USB_QCH_IGNORE_FORCE_PM_EN, CLK_CON_DIV_DIV_CLK_VIPX1_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_VIPX1_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_VIPX1_BUSP_DIVRATIO, PLL_CON0_MUX_CLKCMU_VIPX1_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_VIPX1_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_VIPX1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ACEL_D_VIPX1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ACEL_D_VIPX1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ACEL_D_VIPX1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VIPX1_UID_RSTNSYNC_CLK_VIPX1_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SYSREG_VIPX1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SYSREG_VIPX1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SYSREG_VIPX1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_VIPX1_UID_VIPX1_CMU_VIPX1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VIPX1_UID_VIPX1_CMU_VIPX1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VIPX1_UID_VIPX1_CMU_VIPX1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ATB_VIPX1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ATB_VIPX1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_ATB_VIPX1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BLK_VIPX1_IPCLKPORT_CLK_VIPX1_BUSD_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BLK_VIPX1_IPCLKPORT_CLK_VIPX1_BUSD_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BLK_VIPX1_IPCLKPORT_CLK_VIPX1_BUSD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PPMU_D_VIPX1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SMMU_D_VIPX1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SMMU_D_VIPX1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_SMMU_D_VIPX1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_XIU_D_VIPX1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_XIU_D_VIPX1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_XIU_D_VIPX1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PGEN_LITE_VIPX1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PGEN_LITE_VIPX1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_PGEN_LITE_VIPX1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_VIPX1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_VIPX1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_VIPX1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_BTM_D_VIPX1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_AXI_P_VIPX1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_AXI_P_VIPX1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_AXI_P_VIPX1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_ATB_VIPX1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_ATB_VIPX1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHM_ATB_VIPX1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_AXI_P_VIPX1_LOCAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_AXI_P_VIPX1_LOCAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX1_UID_LHS_AXI_P_VIPX1_LOCAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BTM_D_VIPX1_QCH_ENABLE, QCH_CON_BTM_D_VIPX1_QCH_CLOCK_REQ, QCH_CON_BTM_D_VIPX1_QCH_EXPIRE_VAL, QCH_CON_BTM_D_VIPX1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_ATB_VIPX1_QCH_ENABLE, QCH_CON_LHM_ATB_VIPX1_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_VIPX1_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_VIPX1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_P_VIPX1_QCH_ENABLE, QCH_CON_LHM_AXI_P_VIPX1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_VIPX1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_VIPX1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_ACEL_D_VIPX1_QCH_ENABLE, QCH_CON_LHS_ACEL_D_VIPX1_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_VIPX1_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_VIPX1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_ATB_VIPX1_QCH_ENABLE, QCH_CON_LHS_ATB_VIPX1_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_VIPX1_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_VIPX1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_P_VIPX1_LOCAL_QCH_ENABLE, QCH_CON_LHS_AXI_P_VIPX1_LOCAL_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_VIPX1_LOCAL_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_VIPX1_LOCAL_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PGEN_LITE_VIPX1_QCH_ENABLE, QCH_CON_PGEN_LITE_VIPX1_QCH_CLOCK_REQ, QCH_CON_PGEN_LITE_VIPX1_QCH_EXPIRE_VAL, QCH_CON_PGEN_LITE_VIPX1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_D_VIPX1_QCH_ENABLE, QCH_CON_PPMU_D_VIPX1_QCH_CLOCK_REQ, QCH_CON_PPMU_D_VIPX1_QCH_EXPIRE_VAL, QCH_CON_PPMU_D_VIPX1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SMMU_D_VIPX1_QCH_ENABLE, QCH_CON_SMMU_D_VIPX1_QCH_CLOCK_REQ, QCH_CON_SMMU_D_VIPX1_QCH_EXPIRE_VAL, QCH_CON_SMMU_D_VIPX1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_VIPX1_QCH_ENABLE, QCH_CON_SYSREG_VIPX1_QCH_CLOCK_REQ, QCH_CON_SYSREG_VIPX1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_VIPX1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VIPX1_QCH_ENABLE, QCH_CON_VIPX1_QCH_CLOCK_REQ, QCH_CON_VIPX1_QCH_EXPIRE_VAL, QCH_CON_VIPX1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VIPX1_CMU_VIPX1_QCH_ENABLE, QCH_CON_VIPX1_CMU_VIPX1_QCH_CLOCK_REQ, QCH_CON_VIPX1_CMU_VIPX1_QCH_EXPIRE_VAL, QCH_CON_VIPX1_CMU_VIPX1_QCH_IGNORE_FORCE_PM_EN, CLK_CON_DIV_DIV_CLK_VIPX2_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_VIPX2_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_VIPX2_BUSP_DIVRATIO, PLL_CON0_MUX_CLKCMU_VIPX2_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_VIPX2_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_VIPX2_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_VIPX2_UID_VIPX2_CMU_VIPX2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VIPX2_UID_VIPX2_CMU_VIPX2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VIPX2_UID_VIPX2_CMU_VIPX2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BTM_D_VIPX2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_ATB_VIPX2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_ATB_VIPX2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_ATB_VIPX2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ACEL_D_VIPX2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ACEL_D_VIPX2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ACEL_D_VIPX2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ATB_VIPX2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ATB_VIPX2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHS_ATB_VIPX2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_LOCAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_LOCAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_LHM_AXI_P_VIPX2_LOCAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PGEN_LITE_VIPX2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PGEN_LITE_VIPX2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PGEN_LITE_VIPX2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_PPMU_D_VIPX2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SMMU_D_VIPX2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SMMU_D_VIPX2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SMMU_D_VIPX2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SYSREG_VIPX2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SYSREG_VIPX2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_SYSREG_VIPX2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BLK_VIPX2_IPCLKPORT_CLK_VIPX2_BUSD_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BLK_VIPX2_IPCLKPORT_CLK_VIPX2_BUSD_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_BLK_VIPX2_IPCLKPORT_CLK_VIPX2_BUSD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_VIPX2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_VIPX2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_VIPX2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VIPX2_UID_RSTNSYNC_CLK_VIPX2_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BTM_D_VIPX2_QCH_ENABLE, QCH_CON_BTM_D_VIPX2_QCH_CLOCK_REQ, QCH_CON_BTM_D_VIPX2_QCH_EXPIRE_VAL, QCH_CON_BTM_D_VIPX2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_ATB_VIPX2_QCH_ENABLE, QCH_CON_LHM_ATB_VIPX2_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_VIPX2_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_VIPX2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_P_VIPX2_QCH_ENABLE, QCH_CON_LHM_AXI_P_VIPX2_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_VIPX2_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_VIPX2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_P_VIPX2_LOCAL_QCH_ENABLE, QCH_CON_LHM_AXI_P_VIPX2_LOCAL_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_VIPX2_LOCAL_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_VIPX2_LOCAL_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_ACEL_D_VIPX2_QCH_ENABLE, QCH_CON_LHS_ACEL_D_VIPX2_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_VIPX2_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_VIPX2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_ATB_VIPX2_QCH_ENABLE, QCH_CON_LHS_ATB_VIPX2_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_VIPX2_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_VIPX2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PGEN_LITE_VIPX2_QCH_ENABLE, QCH_CON_PGEN_LITE_VIPX2_QCH_CLOCK_REQ, QCH_CON_PGEN_LITE_VIPX2_QCH_EXPIRE_VAL, QCH_CON_PGEN_LITE_VIPX2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_D_VIPX2_QCH_ENABLE, QCH_CON_PPMU_D_VIPX2_QCH_CLOCK_REQ, QCH_CON_PPMU_D_VIPX2_QCH_EXPIRE_VAL, QCH_CON_PPMU_D_VIPX2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SMMU_D_VIPX2_QCH_ENABLE, QCH_CON_SMMU_D_VIPX2_QCH_CLOCK_REQ, QCH_CON_SMMU_D_VIPX2_QCH_EXPIRE_VAL, QCH_CON_SMMU_D_VIPX2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_VIPX2_QCH_ENABLE, QCH_CON_SYSREG_VIPX2_QCH_CLOCK_REQ, QCH_CON_SYSREG_VIPX2_QCH_EXPIRE_VAL, QCH_CON_SYSREG_VIPX2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VIPX2_QCH_ENABLE, QCH_CON_VIPX2_QCH_CLOCK_REQ, QCH_CON_VIPX2_QCH_EXPIRE_VAL, QCH_CON_VIPX2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VIPX2_QCH_LOCAL_ENABLE, QCH_CON_VIPX2_QCH_LOCAL_CLOCK_REQ, QCH_CON_VIPX2_QCH_LOCAL_EXPIRE_VAL, QCH_CON_VIPX2_QCH_LOCAL_IGNORE_FORCE_PM_EN, QCH_CON_VIPX2_CMU_VIPX2_QCH_ENABLE, QCH_CON_VIPX2_CMU_VIPX2_QCH_CLOCK_REQ, QCH_CON_VIPX2_CMU_VIPX2_QCH_EXPIRE_VAL, QCH_CON_VIPX2_CMU_VIPX2_QCH_IGNORE_FORCE_PM_EN, /*====================The section of controller option SFR access===================*/ APM_CMU_APM_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, APM_CMU_APM_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, CAM_CMU_CAM_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CAM_CMU_CAM_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, CORE_CMU_CORE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CORE_CMU_CORE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, CPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, CPUCL1_EMBEDDED_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL1_EMBEDDED_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, DISPAUD_CMU_DISPAUD_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DISPAUD_CMU_DISPAUD_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, FSYS_CMU_FSYS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, FSYS_CMU_FSYS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, G2D_CMU_G2D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, G2D_CMU_G2D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, ISP_CMU_ISP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, ISP_CMU_ISP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, MFC_CMU_MFC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MFC_CMU_MFC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, MIF1_CMU_MIF1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MIF1_CMU_MIF1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, PERI_CMU_PERI_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, PERI_CMU_PERI_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, SHUB_CMU_SHUB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, SHUB_CMU_SHUB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, USB_CMU_USB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, USB_CMU_USB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, VIPX1_CMU_VIPX1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, VIPX1_CMU_VIPX1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, VIPX2_CMU_VIPX2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, VIPX2_CMU_VIPX2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, end_of_sfr_access, num_of_sfr_access = end_of_sfr_access - SFR_ACCESS_TYPE, }; #endif