#ifndef __CMUCAL_SFR_H__ #define __CMUCAL_SFR_H__ #include "../cmucal.h" /*=================CMUCAL version: S5E8895================================*/ /*====================The section of SFR Block===================*/ enum sfr_block_id { ABOX = SFR_BLOCK_TYPE, APM, BUS1, BUSC, CAM, CMU, CORE, CPUCL0, CPUCL1, DBG, DCAM, DPU0, DPU1, DSP, FSYS0, FSYS1, G2D, G3D, IMEM, ISPHQ, ISPLP, IVA, MFC, MIF, MIF1, MIF2, MIF3, PERIC0, PERIC1, PERIS, SRDZ, VPU, VTS, end_of_sfr_block, num_of_sfr_block = end_of_sfr_block - SFR_BLOCK_TYPE, }; /*====================The section of SFR===================*/ enum sfr_id { PLL_CON0_PLL_AUD = SFR_TYPE, PLL_CON3_PLL_AUD, PLL_LOCKTIME_PLL_AUD, CLK_CON_DIV_DIV_CLK_ABOX_PLL, CLK_CON_DIV_DIV_CLK_ABOX_AUDIF, CLK_CON_DIV_DIV_CLK_ABOX_CPU_ATCLK, CLK_CON_DIV_DIV_CLK_ABOX_CPU_PCLKDBG, CLK_CON_DIV_DIV_CLK_ABOX_DSIF, CLK_CON_DIV_DIV_CLK_ABOX_UAIF0, CLK_CON_DIV_DIV_CLK_ABOX_UAIF1, CLK_CON_DIV_DIV_CLK_ABOX_UAIF2, CLK_CON_DIV_DIV_CLK_ABOX_UAIF3, CLK_CON_MUX_MUX_CLK_ABOX_UAIF3, CLK_CON_MUX_MUX_CLK_ABOX_UAIF2, CLK_CON_MUX_MUX_CLK_ABOX_UAIF1, CLK_CON_MUX_MUX_CLK_ABOX_UAIF0, CLK_CON_GAT_CLK_BLK_ABOX_UID_ABOX_CMU_ABOX_IPCLKPORT_PCLK, PLL_CON0_MUX_CLKCMU_ABOX_CPUABOX_USER, PLL_CON2_MUX_CLKCMU_ABOX_CPUABOX_USER, CLK_CON_MUX_MUX_CLK_ABOX_CPU, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PMU_ABOX_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SYSREG_ABOX_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF0, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF3, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_DSIF, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_ATB_ABOX_IPCLKPORT_I_CLK, CLKOUT_CON_BLK_ABOX_CMU_CLKOUT0, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_GPIO_ABOX_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_AXI_US_32TO128_IPCLKPORT_ACLK, CLKOUT_CON_BLK_ABOX_CMU_CLKOUT1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ATCLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_PCLKDBG_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_DSIF_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF0_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF1_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF2_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF3_IPCLKPORT_CLK, CLK_CON_DIV_DIV_CLK_ABOX_CPU_ACLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ASB, CLK_CON_DIV_DIV_CLK_ABOX_BUS, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ACLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_CA7, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF2, CLK_CON_DIV_DIV_CLK_ABOX_BUSP, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHM_AXI_P_ABOX_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_WDT_ABOXCPU_IPCLKPORT_PCLK, CLK_CON_DIV_DIV_CLK_ABOX_DMIC, CLK_CON_GAT_CLK_BLK_ABOX_UID_DMIC_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ATB, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_DAP_IPCLKPORT_DAPCLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_TREX_ABOX_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_WRAP2_CONV_ABOX_IPCLKPORT_I_CLK, CLK_CON_DIV_DIV_CLK_ABOX_UAIF4, CLK_CON_MUX_MUX_CLK_ABOX_UAIF4, CLK_CON_GAT_CLK_BLK_ABOX_UID_DFTMUX_ABOX_IPCLKPORT_AUD_CODEC_MCLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF4_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF4, QCH_CON_ABOX_CMU_ABOX_QCH, DMYQCH_CON_ABOX_TOP_QCH, QCH_CON_BTM_ABOX_QCH, DMYQCH_CON_DMIC_QCH, QCH_CON_GPIO_ABOX_QCH, QCH_CON_LHM_AXI_P_ABOX_QCH, QCH_CON_LHS_ATB_ABOX_QCH, QCH_CON_LHS_AXI_D_ABOX_QCH, QCH_CON_PMU_ABOX_QCH, QCH_CON_BCM_ABOX_QCH, QCH_CON_SMMU_ABOX_QCH, QCH_CON_SYSREG_ABOX_QCH, QCH_CON_TREX_ABOX_QCH, QCH_CON_WDT_ABOXCPU_QCH, PLL_CON0_MUX_CLKCMU_APM_BUS_USER, PLL_CON2_MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, CLKOUT_CON_BLK_APM_CMU_CLKOUT0, CLKOUT_CON_BLK_APM_CMU_CLKOUT1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_XIU_D_ALIVE, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_SCAN2AXI_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK, QCH_CON_APM_QCH_SYS, QCH_CON_APM_QCH_CPU, DMYQCH_CON_APM_QCH_OSCCLK, QCH_CON_APM_CMU_APM_QCH, QCH_CON_LHM_AXI_P_ALIVE_QCH, QCH_CON_LHS_AXI_D_ALIVE_QCH, QCH_CON_MAILBOX_APM2AP_QCH, QCH_CON_MAILBOX_APM2CP_QCH, QCH_CON_MAILBOX_APM2GNSS_QCH, QCH_CON_SCAN2AXI_QCH, QCH_CON_SYSREG_APM_QCH, QCH_CON_WDT_APM_QCH, CLK_CON_DIV_DIV_CLK_BUS1_BUSP, PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER, PLL_CON2_MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_FSYS1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_FSYS1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_BUS1_UID_PMU_BUS1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK, CLKOUT_CON_BLK_BUS1_CMU_CLKOUT0, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_ALIVE_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_ALIVE_IPCLKPORT_I_CLK, CLKOUT_CON_BLK_BUS1_CMU_CLKOUT1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK, QCH_CON_BUS1_CMU_BUS1_QCH, QCH_CON_LHM_ACEL_D_FSYS1_QCH, QCH_CON_LHM_AXI_D_ALIVE_QCH, QCH_CON_LHM_AXI_D_GNSS_QCH, QCH_CON_LHS_AXI_P_ALIVE_QCH, QCH_CON_LHS_AXI_P_FSYS1_QCH, QCH_CON_PMU_BUS1_QCH, QCH_CON_SYSREG_BUS1_QCH, QCH_CON_TREX_D_BUS1_QCH, QCH_CON_TREX_P_BUS1_QCH, CLK_CON_DIV_DIV_CLK_BUSC_BUSP, CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSC_TDP_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_GPIO_BUSC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PMU_BUSC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SECMBOX_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_MBOX_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S0, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_BUSC, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK, PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER, PLL_CON2_MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK, CLKOUT_CON_BLK_BUSC_CMU_CLKOUT0, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK, CLKOUT_CON_BLK_BUSC_CMU_CLKOUT1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_GNSSMBOX_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_PCLK_BATCHER_SPEEDY, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_AP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_CP, PLL_CON0_MUX_CLKCMU_BUSC_BUSPHSI2C_USER, PLL_CON2_MUX_CLKCMU_BUSC_BUSPHSI2C_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_HSI2CDF_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSPHSI2C_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SCI_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_D_IVASC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D0_G2D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D1_G2D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D2_G2D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_DSP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_FSYS0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_IVA_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_VPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_CAM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_DPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_MFC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_CAM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_DPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_MFC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D2_DPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_SRDZ_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ISPLP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P0_DPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P1_DPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ABOX_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_SRDZ_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_DSP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_FSYS0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPHQ_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPLP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_IVA_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_ACLK_BUSC, QCH_CON_ADCIF_BUSC_QCH_S0, QCH_CON_ADCIF_BUSC_QCH_S1, QCH_CON_BUSC_CMU_BUSC_QCH, QCH_CON_BUSIF_CMUTOPC_QCH, QCH_CON_GNSSMBOX_QCH, QCH_CON_GPIO_BUSC_QCH, QCH_CON_HSI2CDF_QCH, QCH_CON_LHM_ACEL_D0_G2D_QCH, QCH_CON_LHM_ACEL_D1_G2D_QCH, QCH_CON_LHM_ACEL_D2_G2D_QCH, QCH_CON_LHM_ACEL_D_DSP_QCH, QCH_CON_LHM_ACEL_D_FSYS0_QCH, QCH_CON_LHM_ACEL_D_IVA_QCH, QCH_CON_LHM_ACEL_D_VPU_QCH, QCH_CON_LHM_AXI_D0_CAM_QCH, QCH_CON_LHM_AXI_D0_DPU_QCH, QCH_CON_LHM_AXI_D0_MFC_QCH, QCH_CON_LHM_AXI_D1_CAM_QCH, QCH_CON_LHM_AXI_D1_DPU_QCH, QCH_CON_LHM_AXI_D1_MFC_QCH, QCH_CON_LHM_AXI_D2_DPU_QCH, QCH_CON_LHM_AXI_D_ABOX_QCH, QCH_CON_LHM_AXI_D_ISPLP_QCH, QCH_CON_LHM_AXI_D_SRDZ_QCH, QCH_CON_LHM_AXI_D_VTS_QCH, QCH_CON_LHM_AXI_G_CSSYS_QCH, QCH_CON_LHS_AXI_D_IVASC_QCH, QCH_CON_LHS_AXI_P0_DPU_QCH, QCH_CON_LHS_AXI_P1_DPU_QCH, QCH_CON_LHS_AXI_P_ABOX_QCH, QCH_CON_LHS_AXI_P_CAM_QCH, QCH_CON_LHS_AXI_P_DSP_QCH, QCH_CON_LHS_AXI_P_FSYS0_QCH, QCH_CON_LHS_AXI_P_G2D_QCH, QCH_CON_LHS_AXI_P_ISPHQ_QCH, QCH_CON_LHS_AXI_P_ISPLP_QCH, QCH_CON_LHS_AXI_P_IVA_QCH, QCH_CON_LHS_AXI_P_MFC_QCH, QCH_CON_LHS_AXI_P_MIF0_QCH, QCH_CON_LHS_AXI_P_MIF1_QCH, QCH_CON_LHS_AXI_P_MIF2_QCH, QCH_CON_LHS_AXI_P_MIF3_QCH, QCH_CON_LHS_AXI_P_PERIC0_QCH, QCH_CON_LHS_AXI_P_PERIC1_QCH, QCH_CON_LHS_AXI_P_PERIS_QCH, QCH_CON_LHS_AXI_P_SRDZ_QCH, QCH_CON_LHS_AXI_P_VPU_QCH, QCH_CON_LHS_AXI_P_VTS_QCH, QCH_CON_MBOX_QCH, QCH_CON_PDMA0_QCH, QCH_CON_PMU_BUSC_QCH, QCH_CON_SECMBOX_QCH, QCH_CON_SPDMA_QCH, QCH_CON_SPEEDY_QCH, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_SPEEDY, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_CP, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_AP, QCH_CON_SYSREG_BUSC_QCH, QCH_CON_TREX_D_BUSC_QCH, QCH_CON_TREX_P_BUSC_QCH, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_BNS, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSISX4_DMA, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_MC_SCALER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU0, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_VRA, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_CFW_CAM, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM0, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_CSISX4, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU0, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_VRA, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM0, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM1, PLL_CON0_MUX_CLKCMU_CAM_BUS_USER, PLL_CON2_MUX_CLKCMU_CAM_BUS_USER, CLK_CON_DIV_DIV_CLK_CAM_BUSD_DIV2, PLL_CON0_MUX_CLKCMU_CAM_TPU0_USER, PLL_CON2_MUX_CLKCMU_CAM_TPU0_USER, PLL_CON0_MUX_CLKCMU_CAM_VRA_USER, PLL_CON2_MUX_CLKCMU_CAM_VRA_USER, CLK_CON_DIV_DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D0_CAM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D1_CAM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_MC_SCALER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM0, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM0, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_CSISX4, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU0, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_VRA, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU0_MCSC, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU0, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPLP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPHQ, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU0, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU0, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU0_MCSC, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_VRA, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_VRA, CLKOUT_CON_BLK_CAM_CMU_CLKOUT0, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_DIV2, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_DIV2, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_DIV2, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_DIV2, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU0, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_VRA, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_0, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU0, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_VRA, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_D_CAM0_4X1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_P_CAM_1X2, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_MC_SCALER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSISX4_DMA, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_MCSC_VRA, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPLP_CAM, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPHQ_CAM, CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU0, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_VRA, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_ACLK, CLKOUT_CON_BLK_CAM_CMU_CLKOUT1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BNS, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_BNS, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_DIV2_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU0_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_VRA_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSISX4_DMA, CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK, PLL_CON0_MUX_CLKCMU_CAM_TPU1_USER, PLL_CON2_MUX_CLKCMU_CAM_TPU1_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU1_MCSC, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU1_MCSC, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU1, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU1_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS0, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS3, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS2, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS0, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS2, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS3, CLK_CON_GAT_GOUT_BLK_CAM_UID_PMU_CAM_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_ATB_SRDZCAM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CAM_UID_ISP_EWGEN_CAM_IPCLKPORT_I_PCLK, QCH_CON_BTM_CAMD0_QCH, QCH_CON_BTM_CAMD1_QCH, QCH_CON_CAM_CMU_CAM_QCH, QCH_CON_ISP_EWGEN_CAM_QCH, QCH_CON_IS_CAM_QCH_CSIS0, QCH_CON_IS_CAM_QCH_CSIS1, QCH_CON_IS_CAM_QCH_CSIS2, QCH_CON_IS_CAM_QCH_CSIS3, QCH_CON_IS_CAM_QCH_MC_SCALER, QCH_CON_IS_CAM_QCH_CSISX4_DMA, QCH_CON_IS_CAM_QCH_SYSMMU_CAM0, QCH_CON_IS_CAM_QCH_SYSMMU_CAM1, QCH_CON_IS_CAM_QCH_BCM_CAM0, QCH_CON_IS_CAM_QCH_BCM_CAM1, QCH_CON_IS_CAM_QCH_TPU0, QCH_CON_IS_CAM_QCH_VRA, QCH_CON_IS_CAM_QCH_QE_TPU0, QCH_CON_IS_CAM_QCH_QE_VRA, QCH_CON_IS_CAM_QCH_BNS, QCH_CON_IS_CAM_QCH_QE_CSISX4, QCH_CON_IS_CAM_QCH_QE_TPU1, QCH_CON_IS_CAM_QCH_TPU1, QCH_CON_LHM_ATB_SRDZCAM_QCH, QCH_CON_LHM_AXI_P_CAM_QCH, QCH_CON_LHS_AXI_D0_CAM_QCH, QCH_CON_LHS_AXI_D1_CAM_QCH, QCH_CON_PMU_CAM_QCH, QCH_CON_SYSREG_CAM_QCH, CLK_CON_GAT_GATE_CLKCMU_APM_BUS, CLK_CON_DIV_CLKCMU_APM_BUS, CLK_CON_DIV_DIV_PLL_SHARED0_DIV2, CLK_CON_DIV_CLKCMU_G3D_SWITCH, CLK_CON_DIV_CLKCMU_PERIC0_BUS, CLK_CON_DIV_CLKCMU_PERIS_BUS, CLK_CON_DIV_CLKCMU_FSYS0_BUS, CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, CLK_CON_DIV_CLKCMU_DPU_BUS, PLL_CON0_PLL_SHARED1, PLL_LOCKTIME_PLL_SHARED1, CLK_CON_DIV_DIV_PLL_SHARED1_DIV2, CLK_CON_GAT_CLKCMU_MIF_SWITCH, CLK_CON_DIV_CLKCMU_BUS1_BUS, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, CLK_CON_DIV_CLKCMU_PERIC0_USI00, CLK_CON_DIV_CLKCMU_PERIC0_UART_DBG, CLK_CON_DIV_CLKCMU_PERIC0_USI01, CLK_CON_DIV_CLKCMU_PERIC0_USI02, CLK_CON_DIV_CLKCMU_PERIC0_USI03, CLK_CON_DIV_DIV_PLL_SHARED2_DIV2, CLK_CON_DIV_DIV_PLL_SHARED3_DIV2, CLK_CON_DIV_DIV_PLL_SHARED4_DIV2, PLL_CON0_PLL_SHARED4, PLL_LOCKTIME_PLL_SHARED4, CLK_CON_DIV_DIV_PLL_SHARED0_DIV4, CLK_CON_MUX_MUX_CLKCMU_MFC_BUS, CLK_CON_DIV_CLKCMU_MFC_BUS, CLK_CON_GAT_GATE_CLKCMU_MFC_BUS, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, CLK_CON_DIV_CLKCMU_G2D_G2D, CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDRD30, CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDRD30, CLK_CON_DIV_CLKCMU_FSYS0_USBDRD30, CLK_CON_GAT_GATE_CLKCMU_FSYS0_MMC_EMBD, CLK_CON_DIV_CLKCMU_FSYS0_MMC_EMBD, CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD, CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD, CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD, CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD, CLK_CON_DIV_CLKCMU_FSYS1_BUS, CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS, CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS, CLK_CON_GAT_GATE_CLKCMU_VPU_BUS, CLK_CON_DIV_CLKCMU_VPU_BUS, CLK_CON_MUX_MUX_CLKCMU_VPU_BUS, CLK_CON_GAT_GATE_CLKCMU_DSP_BUS, CLK_CON_DIV_CLKCMU_DSP_BUS, CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, CLK_CON_MUX_MUX_CLKCMU_PERIC0_UART_DBG, CLK_CON_GAT_GATE_CLKCMU_PERIC0_UART_DBG, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI00, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI00, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI01, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI02, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI02, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI03, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI05, CLK_CON_GAT_GATE_CLKCMU_PERIC1_UART_BT, CLK_CON_DIV_CLKCMU_PERIC1_BUS, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI04, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI04, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI05, CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, CLK_CON_DIV_CLKCMU_PERIC1_UART_BT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_UART_BT, CLK_CON_DIV_CLKCMU_PERIC1_USI05, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI06, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI06, CLK_CON_DIV_CLKCMU_PERIC1_USI06, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI07, CLK_CON_DIV_CLKCMU_PERIC1_USI07, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI08, CLK_CON_DIV_CLKCMU_PERIC1_USI08, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI09, CLK_CON_DIV_CLKCMU_PERIC1_USI09, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI10, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI10, CLK_CON_DIV_CLKCMU_PERIC1_USI10, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI11, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI11, CLK_CON_DIV_CLKCMU_PERIC1_USI11, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI12, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI12, CLK_CON_DIV_CLKCMU_PERIC1_USI12, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI13, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI13, CLK_CON_DIV_CLKCMU_PERIC1_USI13, PLL_CON0_PLL_SHARED3, PLL_LOCKTIME_PLL_SHARED3, PLL_CON0_MUX_CP2AP_MIF_CLK_USER, PLL_CON2_MUX_CP2AP_MIF_CLK_USER, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS, CLK_CON_DIV_CLKCMU_BUSC_BUS, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI08, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI07, CLK_CON_DIV_CLKCMU_PERIC1_USI04, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI03, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI01, CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, PLL_CON0_PLL_SHARED2, PLL_LOCKTIME_PLL_SHARED2, PLL_CON0_PLL_SHARED0, PLL_LOCKTIME_PLL_SHARED0, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI09, CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS, CLK_CON_MUX_MUX_CLKCMU_FSYS0_MMC_EMBD, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, CLK_CON_DIV_CLKCMU_CORE_BUS, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, CLK_CON_MUX_MUX_CLKCMU_CAM_BUS, CLK_CON_MUX_MUX_CLKCMU_CAM_TPU0, CLK_CON_MUX_MUX_CLKCMU_CAM_TPU1, CLK_CON_GAT_GATE_CLKCMU_CAM_BUS, CLK_CON_DIV_CLKCMU_CAM_BUS, CLK_CON_GAT_GATE_CLKCMU_CAM_TPU0, CLK_CON_DIV_CLKCMU_CAM_TPU0, CLK_CON_GAT_GATE_CLKCMU_CAM_TPU1, CLK_CON_DIV_CLKCMU_CAM_TPU1, CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS, CLK_CON_DIV_CLKCMU_ISPLP_BUS, CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS, CLK_CON_DIV_CLKCMU_ISPHQ_BUS, CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS, CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS, CLK_CON_GAT_GATE_CLKCMU_ABOX_CPUABOX, CLK_CON_MUX_MUX_CLKCMU_ABOX_CPUABOX, CLK_CON_DIV_CLKCMU_ABOX_CPUABOX, CLK_CON_GAT_GATE_CLKCMU_G2D_JPEG, CLK_CON_DIV_CLKCMU_G2D_JPEG, CLK_CON_MUX_MUX_CLKCMU_G2D_JPEG, CLKOUT_CON_BLK_CMU_CMU_CLKOUT0, CLK_CON_MUX_MUX_CLKCMU_HPM, CLK_CON_DIV_CLKCMU_HPM, CLK_CON_GAT_GATE_CLKCMU_HPM, CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE, CLK_CON_DIV_CLKCMU_FSYS1_PCIE, CLK_CON_MUX_MUX_CLKCMU_DBG_BUS, CLK_CON_GAT_GATE_CLKCMU_DBG_BUS, CLK_CON_DIV_CLKCMU_DBG_BUS, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM0, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM0, CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM0, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM1, CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM1, CLK_CON_GAT_CLKCMU_DROOPDETECTOR, CLK_CON_MUX_MUX_CLKCMU_DROOPDETECTOR, CLKOUT_CON_BLK_CMU_CMU_CLKOUT1, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, CLK_CON_DIV_CLKCMU_CIS_CLK0, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, CLK_CON_DIV_CLKCMU_CIS_CLK1, CLK_CON_DIV_CLKCMU_CIS_CLK2, CLK_CON_DIV_CLKCMU_CIS_CLK3, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, CLK_CON_DIV_CLKCMU_OTP, CLK_CON_MUX_MUX_CLKCMU_IVA_BUS, CLK_CON_GAT_GATE_CLKCMU_IVA_BUS, CLK_CON_DIV_CLKCMU_IVA_BUS, CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD, CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD, CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD, CLK_CON_MUX_MUX_CMU_CMUREF, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUSPHSI2C, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUSPHSI2C, CLK_CON_DIV_CLKCMU_BUSC_BUSPHSI2C, CLK_CON_DIV_CLKCMU_CAM_VRA, CLK_CON_GAT_GATE_CLKCMU_CAM_VRA, CLK_CON_MUX_MUX_CLKCMU_CAM_VRA, CLK_CON_DIV_DIV_PLL_SHARED1_DIV4, CLK_CON_DIV_CLKCMU_PERIC1_SPEEDY2, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPEEDY2, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS, CLK_CON_DIV_CLKCMU_FSYS0_DPGTC, CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1, CLK_CON_DIV_CLKCMU_MODEM_SHARED0, CLK_CON_DIV_CLKCMU_MODEM_SHARED1, CLK_CON_DIV_CLKCMU_DCAM_BUS, CLK_CON_GAT_GATE_CLKCMU_DCAM_BUS, CLK_CON_MUX_MUX_CLKCMU_DCAM_BUS, CLK_CON_GAT_GATE_CLKCMU_IMEM_BUS, CLK_CON_DIV_CLKCMU_IMEM_BUS, CLK_CON_MUX_MUX_CLKCMU_IMEM_BUS, CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC, CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE, CLK_CON_DIV_DIV_CLK_CMU_CMUREF, CLK_CON_DIV_CLKCMU_SRDZ_IMGD, CLK_CON_GAT_GATE_CLKCMU_SRDZ_IMGD, CLK_CON_MUX_MUX_CLKCMU_SRDZ_BUS, CLK_CON_MUX_MUX_CLKCMU_SRDZ_IMGD, CLK_CON_DIV_CLKCMU_SRDZ_BUS, CLK_CON_GAT_GATE_CLKCMU_SRDZ_BUS, CLK_CON_DIV_CLKCMU_DCAM_IMGD, CLK_CON_GAT_GATE_CLKCMU_DCAM_IMGD, CLK_CON_MUX_MUX_CLKCMU_DCAM_IMGD, CLK_CON_DIV_DIV_CP2AP_MIF_CLK_DIV2, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPEEDY2, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS, CLK_CON_MUX_MUX_CLK_CMU_CMUREF, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, DMYQCH_CON_CMU_CMU_CMUREF_QCH, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3, CLK_CON_DIV_DIV_CLK_CORE_BUSP, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_PMU_CORE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_CLK, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, PLL_CON2_MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_CPACE_D_CPUCL0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF2_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF3_IPCLKPORT_I_CLK, CLKOUT_CON_BLK_CORE_CMU_CLKOUT0, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK, CLKOUT_CON_BLK_CORE_CMU_CLKOUT1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G0_DMC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G1_DMC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G2_DMC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G3_DMC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_APBBR_CCI_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DBG_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_IMEM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C, CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK, QCH_CON_APBBR_CCI_QCH, QCH_CON_BDU_QCH, QCH_CON_BUSIF_HPMCORE_QCH, DMYQCH_CON_CCI_QCH, QCH_CON_CORE_CMU_CORE_QCH, QCH_CON_LHM_ACE_D0_G3D_QCH, QCH_CON_LHM_ACE_D1_G3D_QCH, QCH_CON_LHM_ACE_D2_G3D_QCH, QCH_CON_LHM_ACE_D3_G3D_QCH, QCH_CON_LHM_ACE_D_CPUCL1_QCH, QCH_CON_LHM_AXI_D_CP_QCH, QCH_CON_LHM_AXI_P_CP_QCH, QCH_CON_LHS_ATB_T_BDU_QCH, QCH_CON_LHS_AXI_P_CPUCL0_QCH, QCH_CON_LHS_AXI_P_CPUCL1_QCH, QCH_CON_LHS_AXI_P_DBG_QCH, QCH_CON_LHS_AXI_P_G3D_QCH, QCH_CON_LHS_AXI_P_IMEM_QCH, QCH_CON_PMU_CORE_QCH, QCH_CON_PPCFW_G3D_QCH, QCH_CON_BCM_CPUCL0_QCH, QCH_CON_BCM_CPUCL1_QCH, QCH_CON_BCM_G3D0_QCH, QCH_CON_BCM_G3D1_QCH, QCH_CON_BCM_G3D2_QCH, QCH_CON_BCM_G3D3_QCH, QCH_CON_SYSREG_CORE_QCH, QCH_CON_TREX_D_CORE_QCH, QCH_CON_TREX_P0_CORE_QCH, QCH_CON_TREX_P1_CORE_QCH, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF, PLL_CON0_PLL_CPUCL0, PLL_LOCKTIME_PLL_CPUCL0, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DROOPDETECTOR_CPUCL0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT0, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP0_IPCLKPORT_CK_IN, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP1_IPCLKPORT_CK_IN, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT1, CLK_CON_GAT_GATE_CLK_CPUCL0_CPU, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLKDBG, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT0, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT1, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP0, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP1, QCH_CON_BUSIF_HPMCPUCL0_QCH, DMYQCH_CON_CLUSTER0_QCH, QCH_CON_CLUSTER0_QCH_LHS_ATB_T0_CLUSTER0, QCH_CON_CLUSTER0_QCH_LHS_ATB_T1_CLUSTER0, QCH_CON_CLUSTER0_QCH_LHS_ATB_T2_CLUSTER0, QCH_CON_CLUSTER0_QCH_LHS_ATB_T3_CLUSTER0, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH, QCH_CON_CPUCL0_CMU_CPUCL0_QCH, QCH_CON_LHM_AXI_P_CPUCL0_QCH, QCH_CON_PMU_CPUCL0_QCH, QCH_CON_SYSREG_CPUCL0_QCH, PLL_CON0_PLL_CPUCL1, PLL_LOCKTIME_PLL_CPUCL1, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_PMU_CPUCL1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT0, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT1, CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG, CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK, CLK_CON_GAT_GATE_CLK_CPUCL1_CPU, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT0, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT1, QCH_CON_BUSIF_HPMCPUCL1_QCH, DMYQCH_CON_CLUSTER1_QCH_CPU, DMYQCH_CON_CLUSTER1_QCH_DBG, QCH_CON_CLUSTER1_QCH_LHS_ACE_D_CPUCL1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH, QCH_CON_CPUCL1_CMU_CPUCL1_QCH, QCH_CON_LHM_AXI_P_CPUCL1_QCH, QCH_CON_PMU_CPUCL1_QCH, QCH_CON_SYSREG_CPUCL1_QCH, CLK_CON_DIV_DIV_CLK_DBG_PCLKDBG, CLK_CON_GAT_CLK_BLK_DBG_UID_DBG_CMU_DBG_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_AXI_P_DBG_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DBG_UID_AXI2APB_CORESIGHT_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_ATCLK, CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_ATCLK, CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_PCLKDBG, CLK_CON_GAT_GOUT_BLK_DBG_UID_SECJTAG_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DBG_UID_PMU_DBG_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DBG_UID_SYSREG_DBG_IPCLKPORT_PCLK, CLKOUT_CON_BLK_DBG_CMU_CLKOUT0, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK, CLKOUT_CON_BLK_DBG_CMU_CLKOUT1, PLL_CON0_MUX_CLKCMU_DBG_BUS_USER, PLL_CON2_MUX_CLKCMU_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_ATCLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_PCLKDBG_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL0_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL1_IPCLKPORT_I_PCLK, QCH_CON_CSSYS_QCH, QCH_CON_DBG_CMU_DBG_QCH, QCH_CON_DUMPPC_CPUCL0_QCH, QCH_CON_DUMPPC_CPUCL1_QCH, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH, QCH_CON_LHM_ATB_T0_CLUSTER1_QCH, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH, QCH_CON_LHM_ATB_T1_CLUSTER1_QCH, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH, QCH_CON_LHM_ATB_T2_CLUSTER1_QCH, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH, QCH_CON_LHM_ATB_T3_CLUSTER1_QCH, QCH_CON_LHM_ATB_T_AUD_QCH, QCH_CON_LHM_ATB_T_BDU_QCH, QCH_CON_LHM_AXI_P_DBG_QCH, QCH_CON_LHS_AXI_G_CSSYS_QCH, QCH_CON_LHS_AXI_G_ETR_QCH, QCH_CON_PMU_DBG_QCH, QCH_CON_SECJTAG_QCH, QCH_CON_STM_TXACTOR_QCH, QCH_CON_SYSREG_DBG_QCH, CLK_CON_DIV_DIV_CLK_DCAM_BUSP, PLL_CON0_MUX_CLKCMU_DCAM_BUS_USER, PLL_CON2_MUX_CLKCMU_DCAM_BUS_USER, CLK_CON_GAT_CLK_BLK_DCAM_UID_DCAM_CMU_DCAM_IPCLKPORT_PCLK, CLKOUT_CON_BLK_DCAM_CMU_CLKOUT0, CLKOUT_CON_BLK_DCAM_CMU_CLKOUT1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_DCP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PMU_DCAM_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DCAM_UID_SYSREG_DCAM_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_SYS_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_DCAM_UID_XIU_P_DCAM_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHM_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBM_DCAM_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSP_IPCLKPORT_CLK, PLL_CON0_MUX_CLKCMU_DCAM_IMGD_USER, PLL_CON2_MUX_CLKCMU_DCAM_IMGD_USER, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBS_DCAM_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_ATB_DCAMSRDZ_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_IMGD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_PCLK, QCH_CON_BTM_DCAM_QCH, QCH_CON_DCAM_CMU_DCAM_QCH, QCH_CON_DCP_QCH, QCH_CON_LHM_AXI_P_SRDZDCAM_QCH, QCH_CON_LHS_ATB_DCAMSRDZ_QCH, QCH_CON_LHS_AXI_D_DCAMSRDZ_QCH, QCH_CON_PMU_DCAM_QCH, QCH_CON_BCM_DCAM_QCH, QCH_CON_SYSREG_DCAM_QCH, PLL_CON0_MUX_CLKCMU_DPU_BUS_USER, PLL_CON2_MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_CLKCMU_DPU1_BUSD, CLK_CON_DIV_DIV_CLK_DPU0_BUSP, CLK_CON_GAT_CLKCMU_DPU1_BUSP, CLK_CON_GAT_CLK_BLK_DPU0_UID_DPU0_CMU_DPU0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DECON0_IPCLKPORT_ACLK, CLKOUT_CON_BLK_DPU0_CMU_CLKOUT0, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_PMU_DPU0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSREG_DPU0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_SECURE, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_NONSECURE, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_SECURE, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_NONSECURE, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHM_AXI_P0_DPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_XIU_P0_DPU_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_VGR_ACLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G0_ACLK, CLKOUT_CON_BLK_DPU0_CMU_CLKOUT1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G1_ACLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_WB_MUX_IPCLKPORT_DPP_G1_ACLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH0, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH2, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_WB, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH_INTF, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_SFR, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D_USBTV_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_SECURE, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_NONSECURE, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSP_IPCLKPORT_CLK, QCH_CON_BTM_DPUD0_QCH, QCH_CON_BTM_DPUD1_QCH, QCH_CON_BTM_DPUD2_QCH, QCH_CON_DECON0_QCH, QCH_CON_DPP_QCH_DPP_G0, QCH_CON_DPP_QCH_DPP_G1, QCH_CON_DPP_QCH_DPP_VGR, QCH_CON_DPU0_CMU_DPU0_QCH, QCH_CON_DPU_DMA_QCH, QCH_CON_DPU_WB_MUX_QCH, QCH_CON_LHM_AXI_P0_DPU_QCH, QCH_CON_LHS_AXI_D0_DPU_QCH, QCH_CON_LHS_AXI_D1_DPU_QCH, QCH_CON_LHS_AXI_D2_DPU_QCH, QCH_CON_LHS_AXI_D_USBTV_QCH, QCH_CON_PMU_DPU0_QCH, QCH_CON_BCM_DPUD0_QCH, QCH_CON_BCM_DPUD1_QCH, QCH_CON_BCM_DPUD2_QCH, QCH_CON_SYSMMU_DPUD0_QCH, QCH_CON_SYSMMU_DPUD1_QCH, QCH_CON_SYSMMU_DPUD2_QCH, QCH_CON_SYSREG_DPU0_QCH, PLL_CON0_MUX_CLKCMU_DPU1_BUSD_USER, PLL_CON2_MUX_CLKCMU_DPU1_BUSD_USER, PLL_CON0_MUX_CLKCMU_DPU1_BUSP_USER, PLL_CON2_MUX_CLKCMU_DPU1_BUSP_USER, CLK_CON_GAT_CLK_BLK_DPU1_UID_DPU1_CMU_DPU1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_ACLK, CLKOUT_CON_BLK_DPU1_CMU_CLKOUT0, CLK_CON_GAT_GOUT_BLK_DPU1_UID_SYSREG_DPU1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DPU1_UID_PMU_DPU1_IPCLKPORT_PCLK, PLL_CON0_PLL_DPU, PLL_LOCKTIME_PLL_DPU, CLK_CON_DIV_DIV_CLKCMU_DPU1_DECON2, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AXI2APB_DPU1P0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DPU1_UID_LHM_AXI_P_DPU1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKM, CLKOUT_CON_BLK_DPU1_CMU_CLKOUT1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_DECON2_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_VCLK, QCH_CON_DECON1_QCH, QCH_CON_DECON2_QCH_ACLK, QCH_CON_DECON2_QCH_VCLK, QCH_CON_DPU1_CMU_DPU1_QCH, QCH_CON_LHM_AXI_P_DPU1_QCH, QCH_CON_LHS_ATB_DPTX_QCH, QCH_CON_PMU_DPU1_QCH, QCH_CON_SYSREG_DPU1_QCH, CLK_CON_DIV_DIV_CLK_DSP_BUSP, PLL_CON0_MUX_CLKCMU_DSP_BUS_USER, PLL_CON2_MUX_CLKCMU_DSP_BUS_USER, CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DSP_UID_SCORE_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DSP_UID_PMU_DSP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DSP_UID_AXI2APB_DSP_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_NONSECURE, CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_DSP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_SECURE, CLKOUT_CON_BLK_DSP_CMU_CLKOUT0, CLKOUT_CON_BLK_DSP_CMU_CLKOUT1, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_ACEL_D_DSP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_P_DSP_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_IVADSP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_VPUDSP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_IVADSP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPIVA_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPVPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DSP_UID_WRAP2_CONV_DSP_IPCLKPORT_I_CLK, QCH_CON_BTM_SCORE_QCH, QCH_CON_DSP_CMU_DSP_QCH, QCH_CON_LHM_AXI_D_IVADSP_QCH, QCH_CON_LHM_AXI_D_VPUDSP_QCH, QCH_CON_LHM_AXI_P_DSP_QCH, QCH_CON_LHM_AXI_P_IVADSP_QCH, QCH_CON_LHS_ACEL_D_DSP_QCH, QCH_CON_LHS_AXI_P_DSPIVA_QCH, QCH_CON_LHS_AXI_P_DSPVPU_QCH, QCH_CON_PMU_DSP_QCH, QCH_CON_BCM_SCORE_QCH, QCH_CON_SCORE_QCH, QCH_CON_SMMU_SCORE_QCH, QCH_CON_SYSREG_DSP_QCH, PLL_CON0_MUX_CLKCMU_FSYS0_UFS_EMBD_USER, PLL_CON2_MUX_CLKCMU_FSYS0_UFS_EMBD_USER, PLL_CON0_MUX_CLKCMU_FSYS0_MMC_EMBD_USER, PLL_CON2_MUX_CLKCMU_FSYS0_MMC_EMBD_USER, PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER, PLL_CON2_MUX_CLKCMU_FSYS0_BUS_USER, PLL_CON0_MUX_CLKCMU_FSYS0_USBDRD30_USER, PLL_CON2_MUX_CLKCMU_FSYS0_USBDRD30_USER, CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHS_ACEL_D_FSYS0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AHBBR_FSYS0_IPCLKPORT_HCLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_G_ETR_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_P_FSYS0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_D_USBTV_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_US_D_FSYS0_USB_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_FSYS0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_USB_FSYS0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2APB_FSYS0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_GPIO_FSYS0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_SDCLKIN, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PMU_FSYS0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_SYSREG_FSYS0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_USB_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_P_FSYS0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_CORE_CLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_SUSPEND_CLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_REF_CLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_ACLK, CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT0, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_AHB_CLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_XIU_CLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_ACLK, CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_RSTNSYNC_CLK_FSYS0_BUS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, PLL_CON0_MUX_CLKCMU_FSYS0_DPGTC_USER, PLL_CON2_MUX_CLKCMU_FSYS0_DPGTC_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_GTC_EXT_CLK, QCH_CON_BTM_FSYS0_QCH, QCH_CON_DP_LINK_QCH, QCH_CON_ETR_MIU_QCH_PCLK, QCH_CON_ETR_MIU_QCH_ACLK, QCH_CON_FSYS0_CMU_FSYS0_QCH, QCH_CON_GPIO_FSYS0_QCH, QCH_CON_LHM_AXI_D_USBTV_QCH, QCH_CON_LHM_AXI_G_ETR_QCH, QCH_CON_LHM_AXI_P_FSYS0_QCH, QCH_CON_LHS_ACEL_D_FSYS0_QCH, QCH_CON_MMC_EMBD_QCH, QCH_CON_PMU_FSYS0_QCH, QCH_CON_BCM_FSYS0_QCH, QCH_CON_SYSREG_FSYS0_QCH, QCH_CON_UFS_EMBD_QCH, QCH_CON_UFS_EMBD_QCH_FMP, QCH_CON_USBTV_QCH_USB30DRD_LINK, QCH_CON_USBTV_QCH_USBTV_HOST, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER, PLL_CON2_MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK, PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER, PLL_CON2_MUX_CLKCMU_FSYS1_MMC_CARD_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PMU_FSYS1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK, CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT0, CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_IPCLKPORT_PHY_REF_CLK_IN, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_0, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_0, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_0, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL, CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK, PLL_CON0_MUX_CLKCMU_FSYS1_PCIE_USER, PLL_CON2_MUX_CLKCMU_FSYS1_PCIE_USER, PLL_CON0_MUX_CLKCMU_FSYS1_UFS_CARD_USER, PLL_CON2_MUX_CLKCMU_FSYS1_UFS_CARD_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, QCH_CON_ADM_AHB_SSS_QCH, QCH_CON_BTM_FSYS1_QCH, QCH_CON_FSYS1_CMU_FSYS1_QCH, QCH_CON_GPIO_FSYS1_QCH, QCH_CON_LHM_AXI_P_FSYS1_QCH, QCH_CON_LHS_ACEL_D_FSYS1_QCH, QCH_CON_MMC_CARD_QCH, QCH_CON_PCIE_QCH_PCIE0_MSTR, QCH_CON_PCIE_QCH_PCIE_PCS, QCH_CON_PCIE_QCH_PCIE_PHY, QCH_CON_PCIE_QCH_PCIE0_DBI, QCH_CON_PCIE_QCH_PCIE0_APB, DMYQCH_CON_PCIE_QCH_PCIE_SOCPLL, QCH_CON_PCIE_QCH_PCIE1_MSTR, QCH_CON_PCIE_QCH_PCIE1_DBI, QCH_CON_PCIE_QCH_PCIE1_APB, QCH_CON_PMU_FSYS1_QCH, QCH_CON_BCM_FSYS1_QCH, QCH_CON_RTIC_QCH, QCH_CON_SSS_QCH, QCH_CON_SYSREG_FSYS1_QCH, QCH_CON_TOE_WIFI0_QCH, QCH_CON_TOE_WIFI1_QCH, QCH_CON_UFS_CARD_QCH, QCH_CON_UFS_CARD_QCH_FMP, PLL_CON0_MUX_CLKCMU_G2D_G2D_USER, PLL_CON2_MUX_CLKCMU_G2D_G2D_USER, CLK_CON_DIV_DIV_CLK_G2D_BUSP, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_NONSECURE, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D0_G2D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D1_G2D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_NONSECURE, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_PMU_G2D_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_P_G2D_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_PCLK, PLL_CON0_MUX_CLKCMU_G2D_JPEG_USER, PLL_CON2_MUX_CLKCMU_G2D_JPEG_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_M2MSCALER_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_NONSECURE, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D2_G2D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_G2D_IPCLKPORT_ACLK, CLKOUT_CON_BLK_G2D_CMU_CLKOUT0, CLKOUT_CON_BLK_G2D_CMU_CLKOUT1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_SECURE, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_SECURE, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_SECURE, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_JPEG_BUSD_IPCLKPORT_CLK, QCH_CON_BTM_G2DD0_QCH, QCH_CON_BTM_G2DD1_QCH, QCH_CON_BTM_G2DD2_QCH, QCH_CON_G2D_QCH, QCH_CON_G2D_CMU_G2D_QCH, QCH_CON_JPEG_QCH, QCH_CON_LHM_AXI_P_G2D_QCH, QCH_CON_LHS_ACEL_D0_G2D_QCH, QCH_CON_LHS_ACEL_D1_G2D_QCH, QCH_CON_LHS_ACEL_D2_G2D_QCH, QCH_CON_M2MSCALER_QCH, QCH_CON_PMU_G2D_QCH, QCH_CON_BCM_G2DD0_QCH, QCH_CON_BCM_G2DD1_QCH, QCH_CON_BCM_G2DD2_QCH, QCH_CON_QE_JPEG_QCH, QCH_CON_QE_M2MSCALER_QCH, QCH_CON_SMMU_G2DD0_QCH, QCH_CON_SMMU_G2DD1_QCH, QCH_CON_SMMU_G2DD2_QCH, QCH_CON_SYSREG_G2D_QCH, CLK_CON_DIV_DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK, CLKOUT_CON_BLK_G3D_CMU_CLKOUT0, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER, CLK_CON_MUX_MUX_CLK_G3D_BUSD, CLKOUT_CON_BLK_G3D_CMU_CLKOUT1, CLK_CON_GAT_GOUT_BLK_G3D_UID_PMU_G3D_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK, PLL_CON0_PLL_G3D, PLL_LOCKTIME_PLL_G3D, CLK_CON_GAT_GATE_CLK_G3D_AGPU, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT0, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT1, QCH_CON_AGPU_QCH_G3D, QCH_CON_AGPU_QCH_LHM_AXI_G3DSFR, QCH_CON_AGPU_QCH_LHS_ACE_D0_G3D, QCH_CON_AGPU_QCH_LHS_ACE_D1_G3D, QCH_CON_AGPU_QCH_LHS_ACE_D2_G3D, QCH_CON_AGPU_QCH_LHS_ACE_D3_G3D, QCH_CON_BUSIF_HPMG3D_QCH, QCH_CON_G3D_CMU_G3D_QCH, QCH_CON_LHM_AXI_P_G3D_QCH, QCH_CON_LHS_AXI_G3DSFR_QCH, QCH_CON_PMU_G3D_QCH, QCH_CON_SYSREG_G3D_QCH, PLL_CON0_MUX_CLKCMU_IMEM_BUS_USER, PLL_CON2_MUX_CLKCMU_IMEM_BUS_USER, CLK_CON_GAT_GOUT_BLK_IMEM_UID_LHM_AXI_P_IMEM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_IMEM_UID_RSTNSYNC_CLK_IMEM_BUS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_IMEM_UID_AXI2APB_IMEM_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_IMEM_UID_XIU_P_IMEM_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_IMEM_UID_SYSREG_IMEM_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_IMEM_UID_PMU_IMEM_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_IMEM_UID_IMEM_CMU_IMEM_IPCLKPORT_PCLK, CLKOUT_CON_BLK_IMEM_CMU_CLKOUT0, CLKOUT_CON_BLK_IMEM_CMU_CLKOUT1, CLK_CON_GAT_GOUT_BLK_IMEM_UID_INTMEM_IPCLKPORT_ACLK, QCH_CON_IMEM_CMU_IMEM_QCH, QCH_CON_INTMEM_QCH, QCH_CON_LHM_AXI_P_IMEM_QCH, QCH_CON_PMU_IMEM_QCH, QCH_CON_SYSREG_IMEM_QCH, PLL_CON0_MUX_CLKCMU_ISPHQ_BUS_USER, PLL_CON2_MUX_CLKCMU_ISPHQ_BUS_USER, CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_TAA_ACLK, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHM_AXI_P_ISPHQ_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHS_AXI_LD_ISPHQ_IPCLKPORT_I_CLK, CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT0, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_ISPHQ_ACLK, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_ACLK, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_ACLK, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_XIU_D_ISPHQ_ACLK, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_AXI2APB_BRIDGE_ISPHQ_ACLK, CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKM, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKM, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKS, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKS, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_PCLK, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_PCLK, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_PMU_ISPHQ_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_SYSREG_ISPHQ_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_ISPHQ_UID_ISPHQ_CMU_ISPHQ_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_ISP_EWGEN_ISPHQ_IPCLKPORT_I_PCLK, QCH_CON_ISPHQ_CMU_ISPHQ_QCH, QCH_CON_ISP_EWGEN_ISPHQ_QCH, QCH_CON_IS_ISPHQ_QCH_3AA, QCH_CON_IS_ISPHQ_QCH_ISPHQ, QCH_CON_IS_ISPHQ_QCH_QE_3AA, QCH_CON_IS_ISPHQ_QCH_QE_ISPHQ, QCH_CON_LHM_AXI_P_ISPHQ_QCH, QCH_CON_LHS_AXI_LD_ISPHQ_QCH, QCH_CON_PMU_ISPHQ_QCH, QCH_CON_SYSREG_ISPHQ_QCH, PLL_CON0_MUX_CLKCMU_ISPLP_BUS_USER, PLL_CON2_MUX_CLKCMU_ISPLP_BUS_USER, CLK_CON_DIV_DIV_CLK_ISPLP_BUSP, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_TAAW_ACLK, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_P_ISPLP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHS_AXI_D_ISPLP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_ACLK, CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT0, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_ISPLP_ACLK, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_ACLK, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_XIU_D_ISPLP_ACLK, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_ACLK, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_ACLK, CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKM, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKM, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKS, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKS, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_PCLK, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_PCLK, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_PCLK, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_NONSECURE, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_SECURE, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_PMU_ISPLP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_SYSREG_ISPLP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_AXI2APB_BRIDGE_ISPLP_ACLK, CLK_CON_GAT_CLK_BLK_ISPLP_UID_ISPLP_CMU_ISPLP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_LD_ISPHQ_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_ISP_EWGEN_ISPLP_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_ACLK, QCH_CON_BTM_ISPLP_QCH, QCH_CON_ISPLP_CMU_ISPLP_QCH, QCH_CON_ISP_EWGEN_ISPLP_QCH, QCH_CON_IS_ISPLP_QCH_3AAW, QCH_CON_IS_ISPLP_QCH_ISPLP, QCH_CON_IS_ISPLP_QCH_QE_3AAW, QCH_CON_IS_ISPLP_QCH_QE_ISPLP, QCH_CON_IS_ISPLP_QCH_SMMU_ISPLP, QCH_CON_IS_ISPLP_QCH_BCM_ISPLP, QCH_CON_LHM_AXI_LD_ISPHQ_QCH, QCH_CON_LHM_AXI_P_ISPLP_QCH, QCH_CON_LHS_AXI_D_ISPLP_QCH, QCH_CON_PMU_ISPLP_QCH, QCH_CON_SYSREG_ISPLP_QCH, PLL_CON0_MUX_CLKCMU_IVA_BUS_USER, PLL_CON2_MUX_CLKCMU_IVA_BUS_USER, CLK_CON_DIV_DIV_CLK_IVA_BUSP, CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK, CLKOUT_CON_BLK_IVA_CMU_CLKOUT0, CLKOUT_CON_BLK_IVA_CMU_CLKOUT1, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_ACEL_D_IVA_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_D_IVADSP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_P_IVADSP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_DSPIVA_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_D_IVA_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_IVA_UID_PMU_IVA_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_CLK_A, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_INTMEM_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_D_IVASC_IPCLKPORT_I_CLK, QCH_CON_BTM_IVA_QCH, QCH_CON_IVA_QCH, QCH_CON_IVA_CMU_IVA_QCH, QCH_CON_IVA_INTMEM_QCH, QCH_CON_LHM_AXI_D_IVASC_QCH, QCH_CON_LHM_AXI_P_DSPIVA_QCH, QCH_CON_LHM_AXI_P_IVA_QCH, QCH_CON_LHS_ACEL_D_IVA_QCH, QCH_CON_LHS_AXI_D_IVADSP_QCH, QCH_CON_LHS_AXI_P_IVADSP_QCH, QCH_CON_PMU_IVA_QCH, QCH_CON_BCM_IVA_QCH, QCH_CON_SMMU_IVA_QCH, QCH_CON_SYSREG_IVA_QCH, PLL_CON0_MUX_CLKCMU_MFC_BUS_USER, PLL_CON2_MUX_CLKCMU_MFC_BUS_USER, CLK_CON_DIV_DIV_CLK_MFC_BUSP, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_MFC_UID_AXI2APB_MFC_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_PMU_MFC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D0_MFC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D1_MFC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_SECURE, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_SECURE, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK, CLKOUT_CON_BLK_MFC_CMU_CLKOUT0, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_NONSECURE, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_NONSECURE, CLKOUT_CON_BLK_MFC_CMU_CLKOUT1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK, QCH_CON_BTM_MFCD0_QCH, QCH_CON_BTM_MFCD1_QCH, QCH_CON_LHM_AXI_P_MFC_QCH, QCH_CON_LHS_AXI_D0_MFC_QCH, QCH_CON_LHS_AXI_D1_MFC_QCH, QCH_CON_MFC_QCH, QCH_CON_MFC_CMU_MFC_QCH, QCH_CON_PMU_MFC_QCH, QCH_CON_BCM_MFCD0_QCH, QCH_CON_BCM_MFCD1_QCH, QCH_CON_SMMU_MFCD0_QCH, QCH_CON_SMMU_MFCD1_QCH, QCH_CON_SYSREG_MFC_QCH, PLL_CON0_PLL_MIF, PLL_LOCKTIME_PLL_MIF, CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X, CLK_CON_DIV_CLK_MIF_BUSD, CLK_CON_DIV_DIV_CLK_MIF_PRE, CLK_CON_DIV_DIV_CLK_MIF_BUSP, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_PMU_MIF_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_MIF_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMCTZ_IPCLKPORT_PCLK, CLKOUT_CON_BLK_MIF_CMU_CLKOUT0, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK2, CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_SOC_CLK, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_PSCDC_D_MIF_IPCLKPORT_I_CLK, CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_ACLK, CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_CLK, CLKOUT_CON_BLK_MIF_CMU_CLKOUT1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK, CLK_CON_MUX_MUX_MIF_CMUREF, QCH_CON_APBBR_DDRPHY_QCH, QCH_CON_APBBR_DMC_QCH, QCH_CON_APBBR_DMCTZ_QCH, QCH_CON_BUSIF_HPMMIF_QCH, DMYQCH_CON_CMU_MIF_CMUREF_QCH, QCH_CON_DDRPHY_QCH, QCH_CON_DMC_QCH, QCH_CON_LHM_AXI_P_MIF_QCH, QCH_CON_MIF_CMU_MIF_QCH, QCH_CON_PMU_MIF_QCH, QCH_CON_BCMPPC_DEBUG_QCH, QCH_CON_BCMPPC_DVFS_QCH, QCH_CON_SYSREG_MIF_QCH, CLKOUT_CON_BLK_MIF1_CMU_CLKOUT0, CLKOUT_CON_BLK_MIF1_CMU_CLKOUT1, CLK_CON_MUX_MUX_MIF1_CMUREF, CLK_CON_DIV_DIV_CLK_MIF1_PRE, CLK_CON_DIV_CLK_MIF1_BUSD, PLL_CON0_PLL_MIF1, PLL_LOCKTIME_PLL_MIF1, CLK_CON_MUX_CLKMUX_MIF1_DDRPHY2X, CLK_CON_DIV_DIV_CLK_MIF1_BUSP, CLK_CON_GAT_CLK_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C, CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DDRPHY1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMC1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMCTZ1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF1_UID_AXI2APB_MIF1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DDRPHY1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK2, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_P_MIF1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MIF1_UID_PMU_MIF1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF1_UID_SYSREG_MIF1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSP1_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_MIF1_UID_DMC1_IPCLKPORT_SOC_CLK, CLK_CON_GAT_CLK_BLK_MIF1_UID_LHM_PSCDC_D_MIF1_IPCLKPORT_I_CLK, CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_ACLK, CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSD1_IPCLKPORT_CLK, QCH_CON_APBBR_DDRPHY1_QCH, QCH_CON_APBBR_DMC1_QCH, QCH_CON_APBBR_DMCTZ1_QCH, QCH_CON_BUSIF_HPMMIF1_QCH, DMYQCH_CON_CMU_MIF1_CMUREF_QCH, QCH_CON_DDRPHY1_QCH, QCH_CON_DMC1_QCH, QCH_CON_LHM_AXI_P_MIF1_QCH, QCH_CON_MIF1_CMU_MIF1_QCH, QCH_CON_PMU_MIF1_QCH, QCH_CON_BCMPPC_DEBUG1_QCH, QCH_CON_BCMPPC_DVFS1_QCH, QCH_CON_SYSREG_MIF1_QCH, CLKOUT_CON_BLK_MIF2_CMU_CLKOUT0, CLKOUT_CON_BLK_MIF2_CMU_CLKOUT1, CLK_CON_MUX_MUX_MIF2_CMUREF, CLK_CON_DIV_DIV_CLK_MIF2_PRE, CLK_CON_DIV_CLK_MIF2_BUSD, PLL_CON0_PLL_MIF2, PLL_LOCKTIME_PLL_MIF2, CLK_CON_MUX_CLKMUX_MIF2_DDRPHY2X, CLK_CON_DIV_DIV_CLK_MIF2_BUSP, CLK_CON_GAT_CLK_BLK_MIF2_UID_MIF2_CMU_MIF2_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_MIF2_UID_HPM_MIF2_IPCLKPORT_HPM_TARGETCLK_C, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DDRPHY2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMC2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMCTZ2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF2_UID_AXI2APB_MIF2_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BUSIF_HPMMIF2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DDRPHY2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK2, CLK_CON_GAT_GOUT_BLK_MIF2_UID_LHM_AXI_P_MIF2_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MIF2_UID_PMU_MIF2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSP2_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MIF2_UID_SYSREG_MIF2_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_MIF2_UID_DMC2_IPCLKPORT_SOC_CLK, CLK_CON_GAT_CLK_BLK_MIF2_UID_LHM_PSCDC_D_MIF2_IPCLKPORT_I_CLK, CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_ACLK, CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSD2_IPCLKPORT_CLK, QCH_CON_APBBR_DDRPHY2_QCH, QCH_CON_APBBR_DMC2_QCH, QCH_CON_APBBR_DMCTZ2_QCH, QCH_CON_BUSIF_HPMMIF2_QCH, DMYQCH_CON_CMU_MIF2_CMUREF_QCH, QCH_CON_DDRPHY2_QCH, QCH_CON_DMC2_QCH, QCH_CON_LHM_AXI_P_MIF2_QCH, QCH_CON_MIF2_CMU_MIF2_QCH, QCH_CON_PMU_MIF2_QCH, QCH_CON_BCMPPC_DEBUG2_QCH, QCH_CON_BCMPPC_DVFS2_QCH, QCH_CON_SYSREG_MIF2_QCH, CLKOUT_CON_BLK_MIF3_CMU_CLKOUT0, CLKOUT_CON_BLK_MIF3_CMU_CLKOUT1, CLK_CON_MUX_MUX_MIF3_CMUREF, CLK_CON_DIV_DIV_CLK_MIF3_PRE, CLK_CON_DIV_CLK_MIF3_BUSD, PLL_CON0_PLL_MIF3, PLL_LOCKTIME_PLL_MIF3, CLK_CON_MUX_CLKMUX_MIF3_DDRPHY2X, CLK_CON_DIV_DIV_CLK_MIF3_BUSP, CLK_CON_GAT_CLK_BLK_MIF3_UID_HPM_MIF3_IPCLKPORT_HPM_TARGETCLK_C, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DDRPHY3_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMC3_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMCTZ3_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF3_UID_AXI2APB_MIF3_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BUSIF_HPMMIF3_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DDRPHY3_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_LHM_AXI_P_MIF3_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MIF3_UID_PMU_MIF3_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSP3_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MIF3_UID_SYSREG_MIF3_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK2, CLK_CON_GAT_CLK_BLK_MIF3_UID_MIF3_CMU_MIF3_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_MIF3_UID_DMC3_IPCLKPORT_SOC_CLK, CLK_CON_GAT_CLK_BLK_MIF3_UID_LHM_PSCDC_D_MIF3_IPCLKPORT_I_CLK, CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_ACLK, CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSD3_IPCLKPORT_CLK, QCH_CON_APBBR_DDRPHY3_QCH, QCH_CON_APBBR_DMC3_QCH, QCH_CON_APBBR_DMCTZ3_QCH, QCH_CON_BUSIF_HPMMIF3_QCH, DMYQCH_CON_CMU_MIF3_CMUREF_QCH, QCH_CON_DDRPHY3_QCH, QCH_CON_DMC3_QCH, QCH_CON_LHM_AXI_P_MIF3_QCH, QCH_CON_MIF3_CMU_MIF3_QCH, QCH_CON_PMU_MIF3_QCH, QCH_CON_BCMPPC_DEBUG3_QCH, QCH_CON_BCMPPC_DVFS3_QCH, QCH_CON_SYSREG_MIF3_QCH, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, PLL_CON2_MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PMU_PERIC0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK, PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG_USER, PLL_CON2_MUX_CLKCMU_PERIC0_UART_DBG_USER, PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USER, PLL_CON2_MUX_CLKCMU_PERIC0_USI00_USER, PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USER, PLL_CON2_MUX_CLKCMU_PERIC0_USI01_USER, PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USER, PLL_CON2_MUX_CLKCMU_PERIC0_USI02_USER, PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USER, PLL_CON2_MUX_CLKCMU_PERIC0_USI03_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_EXT_UCLK, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_SCLK_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_SCLK_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_SCLK_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_SCLK_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0_IPCLKPORT_ACLK, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT0, CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SPEEDY2_TSP_IPCLKPORT_CLK, QCH_CON_GPIO_PERIC0_QCH, QCH_CON_LHM_AXI_P_PERIC0_QCH, QCH_CON_PERIC0_CMU_PERIC0_QCH, QCH_CON_PMU_PERIC0_QCH, QCH_CON_PWM_QCH, QCH_CON_SPEEDY2_TSP_QCH, QCH_CON_SYSREG_PERIC0_QCH, QCH_CON_UART_DBG_QCH, QCH_CON_USI00_QCH, QCH_CON_USI01_QCH, QCH_CON_USI02_QCH, QCH_CON_USI03_QCH, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PMU_PERIC1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK, PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER, PLL_CON2_MUX_CLKCMU_PERIC1_UART_BT_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK, PLL_CON0_MUX_CLKCMU_PERIC1_USI05_USER, PLL_CON2_MUX_CLKCMU_PERIC1_USI05_USER, PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USER, PLL_CON2_MUX_CLKCMU_PERIC1_USI06_USER, PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USER, PLL_CON2_MUX_CLKCMU_PERIC1_USI07_USER, PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USER, PLL_CON2_MUX_CLKCMU_PERIC1_USI08_USER, PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USER, PLL_CON2_MUX_CLKCMU_PERIC1_USI09_USER, PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USER, PLL_CON2_MUX_CLKCMU_PERIC1_USI10_USER, PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USER, PLL_CON2_MUX_CLKCMU_PERIC1_USI11_USER, PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USER, PLL_CON2_MUX_CLKCMU_PERIC1_USI12_USER, PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USER, PLL_CON2_MUX_CLKCMU_PERIC1_USI13_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_EXT_UCLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_SCLK_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_SCLK_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_SCLK_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_SCLK_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_SCLK_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_SCLK_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_SCLK_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_SCLK_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_SCLK_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_SCLK_USI, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, PLL_CON2_MUX_CLKCMU_PERIC1_BUS_USER, PLL_CON0_MUX_CLKCMU_PERIC1_USI04_USER, PLL_CON2_MUX_CLKCMU_PERIC1_USI04_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT0, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM2_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM3_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_PCLK, PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM0_USER, PLL_CON2_MUX_CLKCMU_PERIC1_SPI_CAM0_USER, PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM1_USER, PLL_CON2_MUX_CLKCMU_PERIC1_SPI_CAM1_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_SPI_EXT_CLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_SPI_EXT_CLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM1_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM0_IPCLKPORT_IPCLK, CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_CLK, PLL_CON0_MUX_CLKCMU_PERIC1_SPEEDY2_USER, PLL_CON2_MUX_CLKCMU_PERIC1_SPEEDY2_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_SCLK, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPEEDY2_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_SCLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_SCLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP1_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP2_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P2_IPCLKPORT_ACLK, QCH_CON_GPIO_PERIC1_QCH, QCH_CON_HSI2C_CAM0_QCH, QCH_CON_HSI2C_CAM1_QCH, QCH_CON_HSI2C_CAM2_QCH, QCH_CON_HSI2C_CAM3_QCH, QCH_CON_LHM_AXI_P_PERIC1_QCH, QCH_CON_PERIC1_CMU_PERIC1_QCH, QCH_CON_PMU_PERIC1_QCH, QCH_CON_SPEEDY2_DDI_QCH, QCH_CON_SPEEDY2_DDI1_QCH, QCH_CON_SPEEDY2_DDI2_QCH, QCH_CON_SPEEDY2_TSP1_QCH, QCH_CON_SPEEDY2_TSP2_QCH, QCH_CON_SPI_CAM0_QCH, QCH_CON_SPI_CAM1_QCH, QCH_CON_SYSREG_PERIC1_QCH, QCH_CON_UART_BT_QCH, QCH_CON_USI04_QCH, QCH_CON_USI05_QCH, QCH_CON_USI06_QCH, QCH_CON_USI07_QCH, QCH_CON_USI08_QCH, QCH_CON_USI09_QCH, QCH_CON_USI10_QCH, QCH_CON_USI11_QCH, QCH_CON_USI12_QCH, QCH_CON_USI13_QCH, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_PMU_PERIS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC00_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC01_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC10_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC11_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC12_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC13_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC14_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC15_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC02_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC03_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC04_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC05_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC06_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC07_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC08_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC09_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER, PLL_CON2_MUX_CLKCMU_PERIS_BUS_USER, CLKOUT_CON_BLK_PERIS_CMU_CLKOUT0, CLKOUT_CON_BLK_PERIS_CMU_CLKOUT1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK, CLK_CON_MUX_MUX_CLK_PERIS_GIC, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK, QCH_CON_BUSIF_TMU_QCH, QCH_CON_GIC_QCH, QCH_CON_LHM_AXI_P_PERIS_QCH, QCH_CON_MCT_QCH, QCH_CON_OTP_CON_BIRA_QCH, QCH_CON_OTP_CON_TOP_QCH, QCH_CON_PERIS_CMU_PERIS_QCH, QCH_CON_PMU_PERIS_QCH, QCH_CON_SYSREG_PERIS_QCH, QCH_CON_TZPC00_QCH, QCH_CON_TZPC01_QCH, QCH_CON_TZPC02_QCH, QCH_CON_TZPC03_QCH, QCH_CON_TZPC04_QCH, QCH_CON_TZPC05_QCH, QCH_CON_TZPC06_QCH, QCH_CON_TZPC07_QCH, QCH_CON_TZPC08_QCH, QCH_CON_TZPC09_QCH, QCH_CON_TZPC10_QCH, QCH_CON_TZPC11_QCH, QCH_CON_TZPC12_QCH, QCH_CON_TZPC13_QCH, QCH_CON_TZPC14_QCH, QCH_CON_TZPC15_QCH, QCH_CON_WDT_CLUSTER0_QCH, QCH_CON_WDT_CLUSTER1_QCH, PLL_CON0_MUX_CLKCMU_SRDZ_IMGD_USER, PLL_CON2_MUX_CLKCMU_SRDZ_IMGD_USER, CLK_CON_DIV_DIV_CLK_SRDZ_BUSP, PLL_CON0_MUX_CLKCMU_SRDZ_BUS_USER, PLL_CON2_MUX_CLKCMU_SRDZ_BUS_USER, CLK_CON_GAT_CLK_BLK_SRDZ_UID_SRDZ_CMU_SRDZ_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_IMGD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SRDZ_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PMU_SRDZ_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SYSREG_SRDZ_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_SYS_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_D_SRDZ_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_P_SRDZ_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_NONSECURE, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_SECURE, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_P_SRDZ_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_D_SRDZ_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_ATB_SRDZCAM_IPCLKPORT_I_CLK, CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT0, CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_ATB_DCAMSRDZ_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBM_1TO2_SRDZ_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBS_SRDZ_IPCLKPORT_CLK, QCH_CON_BTM_SRDZ_QCH, QCH_CON_LHM_ATB_DCAMSRDZ_QCH, QCH_CON_LHM_AXI_D_DCAMSRDZ_QCH, QCH_CON_LHM_AXI_P_SRDZ_QCH, QCH_CON_LHS_ATB_SRDZCAM_QCH, QCH_CON_LHS_AXI_D_SRDZ_QCH, QCH_CON_LHS_AXI_P_SRDZDCAM_QCH, QCH_CON_PMU_SRDZ_QCH, QCH_CON_BCM_SRDZ_QCH, QCH_CON_SMMU_SRDZ_QCH, QCH_CON_SRDZ_QCH, QCH_CON_SRDZ_CMU_SRDZ_QCH, QCH_CON_SYSREG_SRDZ_QCH, CLK_CON_DIV_DIV_CLK_VPU_BUSP, PLL_CON0_MUX_CLKCMU_VPU_BUS_USER, PLL_CON2_MUX_CLKCMU_VPU_BUS_USER, CLK_CON_GAT_CLK_BLK_VPU_UID_VPU_CMU_VPU_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_HCLK, CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_VPU_UID_PMU_VPU_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VPU_UID_SYSREG_VPU_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2APB_VPU_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_P_VPU_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_NONSECURE, CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_VPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_ACEL_D_VPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_SECURE, CLKOUT_CON_BLK_VPU_CMU_CLKOUT0, CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2AHB_VPU_IPCLKPORT_ACLK, CLKOUT_CON_BLK_VPU_CMU_CLKOUT1, CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_D_VPU_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_DSPVPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_AXI_D_VPUDSP_IPCLKPORT_I_CLK, QCH_CON_BTM_VPU_QCH, QCH_CON_LHM_AXI_P_DSPVPU_QCH, QCH_CON_LHM_AXI_P_VPU_QCH, QCH_CON_LHS_ACEL_D_VPU_QCH, QCH_CON_LHS_AXI_D_VPUDSP_QCH, QCH_CON_PMU_VPU_QCH, QCH_CON_BCM_VPU_QCH, QCH_CON_SMMU_VPU_QCH, QCH_CON_SYSREG_VPU_QCH, QCH_CON_VPU_QCH, QCH_CON_VPU_CMU_VPU_QCH, CLK_CON_DIV_DIV_CLK_VTS_BUS, CLK_CON_DIV_DIV_CLK_VTS_DMICIF, CLK_CON_DIV_DIV_CLK_VTS_DMIC, CLKOUT_CON_BLK_VTS_CMU_CLKOUT0, CLKOUT_CON_BLK_VTS_CMU_CLKOUT1, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_SYS, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMICIF_IPCLKPORT_CLK, OSC_CON2_OSC_VTS, CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_CPU, CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMICIF_CLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_VTS2AP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_HCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_PCLK, CLK_CON_DIV_DIV_CLK_VTS_CMUREF, CLK_CON_MUX_MUX_CLK_VTS_CMUREF, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_DIV2_CLK, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_CLK, DMYQCH_CON_CMU_VTS_CMUREF_QCH, QCH_CON_DMIC_AHB_QCH_PCLK, DMYQCH_CON_DMIC_AHB_QCH_HCLK, QCH_CON_DMIC_IF_QCH_PCLK, DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK, QCH_CON_GPIO_VTS_QCH, QCH_CON_LHM_AXI_P_VTS_QCH, QCH_CON_LHS_AXI_D_VTS_QCH, QCH_CON_MAILBOX_VTS2AP_QCH, QCH_CON_SYSREG_VTS_QCH, QCH_CON_VTS_QCH_CPU, QCH_CON_VTS_QCH_SYS, QCH_CON_VTS_QCH_SYS_DMIC, QCH_CON_VTS_CMU_VTS_QCH, QCH_CON_WDT_VTS_QCH, /*====================The section of controller option SFR===================*/ ABOX_CMU_CONTROLLER_OPTION, APM_CMU_CONTROLLER_OPTION, BUS1_CMU_CONTROLLER_OPTION, BUSC_CMU_CONTROLLER_OPTION, CAM_CMU_CONTROLLER_OPTION, CMU_CMU_CONTROLLER_OPTION, CORE_CMU_CONTROLLER_OPTION, CPUCL0_CMU_CONTROLLER_OPTION, CPUCL1_CMU_CONTROLLER_OPTION, DBG_CMU_CONTROLLER_OPTION, DCAM_CMU_CONTROLLER_OPTION, DPU0_CMU_CONTROLLER_OPTION, DPU1_CMU_CONTROLLER_OPTION, DSP_CMU_CONTROLLER_OPTION, FSYS0_CMU_CONTROLLER_OPTION, FSYS1_CMU_CONTROLLER_OPTION, G2D_CMU_CONTROLLER_OPTION, G3D_CMU_CONTROLLER_OPTION, IMEM_CMU_CONTROLLER_OPTION, ISPHQ_CMU_CONTROLLER_OPTION, ISPLP_CMU_CONTROLLER_OPTION, IVA_CMU_CONTROLLER_OPTION, MFC_CMU_CONTROLLER_OPTION, MIF_CMU_CONTROLLER_OPTION, MIF1_CMU_CONTROLLER_OPTION, MIF2_CMU_CONTROLLER_OPTION, MIF3_CMU_CONTROLLER_OPTION, PERIC0_CMU_CONTROLLER_OPTION, PERIC1_CMU_CONTROLLER_OPTION, PERIS_CMU_CONTROLLER_OPTION, SRDZ_CMU_CONTROLLER_OPTION, VPU_CMU_CONTROLLER_OPTION, VTS_CMU_CONTROLLER_OPTION, end_of_sfr, num_of_sfr = end_of_sfr - SFR_TYPE, }; /*====================The section of SFR access===================*/ enum sfr_access_id { PLL_CON0_PLL_AUD_DIV_P = SFR_ACCESS_TYPE, PLL_CON0_PLL_AUD_DIV_M, PLL_CON0_PLL_AUD_DIV_S, PLL_CON0_PLL_AUD_ENABLE, PLL_CON0_PLL_AUD_STABLE, PLL_CON3_PLL_AUD_DIV_K, PLL_LOCKTIME_PLL_AUD_PLL_LOCK_TIME, CLK_CON_DIV_DIV_CLK_ABOX_PLL_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_PLL_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ABOX_PLL_DIVRATIO, CLK_CON_DIV_DIV_CLK_ABOX_AUDIF_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_AUDIF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ABOX_AUDIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_ABOX_CPU_ATCLK_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_CPU_ATCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ABOX_CPU_ATCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_ABOX_CPU_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_CPU_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ABOX_CPU_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_ABOX_DSIF_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_DSIF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ABOX_DSIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_ABOX_UAIF0_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_UAIF0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ABOX_UAIF0_DIVRATIO, CLK_CON_DIV_DIV_CLK_ABOX_UAIF1_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_UAIF1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ABOX_UAIF1_DIVRATIO, CLK_CON_DIV_DIV_CLK_ABOX_UAIF2_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_UAIF2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ABOX_UAIF2_DIVRATIO, CLK_CON_DIV_DIV_CLK_ABOX_UAIF3_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_UAIF3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ABOX_UAIF3_DIVRATIO, CLK_CON_MUX_MUX_CLK_ABOX_UAIF3_BUSY, CLK_CON_MUX_MUX_CLK_ABOX_UAIF3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_ABOX_UAIF3_SELECT, CLK_CON_MUX_MUX_CLK_ABOX_UAIF2_BUSY, CLK_CON_MUX_MUX_CLK_ABOX_UAIF2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_ABOX_UAIF2_SELECT, CLK_CON_MUX_MUX_CLK_ABOX_UAIF1_BUSY, CLK_CON_MUX_MUX_CLK_ABOX_UAIF1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_ABOX_UAIF1_SELECT, CLK_CON_MUX_MUX_CLK_ABOX_UAIF0_BUSY, CLK_CON_MUX_MUX_CLK_ABOX_UAIF0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_ABOX_UAIF0_SELECT, CLK_CON_GAT_CLK_BLK_ABOX_UID_ABOX_CMU_ABOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ABOX_UID_ABOX_CMU_ABOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ABOX_UID_ABOX_CMU_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_ABOX_CPUABOX_USER_BUSY, PLL_CON0_MUX_CLKCMU_ABOX_CPUABOX_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_ABOX_CPUABOX_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_ABOX_CPU_BUSY, CLK_CON_MUX_MUX_CLK_ABOX_CPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_ABOX_CPU_SELECT, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PMU_ABOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PMU_ABOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PMU_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SYSREG_ABOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SYSREG_ABOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SYSREG_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF0_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF0_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF1_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF1_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF3_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF3_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_DSIF_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_DSIF_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_DSIF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_ATB_ABOX_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_ATB_ABOX_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_ATB_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_ABOX_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_ABOX_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_ABOX_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_GPIO_ABOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_GPIO_ABOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_GPIO_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_AXI_US_32TO128_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_AXI_US_32TO128_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_AXI_US_32TO128_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_ABOX_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_ABOX_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_ABOX_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ATCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ATCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_DSIF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_DSIF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_DSIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF3_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF3_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ABOX_CPU_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_CPU_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ABOX_CPU_ACLK_DIVRATIO, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ASB_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ASB_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ASB_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ABOX_BUS_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ABOX_BUS_DIVRATIO, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ACLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ACLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_CA7_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_CA7_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_CA7_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF2_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF2_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ABOX_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ABOX_BUSP_DIVRATIO, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHM_AXI_P_ABOX_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHM_AXI_P_ABOX_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHM_AXI_P_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_WDT_ABOXCPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_WDT_ABOXCPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_WDT_ABOXCPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ABOX_DMIC_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_DMIC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ABOX_DMIC_DIVRATIO, CLK_CON_GAT_CLK_BLK_ABOX_UID_DMIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ABOX_UID_DMIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ABOX_UID_DMIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ATB_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ATB_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ATB_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_DAP_IPCLKPORT_DAPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_DAP_IPCLKPORT_DAPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_DAP_IPCLKPORT_DAPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_TREX_ABOX_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_TREX_ABOX_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_TREX_ABOX_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_WRAP2_CONV_ABOX_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_WRAP2_CONV_ABOX_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_WRAP2_CONV_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ABOX_UAIF4_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_UAIF4_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ABOX_UAIF4_DIVRATIO, CLK_CON_MUX_MUX_CLK_ABOX_UAIF4_BUSY, CLK_CON_MUX_MUX_CLK_ABOX_UAIF4_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_ABOX_UAIF4_SELECT, CLK_CON_GAT_CLK_BLK_ABOX_UID_DFTMUX_ABOX_IPCLKPORT_AUD_CODEC_MCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ABOX_UID_DFTMUX_ABOX_IPCLKPORT_AUD_CODEC_MCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ABOX_UID_DFTMUX_ABOX_IPCLKPORT_AUD_CODEC_MCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF4_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF4_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF4_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF4_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF4_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF4_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_ABOX_CMU_ABOX_QCH_ENABLE, QCH_CON_ABOX_CMU_ABOX_QCH_CLOCK_REQ, QCH_CON_ABOX_CMU_ABOX_QCH_EXPIRE_VAL, DMYQCH_CON_ABOX_TOP_QCH_ENABLE, DMYQCH_CON_ABOX_TOP_QCH_CLOCK_REQ, QCH_CON_BTM_ABOX_QCH_ENABLE, QCH_CON_BTM_ABOX_QCH_CLOCK_REQ, QCH_CON_BTM_ABOX_QCH_EXPIRE_VAL, DMYQCH_CON_DMIC_QCH_ENABLE, DMYQCH_CON_DMIC_QCH_CLOCK_REQ, QCH_CON_GPIO_ABOX_QCH_ENABLE, QCH_CON_GPIO_ABOX_QCH_CLOCK_REQ, QCH_CON_GPIO_ABOX_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_ABOX_QCH_ENABLE, QCH_CON_LHM_AXI_P_ABOX_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_ABOX_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_ABOX_QCH_ENABLE, QCH_CON_LHS_ATB_ABOX_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_ABOX_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_ABOX_QCH_ENABLE, QCH_CON_LHS_AXI_D_ABOX_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_ABOX_QCH_EXPIRE_VAL, QCH_CON_PMU_ABOX_QCH_ENABLE, QCH_CON_PMU_ABOX_QCH_CLOCK_REQ, QCH_CON_PMU_ABOX_QCH_EXPIRE_VAL, QCH_CON_BCM_ABOX_QCH_ENABLE, QCH_CON_BCM_ABOX_QCH_CLOCK_REQ, QCH_CON_BCM_ABOX_QCH_EXPIRE_VAL, QCH_CON_SMMU_ABOX_QCH_ENABLE, QCH_CON_SMMU_ABOX_QCH_CLOCK_REQ, QCH_CON_SMMU_ABOX_QCH_EXPIRE_VAL, QCH_CON_SYSREG_ABOX_QCH_ENABLE, QCH_CON_SYSREG_ABOX_QCH_CLOCK_REQ, QCH_CON_SYSREG_ABOX_QCH_EXPIRE_VAL, QCH_CON_TREX_ABOX_QCH_ENABLE, QCH_CON_TREX_ABOX_QCH_CLOCK_REQ, QCH_CON_TREX_ABOX_QCH_EXPIRE_VAL, QCH_CON_WDT_ABOXCPU_QCH_ENABLE, QCH_CON_WDT_ABOXCPU_QCH_CLOCK_REQ, QCH_CON_WDT_ABOXCPU_QCH_EXPIRE_VAL, PLL_CON0_MUX_CLKCMU_APM_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_APM_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_APM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_APM_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_APM_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_APM_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_APM_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_APM_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_APM_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_XIU_D_ALIVE_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_XIU_D_ALIVE_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_XIU_D_ALIVE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_SCAN2AXI_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SCAN2AXI_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SCAN2AXI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_APM_QCH_SYS_ENABLE, QCH_CON_APM_QCH_SYS_CLOCK_REQ, QCH_CON_APM_QCH_SYS_EXPIRE_VAL, QCH_CON_APM_QCH_CPU_ENABLE, QCH_CON_APM_QCH_CPU_CLOCK_REQ, QCH_CON_APM_QCH_CPU_EXPIRE_VAL, DMYQCH_CON_APM_QCH_OSCCLK_ENABLE, DMYQCH_CON_APM_QCH_OSCCLK_CLOCK_REQ, QCH_CON_APM_CMU_APM_QCH_ENABLE, QCH_CON_APM_CMU_APM_QCH_CLOCK_REQ, QCH_CON_APM_CMU_APM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_ALIVE_QCH_ENABLE, QCH_CON_LHM_AXI_P_ALIVE_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_ALIVE_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_ALIVE_QCH_ENABLE, QCH_CON_LHS_AXI_D_ALIVE_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_ALIVE_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM2AP_QCH_ENABLE, QCH_CON_MAILBOX_APM2AP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM2AP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM2CP_QCH_ENABLE, QCH_CON_MAILBOX_APM2CP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM2CP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM2GNSS_QCH_ENABLE, QCH_CON_MAILBOX_APM2GNSS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM2GNSS_QCH_EXPIRE_VAL, QCH_CON_SCAN2AXI_QCH_ENABLE, QCH_CON_SCAN2AXI_QCH_CLOCK_REQ, QCH_CON_SCAN2AXI_QCH_EXPIRE_VAL, QCH_CON_SYSREG_APM_QCH_ENABLE, QCH_CON_SYSREG_APM_QCH_CLOCK_REQ, QCH_CON_SYSREG_APM_QCH_EXPIRE_VAL, QCH_CON_WDT_APM_QCH_ENABLE, QCH_CON_WDT_APM_QCH_CLOCK_REQ, QCH_CON_WDT_APM_QCH_EXPIRE_VAL, CLK_CON_DIV_DIV_CLK_BUS1_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_BUS1_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_BUS1_BUSP_DIVRATIO, PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_BUS1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_FSYS1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_FSYS1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_FSYS1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_FSYS1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_FSYS1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_FSYS1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUS1_UID_PMU_BUS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_PMU_BUS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_PMU_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_BUS1_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_BUS1_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_BUS1_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_ALIVE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_ALIVE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_ALIVE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_ALIVE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_BUS1_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_BUS1_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_BUS1_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BUS1_CMU_BUS1_QCH_ENABLE, QCH_CON_BUS1_CMU_BUS1_QCH_CLOCK_REQ, QCH_CON_BUS1_CMU_BUS1_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_FSYS1_QCH_ENABLE, QCH_CON_LHM_ACEL_D_FSYS1_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_FSYS1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_ALIVE_QCH_ENABLE, QCH_CON_LHM_AXI_D_ALIVE_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_ALIVE_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_GNSS_QCH_ENABLE, QCH_CON_LHM_AXI_D_GNSS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_GNSS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_ALIVE_QCH_ENABLE, QCH_CON_LHS_AXI_P_ALIVE_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_ALIVE_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_FSYS1_QCH_ENABLE, QCH_CON_LHS_AXI_P_FSYS1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_FSYS1_QCH_EXPIRE_VAL, QCH_CON_PMU_BUS1_QCH_ENABLE, QCH_CON_PMU_BUS1_QCH_CLOCK_REQ, QCH_CON_PMU_BUS1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_BUS1_QCH_ENABLE, QCH_CON_SYSREG_BUS1_QCH_CLOCK_REQ, QCH_CON_SYSREG_BUS1_QCH_EXPIRE_VAL, QCH_CON_TREX_D_BUS1_QCH_ENABLE, QCH_CON_TREX_D_BUS1_QCH_CLOCK_REQ, QCH_CON_TREX_D_BUS1_QCH_EXPIRE_VAL, QCH_CON_TREX_P_BUS1_QCH_ENABLE, QCH_CON_TREX_P_BUS1_QCH_CLOCK_REQ, QCH_CON_TREX_P_BUS1_QCH_EXPIRE_VAL, CLK_CON_DIV_DIV_CLK_BUSC_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_BUSC_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_BUSC_BUSP_DIVRATIO, CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSC_TDP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSC_TDP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSC_TDP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_GPIO_BUSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_GPIO_BUSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_GPIO_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PMU_BUSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PMU_BUSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PMU_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SECMBOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SECMBOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SECMBOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_MBOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_MBOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_MBOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S0_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S0_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_BUSC_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_BUSC_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_BUSC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_BUSC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_BUSC_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_BUSC_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_BUSC_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_BUSC_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_BUSC_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_BUSC_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_GNSSMBOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_GNSSMBOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_GNSSMBOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_PCLK_BATCHER_SPEEDY_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_PCLK_BATCHER_SPEEDY_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_PCLK_BATCHER_SPEEDY_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_AP_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_AP_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_AP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_CP_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_CP_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_CP_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_BUSC_BUSPHSI2C_USER_BUSY, PLL_CON0_MUX_CLKCMU_BUSC_BUSPHSI2C_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_BUSC_BUSPHSI2C_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_HSI2CDF_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_HSI2CDF_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_HSI2CDF_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSPHSI2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSPHSI2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSPHSI2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SCI_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SCI_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SCI_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_D_IVASC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_D_IVASC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_D_IVASC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D0_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D0_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D0_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D1_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D1_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D1_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D2_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D2_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D2_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_DSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_DSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_DSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_FSYS0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_FSYS0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_FSYS0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_IVA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_IVA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_IVA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_VPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_VPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_VPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_CAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_CAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_CAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_CAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D2_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D2_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D2_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_SRDZ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_SRDZ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_SRDZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ISPLP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ISPLP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ISPLP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P0_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P0_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P0_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P1_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P1_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P1_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ABOX_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ABOX_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_SRDZ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_SRDZ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_SRDZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_DSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_DSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_DSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_FSYS0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_FSYS0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_FSYS0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPHQ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPHQ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPHQ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPLP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPLP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPLP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_IVA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_IVA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_IVA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_ACLK_BUSC_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_ACLK_BUSC_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_ACLK_BUSC_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_ADCIF_BUSC_QCH_S0_ENABLE, QCH_CON_ADCIF_BUSC_QCH_S0_CLOCK_REQ, QCH_CON_ADCIF_BUSC_QCH_S0_EXPIRE_VAL, QCH_CON_ADCIF_BUSC_QCH_S1_ENABLE, QCH_CON_ADCIF_BUSC_QCH_S1_CLOCK_REQ, QCH_CON_ADCIF_BUSC_QCH_S1_EXPIRE_VAL, QCH_CON_BUSC_CMU_BUSC_QCH_ENABLE, QCH_CON_BUSC_CMU_BUSC_QCH_CLOCK_REQ, QCH_CON_BUSC_CMU_BUSC_QCH_EXPIRE_VAL, QCH_CON_BUSIF_CMUTOPC_QCH_ENABLE, QCH_CON_BUSIF_CMUTOPC_QCH_CLOCK_REQ, QCH_CON_BUSIF_CMUTOPC_QCH_EXPIRE_VAL, QCH_CON_GNSSMBOX_QCH_ENABLE, QCH_CON_GNSSMBOX_QCH_CLOCK_REQ, QCH_CON_GNSSMBOX_QCH_EXPIRE_VAL, QCH_CON_GPIO_BUSC_QCH_ENABLE, QCH_CON_GPIO_BUSC_QCH_CLOCK_REQ, QCH_CON_GPIO_BUSC_QCH_EXPIRE_VAL, QCH_CON_HSI2CDF_QCH_ENABLE, QCH_CON_HSI2CDF_QCH_CLOCK_REQ, QCH_CON_HSI2CDF_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D0_G2D_QCH_ENABLE, QCH_CON_LHM_ACEL_D0_G2D_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D0_G2D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D1_G2D_QCH_ENABLE, QCH_CON_LHM_ACEL_D1_G2D_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D1_G2D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D2_G2D_QCH_ENABLE, QCH_CON_LHM_ACEL_D2_G2D_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D2_G2D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_DSP_QCH_ENABLE, QCH_CON_LHM_ACEL_D_DSP_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_DSP_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_FSYS0_QCH_ENABLE, QCH_CON_LHM_ACEL_D_FSYS0_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_FSYS0_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_IVA_QCH_ENABLE, QCH_CON_LHM_ACEL_D_IVA_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_IVA_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_VPU_QCH_ENABLE, QCH_CON_LHM_ACEL_D_VPU_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_VPU_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_CAM_QCH_ENABLE, QCH_CON_LHM_AXI_D0_CAM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_CAM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_DPU_QCH_ENABLE, QCH_CON_LHM_AXI_D0_DPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_DPU_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_MFC_QCH_ENABLE, QCH_CON_LHM_AXI_D0_MFC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_MFC_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_CAM_QCH_ENABLE, QCH_CON_LHM_AXI_D1_CAM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_CAM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_DPU_QCH_ENABLE, QCH_CON_LHM_AXI_D1_DPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_DPU_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_MFC_QCH_ENABLE, QCH_CON_LHM_AXI_D1_MFC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_MFC_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D2_DPU_QCH_ENABLE, QCH_CON_LHM_AXI_D2_DPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D2_DPU_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_ABOX_QCH_ENABLE, QCH_CON_LHM_AXI_D_ABOX_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_ABOX_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_ISPLP_QCH_ENABLE, QCH_CON_LHM_AXI_D_ISPLP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_ISPLP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_SRDZ_QCH_ENABLE, QCH_CON_LHM_AXI_D_SRDZ_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_SRDZ_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_VTS_QCH_ENABLE, QCH_CON_LHM_AXI_D_VTS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_VTS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_G_CSSYS_QCH_ENABLE, QCH_CON_LHM_AXI_G_CSSYS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_G_CSSYS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_IVASC_QCH_ENABLE, QCH_CON_LHS_AXI_D_IVASC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_IVASC_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P0_DPU_QCH_ENABLE, QCH_CON_LHS_AXI_P0_DPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P0_DPU_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P1_DPU_QCH_ENABLE, QCH_CON_LHS_AXI_P1_DPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P1_DPU_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_ABOX_QCH_ENABLE, QCH_CON_LHS_AXI_P_ABOX_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_ABOX_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_CAM_QCH_ENABLE, QCH_CON_LHS_AXI_P_CAM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_CAM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_DSP_QCH_ENABLE, QCH_CON_LHS_AXI_P_DSP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_DSP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_FSYS0_QCH_ENABLE, QCH_CON_LHS_AXI_P_FSYS0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_FSYS0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_G2D_QCH_ENABLE, QCH_CON_LHS_AXI_P_G2D_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_G2D_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_ISPHQ_QCH_ENABLE, QCH_CON_LHS_AXI_P_ISPHQ_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_ISPHQ_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_ISPLP_QCH_ENABLE, QCH_CON_LHS_AXI_P_ISPLP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_ISPLP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_IVA_QCH_ENABLE, QCH_CON_LHS_AXI_P_IVA_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_IVA_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MFC_QCH_ENABLE, QCH_CON_LHS_AXI_P_MFC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MFC_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MIF0_QCH_ENABLE, QCH_CON_LHS_AXI_P_MIF0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MIF0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MIF1_QCH_ENABLE, QCH_CON_LHS_AXI_P_MIF1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MIF1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MIF2_QCH_ENABLE, QCH_CON_LHS_AXI_P_MIF2_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MIF2_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MIF3_QCH_ENABLE, QCH_CON_LHS_AXI_P_MIF3_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MIF3_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_PERIC0_QCH_ENABLE, QCH_CON_LHS_AXI_P_PERIC0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_PERIC0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_PERIC1_QCH_ENABLE, QCH_CON_LHS_AXI_P_PERIC1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_PERIC1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_PERIS_QCH_ENABLE, QCH_CON_LHS_AXI_P_PERIS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_PERIS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_SRDZ_QCH_ENABLE, QCH_CON_LHS_AXI_P_SRDZ_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_SRDZ_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_VPU_QCH_ENABLE, QCH_CON_LHS_AXI_P_VPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_VPU_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_VTS_QCH_ENABLE, QCH_CON_LHS_AXI_P_VTS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_VTS_QCH_EXPIRE_VAL, QCH_CON_MBOX_QCH_ENABLE, QCH_CON_MBOX_QCH_CLOCK_REQ, QCH_CON_MBOX_QCH_EXPIRE_VAL, QCH_CON_PDMA0_QCH_ENABLE, QCH_CON_PDMA0_QCH_CLOCK_REQ, QCH_CON_PDMA0_QCH_EXPIRE_VAL, QCH_CON_PMU_BUSC_QCH_ENABLE, QCH_CON_PMU_BUSC_QCH_CLOCK_REQ, QCH_CON_PMU_BUSC_QCH_EXPIRE_VAL, QCH_CON_SECMBOX_QCH_ENABLE, QCH_CON_SECMBOX_QCH_CLOCK_REQ, QCH_CON_SECMBOX_QCH_EXPIRE_VAL, QCH_CON_SPDMA_QCH_ENABLE, QCH_CON_SPDMA_QCH_CLOCK_REQ, QCH_CON_SPDMA_QCH_EXPIRE_VAL, QCH_CON_SPEEDY_QCH_ENABLE, QCH_CON_SPEEDY_QCH_CLOCK_REQ, QCH_CON_SPEEDY_QCH_EXPIRE_VAL, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_SPEEDY_ENABLE, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_SPEEDY_CLOCK_REQ, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_SPEEDY_EXPIRE_VAL, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_CP_ENABLE, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_CP_CLOCK_REQ, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_CP_EXPIRE_VAL, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_AP_ENABLE, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_AP_CLOCK_REQ, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_AP_EXPIRE_VAL, QCH_CON_SYSREG_BUSC_QCH_ENABLE, QCH_CON_SYSREG_BUSC_QCH_CLOCK_REQ, QCH_CON_SYSREG_BUSC_QCH_EXPIRE_VAL, QCH_CON_TREX_D_BUSC_QCH_ENABLE, QCH_CON_TREX_D_BUSC_QCH_CLOCK_REQ, QCH_CON_TREX_D_BUSC_QCH_EXPIRE_VAL, QCH_CON_TREX_P_BUSC_QCH_ENABLE, QCH_CON_TREX_P_BUSC_QCH_CLOCK_REQ, QCH_CON_TREX_P_BUSC_QCH_EXPIRE_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_BNS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_BNS_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_BNS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSISX4_DMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSISX4_DMA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSISX4_DMA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_MC_SCALER_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_MC_SCALER_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_MC_SCALER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_VRA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_CFW_CAM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_CFW_CAM_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_CFW_CAM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_CSISX4_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_CSISX4_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_CSISX4_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_VRA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM1_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_CAM_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_CAM_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_CAM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CAM_BUSD_DIV2_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_CAM_TPU0_USER_BUSY, PLL_CON0_MUX_CLKCMU_CAM_TPU0_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_CAM_TPU0_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_CAM_VRA_USER_BUSY, PLL_CON0_MUX_CLKCMU_CAM_VRA_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_CAM_VRA_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CAM_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_CAM_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CAM_BUSP_DIVRATIO, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D0_CAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D0_CAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D0_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D1_CAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D1_CAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D1_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_MC_SCALER_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_MC_SCALER_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_MC_SCALER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_CSISX4_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_CSISX4_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_CSISX4_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_VRA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU0_MCSC_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU0_MCSC_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU0_MCSC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPLP_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPLP_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPLP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPHQ_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPHQ_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPHQ_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU0_MCSC_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU0_MCSC_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU0_MCSC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_VRA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_VRA_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_CAM_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_CAM_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_CAM_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_DIV2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_DIV2_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_DIV2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_DIV2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_DIV2_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_DIV2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_DIV2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_DIV2_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_DIV2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_DIV2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_DIV2_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_DIV2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_VRA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_VRA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_D_CAM0_4X1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_D_CAM0_4X1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_D_CAM0_4X1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_P_CAM_1X2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_P_CAM_1X2_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_P_CAM_1X2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_MC_SCALER_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_MC_SCALER_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_MC_SCALER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSISX4_DMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSISX4_DMA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSISX4_DMA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_MCSC_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_MCSC_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_MCSC_VRA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPLP_CAM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPLP_CAM_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPLP_CAM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPHQ_CAM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPHQ_CAM_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPHQ_CAM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_VRA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_CAM_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_CAM_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_CAM_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BNS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BNS_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BNS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_BNS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_BNS_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_BNS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_DIV2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_DIV2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_DIV2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_VRA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_VRA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_VRA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSISX4_DMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSISX4_DMA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSISX4_DMA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_CAM_TPU1_USER_BUSY, PLL_CON0_MUX_CLKCMU_CAM_TPU1_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_CAM_TPU1_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU1_MCSC_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU1_MCSC_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU1_MCSC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU1_MCSC_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU1_MCSC_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU1_MCSC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS3_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS3_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS2_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS2_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS3_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS3_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_PMU_CAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_PMU_CAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_PMU_CAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_ATB_SRDZCAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_ATB_SRDZCAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_ATB_SRDZCAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CAM_UID_ISP_EWGEN_CAM_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_ISP_EWGEN_CAM_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_ISP_EWGEN_CAM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BTM_CAMD0_QCH_ENABLE, QCH_CON_BTM_CAMD0_QCH_CLOCK_REQ, QCH_CON_BTM_CAMD0_QCH_EXPIRE_VAL, QCH_CON_BTM_CAMD1_QCH_ENABLE, QCH_CON_BTM_CAMD1_QCH_CLOCK_REQ, QCH_CON_BTM_CAMD1_QCH_EXPIRE_VAL, QCH_CON_CAM_CMU_CAM_QCH_ENABLE, QCH_CON_CAM_CMU_CAM_QCH_CLOCK_REQ, QCH_CON_CAM_CMU_CAM_QCH_EXPIRE_VAL, QCH_CON_ISP_EWGEN_CAM_QCH_ENABLE, QCH_CON_ISP_EWGEN_CAM_QCH_CLOCK_REQ, QCH_CON_ISP_EWGEN_CAM_QCH_EXPIRE_VAL, QCH_CON_IS_CAM_QCH_CSIS0_ENABLE, QCH_CON_IS_CAM_QCH_CSIS0_CLOCK_REQ, QCH_CON_IS_CAM_QCH_CSIS0_EXPIRE_VAL, QCH_CON_IS_CAM_QCH_CSIS1_ENABLE, QCH_CON_IS_CAM_QCH_CSIS1_CLOCK_REQ, QCH_CON_IS_CAM_QCH_CSIS1_EXPIRE_VAL, QCH_CON_IS_CAM_QCH_CSIS2_ENABLE, QCH_CON_IS_CAM_QCH_CSIS2_CLOCK_REQ, QCH_CON_IS_CAM_QCH_CSIS2_EXPIRE_VAL, QCH_CON_IS_CAM_QCH_CSIS3_ENABLE, QCH_CON_IS_CAM_QCH_CSIS3_CLOCK_REQ, QCH_CON_IS_CAM_QCH_CSIS3_EXPIRE_VAL, QCH_CON_IS_CAM_QCH_MC_SCALER_ENABLE, QCH_CON_IS_CAM_QCH_MC_SCALER_CLOCK_REQ, QCH_CON_IS_CAM_QCH_MC_SCALER_EXPIRE_VAL, QCH_CON_IS_CAM_QCH_CSISX4_DMA_ENABLE, QCH_CON_IS_CAM_QCH_CSISX4_DMA_CLOCK_REQ, QCH_CON_IS_CAM_QCH_CSISX4_DMA_EXPIRE_VAL, QCH_CON_IS_CAM_QCH_SYSMMU_CAM0_ENABLE, QCH_CON_IS_CAM_QCH_SYSMMU_CAM0_CLOCK_REQ, QCH_CON_IS_CAM_QCH_SYSMMU_CAM0_EXPIRE_VAL, QCH_CON_IS_CAM_QCH_SYSMMU_CAM1_ENABLE, QCH_CON_IS_CAM_QCH_SYSMMU_CAM1_CLOCK_REQ, QCH_CON_IS_CAM_QCH_SYSMMU_CAM1_EXPIRE_VAL, QCH_CON_IS_CAM_QCH_BCM_CAM0_ENABLE, QCH_CON_IS_CAM_QCH_BCM_CAM0_CLOCK_REQ, QCH_CON_IS_CAM_QCH_BCM_CAM0_EXPIRE_VAL, QCH_CON_IS_CAM_QCH_BCM_CAM1_ENABLE, QCH_CON_IS_CAM_QCH_BCM_CAM1_CLOCK_REQ, QCH_CON_IS_CAM_QCH_BCM_CAM1_EXPIRE_VAL, QCH_CON_IS_CAM_QCH_TPU0_ENABLE, QCH_CON_IS_CAM_QCH_TPU0_CLOCK_REQ, QCH_CON_IS_CAM_QCH_TPU0_EXPIRE_VAL, QCH_CON_IS_CAM_QCH_VRA_ENABLE, QCH_CON_IS_CAM_QCH_VRA_CLOCK_REQ, QCH_CON_IS_CAM_QCH_VRA_EXPIRE_VAL, QCH_CON_IS_CAM_QCH_QE_TPU0_ENABLE, QCH_CON_IS_CAM_QCH_QE_TPU0_CLOCK_REQ, QCH_CON_IS_CAM_QCH_QE_TPU0_EXPIRE_VAL, QCH_CON_IS_CAM_QCH_QE_VRA_ENABLE, QCH_CON_IS_CAM_QCH_QE_VRA_CLOCK_REQ, QCH_CON_IS_CAM_QCH_QE_VRA_EXPIRE_VAL, QCH_CON_IS_CAM_QCH_BNS_ENABLE, QCH_CON_IS_CAM_QCH_BNS_CLOCK_REQ, QCH_CON_IS_CAM_QCH_BNS_EXPIRE_VAL, QCH_CON_IS_CAM_QCH_QE_CSISX4_ENABLE, QCH_CON_IS_CAM_QCH_QE_CSISX4_CLOCK_REQ, QCH_CON_IS_CAM_QCH_QE_CSISX4_EXPIRE_VAL, QCH_CON_IS_CAM_QCH_QE_TPU1_ENABLE, QCH_CON_IS_CAM_QCH_QE_TPU1_CLOCK_REQ, QCH_CON_IS_CAM_QCH_QE_TPU1_EXPIRE_VAL, QCH_CON_IS_CAM_QCH_TPU1_ENABLE, QCH_CON_IS_CAM_QCH_TPU1_CLOCK_REQ, QCH_CON_IS_CAM_QCH_TPU1_EXPIRE_VAL, QCH_CON_LHM_ATB_SRDZCAM_QCH_ENABLE, QCH_CON_LHM_ATB_SRDZCAM_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_SRDZCAM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_CAM_QCH_ENABLE, QCH_CON_LHM_AXI_P_CAM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_CAM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_CAM_QCH_ENABLE, QCH_CON_LHS_AXI_D0_CAM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_CAM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_CAM_QCH_ENABLE, QCH_CON_LHS_AXI_D1_CAM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_CAM_QCH_EXPIRE_VAL, QCH_CON_PMU_CAM_QCH_ENABLE, QCH_CON_PMU_CAM_QCH_CLOCK_REQ, QCH_CON_PMU_CAM_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CAM_QCH_ENABLE, QCH_CON_SYSREG_CAM_QCH_CLOCK_REQ, QCH_CON_SYSREG_CAM_QCH_EXPIRE_VAL, CLK_CON_GAT_GATE_CLKCMU_APM_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_APM_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_APM_BUS_BUSY, CLK_CON_DIV_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_APM_BUS_DIVRATIO, CLK_CON_DIV_DIV_PLL_SHARED0_DIV2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_G3D_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_G3D_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC0_BUS_BUSY, CLK_CON_DIV_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC0_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIS_BUS_BUSY, CLK_CON_DIV_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIS_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS0_BUS_BUSY, CLK_CON_DIV_CLKCMU_FSYS0_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_FSYS0_BUS_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_SELECT, CLK_CON_DIV_CLKCMU_DPU_BUS_BUSY, CLK_CON_DIV_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_DPU_BUS_DIVRATIO, PLL_CON0_PLL_SHARED1_DIV_P, PLL_CON0_PLL_SHARED1_DIV_M, PLL_CON0_PLL_SHARED1_DIV_S, PLL_CON0_PLL_SHARED1_ENABLE, PLL_CON0_PLL_SHARED1_STABLE, PLL_LOCKTIME_PLL_SHARED1_PLL_LOCK_TIME, CLK_CON_DIV_DIV_PLL_SHARED1_DIV2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLKCMU_MIF_SWITCH_CG_VAL, CLK_CON_GAT_CLKCMU_MIF_SWITCH_MANUAL, CLK_CON_GAT_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_BUS1_BUS_BUSY, CLK_CON_DIV_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_BUS1_BUS_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_SELECT, CLK_CON_DIV_CLKCMU_PERIC0_USI00_BUSY, CLK_CON_DIV_CLKCMU_PERIC0_USI00_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC0_USI00_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC0_UART_DBG_BUSY, CLK_CON_DIV_CLKCMU_PERIC0_UART_DBG_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC0_UART_DBG_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC0_USI01_BUSY, CLK_CON_DIV_CLKCMU_PERIC0_USI01_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC0_USI01_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC0_USI02_BUSY, CLK_CON_DIV_CLKCMU_PERIC0_USI02_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC0_USI02_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC0_USI03_BUSY, CLK_CON_DIV_CLKCMU_PERIC0_USI03_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC0_USI03_DIVRATIO, CLK_CON_DIV_DIV_PLL_SHARED2_DIV2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_PLL_SHARED3_DIV2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_PLL_SHARED4_DIV2_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_PLL_SHARED4_DIV_P, PLL_CON0_PLL_SHARED4_DIV_M, PLL_CON0_PLL_SHARED4_DIV_S, PLL_CON0_PLL_SHARED4_ENABLE, PLL_CON0_PLL_SHARED4_STABLE, PLL_LOCKTIME_PLL_SHARED4_PLL_LOCK_TIME, CLK_CON_DIV_DIV_PLL_SHARED0_DIV4_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_MFC_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_MFC_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_MFC_BUS_SELECT, CLK_CON_DIV_CLKCMU_MFC_BUS_BUSY, CLK_CON_DIV_CLKCMU_MFC_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_MFC_BUS_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_MFC_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MFC_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MFC_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_G2D_G2D_BUSY, CLK_CON_DIV_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_G2D_G2D_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDRD30_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDRD30_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDRD30_SELECT, CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDRD30_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDRD30_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDRD30_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_FSYS0_USBDRD30_BUSY, CLK_CON_DIV_CLKCMU_FSYS0_USBDRD30_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_FSYS0_USBDRD30_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_FSYS0_MMC_EMBD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_MMC_EMBD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_FSYS0_MMC_EMBD_BUSY, CLK_CON_DIV_CLKCMU_FSYS0_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_FSYS0_MMC_EMBD_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD_BUSY, CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD_SELECT, CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD_BUSY, CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS1_BUS_BUSY, CLK_CON_DIV_CLKCMU_FSYS1_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_FSYS1_BUS_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_VPU_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_VPU_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_VPU_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_VPU_BUS_BUSY, CLK_CON_DIV_CLKCMU_VPU_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_VPU_BUS_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_VPU_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_VPU_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_VPU_BUS_SELECT, CLK_CON_GAT_GATE_CLKCMU_DSP_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DSP_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DSP_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_DSP_BUS_BUSY, CLK_CON_DIV_CLKCMU_DSP_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_DSP_BUS_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC0_UART_DBG_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC0_UART_DBG_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC0_UART_DBG_SELECT, CLK_CON_GAT_GATE_CLKCMU_PERIC0_UART_DBG_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_UART_DBG_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_UART_DBG_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI00_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI00_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI00_SELECT, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI00_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI00_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI00_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI01_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI01_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI01_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI02_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI02_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI02_SELECT, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI02_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI02_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI02_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI03_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI03_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI03_SELECT, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI05_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI05_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI05_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_PERIC1_UART_BT_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_UART_BT_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC1_BUS_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC1_BUS_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI04_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI04_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI04_SELECT, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI04_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI04_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI04_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI05_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI05_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI05_SELECT, CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC1_UART_BT_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC1_UART_BT_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_PERIC1_UART_BT_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC1_UART_BT_SELECT, CLK_CON_DIV_CLKCMU_PERIC1_USI05_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_USI05_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC1_USI05_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI06_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI06_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI06_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI06_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI06_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI06_SELECT, CLK_CON_DIV_CLKCMU_PERIC1_USI06_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_USI06_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC1_USI06_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI07_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI07_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI07_SELECT, CLK_CON_DIV_CLKCMU_PERIC1_USI07_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_USI07_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC1_USI07_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI08_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI08_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI08_SELECT, CLK_CON_DIV_CLKCMU_PERIC1_USI08_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_USI08_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC1_USI08_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI09_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI09_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI09_SELECT, CLK_CON_DIV_CLKCMU_PERIC1_USI09_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_USI09_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC1_USI09_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI10_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI10_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI10_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI10_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI10_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI10_SELECT, CLK_CON_DIV_CLKCMU_PERIC1_USI10_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_USI10_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC1_USI10_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI11_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI11_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI11_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI11_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI11_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI11_SELECT, CLK_CON_DIV_CLKCMU_PERIC1_USI11_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_USI11_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC1_USI11_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI12_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI12_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI12_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI12_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI12_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI12_SELECT, CLK_CON_DIV_CLKCMU_PERIC1_USI12_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_USI12_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC1_USI12_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI13_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI13_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI13_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI13_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI13_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI13_SELECT, CLK_CON_DIV_CLKCMU_PERIC1_USI13_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_USI13_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC1_USI13_DIVRATIO, PLL_CON0_PLL_SHARED3_DIV_P, PLL_CON0_PLL_SHARED3_DIV_M, PLL_CON0_PLL_SHARED3_DIV_S, PLL_CON0_PLL_SHARED3_ENABLE, PLL_CON0_PLL_SHARED3_STABLE, PLL_LOCKTIME_PLL_SHARED3_PLL_LOCK_TIME, PLL_CON0_MUX_CP2AP_MIF_CLK_USER_BUSY, PLL_CON0_MUX_CP2AP_MIF_CLK_USER_MUX_SEL, PLL_CON2_MUX_CP2AP_MIF_CLK_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_SELECT, CLK_CON_DIV_CLKCMU_BUSC_BUS_BUSY, CLK_CON_DIV_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_BUSC_BUS_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_BUSY, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_SELECT, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI08_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI08_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI08_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI07_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI07_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI07_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC1_USI04_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_USI04_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC1_USI04_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI03_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI03_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI03_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI01_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI01_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI01_SELECT, CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_PLL_SHARED2_DIV_P, PLL_CON0_PLL_SHARED2_DIV_M, PLL_CON0_PLL_SHARED2_DIV_S, PLL_CON0_PLL_SHARED2_ENABLE, PLL_CON0_PLL_SHARED2_STABLE, PLL_LOCKTIME_PLL_SHARED2_PLL_LOCK_TIME, PLL_CON0_PLL_SHARED0_DIV_P, PLL_CON0_PLL_SHARED0_DIV_M, PLL_CON0_PLL_SHARED0_DIV_S, PLL_CON0_PLL_SHARED0_ENABLE, PLL_CON0_PLL_SHARED0_STABLE, PLL_LOCKTIME_PLL_SHARED0_PLL_LOCK_TIME, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI09_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI09_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI09_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD_SELECT, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS0_MMC_EMBD_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS0_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_FSYS0_MMC_EMBD_SELECT, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_SELECT, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_CORE_BUS_BUSY, CLK_CON_DIV_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CORE_BUS_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_CAM_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CAM_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CAM_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CAM_TPU0_BUSY, CLK_CON_MUX_MUX_CLKCMU_CAM_TPU0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CAM_TPU0_SELECT, CLK_CON_MUX_MUX_CLKCMU_CAM_TPU1_BUSY, CLK_CON_MUX_MUX_CLKCMU_CAM_TPU1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CAM_TPU1_SELECT, CLK_CON_GAT_GATE_CLKCMU_CAM_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CAM_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CAM_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CAM_BUS_BUSY, CLK_CON_DIV_CLKCMU_CAM_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CAM_BUS_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_CAM_TPU0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CAM_TPU0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CAM_TPU0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CAM_TPU0_BUSY, CLK_CON_DIV_CLKCMU_CAM_TPU0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CAM_TPU0_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_CAM_TPU1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CAM_TPU1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CAM_TPU1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CAM_TPU1_BUSY, CLK_CON_DIV_CLKCMU_CAM_TPU1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CAM_TPU1_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS_SELECT, CLK_CON_DIV_CLKCMU_ISPLP_BUS_BUSY, CLK_CON_DIV_CLKCMU_ISPLP_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_ISPLP_BUS_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_ISPHQ_BUS_BUSY, CLK_CON_DIV_CLKCMU_ISPHQ_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_ISPHQ_BUS_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS_SELECT, CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_ABOX_CPUABOX_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ABOX_CPUABOX_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ABOX_CPUABOX_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_ABOX_CPUABOX_BUSY, CLK_CON_MUX_MUX_CLKCMU_ABOX_CPUABOX_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_ABOX_CPUABOX_SELECT, CLK_CON_DIV_CLKCMU_ABOX_CPUABOX_BUSY, CLK_CON_DIV_CLKCMU_ABOX_CPUABOX_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_ABOX_CPUABOX_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_G2D_JPEG_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G2D_JPEG_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G2D_JPEG_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_G2D_JPEG_BUSY, CLK_CON_DIV_CLKCMU_G2D_JPEG_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_G2D_JPEG_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_G2D_JPEG_BUSY, CLK_CON_MUX_MUX_CLKCMU_G2D_JPEG_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_G2D_JPEG_SELECT, CLKOUT_CON_BLK_CMU_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_CMU_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_CMU_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_HPM_BUSY, CLK_CON_MUX_MUX_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_HPM_SELECT, CLK_CON_DIV_CLKCMU_HPM_BUSY, CLK_CON_DIV_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_HPM_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_HPM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HPM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_FSYS1_PCIE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_DBG_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_DBG_BUS_SELECT, CLK_CON_GAT_GATE_CLKCMU_DBG_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DBG_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_DBG_BUS_BUSY, CLK_CON_DIV_CLKCMU_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_DBG_BUS_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM0_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM0_SELECT, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM0_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM0_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM1_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM1_SELECT, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM1_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM1_DIVRATIO, CLK_CON_GAT_CLKCMU_DROOPDETECTOR_CG_VAL, CLK_CON_GAT_CLKCMU_DROOPDETECTOR_MANUAL, CLK_CON_GAT_CLKCMU_DROOPDETECTOR_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_DROOPDETECTOR_BUSY, CLK_CON_MUX_MUX_CLKCMU_DROOPDETECTOR_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_DROOPDETECTOR_SELECT, CLKOUT_CON_BLK_CMU_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_CMU_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_CMU_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_SELECT, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CIS_CLK0_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CIS_CLK0_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CIS_CLK1_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CIS_CLK1_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK2_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CIS_CLK2_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK3_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CIS_CLK3_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_SELECT, CLK_CON_DIV_CLKCMU_OTP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_IVA_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_IVA_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_IVA_BUS_SELECT, CLK_CON_GAT_GATE_CLKCMU_IVA_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_IVA_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_IVA_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_IVA_BUS_BUSY, CLK_CON_DIV_CLKCMU_IVA_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_IVA_BUS_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD_SELECT, CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD_BUSY, CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD_DIVRATIO, CLK_CON_MUX_MUX_CMU_CMUREF_BUSY, CLK_CON_MUX_MUX_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CMU_CMUREF_SELECT, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUSPHSI2C_BUSY, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUSPHSI2C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUSPHSI2C_SELECT, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUSPHSI2C_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUSPHSI2C_MANUAL, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUSPHSI2C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_BUSC_BUSPHSI2C_BUSY, CLK_CON_DIV_CLKCMU_BUSC_BUSPHSI2C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_BUSC_BUSPHSI2C_DIVRATIO, CLK_CON_DIV_CLKCMU_CAM_VRA_BUSY, CLK_CON_DIV_CLKCMU_CAM_VRA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CAM_VRA_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_CAM_VRA_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CAM_VRA_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CAM_VRA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CAM_VRA_BUSY, CLK_CON_MUX_MUX_CLKCMU_CAM_VRA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CAM_VRA_SELECT, CLK_CON_DIV_DIV_PLL_SHARED1_DIV4_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC1_SPEEDY2_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_SPEEDY2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERIC1_SPEEDY2_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPEEDY2_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPEEDY2_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPEEDY2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_SELECT, CLK_CON_DIV_CLKCMU_FSYS0_DPGTC_BUSY, CLK_CON_DIV_CLKCMU_FSYS0_DPGTC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_FSYS0_DPGTC_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_MODEM_SHARED0_BUSY, CLK_CON_DIV_CLKCMU_MODEM_SHARED0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_MODEM_SHARED0_DIVRATIO, CLK_CON_DIV_CLKCMU_MODEM_SHARED1_BUSY, CLK_CON_DIV_CLKCMU_MODEM_SHARED1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_MODEM_SHARED1_DIVRATIO, CLK_CON_DIV_CLKCMU_DCAM_BUS_BUSY, CLK_CON_DIV_CLKCMU_DCAM_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_DCAM_BUS_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_DCAM_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DCAM_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DCAM_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_DCAM_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_DCAM_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_DCAM_BUS_SELECT, CLK_CON_GAT_GATE_CLKCMU_IMEM_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_IMEM_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_IMEM_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_IMEM_BUS_BUSY, CLK_CON_DIV_CLKCMU_IMEM_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_IMEM_BUS_DIVRATIO, CLK_CON_MUX_MUX_CLKCMU_IMEM_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_IMEM_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_IMEM_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE_SELECT, CLK_CON_DIV_DIV_CLK_CMU_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CMU_CMUREF_DIVRATIO, CLK_CON_DIV_CLKCMU_SRDZ_IMGD_BUSY, CLK_CON_DIV_CLKCMU_SRDZ_IMGD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_SRDZ_IMGD_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_SRDZ_IMGD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_SRDZ_IMGD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_SRDZ_IMGD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_SRDZ_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_SRDZ_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_SRDZ_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_SRDZ_IMGD_BUSY, CLK_CON_MUX_MUX_CLKCMU_SRDZ_IMGD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_SRDZ_IMGD_SELECT, CLK_CON_DIV_CLKCMU_SRDZ_BUS_BUSY, CLK_CON_DIV_CLKCMU_SRDZ_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_SRDZ_BUS_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_SRDZ_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_SRDZ_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_SRDZ_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_DCAM_IMGD_BUSY, CLK_CON_DIV_CLKCMU_DCAM_IMGD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_DCAM_IMGD_DIVRATIO, CLK_CON_GAT_GATE_CLKCMU_DCAM_IMGD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DCAM_IMGD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DCAM_IMGD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_DCAM_IMGD_BUSY, CLK_CON_MUX_MUX_CLKCMU_DCAM_IMGD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_DCAM_IMGD_SELECT, CLK_CON_DIV_DIV_CP2AP_MIF_CLK_DIV2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPEEDY2_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPEEDY2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPEEDY2_SELECT, CLK_CON_MUX_MUX_CLKCMU_APM_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_APM_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS_SELECT, CLK_CON_MUX_MUX_CLK_CMU_CMUREF_BUSY, CLK_CON_MUX_MUX_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CMU_CMUREF_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_SELECT, DMYQCH_CON_CMU_CMU_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CMU_CMUREF_QCH_CLOCK_REQ, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_CLOCK_REQ, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_CLOCK_REQ, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_CLOCK_REQ, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_CLOCK_REQ, CLK_CON_DIV_DIV_CLK_CORE_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_CORE_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CORE_BUSP_DIVRATIO, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_PMU_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PMU_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PMU_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_CORE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_CPACE_D_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_CPACE_D_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_CPACE_D_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF3_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF3_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_CORE_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_CORE_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_CORE_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_CORE_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_CORE_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_CORE_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G0_DMC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G0_DMC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G0_DMC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G1_DMC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G1_DMC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G1_DMC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G2_DMC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G2_DMC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G2_DMC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G3_DMC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G3_DMC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G3_DMC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_APBBR_CCI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_APBBR_CCI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_APBBR_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DBG_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DBG_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DBG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_IMEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_IMEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_IMEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_APBBR_CCI_QCH_ENABLE, QCH_CON_APBBR_CCI_QCH_CLOCK_REQ, QCH_CON_APBBR_CCI_QCH_EXPIRE_VAL, QCH_CON_BDU_QCH_ENABLE, QCH_CON_BDU_QCH_CLOCK_REQ, QCH_CON_BDU_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMCORE_QCH_ENABLE, QCH_CON_BUSIF_HPMCORE_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMCORE_QCH_EXPIRE_VAL, DMYQCH_CON_CCI_QCH_ENABLE, DMYQCH_CON_CCI_QCH_CLOCK_REQ, QCH_CON_CORE_CMU_CORE_QCH_ENABLE, QCH_CON_CORE_CMU_CORE_QCH_CLOCK_REQ, QCH_CON_CORE_CMU_CORE_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D0_G3D_QCH_ENABLE, QCH_CON_LHM_ACE_D0_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D0_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D1_G3D_QCH_ENABLE, QCH_CON_LHM_ACE_D1_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D1_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D2_G3D_QCH_ENABLE, QCH_CON_LHM_ACE_D2_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D2_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D3_G3D_QCH_ENABLE, QCH_CON_LHM_ACE_D3_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D3_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D_CPUCL1_QCH_ENABLE, QCH_CON_LHM_ACE_D_CPUCL1_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_CP_QCH_ENABLE, QCH_CON_LHM_AXI_D_CP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_CP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_CP_QCH_ENABLE, QCH_CON_LHM_AXI_P_CP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_CP_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_T_BDU_QCH_ENABLE, QCH_CON_LHS_ATB_T_BDU_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T_BDU_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_CPUCL0_QCH_ENABLE, QCH_CON_LHS_AXI_P_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_CPUCL1_QCH_ENABLE, QCH_CON_LHS_AXI_P_CPUCL1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_DBG_QCH_ENABLE, QCH_CON_LHS_AXI_P_DBG_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_DBG_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_G3D_QCH_ENABLE, QCH_CON_LHS_AXI_P_G3D_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_G3D_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_IMEM_QCH_ENABLE, QCH_CON_LHS_AXI_P_IMEM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_IMEM_QCH_EXPIRE_VAL, QCH_CON_PMU_CORE_QCH_ENABLE, QCH_CON_PMU_CORE_QCH_CLOCK_REQ, QCH_CON_PMU_CORE_QCH_EXPIRE_VAL, QCH_CON_PPCFW_G3D_QCH_ENABLE, QCH_CON_PPCFW_G3D_QCH_CLOCK_REQ, QCH_CON_PPCFW_G3D_QCH_EXPIRE_VAL, QCH_CON_BCM_CPUCL0_QCH_ENABLE, QCH_CON_BCM_CPUCL0_QCH_CLOCK_REQ, QCH_CON_BCM_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_BCM_CPUCL1_QCH_ENABLE, QCH_CON_BCM_CPUCL1_QCH_CLOCK_REQ, QCH_CON_BCM_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_BCM_G3D0_QCH_ENABLE, QCH_CON_BCM_G3D0_QCH_CLOCK_REQ, QCH_CON_BCM_G3D0_QCH_EXPIRE_VAL, QCH_CON_BCM_G3D1_QCH_ENABLE, QCH_CON_BCM_G3D1_QCH_CLOCK_REQ, QCH_CON_BCM_G3D1_QCH_EXPIRE_VAL, QCH_CON_BCM_G3D2_QCH_ENABLE, QCH_CON_BCM_G3D2_QCH_CLOCK_REQ, QCH_CON_BCM_G3D2_QCH_EXPIRE_VAL, QCH_CON_BCM_G3D3_QCH_ENABLE, QCH_CON_BCM_G3D3_QCH_CLOCK_REQ, QCH_CON_BCM_G3D3_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CORE_QCH_ENABLE, QCH_CON_SYSREG_CORE_QCH_CLOCK_REQ, QCH_CON_SYSREG_CORE_QCH_EXPIRE_VAL, QCH_CON_TREX_D_CORE_QCH_ENABLE, QCH_CON_TREX_D_CORE_QCH_CLOCK_REQ, QCH_CON_TREX_D_CORE_QCH_EXPIRE_VAL, QCH_CON_TREX_P0_CORE_QCH_ENABLE, QCH_CON_TREX_P0_CORE_QCH_CLOCK_REQ, QCH_CON_TREX_P0_CORE_QCH_EXPIRE_VAL, QCH_CON_TREX_P1_CORE_QCH_ENABLE, QCH_CON_TREX_P1_CORE_QCH_CLOCK_REQ, QCH_CON_TREX_P1_CORE_QCH_EXPIRE_VAL, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_SELECT, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_DIVRATIO, PLL_CON0_PLL_CPUCL0_DIV_P, PLL_CON0_PLL_CPUCL0_DIV_M, PLL_CON0_PLL_CPUCL0_DIV_S, PLL_CON0_PLL_CPUCL0_ENABLE, PLL_CON0_PLL_CPUCL0_STABLE, PLL_LOCKTIME_PLL_CPUCL0_PLL_LOCK_TIME, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_DIVRATIO, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_BUSY, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DROOPDETECTOR_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DROOPDETECTOR_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DROOPDETECTOR_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_DIVRATIO, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP0_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP0_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP0_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP1_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP1_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP1_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLK_CPUCL0_CPU_CG_VAL, CLK_CON_GAT_GATE_CLK_CPUCL0_CPU_MANUAL, CLK_CON_GAT_GATE_CLK_CPUCL0_CPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_DIVRATIO, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_ENABLE, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_CLOCK_REQ, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP0_ENABLE, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP0_CLOCK_REQ, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP0_EXPIRE_VAL, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP1_ENABLE, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP1_CLOCK_REQ, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP1_EXPIRE_VAL, QCH_CON_BUSIF_HPMCPUCL0_QCH_ENABLE, QCH_CON_BUSIF_HPMCPUCL0_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMCPUCL0_QCH_EXPIRE_VAL, DMYQCH_CON_CLUSTER0_QCH_ENABLE, DMYQCH_CON_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_LHS_ATB_T0_CLUSTER0_ENABLE, QCH_CON_CLUSTER0_QCH_LHS_ATB_T0_CLUSTER0_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_LHS_ATB_T0_CLUSTER0_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_LHS_ATB_T1_CLUSTER0_ENABLE, QCH_CON_CLUSTER0_QCH_LHS_ATB_T1_CLUSTER0_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_LHS_ATB_T1_CLUSTER0_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_LHS_ATB_T2_CLUSTER0_ENABLE, QCH_CON_CLUSTER0_QCH_LHS_ATB_T2_CLUSTER0_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_LHS_ATB_T2_CLUSTER0_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_LHS_ATB_T3_CLUSTER0_ENABLE, QCH_CON_CLUSTER0_QCH_LHS_ATB_T3_CLUSTER0_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_LHS_ATB_T3_CLUSTER0_EXPIRE_VAL, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_EXPIRE_VAL, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_ENABLE, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_CLOCK_REQ, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_CPUCL0_QCH_ENABLE, QCH_CON_LHM_AXI_P_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_PMU_CPUCL0_QCH_ENABLE, QCH_CON_PMU_CPUCL0_QCH_CLOCK_REQ, QCH_CON_PMU_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CPUCL0_QCH_ENABLE, QCH_CON_SYSREG_CPUCL0_QCH_CLOCK_REQ, QCH_CON_SYSREG_CPUCL0_QCH_EXPIRE_VAL, PLL_CON0_PLL_CPUCL1_DIV_P, PLL_CON0_PLL_CPUCL1_DIV_M, PLL_CON0_PLL_CPUCL1_DIV_S, PLL_CON0_PLL_CPUCL1_ENABLE, PLL_CON0_PLL_CPUCL1_STABLE, PLL_LOCKTIME_PLL_CPUCL1_PLL_LOCK_TIME, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_BUSY, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_SELECT, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_DIVRATIO, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_PMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_PMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_PMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK_DIVRATIO, CLK_CON_GAT_GATE_CLK_CPUCL1_CPU_CG_VAL, CLK_CON_GAT_GATE_CLK_CPUCL1_CPU_MANUAL, CLK_CON_GAT_GATE_CLK_CPUCL1_CPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_DIVRATIO, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BUSIF_HPMCPUCL1_QCH_ENABLE, QCH_CON_BUSIF_HPMCPUCL1_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMCPUCL1_QCH_EXPIRE_VAL, DMYQCH_CON_CLUSTER1_QCH_CPU_ENABLE, DMYQCH_CON_CLUSTER1_QCH_CPU_CLOCK_REQ, DMYQCH_CON_CLUSTER1_QCH_DBG_ENABLE, DMYQCH_CON_CLUSTER1_QCH_DBG_CLOCK_REQ, QCH_CON_CLUSTER1_QCH_LHS_ACE_D_CPUCL1_ENABLE, QCH_CON_CLUSTER1_QCH_LHS_ACE_D_CPUCL1_CLOCK_REQ, QCH_CON_CLUSTER1_QCH_LHS_ACE_D_CPUCL1_EXPIRE_VAL, QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1_ENABLE, QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1_CLOCK_REQ, QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1_EXPIRE_VAL, QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1_ENABLE, QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1_CLOCK_REQ, QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1_EXPIRE_VAL, QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1_ENABLE, QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1_CLOCK_REQ, QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1_EXPIRE_VAL, QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1_ENABLE, QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1_CLOCK_REQ, QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1_EXPIRE_VAL, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_EXPIRE_VAL, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_ENABLE, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_CLOCK_REQ, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_CPUCL1_QCH_ENABLE, QCH_CON_LHM_AXI_P_CPUCL1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_PMU_CPUCL1_QCH_ENABLE, QCH_CON_PMU_CPUCL1_QCH_CLOCK_REQ, QCH_CON_PMU_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CPUCL1_QCH_ENABLE, QCH_CON_SYSREG_CPUCL1_QCH_CLOCK_REQ, QCH_CON_SYSREG_CPUCL1_QCH_EXPIRE_VAL, CLK_CON_DIV_DIV_CLK_DBG_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_DBG_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_DBG_PCLKDBG_DIVRATIO, CLK_CON_GAT_CLK_BLK_DBG_UID_DBG_CMU_DBG_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DBG_UID_DBG_CMU_DBG_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DBG_UID_DBG_CMU_DBG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_AXI_P_DBG_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_AXI_P_DBG_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_AXI_P_DBG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_AXI2APB_CORESIGHT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_AXI2APB_CORESIGHT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_AXI2APB_CORESIGHT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_ATCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_ATCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_ATCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_ATCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_ATCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_PCLKDBG_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_PCLKDBG_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_SECJTAG_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_SECJTAG_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_SECJTAG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_PMU_DBG_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_PMU_DBG_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_PMU_DBG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_SYSREG_DBG_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_SYSREG_DBG_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_SYSREG_DBG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_DBG_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_DBG_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_DBG_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_DBG_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_DBG_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_DBG_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_DBG_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_DBG_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_DBG_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_ATCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_ATCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_CSSYS_QCH_ENABLE, QCH_CON_CSSYS_QCH_CLOCK_REQ, QCH_CON_CSSYS_QCH_EXPIRE_VAL, QCH_CON_DBG_CMU_DBG_QCH_ENABLE, QCH_CON_DBG_CMU_DBG_QCH_CLOCK_REQ, QCH_CON_DBG_CMU_DBG_QCH_EXPIRE_VAL, QCH_CON_DUMPPC_CPUCL0_QCH_ENABLE, QCH_CON_DUMPPC_CPUCL0_QCH_CLOCK_REQ, QCH_CON_DUMPPC_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_DUMPPC_CPUCL1_QCH_ENABLE, QCH_CON_DUMPPC_CPUCL1_QCH_CLOCK_REQ, QCH_CON_DUMPPC_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T0_CLUSTER1_QCH_ENABLE, QCH_CON_LHM_ATB_T0_CLUSTER1_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T0_CLUSTER1_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T1_CLUSTER1_QCH_ENABLE, QCH_CON_LHM_ATB_T1_CLUSTER1_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T1_CLUSTER1_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T2_CLUSTER1_QCH_ENABLE, QCH_CON_LHM_ATB_T2_CLUSTER1_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T2_CLUSTER1_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T3_CLUSTER1_QCH_ENABLE, QCH_CON_LHM_ATB_T3_CLUSTER1_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T3_CLUSTER1_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T_AUD_QCH_ENABLE, QCH_CON_LHM_ATB_T_AUD_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T_AUD_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T_BDU_QCH_ENABLE, QCH_CON_LHM_ATB_T_BDU_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T_BDU_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_DBG_QCH_ENABLE, QCH_CON_LHM_AXI_P_DBG_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DBG_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_G_CSSYS_QCH_ENABLE, QCH_CON_LHS_AXI_G_CSSYS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G_CSSYS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_G_ETR_QCH_ENABLE, QCH_CON_LHS_AXI_G_ETR_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G_ETR_QCH_EXPIRE_VAL, QCH_CON_PMU_DBG_QCH_ENABLE, QCH_CON_PMU_DBG_QCH_CLOCK_REQ, QCH_CON_PMU_DBG_QCH_EXPIRE_VAL, QCH_CON_SECJTAG_QCH_ENABLE, QCH_CON_SECJTAG_QCH_CLOCK_REQ, QCH_CON_SECJTAG_QCH_EXPIRE_VAL, QCH_CON_STM_TXACTOR_QCH_ENABLE, QCH_CON_STM_TXACTOR_QCH_CLOCK_REQ, QCH_CON_STM_TXACTOR_QCH_EXPIRE_VAL, QCH_CON_SYSREG_DBG_QCH_ENABLE, QCH_CON_SYSREG_DBG_QCH_CLOCK_REQ, QCH_CON_SYSREG_DBG_QCH_EXPIRE_VAL, CLK_CON_DIV_DIV_CLK_DCAM_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_DCAM_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_DCAM_BUSP_DIVRATIO, PLL_CON0_MUX_CLKCMU_DCAM_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_DCAM_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_DCAM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_DCAM_UID_DCAM_CMU_DCAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DCAM_UID_DCAM_CMU_DCAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DCAM_UID_DCAM_CMU_DCAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_DCAM_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_DCAM_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_DCAM_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_DCAM_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_DCAM_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_DCAM_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DCAM_UID_DCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_DCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_DCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PMU_DCAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PMU_DCAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PMU_DCAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DCAM_UID_SYSREG_DCAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_SYSREG_DCAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_SYSREG_DCAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_SYS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_SYS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_SYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DCAM_UID_XIU_P_DCAM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_XIU_P_DCAM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_XIU_P_DCAM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHM_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHM_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHM_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBM_DCAM_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBM_DCAM_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBM_DCAM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_DCAM_IMGD_USER_BUSY, PLL_CON0_MUX_CLKCMU_DCAM_IMGD_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_DCAM_IMGD_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBS_DCAM_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBS_DCAM_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBS_DCAM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_ATB_DCAMSRDZ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_ATB_DCAMSRDZ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_ATB_DCAMSRDZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_IMGD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_IMGD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_IMGD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BTM_DCAM_QCH_ENABLE, QCH_CON_BTM_DCAM_QCH_CLOCK_REQ, QCH_CON_BTM_DCAM_QCH_EXPIRE_VAL, QCH_CON_DCAM_CMU_DCAM_QCH_ENABLE, QCH_CON_DCAM_CMU_DCAM_QCH_CLOCK_REQ, QCH_CON_DCAM_CMU_DCAM_QCH_EXPIRE_VAL, QCH_CON_DCP_QCH_ENABLE, QCH_CON_DCP_QCH_CLOCK_REQ, QCH_CON_DCP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_SRDZDCAM_QCH_ENABLE, QCH_CON_LHM_AXI_P_SRDZDCAM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_SRDZDCAM_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_DCAMSRDZ_QCH_ENABLE, QCH_CON_LHS_ATB_DCAMSRDZ_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_DCAMSRDZ_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_DCAMSRDZ_QCH_ENABLE, QCH_CON_LHS_AXI_D_DCAMSRDZ_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_DCAMSRDZ_QCH_EXPIRE_VAL, QCH_CON_PMU_DCAM_QCH_ENABLE, QCH_CON_PMU_DCAM_QCH_CLOCK_REQ, QCH_CON_PMU_DCAM_QCH_EXPIRE_VAL, QCH_CON_BCM_DCAM_QCH_ENABLE, QCH_CON_BCM_DCAM_QCH_CLOCK_REQ, QCH_CON_BCM_DCAM_QCH_EXPIRE_VAL, QCH_CON_SYSREG_DCAM_QCH_ENABLE, QCH_CON_SYSREG_DCAM_QCH_CLOCK_REQ, QCH_CON_SYSREG_DCAM_QCH_EXPIRE_VAL, PLL_CON0_MUX_CLKCMU_DPU_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_DPU_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_DPU_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLKCMU_DPU1_BUSD_CG_VAL, CLK_CON_GAT_CLKCMU_DPU1_BUSD_MANUAL, CLK_CON_GAT_CLKCMU_DPU1_BUSD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_DPU0_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_DPU0_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_DPU0_BUSP_DIVRATIO, CLK_CON_GAT_CLKCMU_DPU1_BUSP_CG_VAL, CLK_CON_GAT_CLKCMU_DPU1_BUSP_MANUAL, CLK_CON_GAT_CLKCMU_DPU1_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_DPU0_UID_DPU0_CMU_DPU0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPU0_UID_DPU0_CMU_DPU0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPU0_UID_DPU0_CMU_DPU0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DECON0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DECON0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DECON0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_DPU0_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_DPU0_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_DPU0_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_PMU_DPU0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_PMU_DPU0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_PMU_DPU0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSREG_DPU0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSREG_DPU0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSREG_DPU0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_NONSECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_NONSECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_NONSECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_NONSECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHM_AXI_P0_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHM_AXI_P0_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHM_AXI_P0_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_XIU_P0_DPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_XIU_P0_DPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_XIU_P0_DPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_VGR_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_VGR_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_VGR_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G0_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G0_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G0_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_DPU0_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_DPU0_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_DPU0_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G1_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G1_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G1_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_WB_MUX_IPCLKPORT_DPP_G1_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_WB_MUX_IPCLKPORT_DPP_G1_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_WB_MUX_IPCLKPORT_DPP_G1_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH0_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH0_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH1_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH1_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH2_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH2_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_WB_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_WB_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_WB_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH_INTF_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH_INTF_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH_INTF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_SFR_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_SFR_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_SFR_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D_USBTV_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D_USBTV_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D_USBTV_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_NONSECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_NONSECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BTM_DPUD0_QCH_ENABLE, QCH_CON_BTM_DPUD0_QCH_CLOCK_REQ, QCH_CON_BTM_DPUD0_QCH_EXPIRE_VAL, QCH_CON_BTM_DPUD1_QCH_ENABLE, QCH_CON_BTM_DPUD1_QCH_CLOCK_REQ, QCH_CON_BTM_DPUD1_QCH_EXPIRE_VAL, QCH_CON_BTM_DPUD2_QCH_ENABLE, QCH_CON_BTM_DPUD2_QCH_CLOCK_REQ, QCH_CON_BTM_DPUD2_QCH_EXPIRE_VAL, QCH_CON_DECON0_QCH_ENABLE, QCH_CON_DECON0_QCH_CLOCK_REQ, QCH_CON_DECON0_QCH_EXPIRE_VAL, QCH_CON_DPP_QCH_DPP_G0_ENABLE, QCH_CON_DPP_QCH_DPP_G0_CLOCK_REQ, QCH_CON_DPP_QCH_DPP_G0_EXPIRE_VAL, QCH_CON_DPP_QCH_DPP_G1_ENABLE, QCH_CON_DPP_QCH_DPP_G1_CLOCK_REQ, QCH_CON_DPP_QCH_DPP_G1_EXPIRE_VAL, QCH_CON_DPP_QCH_DPP_VGR_ENABLE, QCH_CON_DPP_QCH_DPP_VGR_CLOCK_REQ, QCH_CON_DPP_QCH_DPP_VGR_EXPIRE_VAL, QCH_CON_DPU0_CMU_DPU0_QCH_ENABLE, QCH_CON_DPU0_CMU_DPU0_QCH_CLOCK_REQ, QCH_CON_DPU0_CMU_DPU0_QCH_EXPIRE_VAL, QCH_CON_DPU_DMA_QCH_ENABLE, QCH_CON_DPU_DMA_QCH_CLOCK_REQ, QCH_CON_DPU_DMA_QCH_EXPIRE_VAL, QCH_CON_DPU_WB_MUX_QCH_ENABLE, QCH_CON_DPU_WB_MUX_QCH_CLOCK_REQ, QCH_CON_DPU_WB_MUX_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P0_DPU_QCH_ENABLE, QCH_CON_LHM_AXI_P0_DPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P0_DPU_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_DPU_QCH_ENABLE, QCH_CON_LHS_AXI_D0_DPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_DPU_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_DPU_QCH_ENABLE, QCH_CON_LHS_AXI_D1_DPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_DPU_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D2_DPU_QCH_ENABLE, QCH_CON_LHS_AXI_D2_DPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D2_DPU_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_USBTV_QCH_ENABLE, QCH_CON_LHS_AXI_D_USBTV_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_USBTV_QCH_EXPIRE_VAL, QCH_CON_PMU_DPU0_QCH_ENABLE, QCH_CON_PMU_DPU0_QCH_CLOCK_REQ, QCH_CON_PMU_DPU0_QCH_EXPIRE_VAL, QCH_CON_BCM_DPUD0_QCH_ENABLE, QCH_CON_BCM_DPUD0_QCH_CLOCK_REQ, QCH_CON_BCM_DPUD0_QCH_EXPIRE_VAL, QCH_CON_BCM_DPUD1_QCH_ENABLE, QCH_CON_BCM_DPUD1_QCH_CLOCK_REQ, QCH_CON_BCM_DPUD1_QCH_EXPIRE_VAL, QCH_CON_BCM_DPUD2_QCH_ENABLE, QCH_CON_BCM_DPUD2_QCH_CLOCK_REQ, QCH_CON_BCM_DPUD2_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_DPUD0_QCH_ENABLE, QCH_CON_SYSMMU_DPUD0_QCH_CLOCK_REQ, QCH_CON_SYSMMU_DPUD0_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_DPUD1_QCH_ENABLE, QCH_CON_SYSMMU_DPUD1_QCH_CLOCK_REQ, QCH_CON_SYSMMU_DPUD1_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_DPUD2_QCH_ENABLE, QCH_CON_SYSMMU_DPUD2_QCH_CLOCK_REQ, QCH_CON_SYSMMU_DPUD2_QCH_EXPIRE_VAL, QCH_CON_SYSREG_DPU0_QCH_ENABLE, QCH_CON_SYSREG_DPU0_QCH_CLOCK_REQ, QCH_CON_SYSREG_DPU0_QCH_EXPIRE_VAL, PLL_CON0_MUX_CLKCMU_DPU1_BUSD_USER_BUSY, PLL_CON0_MUX_CLKCMU_DPU1_BUSD_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_DPU1_BUSD_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_DPU1_BUSP_USER_BUSY, PLL_CON0_MUX_CLKCMU_DPU1_BUSP_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_DPU1_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_DPU1_UID_DPU1_CMU_DPU1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPU1_UID_DPU1_CMU_DPU1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPU1_UID_DPU1_CMU_DPU1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_DPU1_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_DPU1_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_DPU1_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU1_UID_SYSREG_DPU1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_SYSREG_DPU1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_SYSREG_DPU1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU1_UID_PMU_DPU1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_PMU_DPU1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_PMU_DPU1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_PLL_DPU_DIV_P, PLL_CON0_PLL_DPU_DIV_M, PLL_CON0_PLL_DPU_DIV_S, PLL_CON0_PLL_DPU_ENABLE, PLL_CON0_PLL_DPU_STABLE, PLL_LOCKTIME_PLL_DPU_PLL_LOCK_TIME, CLK_CON_DIV_DIV_CLKCMU_DPU1_DECON2_BUSY, CLK_CON_DIV_DIV_CLKCMU_DPU1_DECON2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLKCMU_DPU1_DECON2_DIVRATIO, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AXI2APB_DPU1P0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AXI2APB_DPU1P0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AXI2APB_DPU1P0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU1_UID_LHM_AXI_P_DPU1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_LHM_AXI_P_DPU1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_LHM_AXI_P_DPU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_DPU1_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_DPU1_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_DPU1_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_DECON2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_DECON2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_DECON2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_VCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_VCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_VCLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_DECON1_QCH_ENABLE, QCH_CON_DECON1_QCH_CLOCK_REQ, QCH_CON_DECON1_QCH_EXPIRE_VAL, QCH_CON_DECON2_QCH_ACLK_ENABLE, QCH_CON_DECON2_QCH_ACLK_CLOCK_REQ, QCH_CON_DECON2_QCH_ACLK_EXPIRE_VAL, QCH_CON_DECON2_QCH_VCLK_ENABLE, QCH_CON_DECON2_QCH_VCLK_CLOCK_REQ, QCH_CON_DECON2_QCH_VCLK_EXPIRE_VAL, QCH_CON_DPU1_CMU_DPU1_QCH_ENABLE, QCH_CON_DPU1_CMU_DPU1_QCH_CLOCK_REQ, QCH_CON_DPU1_CMU_DPU1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_DPU1_QCH_ENABLE, QCH_CON_LHM_AXI_P_DPU1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DPU1_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_DPTX_QCH_ENABLE, QCH_CON_LHS_ATB_DPTX_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_DPTX_QCH_EXPIRE_VAL, QCH_CON_PMU_DPU1_QCH_ENABLE, QCH_CON_PMU_DPU1_QCH_CLOCK_REQ, QCH_CON_PMU_DPU1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_DPU1_QCH_ENABLE, QCH_CON_SYSREG_DPU1_QCH_CLOCK_REQ, QCH_CON_SYSREG_DPU1_QCH_EXPIRE_VAL, CLK_CON_DIV_DIV_CLK_DSP_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_DSP_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_DSP_BUSP_DIVRATIO, PLL_CON0_MUX_CLKCMU_DSP_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_DSP_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_DSP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_SCORE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_SCORE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_SCORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_PMU_DSP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_PMU_DSP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_PMU_DSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_AXI2APB_DSP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_AXI2APB_DSP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_AXI2APB_DSP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_NONSECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_NONSECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_DSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_DSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_DSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_DSP_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_DSP_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_DSP_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_DSP_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_DSP_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_DSP_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_ACEL_D_DSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_ACEL_D_DSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_ACEL_D_DSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_P_DSP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_P_DSP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_P_DSP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_IVADSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_IVADSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_IVADSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_VPUDSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_VPUDSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_VPUDSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_IVADSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_IVADSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_IVADSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPIVA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPIVA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPIVA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPVPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPVPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPVPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSP_UID_WRAP2_CONV_DSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_WRAP2_CONV_DSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_WRAP2_CONV_DSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BTM_SCORE_QCH_ENABLE, QCH_CON_BTM_SCORE_QCH_CLOCK_REQ, QCH_CON_BTM_SCORE_QCH_EXPIRE_VAL, QCH_CON_DSP_CMU_DSP_QCH_ENABLE, QCH_CON_DSP_CMU_DSP_QCH_CLOCK_REQ, QCH_CON_DSP_CMU_DSP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_IVADSP_QCH_ENABLE, QCH_CON_LHM_AXI_D_IVADSP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_IVADSP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_VPUDSP_QCH_ENABLE, QCH_CON_LHM_AXI_D_VPUDSP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_VPUDSP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_DSP_QCH_ENABLE, QCH_CON_LHM_AXI_P_DSP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DSP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_IVADSP_QCH_ENABLE, QCH_CON_LHM_AXI_P_IVADSP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_IVADSP_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_DSP_QCH_ENABLE, QCH_CON_LHS_ACEL_D_DSP_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_DSP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_DSPIVA_QCH_ENABLE, QCH_CON_LHS_AXI_P_DSPIVA_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_DSPIVA_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_DSPVPU_QCH_ENABLE, QCH_CON_LHS_AXI_P_DSPVPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_DSPVPU_QCH_EXPIRE_VAL, QCH_CON_PMU_DSP_QCH_ENABLE, QCH_CON_PMU_DSP_QCH_CLOCK_REQ, QCH_CON_PMU_DSP_QCH_EXPIRE_VAL, QCH_CON_BCM_SCORE_QCH_ENABLE, QCH_CON_BCM_SCORE_QCH_CLOCK_REQ, QCH_CON_BCM_SCORE_QCH_EXPIRE_VAL, QCH_CON_SCORE_QCH_ENABLE, QCH_CON_SCORE_QCH_CLOCK_REQ, QCH_CON_SCORE_QCH_EXPIRE_VAL, QCH_CON_SMMU_SCORE_QCH_ENABLE, QCH_CON_SMMU_SCORE_QCH_CLOCK_REQ, QCH_CON_SMMU_SCORE_QCH_EXPIRE_VAL, QCH_CON_SYSREG_DSP_QCH_ENABLE, QCH_CON_SYSREG_DSP_QCH_CLOCK_REQ, QCH_CON_SYSREG_DSP_QCH_EXPIRE_VAL, PLL_CON0_MUX_CLKCMU_FSYS0_UFS_EMBD_USER_BUSY, PLL_CON0_MUX_CLKCMU_FSYS0_UFS_EMBD_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_FSYS0_UFS_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_FSYS0_MMC_EMBD_USER_BUSY, PLL_CON0_MUX_CLKCMU_FSYS0_MMC_EMBD_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_FSYS0_MMC_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_FSYS0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_FSYS0_USBDRD30_USER_BUSY, PLL_CON0_MUX_CLKCMU_FSYS0_USBDRD30_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_FSYS0_USBDRD30_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHS_ACEL_D_FSYS0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHS_ACEL_D_FSYS0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHS_ACEL_D_FSYS0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AHBBR_FSYS0_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AHBBR_FSYS0_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AHBBR_FSYS0_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_G_ETR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_G_ETR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_G_ETR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_P_FSYS0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_P_FSYS0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_P_FSYS0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_D_USBTV_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_D_USBTV_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_D_USBTV_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_US_D_FSYS0_USB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_US_D_FSYS0_USB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_US_D_FSYS0_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_FSYS0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_FSYS0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_FSYS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_USB_FSYS0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_USB_FSYS0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_USB_FSYS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2APB_FSYS0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2APB_FSYS0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2APB_FSYS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_GPIO_FSYS0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_GPIO_FSYS0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_GPIO_FSYS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PMU_FSYS0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PMU_FSYS0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PMU_FSYS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_SYSREG_FSYS0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_SYSREG_FSYS0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_SYSREG_FSYS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_USB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_USB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_P_FSYS0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_P_FSYS0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_P_FSYS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_CORE_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_CORE_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_CORE_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_SUSPEND_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_SUSPEND_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_SUSPEND_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_REF_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_REF_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_REF_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_AHB_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_AHB_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_AHB_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_XIU_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_XIU_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_XIU_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_RSTNSYNC_CLK_FSYS0_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_RSTNSYNC_CLK_FSYS0_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_RSTNSYNC_CLK_FSYS0_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_FSYS0_DPGTC_USER_BUSY, PLL_CON0_MUX_CLKCMU_FSYS0_DPGTC_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_FSYS0_DPGTC_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_GTC_EXT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_GTC_EXT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_GTC_EXT_CLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BTM_FSYS0_QCH_ENABLE, QCH_CON_BTM_FSYS0_QCH_CLOCK_REQ, QCH_CON_BTM_FSYS0_QCH_EXPIRE_VAL, QCH_CON_DP_LINK_QCH_ENABLE, QCH_CON_DP_LINK_QCH_CLOCK_REQ, QCH_CON_DP_LINK_QCH_EXPIRE_VAL, QCH_CON_ETR_MIU_QCH_PCLK_ENABLE, QCH_CON_ETR_MIU_QCH_PCLK_CLOCK_REQ, QCH_CON_ETR_MIU_QCH_PCLK_EXPIRE_VAL, QCH_CON_ETR_MIU_QCH_ACLK_ENABLE, QCH_CON_ETR_MIU_QCH_ACLK_CLOCK_REQ, QCH_CON_ETR_MIU_QCH_ACLK_EXPIRE_VAL, QCH_CON_FSYS0_CMU_FSYS0_QCH_ENABLE, QCH_CON_FSYS0_CMU_FSYS0_QCH_CLOCK_REQ, QCH_CON_FSYS0_CMU_FSYS0_QCH_EXPIRE_VAL, QCH_CON_GPIO_FSYS0_QCH_ENABLE, QCH_CON_GPIO_FSYS0_QCH_CLOCK_REQ, QCH_CON_GPIO_FSYS0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_USBTV_QCH_ENABLE, QCH_CON_LHM_AXI_D_USBTV_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_USBTV_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_G_ETR_QCH_ENABLE, QCH_CON_LHM_AXI_G_ETR_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_G_ETR_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_FSYS0_QCH_ENABLE, QCH_CON_LHM_AXI_P_FSYS0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_FSYS0_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_FSYS0_QCH_ENABLE, QCH_CON_LHS_ACEL_D_FSYS0_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_FSYS0_QCH_EXPIRE_VAL, QCH_CON_MMC_EMBD_QCH_ENABLE, QCH_CON_MMC_EMBD_QCH_CLOCK_REQ, QCH_CON_MMC_EMBD_QCH_EXPIRE_VAL, QCH_CON_PMU_FSYS0_QCH_ENABLE, QCH_CON_PMU_FSYS0_QCH_CLOCK_REQ, QCH_CON_PMU_FSYS0_QCH_EXPIRE_VAL, QCH_CON_BCM_FSYS0_QCH_ENABLE, QCH_CON_BCM_FSYS0_QCH_CLOCK_REQ, QCH_CON_BCM_FSYS0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_FSYS0_QCH_ENABLE, QCH_CON_SYSREG_FSYS0_QCH_CLOCK_REQ, QCH_CON_SYSREG_FSYS0_QCH_EXPIRE_VAL, QCH_CON_UFS_EMBD_QCH_ENABLE, QCH_CON_UFS_EMBD_QCH_CLOCK_REQ, QCH_CON_UFS_EMBD_QCH_EXPIRE_VAL, QCH_CON_UFS_EMBD_QCH_FMP_ENABLE, QCH_CON_UFS_EMBD_QCH_FMP_CLOCK_REQ, QCH_CON_UFS_EMBD_QCH_FMP_EXPIRE_VAL, QCH_CON_USBTV_QCH_USB30DRD_LINK_ENABLE, QCH_CON_USBTV_QCH_USB30DRD_LINK_CLOCK_REQ, QCH_CON_USBTV_QCH_USB30DRD_LINK_EXPIRE_VAL, QCH_CON_USBTV_QCH_USBTV_HOST_ENABLE, QCH_CON_USBTV_QCH_USBTV_HOST_CLOCK_REQ, QCH_CON_USBTV_QCH_USBTV_HOST_EXPIRE_VAL, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_FSYS1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER_BUSY, PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_FSYS1_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PMU_FSYS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PMU_FSYS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PMU_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_IPCLKPORT_PHY_REF_CLK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_IPCLKPORT_PHY_REF_CLK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_IPCLKPORT_PHY_REF_CLK_IN_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_0_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_0_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_0_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_0_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_0_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_0_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_FSYS1_PCIE_USER_BUSY, PLL_CON0_MUX_CLKCMU_FSYS1_PCIE_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_FSYS1_PCIE_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_FSYS1_UFS_CARD_USER_BUSY, PLL_CON0_MUX_CLKCMU_FSYS1_UFS_CARD_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_FSYS1_UFS_CARD_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_1_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_1_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_1_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_1_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_1_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_1_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_ADM_AHB_SSS_QCH_ENABLE, QCH_CON_ADM_AHB_SSS_QCH_CLOCK_REQ, QCH_CON_ADM_AHB_SSS_QCH_EXPIRE_VAL, QCH_CON_BTM_FSYS1_QCH_ENABLE, QCH_CON_BTM_FSYS1_QCH_CLOCK_REQ, QCH_CON_BTM_FSYS1_QCH_EXPIRE_VAL, QCH_CON_FSYS1_CMU_FSYS1_QCH_ENABLE, QCH_CON_FSYS1_CMU_FSYS1_QCH_CLOCK_REQ, QCH_CON_FSYS1_CMU_FSYS1_QCH_EXPIRE_VAL, QCH_CON_GPIO_FSYS1_QCH_ENABLE, QCH_CON_GPIO_FSYS1_QCH_CLOCK_REQ, QCH_CON_GPIO_FSYS1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_FSYS1_QCH_ENABLE, QCH_CON_LHM_AXI_P_FSYS1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_FSYS1_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_FSYS1_QCH_ENABLE, QCH_CON_LHS_ACEL_D_FSYS1_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_FSYS1_QCH_EXPIRE_VAL, QCH_CON_MMC_CARD_QCH_ENABLE, QCH_CON_MMC_CARD_QCH_CLOCK_REQ, QCH_CON_MMC_CARD_QCH_EXPIRE_VAL, QCH_CON_PCIE_QCH_PCIE0_MSTR_ENABLE, QCH_CON_PCIE_QCH_PCIE0_MSTR_CLOCK_REQ, QCH_CON_PCIE_QCH_PCIE0_MSTR_EXPIRE_VAL, QCH_CON_PCIE_QCH_PCIE_PCS_ENABLE, QCH_CON_PCIE_QCH_PCIE_PCS_CLOCK_REQ, QCH_CON_PCIE_QCH_PCIE_PCS_EXPIRE_VAL, QCH_CON_PCIE_QCH_PCIE_PHY_ENABLE, QCH_CON_PCIE_QCH_PCIE_PHY_CLOCK_REQ, QCH_CON_PCIE_QCH_PCIE_PHY_EXPIRE_VAL, QCH_CON_PCIE_QCH_PCIE0_DBI_ENABLE, QCH_CON_PCIE_QCH_PCIE0_DBI_CLOCK_REQ, QCH_CON_PCIE_QCH_PCIE0_DBI_EXPIRE_VAL, QCH_CON_PCIE_QCH_PCIE0_APB_ENABLE, QCH_CON_PCIE_QCH_PCIE0_APB_CLOCK_REQ, QCH_CON_PCIE_QCH_PCIE0_APB_EXPIRE_VAL, DMYQCH_CON_PCIE_QCH_PCIE_SOCPLL_ENABLE, DMYQCH_CON_PCIE_QCH_PCIE_SOCPLL_CLOCK_REQ, QCH_CON_PCIE_QCH_PCIE1_MSTR_ENABLE, QCH_CON_PCIE_QCH_PCIE1_MSTR_CLOCK_REQ, QCH_CON_PCIE_QCH_PCIE1_MSTR_EXPIRE_VAL, QCH_CON_PCIE_QCH_PCIE1_DBI_ENABLE, QCH_CON_PCIE_QCH_PCIE1_DBI_CLOCK_REQ, QCH_CON_PCIE_QCH_PCIE1_DBI_EXPIRE_VAL, QCH_CON_PCIE_QCH_PCIE1_APB_ENABLE, QCH_CON_PCIE_QCH_PCIE1_APB_CLOCK_REQ, QCH_CON_PCIE_QCH_PCIE1_APB_EXPIRE_VAL, QCH_CON_PMU_FSYS1_QCH_ENABLE, QCH_CON_PMU_FSYS1_QCH_CLOCK_REQ, QCH_CON_PMU_FSYS1_QCH_EXPIRE_VAL, QCH_CON_BCM_FSYS1_QCH_ENABLE, QCH_CON_BCM_FSYS1_QCH_CLOCK_REQ, QCH_CON_BCM_FSYS1_QCH_EXPIRE_VAL, QCH_CON_RTIC_QCH_ENABLE, QCH_CON_RTIC_QCH_CLOCK_REQ, QCH_CON_RTIC_QCH_EXPIRE_VAL, QCH_CON_SSS_QCH_ENABLE, QCH_CON_SSS_QCH_CLOCK_REQ, QCH_CON_SSS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_FSYS1_QCH_ENABLE, QCH_CON_SYSREG_FSYS1_QCH_CLOCK_REQ, QCH_CON_SYSREG_FSYS1_QCH_EXPIRE_VAL, QCH_CON_TOE_WIFI0_QCH_ENABLE, QCH_CON_TOE_WIFI0_QCH_CLOCK_REQ, QCH_CON_TOE_WIFI0_QCH_EXPIRE_VAL, QCH_CON_TOE_WIFI1_QCH_ENABLE, QCH_CON_TOE_WIFI1_QCH_CLOCK_REQ, QCH_CON_TOE_WIFI1_QCH_EXPIRE_VAL, QCH_CON_UFS_CARD_QCH_ENABLE, QCH_CON_UFS_CARD_QCH_CLOCK_REQ, QCH_CON_UFS_CARD_QCH_EXPIRE_VAL, QCH_CON_UFS_CARD_QCH_FMP_ENABLE, QCH_CON_UFS_CARD_QCH_FMP_CLOCK_REQ, QCH_CON_UFS_CARD_QCH_FMP_EXPIRE_VAL, PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_BUSY, PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_G2D_G2D_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_G2D_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_G2D_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_G2D_BUSP_DIVRATIO, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_NONSECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_NONSECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D0_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D0_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D0_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D1_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D1_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D1_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_NONSECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_NONSECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_PMU_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PMU_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PMU_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_P_G2D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_P_G2D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_P_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_G2D_JPEG_USER_BUSY, PLL_CON0_MUX_CLKCMU_G2D_JPEG_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_G2D_JPEG_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_M2MSCALER_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_M2MSCALER_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_M2MSCALER_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_NONSECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_NONSECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D2_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D2_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D2_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_G2D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_G2D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_G2D_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_G2D_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_G2D_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_G2D_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_G2D_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_G2D_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_JPEG_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_JPEG_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_JPEG_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BTM_G2DD0_QCH_ENABLE, QCH_CON_BTM_G2DD0_QCH_CLOCK_REQ, QCH_CON_BTM_G2DD0_QCH_EXPIRE_VAL, QCH_CON_BTM_G2DD1_QCH_ENABLE, QCH_CON_BTM_G2DD1_QCH_CLOCK_REQ, QCH_CON_BTM_G2DD1_QCH_EXPIRE_VAL, QCH_CON_BTM_G2DD2_QCH_ENABLE, QCH_CON_BTM_G2DD2_QCH_CLOCK_REQ, QCH_CON_BTM_G2DD2_QCH_EXPIRE_VAL, QCH_CON_G2D_QCH_ENABLE, QCH_CON_G2D_QCH_CLOCK_REQ, QCH_CON_G2D_QCH_EXPIRE_VAL, QCH_CON_G2D_CMU_G2D_QCH_ENABLE, QCH_CON_G2D_CMU_G2D_QCH_CLOCK_REQ, QCH_CON_G2D_CMU_G2D_QCH_EXPIRE_VAL, QCH_CON_JPEG_QCH_ENABLE, QCH_CON_JPEG_QCH_CLOCK_REQ, QCH_CON_JPEG_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_G2D_QCH_ENABLE, QCH_CON_LHM_AXI_P_G2D_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_G2D_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D0_G2D_QCH_ENABLE, QCH_CON_LHS_ACEL_D0_G2D_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D0_G2D_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D1_G2D_QCH_ENABLE, QCH_CON_LHS_ACEL_D1_G2D_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D1_G2D_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D2_G2D_QCH_ENABLE, QCH_CON_LHS_ACEL_D2_G2D_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D2_G2D_QCH_EXPIRE_VAL, QCH_CON_M2MSCALER_QCH_ENABLE, QCH_CON_M2MSCALER_QCH_CLOCK_REQ, QCH_CON_M2MSCALER_QCH_EXPIRE_VAL, QCH_CON_PMU_G2D_QCH_ENABLE, QCH_CON_PMU_G2D_QCH_CLOCK_REQ, QCH_CON_PMU_G2D_QCH_EXPIRE_VAL, QCH_CON_BCM_G2DD0_QCH_ENABLE, QCH_CON_BCM_G2DD0_QCH_CLOCK_REQ, QCH_CON_BCM_G2DD0_QCH_EXPIRE_VAL, QCH_CON_BCM_G2DD1_QCH_ENABLE, QCH_CON_BCM_G2DD1_QCH_CLOCK_REQ, QCH_CON_BCM_G2DD1_QCH_EXPIRE_VAL, QCH_CON_BCM_G2DD2_QCH_ENABLE, QCH_CON_BCM_G2DD2_QCH_CLOCK_REQ, QCH_CON_BCM_G2DD2_QCH_EXPIRE_VAL, QCH_CON_QE_JPEG_QCH_ENABLE, QCH_CON_QE_JPEG_QCH_CLOCK_REQ, QCH_CON_QE_JPEG_QCH_EXPIRE_VAL, QCH_CON_QE_M2MSCALER_QCH_ENABLE, QCH_CON_QE_M2MSCALER_QCH_CLOCK_REQ, QCH_CON_QE_M2MSCALER_QCH_EXPIRE_VAL, QCH_CON_SMMU_G2DD0_QCH_ENABLE, QCH_CON_SMMU_G2DD0_QCH_CLOCK_REQ, QCH_CON_SMMU_G2DD0_QCH_EXPIRE_VAL, QCH_CON_SMMU_G2DD1_QCH_ENABLE, QCH_CON_SMMU_G2DD1_QCH_CLOCK_REQ, QCH_CON_SMMU_G2DD1_QCH_EXPIRE_VAL, QCH_CON_SMMU_G2DD2_QCH_ENABLE, QCH_CON_SMMU_G2DD2_QCH_CLOCK_REQ, QCH_CON_SMMU_G2DD2_QCH_EXPIRE_VAL, QCH_CON_SYSREG_G2D_QCH_ENABLE, QCH_CON_SYSREG_G2D_QCH_CLOCK_REQ, QCH_CON_SYSREG_G2D_QCH_EXPIRE_VAL, CLK_CON_DIV_DIV_CLK_G3D_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_G3D_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_G3D_BUSP_DIVRATIO, CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_G3D_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_G3D_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_G3D_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_BUSY, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_G3D_BUSD_BUSY, CLK_CON_MUX_MUX_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_G3D_BUSD_SELECT, CLKOUT_CON_BLK_G3D_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_G3D_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_G3D_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_PMU_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_PMU_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_PMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_PLL_G3D_DIV_P, PLL_CON0_PLL_G3D_DIV_M, PLL_CON0_PLL_G3D_DIV_S, PLL_CON0_PLL_G3D_ENABLE, PLL_CON0_PLL_G3D_STABLE, PLL_LOCKTIME_PLL_G3D_PLL_LOCK_TIME, CLK_CON_GAT_GATE_CLK_G3D_AGPU_CG_VAL, CLK_CON_GAT_GATE_CLK_G3D_AGPU_MANUAL, CLK_CON_GAT_GATE_CLK_G3D_AGPU_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_AGPU_QCH_G3D_ENABLE, QCH_CON_AGPU_QCH_G3D_CLOCK_REQ, QCH_CON_AGPU_QCH_G3D_EXPIRE_VAL, QCH_CON_AGPU_QCH_LHM_AXI_G3DSFR_ENABLE, QCH_CON_AGPU_QCH_LHM_AXI_G3DSFR_CLOCK_REQ, QCH_CON_AGPU_QCH_LHM_AXI_G3DSFR_EXPIRE_VAL, QCH_CON_AGPU_QCH_LHS_ACE_D0_G3D_ENABLE, QCH_CON_AGPU_QCH_LHS_ACE_D0_G3D_CLOCK_REQ, QCH_CON_AGPU_QCH_LHS_ACE_D0_G3D_EXPIRE_VAL, QCH_CON_AGPU_QCH_LHS_ACE_D1_G3D_ENABLE, QCH_CON_AGPU_QCH_LHS_ACE_D1_G3D_CLOCK_REQ, QCH_CON_AGPU_QCH_LHS_ACE_D1_G3D_EXPIRE_VAL, QCH_CON_AGPU_QCH_LHS_ACE_D2_G3D_ENABLE, QCH_CON_AGPU_QCH_LHS_ACE_D2_G3D_CLOCK_REQ, QCH_CON_AGPU_QCH_LHS_ACE_D2_G3D_EXPIRE_VAL, QCH_CON_AGPU_QCH_LHS_ACE_D3_G3D_ENABLE, QCH_CON_AGPU_QCH_LHS_ACE_D3_G3D_CLOCK_REQ, QCH_CON_AGPU_QCH_LHS_ACE_D3_G3D_EXPIRE_VAL, QCH_CON_BUSIF_HPMG3D_QCH_ENABLE, QCH_CON_BUSIF_HPMG3D_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMG3D_QCH_EXPIRE_VAL, QCH_CON_G3D_CMU_G3D_QCH_ENABLE, QCH_CON_G3D_CMU_G3D_QCH_CLOCK_REQ, QCH_CON_G3D_CMU_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_G3D_QCH_ENABLE, QCH_CON_LHM_AXI_P_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_G3D_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_G3DSFR_QCH_ENABLE, QCH_CON_LHS_AXI_G3DSFR_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G3DSFR_QCH_EXPIRE_VAL, QCH_CON_PMU_G3D_QCH_ENABLE, QCH_CON_PMU_G3D_QCH_CLOCK_REQ, QCH_CON_PMU_G3D_QCH_EXPIRE_VAL, QCH_CON_SYSREG_G3D_QCH_ENABLE, QCH_CON_SYSREG_G3D_QCH_CLOCK_REQ, QCH_CON_SYSREG_G3D_QCH_EXPIRE_VAL, PLL_CON0_MUX_CLKCMU_IMEM_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_IMEM_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_IMEM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IMEM_UID_LHM_AXI_P_IMEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_LHM_AXI_P_IMEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_LHM_AXI_P_IMEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IMEM_UID_RSTNSYNC_CLK_IMEM_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_RSTNSYNC_CLK_IMEM_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_RSTNSYNC_CLK_IMEM_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IMEM_UID_AXI2APB_IMEM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_AXI2APB_IMEM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_AXI2APB_IMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IMEM_UID_XIU_P_IMEM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_XIU_P_IMEM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_XIU_P_IMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IMEM_UID_SYSREG_IMEM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_SYSREG_IMEM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_SYSREG_IMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IMEM_UID_PMU_IMEM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_PMU_IMEM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_PMU_IMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_IMEM_UID_IMEM_CMU_IMEM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_IMEM_UID_IMEM_CMU_IMEM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_IMEM_UID_IMEM_CMU_IMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_IMEM_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_IMEM_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_IMEM_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_IMEM_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_IMEM_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_IMEM_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IMEM_UID_INTMEM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_INTMEM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_INTMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_IMEM_CMU_IMEM_QCH_ENABLE, QCH_CON_IMEM_CMU_IMEM_QCH_CLOCK_REQ, QCH_CON_IMEM_CMU_IMEM_QCH_EXPIRE_VAL, QCH_CON_INTMEM_QCH_ENABLE, QCH_CON_INTMEM_QCH_CLOCK_REQ, QCH_CON_INTMEM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_IMEM_QCH_ENABLE, QCH_CON_LHM_AXI_P_IMEM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_IMEM_QCH_EXPIRE_VAL, QCH_CON_PMU_IMEM_QCH_ENABLE, QCH_CON_PMU_IMEM_QCH_CLOCK_REQ, QCH_CON_PMU_IMEM_QCH_EXPIRE_VAL, QCH_CON_SYSREG_IMEM_QCH_ENABLE, QCH_CON_SYSREG_IMEM_QCH_CLOCK_REQ, QCH_CON_SYSREG_IMEM_QCH_EXPIRE_VAL, PLL_CON0_MUX_CLKCMU_ISPHQ_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_ISPHQ_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_ISPHQ_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP_DIVRATIO, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_TAA_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_TAA_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_TAA_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHM_AXI_P_ISPHQ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHM_AXI_P_ISPHQ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHM_AXI_P_ISPHQ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHS_AXI_LD_ISPHQ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHS_AXI_LD_ISPHQ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHS_AXI_LD_ISPHQ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_ISPHQ_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_ISPHQ_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_ISPHQ_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_XIU_D_ISPHQ_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_XIU_D_ISPHQ_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_XIU_D_ISPHQ_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_AXI2APB_BRIDGE_ISPHQ_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_AXI2APB_BRIDGE_ISPHQ_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_AXI2APB_BRIDGE_ISPHQ_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_PMU_ISPHQ_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_PMU_ISPHQ_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_PMU_ISPHQ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_SYSREG_ISPHQ_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_SYSREG_ISPHQ_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_SYSREG_ISPHQ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_ISPHQ_UID_ISPHQ_CMU_ISPHQ_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ISPHQ_UID_ISPHQ_CMU_ISPHQ_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ISPHQ_UID_ISPHQ_CMU_ISPHQ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_ISP_EWGEN_ISPHQ_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_ISP_EWGEN_ISPHQ_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_ISP_EWGEN_ISPHQ_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_ISPHQ_CMU_ISPHQ_QCH_ENABLE, QCH_CON_ISPHQ_CMU_ISPHQ_QCH_CLOCK_REQ, QCH_CON_ISPHQ_CMU_ISPHQ_QCH_EXPIRE_VAL, QCH_CON_ISP_EWGEN_ISPHQ_QCH_ENABLE, QCH_CON_ISP_EWGEN_ISPHQ_QCH_CLOCK_REQ, QCH_CON_ISP_EWGEN_ISPHQ_QCH_EXPIRE_VAL, QCH_CON_IS_ISPHQ_QCH_3AA_ENABLE, QCH_CON_IS_ISPHQ_QCH_3AA_CLOCK_REQ, QCH_CON_IS_ISPHQ_QCH_3AA_EXPIRE_VAL, QCH_CON_IS_ISPHQ_QCH_ISPHQ_ENABLE, QCH_CON_IS_ISPHQ_QCH_ISPHQ_CLOCK_REQ, QCH_CON_IS_ISPHQ_QCH_ISPHQ_EXPIRE_VAL, QCH_CON_IS_ISPHQ_QCH_QE_3AA_ENABLE, QCH_CON_IS_ISPHQ_QCH_QE_3AA_CLOCK_REQ, QCH_CON_IS_ISPHQ_QCH_QE_3AA_EXPIRE_VAL, QCH_CON_IS_ISPHQ_QCH_QE_ISPHQ_ENABLE, QCH_CON_IS_ISPHQ_QCH_QE_ISPHQ_CLOCK_REQ, QCH_CON_IS_ISPHQ_QCH_QE_ISPHQ_EXPIRE_VAL, QCH_CON_LHM_AXI_P_ISPHQ_QCH_ENABLE, QCH_CON_LHM_AXI_P_ISPHQ_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_ISPHQ_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_LD_ISPHQ_QCH_ENABLE, QCH_CON_LHS_AXI_LD_ISPHQ_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_LD_ISPHQ_QCH_EXPIRE_VAL, QCH_CON_PMU_ISPHQ_QCH_ENABLE, QCH_CON_PMU_ISPHQ_QCH_CLOCK_REQ, QCH_CON_PMU_ISPHQ_QCH_EXPIRE_VAL, QCH_CON_SYSREG_ISPHQ_QCH_ENABLE, QCH_CON_SYSREG_ISPHQ_QCH_CLOCK_REQ, QCH_CON_SYSREG_ISPHQ_QCH_EXPIRE_VAL, PLL_CON0_MUX_CLKCMU_ISPLP_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_ISPLP_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_ISPLP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ISPLP_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_ISPLP_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ISPLP_BUSP_DIVRATIO, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_TAAW_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_TAAW_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_TAAW_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_P_ISPLP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_P_ISPLP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_P_ISPLP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHS_AXI_D_ISPLP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHS_AXI_D_ISPLP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHS_AXI_D_ISPLP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_ISPLP_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_ISPLP_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_ISPLP_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_XIU_D_ISPLP_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_XIU_D_ISPLP_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_XIU_D_ISPLP_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_NONSECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_NONSECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_PMU_ISPLP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_PMU_ISPLP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_PMU_ISPLP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_SYSREG_ISPLP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_SYSREG_ISPLP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_SYSREG_ISPLP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_AXI2APB_BRIDGE_ISPLP_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_AXI2APB_BRIDGE_ISPLP_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_AXI2APB_BRIDGE_ISPLP_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_ISPLP_UID_ISPLP_CMU_ISPLP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ISPLP_UID_ISPLP_CMU_ISPLP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ISPLP_UID_ISPLP_CMU_ISPLP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_LD_ISPHQ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_LD_ISPHQ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_LD_ISPHQ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_ISP_EWGEN_ISPLP_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_ISP_EWGEN_ISPLP_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_ISP_EWGEN_ISPLP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_ACLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BTM_ISPLP_QCH_ENABLE, QCH_CON_BTM_ISPLP_QCH_CLOCK_REQ, QCH_CON_BTM_ISPLP_QCH_EXPIRE_VAL, QCH_CON_ISPLP_CMU_ISPLP_QCH_ENABLE, QCH_CON_ISPLP_CMU_ISPLP_QCH_CLOCK_REQ, QCH_CON_ISPLP_CMU_ISPLP_QCH_EXPIRE_VAL, QCH_CON_ISP_EWGEN_ISPLP_QCH_ENABLE, QCH_CON_ISP_EWGEN_ISPLP_QCH_CLOCK_REQ, QCH_CON_ISP_EWGEN_ISPLP_QCH_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_3AAW_ENABLE, QCH_CON_IS_ISPLP_QCH_3AAW_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_3AAW_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_ISPLP_ENABLE, QCH_CON_IS_ISPLP_QCH_ISPLP_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_ISPLP_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_QE_3AAW_ENABLE, QCH_CON_IS_ISPLP_QCH_QE_3AAW_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_QE_3AAW_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_QE_ISPLP_ENABLE, QCH_CON_IS_ISPLP_QCH_QE_ISPLP_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_QE_ISPLP_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_SMMU_ISPLP_ENABLE, QCH_CON_IS_ISPLP_QCH_SMMU_ISPLP_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_SMMU_ISPLP_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_BCM_ISPLP_ENABLE, QCH_CON_IS_ISPLP_QCH_BCM_ISPLP_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_BCM_ISPLP_EXPIRE_VAL, QCH_CON_LHM_AXI_LD_ISPHQ_QCH_ENABLE, QCH_CON_LHM_AXI_LD_ISPHQ_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_LD_ISPHQ_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_ISPLP_QCH_ENABLE, QCH_CON_LHM_AXI_P_ISPLP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_ISPLP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_ISPLP_QCH_ENABLE, QCH_CON_LHS_AXI_D_ISPLP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_ISPLP_QCH_EXPIRE_VAL, QCH_CON_PMU_ISPLP_QCH_ENABLE, QCH_CON_PMU_ISPLP_QCH_CLOCK_REQ, QCH_CON_PMU_ISPLP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_ISPLP_QCH_ENABLE, QCH_CON_SYSREG_ISPLP_QCH_CLOCK_REQ, QCH_CON_SYSREG_ISPLP_QCH_EXPIRE_VAL, PLL_CON0_MUX_CLKCMU_IVA_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_IVA_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_IVA_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_IVA_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_IVA_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_IVA_BUSP_DIVRATIO, CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_IVA_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_IVA_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_IVA_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_IVA_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_IVA_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_IVA_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_ACEL_D_IVA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_ACEL_D_IVA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_ACEL_D_IVA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_D_IVADSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_D_IVADSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_D_IVADSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_P_IVADSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_P_IVADSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_P_IVADSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_DSPIVA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_DSPIVA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_DSPIVA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_D_IVA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_D_IVA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_D_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IVA_UID_PMU_IVA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_PMU_IVA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_PMU_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_CLK_A_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_CLK_A_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_CLK_A_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_INTMEM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_INTMEM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_INTMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_D_IVASC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_D_IVASC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_D_IVASC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BTM_IVA_QCH_ENABLE, QCH_CON_BTM_IVA_QCH_CLOCK_REQ, QCH_CON_BTM_IVA_QCH_EXPIRE_VAL, QCH_CON_IVA_QCH_ENABLE, QCH_CON_IVA_QCH_CLOCK_REQ, QCH_CON_IVA_QCH_EXPIRE_VAL, QCH_CON_IVA_CMU_IVA_QCH_ENABLE, QCH_CON_IVA_CMU_IVA_QCH_CLOCK_REQ, QCH_CON_IVA_CMU_IVA_QCH_EXPIRE_VAL, QCH_CON_IVA_INTMEM_QCH_ENABLE, QCH_CON_IVA_INTMEM_QCH_CLOCK_REQ, QCH_CON_IVA_INTMEM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_IVASC_QCH_ENABLE, QCH_CON_LHM_AXI_D_IVASC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_IVASC_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_DSPIVA_QCH_ENABLE, QCH_CON_LHM_AXI_P_DSPIVA_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DSPIVA_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_IVA_QCH_ENABLE, QCH_CON_LHM_AXI_P_IVA_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_IVA_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_IVA_QCH_ENABLE, QCH_CON_LHS_ACEL_D_IVA_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_IVA_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_IVADSP_QCH_ENABLE, QCH_CON_LHS_AXI_D_IVADSP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_IVADSP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_IVADSP_QCH_ENABLE, QCH_CON_LHS_AXI_P_IVADSP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_IVADSP_QCH_EXPIRE_VAL, QCH_CON_PMU_IVA_QCH_ENABLE, QCH_CON_PMU_IVA_QCH_CLOCK_REQ, QCH_CON_PMU_IVA_QCH_EXPIRE_VAL, QCH_CON_BCM_IVA_QCH_ENABLE, QCH_CON_BCM_IVA_QCH_CLOCK_REQ, QCH_CON_BCM_IVA_QCH_EXPIRE_VAL, QCH_CON_SMMU_IVA_QCH_ENABLE, QCH_CON_SMMU_IVA_QCH_CLOCK_REQ, QCH_CON_SMMU_IVA_QCH_EXPIRE_VAL, QCH_CON_SYSREG_IVA_QCH_ENABLE, QCH_CON_SYSREG_IVA_QCH_CLOCK_REQ, QCH_CON_SYSREG_IVA_QCH_EXPIRE_VAL, PLL_CON0_MUX_CLKCMU_MFC_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_MFC_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_MFC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_MFC_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MFC_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_MFC_BUSP_DIVRATIO, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_AXI2APB_MFC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AXI2APB_MFC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AXI2APB_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_PMU_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PMU_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PMU_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D0_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D0_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D0_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D1_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D1_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D1_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_MFC_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_MFC_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_MFC_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_NONSECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_NONSECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_NONSECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_NONSECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_MFC_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_MFC_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_MFC_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BTM_MFCD0_QCH_ENABLE, QCH_CON_BTM_MFCD0_QCH_CLOCK_REQ, QCH_CON_BTM_MFCD0_QCH_EXPIRE_VAL, QCH_CON_BTM_MFCD1_QCH_ENABLE, QCH_CON_BTM_MFCD1_QCH_CLOCK_REQ, QCH_CON_BTM_MFCD1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_MFC_QCH_ENABLE, QCH_CON_LHM_AXI_P_MFC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MFC_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_MFC_QCH_ENABLE, QCH_CON_LHS_AXI_D0_MFC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_MFC_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_MFC_QCH_ENABLE, QCH_CON_LHS_AXI_D1_MFC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_MFC_QCH_EXPIRE_VAL, QCH_CON_MFC_QCH_ENABLE, QCH_CON_MFC_QCH_CLOCK_REQ, QCH_CON_MFC_QCH_EXPIRE_VAL, QCH_CON_MFC_CMU_MFC_QCH_ENABLE, QCH_CON_MFC_CMU_MFC_QCH_CLOCK_REQ, QCH_CON_MFC_CMU_MFC_QCH_EXPIRE_VAL, QCH_CON_PMU_MFC_QCH_ENABLE, QCH_CON_PMU_MFC_QCH_CLOCK_REQ, QCH_CON_PMU_MFC_QCH_EXPIRE_VAL, QCH_CON_BCM_MFCD0_QCH_ENABLE, QCH_CON_BCM_MFCD0_QCH_CLOCK_REQ, QCH_CON_BCM_MFCD0_QCH_EXPIRE_VAL, QCH_CON_BCM_MFCD1_QCH_ENABLE, QCH_CON_BCM_MFCD1_QCH_CLOCK_REQ, QCH_CON_BCM_MFCD1_QCH_EXPIRE_VAL, QCH_CON_SMMU_MFCD0_QCH_ENABLE, QCH_CON_SMMU_MFCD0_QCH_CLOCK_REQ, QCH_CON_SMMU_MFCD0_QCH_EXPIRE_VAL, QCH_CON_SMMU_MFCD1_QCH_ENABLE, QCH_CON_SMMU_MFCD1_QCH_CLOCK_REQ, QCH_CON_SMMU_MFCD1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MFC_QCH_ENABLE, QCH_CON_SYSREG_MFC_QCH_CLOCK_REQ, QCH_CON_SYSREG_MFC_QCH_EXPIRE_VAL, PLL_CON0_PLL_MIF_DIV_P, PLL_CON0_PLL_MIF_DIV_M, PLL_CON0_PLL_MIF_DIV_S, PLL_CON0_PLL_MIF_ENABLE, PLL_CON0_PLL_MIF_STABLE, PLL_LOCKTIME_PLL_MIF_PLL_LOCK_TIME, CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X_BUSY, CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X_SELECT, CLK_CON_DIV_CLK_MIF_BUSD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_MIF_PRE_BUSY, CLK_CON_DIV_DIV_CLK_MIF_PRE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_MIF_PRE_DIVRATIO, CLK_CON_DIV_DIV_CLK_MIF_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_MIF_BUSP_DIVRATIO, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_PMU_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PMU_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PMU_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_MIF_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_MIF_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_MIF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMCTZ_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMCTZ_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMCTZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_MIF_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_MIF_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_MIF_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK1_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK2_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_SOC_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_SOC_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_SOC_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_PSCDC_D_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_PSCDC_D_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_PSCDC_D_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_MIF_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_MIF_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_MIF_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_MIF_CMUREF_BUSY, CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_MIF_CMUREF_SELECT, QCH_CON_APBBR_DDRPHY_QCH_ENABLE, QCH_CON_APBBR_DDRPHY_QCH_CLOCK_REQ, QCH_CON_APBBR_DDRPHY_QCH_EXPIRE_VAL, QCH_CON_APBBR_DMC_QCH_ENABLE, QCH_CON_APBBR_DMC_QCH_CLOCK_REQ, QCH_CON_APBBR_DMC_QCH_EXPIRE_VAL, QCH_CON_APBBR_DMCTZ_QCH_ENABLE, QCH_CON_APBBR_DMCTZ_QCH_CLOCK_REQ, QCH_CON_APBBR_DMCTZ_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMMIF_QCH_ENABLE, QCH_CON_BUSIF_HPMMIF_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMMIF_QCH_EXPIRE_VAL, DMYQCH_CON_CMU_MIF_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_MIF_CMUREF_QCH_CLOCK_REQ, QCH_CON_DDRPHY_QCH_ENABLE, QCH_CON_DDRPHY_QCH_CLOCK_REQ, QCH_CON_DDRPHY_QCH_EXPIRE_VAL, QCH_CON_DMC_QCH_ENABLE, QCH_CON_DMC_QCH_CLOCK_REQ, QCH_CON_DMC_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_MIF_QCH_ENABLE, QCH_CON_LHM_AXI_P_MIF_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MIF_QCH_EXPIRE_VAL, QCH_CON_MIF_CMU_MIF_QCH_ENABLE, QCH_CON_MIF_CMU_MIF_QCH_CLOCK_REQ, QCH_CON_MIF_CMU_MIF_QCH_EXPIRE_VAL, QCH_CON_PMU_MIF_QCH_ENABLE, QCH_CON_PMU_MIF_QCH_CLOCK_REQ, QCH_CON_PMU_MIF_QCH_EXPIRE_VAL, QCH_CON_BCMPPC_DEBUG_QCH_ENABLE, QCH_CON_BCMPPC_DEBUG_QCH_CLOCK_REQ, QCH_CON_BCMPPC_DEBUG_QCH_EXPIRE_VAL, QCH_CON_BCMPPC_DVFS_QCH_ENABLE, QCH_CON_BCMPPC_DVFS_QCH_CLOCK_REQ, QCH_CON_BCMPPC_DVFS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MIF_QCH_ENABLE, QCH_CON_SYSREG_MIF_QCH_CLOCK_REQ, QCH_CON_SYSREG_MIF_QCH_EXPIRE_VAL, CLKOUT_CON_BLK_MIF1_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_MIF1_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_MIF1_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_MIF1_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_MIF1_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_MIF1_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_MIF1_CMUREF_BUSY, CLK_CON_MUX_MUX_MIF1_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_MIF1_CMUREF_SELECT, CLK_CON_DIV_DIV_CLK_MIF1_PRE_BUSY, CLK_CON_DIV_DIV_CLK_MIF1_PRE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_MIF1_PRE_DIVRATIO, CLK_CON_DIV_CLK_MIF1_BUSD_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_PLL_MIF1_DIV_P, PLL_CON0_PLL_MIF1_DIV_M, PLL_CON0_PLL_MIF1_DIV_S, PLL_CON0_PLL_MIF1_ENABLE, PLL_CON0_PLL_MIF1_STABLE, PLL_LOCKTIME_PLL_MIF1_PLL_LOCK_TIME, CLK_CON_MUX_CLKMUX_MIF1_DDRPHY2X_BUSY, CLK_CON_MUX_CLKMUX_MIF1_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_CLKMUX_MIF1_DDRPHY2X_SELECT, CLK_CON_DIV_DIV_CLK_MIF1_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MIF1_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_MIF1_BUSP_DIVRATIO, CLK_CON_GAT_CLK_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DDRPHY1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DDRPHY1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DDRPHY1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMCTZ1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMCTZ1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMCTZ1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_AXI2APB_MIF1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_AXI2APB_MIF1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_AXI2APB_MIF1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DDRPHY1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DDRPHY1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DDRPHY1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK1_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK2_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_P_MIF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_P_MIF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_P_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_PMU_MIF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_PMU_MIF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_PMU_MIF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_SYSREG_MIF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_SYSREG_MIF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_SYSREG_MIF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSP1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSP1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSP1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF1_UID_DMC1_IPCLKPORT_SOC_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_DMC1_IPCLKPORT_SOC_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_DMC1_IPCLKPORT_SOC_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF1_UID_LHM_PSCDC_D_MIF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_LHM_PSCDC_D_MIF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_LHM_PSCDC_D_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSD1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSD1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSD1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_APBBR_DDRPHY1_QCH_ENABLE, QCH_CON_APBBR_DDRPHY1_QCH_CLOCK_REQ, QCH_CON_APBBR_DDRPHY1_QCH_EXPIRE_VAL, QCH_CON_APBBR_DMC1_QCH_ENABLE, QCH_CON_APBBR_DMC1_QCH_CLOCK_REQ, QCH_CON_APBBR_DMC1_QCH_EXPIRE_VAL, QCH_CON_APBBR_DMCTZ1_QCH_ENABLE, QCH_CON_APBBR_DMCTZ1_QCH_CLOCK_REQ, QCH_CON_APBBR_DMCTZ1_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMMIF1_QCH_ENABLE, QCH_CON_BUSIF_HPMMIF1_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMMIF1_QCH_EXPIRE_VAL, DMYQCH_CON_CMU_MIF1_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_MIF1_CMUREF_QCH_CLOCK_REQ, QCH_CON_DDRPHY1_QCH_ENABLE, QCH_CON_DDRPHY1_QCH_CLOCK_REQ, QCH_CON_DDRPHY1_QCH_EXPIRE_VAL, QCH_CON_DMC1_QCH_ENABLE, QCH_CON_DMC1_QCH_CLOCK_REQ, QCH_CON_DMC1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_MIF1_QCH_ENABLE, QCH_CON_LHM_AXI_P_MIF1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MIF1_QCH_EXPIRE_VAL, QCH_CON_MIF1_CMU_MIF1_QCH_ENABLE, QCH_CON_MIF1_CMU_MIF1_QCH_CLOCK_REQ, QCH_CON_MIF1_CMU_MIF1_QCH_EXPIRE_VAL, QCH_CON_PMU_MIF1_QCH_ENABLE, QCH_CON_PMU_MIF1_QCH_CLOCK_REQ, QCH_CON_PMU_MIF1_QCH_EXPIRE_VAL, QCH_CON_BCMPPC_DEBUG1_QCH_ENABLE, QCH_CON_BCMPPC_DEBUG1_QCH_CLOCK_REQ, QCH_CON_BCMPPC_DEBUG1_QCH_EXPIRE_VAL, QCH_CON_BCMPPC_DVFS1_QCH_ENABLE, QCH_CON_BCMPPC_DVFS1_QCH_CLOCK_REQ, QCH_CON_BCMPPC_DVFS1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MIF1_QCH_ENABLE, QCH_CON_SYSREG_MIF1_QCH_CLOCK_REQ, QCH_CON_SYSREG_MIF1_QCH_EXPIRE_VAL, CLKOUT_CON_BLK_MIF2_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_MIF2_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_MIF2_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_MIF2_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_MIF2_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_MIF2_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_MIF2_CMUREF_BUSY, CLK_CON_MUX_MUX_MIF2_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_MIF2_CMUREF_SELECT, CLK_CON_DIV_DIV_CLK_MIF2_PRE_BUSY, CLK_CON_DIV_DIV_CLK_MIF2_PRE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_MIF2_PRE_DIVRATIO, CLK_CON_DIV_CLK_MIF2_BUSD_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_PLL_MIF2_DIV_P, PLL_CON0_PLL_MIF2_DIV_M, PLL_CON0_PLL_MIF2_DIV_S, PLL_CON0_PLL_MIF2_ENABLE, PLL_CON0_PLL_MIF2_STABLE, PLL_LOCKTIME_PLL_MIF2_PLL_LOCK_TIME, CLK_CON_MUX_CLKMUX_MIF2_DDRPHY2X_BUSY, CLK_CON_MUX_CLKMUX_MIF2_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_CLKMUX_MIF2_DDRPHY2X_SELECT, CLK_CON_DIV_DIV_CLK_MIF2_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MIF2_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_MIF2_BUSP_DIVRATIO, CLK_CON_GAT_CLK_BLK_MIF2_UID_MIF2_CMU_MIF2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_MIF2_CMU_MIF2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_MIF2_CMU_MIF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF2_UID_HPM_MIF2_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_HPM_MIF2_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_HPM_MIF2_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DDRPHY2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DDRPHY2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DDRPHY2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMC2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMC2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMCTZ2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMCTZ2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMCTZ2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF2_UID_AXI2APB_MIF2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_AXI2APB_MIF2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_AXI2APB_MIF2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BUSIF_HPMMIF2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BUSIF_HPMMIF2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BUSIF_HPMMIF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DDRPHY2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DDRPHY2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DDRPHY2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK1_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK2_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF2_UID_LHM_AXI_P_MIF2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_LHM_AXI_P_MIF2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_LHM_AXI_P_MIF2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF2_UID_PMU_MIF2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_PMU_MIF2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_PMU_MIF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSP2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSP2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSP2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF2_UID_SYSREG_MIF2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_SYSREG_MIF2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_SYSREG_MIF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF2_UID_DMC2_IPCLKPORT_SOC_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_DMC2_IPCLKPORT_SOC_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_DMC2_IPCLKPORT_SOC_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF2_UID_LHM_PSCDC_D_MIF2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_LHM_PSCDC_D_MIF2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_LHM_PSCDC_D_MIF2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSD2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSD2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSD2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_APBBR_DDRPHY2_QCH_ENABLE, QCH_CON_APBBR_DDRPHY2_QCH_CLOCK_REQ, QCH_CON_APBBR_DDRPHY2_QCH_EXPIRE_VAL, QCH_CON_APBBR_DMC2_QCH_ENABLE, QCH_CON_APBBR_DMC2_QCH_CLOCK_REQ, QCH_CON_APBBR_DMC2_QCH_EXPIRE_VAL, QCH_CON_APBBR_DMCTZ2_QCH_ENABLE, QCH_CON_APBBR_DMCTZ2_QCH_CLOCK_REQ, QCH_CON_APBBR_DMCTZ2_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMMIF2_QCH_ENABLE, QCH_CON_BUSIF_HPMMIF2_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMMIF2_QCH_EXPIRE_VAL, DMYQCH_CON_CMU_MIF2_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_MIF2_CMUREF_QCH_CLOCK_REQ, QCH_CON_DDRPHY2_QCH_ENABLE, QCH_CON_DDRPHY2_QCH_CLOCK_REQ, QCH_CON_DDRPHY2_QCH_EXPIRE_VAL, QCH_CON_DMC2_QCH_ENABLE, QCH_CON_DMC2_QCH_CLOCK_REQ, QCH_CON_DMC2_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_MIF2_QCH_ENABLE, QCH_CON_LHM_AXI_P_MIF2_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MIF2_QCH_EXPIRE_VAL, QCH_CON_MIF2_CMU_MIF2_QCH_ENABLE, QCH_CON_MIF2_CMU_MIF2_QCH_CLOCK_REQ, QCH_CON_MIF2_CMU_MIF2_QCH_EXPIRE_VAL, QCH_CON_PMU_MIF2_QCH_ENABLE, QCH_CON_PMU_MIF2_QCH_CLOCK_REQ, QCH_CON_PMU_MIF2_QCH_EXPIRE_VAL, QCH_CON_BCMPPC_DEBUG2_QCH_ENABLE, QCH_CON_BCMPPC_DEBUG2_QCH_CLOCK_REQ, QCH_CON_BCMPPC_DEBUG2_QCH_EXPIRE_VAL, QCH_CON_BCMPPC_DVFS2_QCH_ENABLE, QCH_CON_BCMPPC_DVFS2_QCH_CLOCK_REQ, QCH_CON_BCMPPC_DVFS2_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MIF2_QCH_ENABLE, QCH_CON_SYSREG_MIF2_QCH_CLOCK_REQ, QCH_CON_SYSREG_MIF2_QCH_EXPIRE_VAL, CLKOUT_CON_BLK_MIF3_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_MIF3_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_MIF3_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_MIF3_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_MIF3_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_MIF3_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_MIF3_CMUREF_BUSY, CLK_CON_MUX_MUX_MIF3_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_MIF3_CMUREF_SELECT, CLK_CON_DIV_DIV_CLK_MIF3_PRE_BUSY, CLK_CON_DIV_DIV_CLK_MIF3_PRE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_MIF3_PRE_DIVRATIO, CLK_CON_DIV_CLK_MIF3_BUSD_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_PLL_MIF3_DIV_P, PLL_CON0_PLL_MIF3_DIV_M, PLL_CON0_PLL_MIF3_DIV_S, PLL_CON0_PLL_MIF3_ENABLE, PLL_CON0_PLL_MIF3_STABLE, PLL_LOCKTIME_PLL_MIF3_PLL_LOCK_TIME, CLK_CON_MUX_CLKMUX_MIF3_DDRPHY2X_BUSY, CLK_CON_MUX_CLKMUX_MIF3_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_CLKMUX_MIF3_DDRPHY2X_SELECT, CLK_CON_DIV_DIV_CLK_MIF3_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MIF3_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_MIF3_BUSP_DIVRATIO, CLK_CON_GAT_CLK_BLK_MIF3_UID_HPM_MIF3_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF3_UID_HPM_MIF3_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_MIF3_UID_HPM_MIF3_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DDRPHY3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DDRPHY3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DDRPHY3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMC3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMC3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMC3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMCTZ3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMCTZ3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMCTZ3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF3_UID_AXI2APB_MIF3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_AXI2APB_MIF3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_AXI2APB_MIF3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BUSIF_HPMMIF3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BUSIF_HPMMIF3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BUSIF_HPMMIF3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DDRPHY3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DDRPHY3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DDRPHY3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK1_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF3_UID_LHM_AXI_P_MIF3_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_LHM_AXI_P_MIF3_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_LHM_AXI_P_MIF3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF3_UID_PMU_MIF3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_PMU_MIF3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_PMU_MIF3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSP3_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSP3_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSP3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF3_UID_SYSREG_MIF3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_SYSREG_MIF3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_SYSREG_MIF3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK2_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF3_UID_MIF3_CMU_MIF3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF3_UID_MIF3_CMU_MIF3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF3_UID_MIF3_CMU_MIF3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF3_UID_DMC3_IPCLKPORT_SOC_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF3_UID_DMC3_IPCLKPORT_SOC_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF3_UID_DMC3_IPCLKPORT_SOC_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF3_UID_LHM_PSCDC_D_MIF3_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF3_UID_LHM_PSCDC_D_MIF3_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF3_UID_LHM_PSCDC_D_MIF3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSD3_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSD3_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSD3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_APBBR_DDRPHY3_QCH_ENABLE, QCH_CON_APBBR_DDRPHY3_QCH_CLOCK_REQ, QCH_CON_APBBR_DDRPHY3_QCH_EXPIRE_VAL, QCH_CON_APBBR_DMC3_QCH_ENABLE, QCH_CON_APBBR_DMC3_QCH_CLOCK_REQ, QCH_CON_APBBR_DMC3_QCH_EXPIRE_VAL, QCH_CON_APBBR_DMCTZ3_QCH_ENABLE, QCH_CON_APBBR_DMCTZ3_QCH_CLOCK_REQ, QCH_CON_APBBR_DMCTZ3_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMMIF3_QCH_ENABLE, QCH_CON_BUSIF_HPMMIF3_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMMIF3_QCH_EXPIRE_VAL, DMYQCH_CON_CMU_MIF3_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_MIF3_CMUREF_QCH_CLOCK_REQ, QCH_CON_DDRPHY3_QCH_ENABLE, QCH_CON_DDRPHY3_QCH_CLOCK_REQ, QCH_CON_DDRPHY3_QCH_EXPIRE_VAL, QCH_CON_DMC3_QCH_ENABLE, QCH_CON_DMC3_QCH_CLOCK_REQ, QCH_CON_DMC3_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_MIF3_QCH_ENABLE, QCH_CON_LHM_AXI_P_MIF3_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MIF3_QCH_EXPIRE_VAL, QCH_CON_MIF3_CMU_MIF3_QCH_ENABLE, QCH_CON_MIF3_CMU_MIF3_QCH_CLOCK_REQ, QCH_CON_MIF3_CMU_MIF3_QCH_EXPIRE_VAL, QCH_CON_PMU_MIF3_QCH_ENABLE, QCH_CON_PMU_MIF3_QCH_CLOCK_REQ, QCH_CON_PMU_MIF3_QCH_EXPIRE_VAL, QCH_CON_BCMPPC_DEBUG3_QCH_ENABLE, QCH_CON_BCMPPC_DEBUG3_QCH_CLOCK_REQ, QCH_CON_BCMPPC_DEBUG3_QCH_EXPIRE_VAL, QCH_CON_BCMPPC_DVFS3_QCH_ENABLE, QCH_CON_BCMPPC_DVFS3_QCH_CLOCK_REQ, QCH_CON_BCMPPC_DVFS3_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MIF3_QCH_ENABLE, QCH_CON_SYSREG_MIF3_QCH_CLOCK_REQ, QCH_CON_SYSREG_MIF3_QCH_EXPIRE_VAL, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERIC0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PMU_PERIC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PMU_PERIC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PMU_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERIC0_UART_DBG_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERIC0_USI00_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERIC0_USI01_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERIC0_USI02_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERIC0_USI03_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_EXT_UCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_EXT_UCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_EXT_UCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SPEEDY2_TSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SPEEDY2_TSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SPEEDY2_TSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_GPIO_PERIC0_QCH_ENABLE, QCH_CON_GPIO_PERIC0_QCH_CLOCK_REQ, QCH_CON_GPIO_PERIC0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_PERIC0_QCH_ENABLE, QCH_CON_LHM_AXI_P_PERIC0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_PERIC0_QCH_EXPIRE_VAL, QCH_CON_PERIC0_CMU_PERIC0_QCH_ENABLE, QCH_CON_PERIC0_CMU_PERIC0_QCH_CLOCK_REQ, QCH_CON_PERIC0_CMU_PERIC0_QCH_EXPIRE_VAL, QCH_CON_PMU_PERIC0_QCH_ENABLE, QCH_CON_PMU_PERIC0_QCH_CLOCK_REQ, QCH_CON_PMU_PERIC0_QCH_EXPIRE_VAL, QCH_CON_PWM_QCH_ENABLE, QCH_CON_PWM_QCH_CLOCK_REQ, QCH_CON_PWM_QCH_EXPIRE_VAL, QCH_CON_SPEEDY2_TSP_QCH_ENABLE, QCH_CON_SPEEDY2_TSP_QCH_CLOCK_REQ, QCH_CON_SPEEDY2_TSP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_PERIC0_QCH_ENABLE, QCH_CON_SYSREG_PERIC0_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERIC0_QCH_EXPIRE_VAL, QCH_CON_UART_DBG_QCH_ENABLE, QCH_CON_UART_DBG_QCH_CLOCK_REQ, QCH_CON_UART_DBG_QCH_EXPIRE_VAL, QCH_CON_USI00_QCH_ENABLE, QCH_CON_USI00_QCH_CLOCK_REQ, QCH_CON_USI00_QCH_EXPIRE_VAL, QCH_CON_USI01_QCH_ENABLE, QCH_CON_USI01_QCH_CLOCK_REQ, QCH_CON_USI01_QCH_EXPIRE_VAL, QCH_CON_USI02_QCH_ENABLE, QCH_CON_USI02_QCH_CLOCK_REQ, QCH_CON_USI02_QCH_EXPIRE_VAL, QCH_CON_USI03_QCH_ENABLE, QCH_CON_USI03_QCH_CLOCK_REQ, QCH_CON_USI03_QCH_EXPIRE_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PMU_PERIC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PMU_PERIC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PMU_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERIC1_UART_BT_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_PERIC1_USI05_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERIC1_USI05_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERIC1_USI05_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERIC1_USI06_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERIC1_USI07_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERIC1_USI08_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERIC1_USI09_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERIC1_USI10_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERIC1_USI11_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERIC1_USI12_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERIC1_USI13_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_EXT_UCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_EXT_UCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_EXT_UCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERIC1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_PERIC1_USI04_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERIC1_USI04_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERIC1_USI04_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM2_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM2_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM3_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM3_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM0_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM0_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERIC1_SPI_CAM0_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM1_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM1_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERIC1_SPI_CAM1_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_SPI_EXT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_SPI_EXT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_SPI_EXT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_SPI_EXT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_SPI_EXT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_SPI_EXT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM1_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM1_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_PERIC1_SPEEDY2_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERIC1_SPEEDY2_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERIC1_SPEEDY2_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_SCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_SCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPEEDY2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPEEDY2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPEEDY2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_SCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_SCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_SCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_SCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_GPIO_PERIC1_QCH_ENABLE, QCH_CON_GPIO_PERIC1_QCH_CLOCK_REQ, QCH_CON_GPIO_PERIC1_QCH_EXPIRE_VAL, QCH_CON_HSI2C_CAM0_QCH_ENABLE, QCH_CON_HSI2C_CAM0_QCH_CLOCK_REQ, QCH_CON_HSI2C_CAM0_QCH_EXPIRE_VAL, QCH_CON_HSI2C_CAM1_QCH_ENABLE, QCH_CON_HSI2C_CAM1_QCH_CLOCK_REQ, QCH_CON_HSI2C_CAM1_QCH_EXPIRE_VAL, QCH_CON_HSI2C_CAM2_QCH_ENABLE, QCH_CON_HSI2C_CAM2_QCH_CLOCK_REQ, QCH_CON_HSI2C_CAM2_QCH_EXPIRE_VAL, QCH_CON_HSI2C_CAM3_QCH_ENABLE, QCH_CON_HSI2C_CAM3_QCH_CLOCK_REQ, QCH_CON_HSI2C_CAM3_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_PERIC1_QCH_ENABLE, QCH_CON_LHM_AXI_P_PERIC1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_PERIC1_QCH_EXPIRE_VAL, QCH_CON_PERIC1_CMU_PERIC1_QCH_ENABLE, QCH_CON_PERIC1_CMU_PERIC1_QCH_CLOCK_REQ, QCH_CON_PERIC1_CMU_PERIC1_QCH_EXPIRE_VAL, QCH_CON_PMU_PERIC1_QCH_ENABLE, QCH_CON_PMU_PERIC1_QCH_CLOCK_REQ, QCH_CON_PMU_PERIC1_QCH_EXPIRE_VAL, QCH_CON_SPEEDY2_DDI_QCH_ENABLE, QCH_CON_SPEEDY2_DDI_QCH_CLOCK_REQ, QCH_CON_SPEEDY2_DDI_QCH_EXPIRE_VAL, QCH_CON_SPEEDY2_DDI1_QCH_ENABLE, QCH_CON_SPEEDY2_DDI1_QCH_CLOCK_REQ, QCH_CON_SPEEDY2_DDI1_QCH_EXPIRE_VAL, QCH_CON_SPEEDY2_DDI2_QCH_ENABLE, QCH_CON_SPEEDY2_DDI2_QCH_CLOCK_REQ, QCH_CON_SPEEDY2_DDI2_QCH_EXPIRE_VAL, QCH_CON_SPEEDY2_TSP1_QCH_ENABLE, QCH_CON_SPEEDY2_TSP1_QCH_CLOCK_REQ, QCH_CON_SPEEDY2_TSP1_QCH_EXPIRE_VAL, QCH_CON_SPEEDY2_TSP2_QCH_ENABLE, QCH_CON_SPEEDY2_TSP2_QCH_CLOCK_REQ, QCH_CON_SPEEDY2_TSP2_QCH_EXPIRE_VAL, QCH_CON_SPI_CAM0_QCH_ENABLE, QCH_CON_SPI_CAM0_QCH_CLOCK_REQ, QCH_CON_SPI_CAM0_QCH_EXPIRE_VAL, QCH_CON_SPI_CAM1_QCH_ENABLE, QCH_CON_SPI_CAM1_QCH_CLOCK_REQ, QCH_CON_SPI_CAM1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_PERIC1_QCH_ENABLE, QCH_CON_SYSREG_PERIC1_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERIC1_QCH_EXPIRE_VAL, QCH_CON_UART_BT_QCH_ENABLE, QCH_CON_UART_BT_QCH_CLOCK_REQ, QCH_CON_UART_BT_QCH_EXPIRE_VAL, QCH_CON_USI04_QCH_ENABLE, QCH_CON_USI04_QCH_CLOCK_REQ, QCH_CON_USI04_QCH_EXPIRE_VAL, QCH_CON_USI05_QCH_ENABLE, QCH_CON_USI05_QCH_CLOCK_REQ, QCH_CON_USI05_QCH_EXPIRE_VAL, QCH_CON_USI06_QCH_ENABLE, QCH_CON_USI06_QCH_CLOCK_REQ, QCH_CON_USI06_QCH_EXPIRE_VAL, QCH_CON_USI07_QCH_ENABLE, QCH_CON_USI07_QCH_CLOCK_REQ, QCH_CON_USI07_QCH_EXPIRE_VAL, QCH_CON_USI08_QCH_ENABLE, QCH_CON_USI08_QCH_CLOCK_REQ, QCH_CON_USI08_QCH_EXPIRE_VAL, QCH_CON_USI09_QCH_ENABLE, QCH_CON_USI09_QCH_CLOCK_REQ, QCH_CON_USI09_QCH_EXPIRE_VAL, QCH_CON_USI10_QCH_ENABLE, QCH_CON_USI10_QCH_CLOCK_REQ, QCH_CON_USI10_QCH_EXPIRE_VAL, QCH_CON_USI11_QCH_ENABLE, QCH_CON_USI11_QCH_CLOCK_REQ, QCH_CON_USI11_QCH_EXPIRE_VAL, QCH_CON_USI12_QCH_ENABLE, QCH_CON_USI12_QCH_CLOCK_REQ, QCH_CON_USI12_QCH_EXPIRE_VAL, QCH_CON_USI13_QCH_ENABLE, QCH_CON_USI13_QCH_CLOCK_REQ, QCH_CON_USI13_QCH_EXPIRE_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_PMU_PERIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_PMU_PERIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_PMU_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC00_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC00_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC01_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC01_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC01_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC10_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC10_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC10_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC11_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC11_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC11_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC12_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC12_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC12_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC13_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC13_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC13_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC14_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC14_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC14_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC15_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC15_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC15_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC02_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC02_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC02_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC03_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC03_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC03_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC04_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC04_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC04_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC05_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC05_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC05_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC06_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC06_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC06_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC07_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC07_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC07_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC08_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC08_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC08_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC09_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC09_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC09_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_PERIS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_PERIS_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_PERIS_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_PERIS_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_PERIS_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_PERIS_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_PERIS_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_PERIS_GIC_BUSY, CLK_CON_MUX_MUX_CLK_PERIS_GIC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_PERIS_GIC_SELECT, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BUSIF_TMU_QCH_ENABLE, QCH_CON_BUSIF_TMU_QCH_CLOCK_REQ, QCH_CON_BUSIF_TMU_QCH_EXPIRE_VAL, QCH_CON_GIC_QCH_ENABLE, QCH_CON_GIC_QCH_CLOCK_REQ, QCH_CON_GIC_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_PERIS_QCH_ENABLE, QCH_CON_LHM_AXI_P_PERIS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_PERIS_QCH_EXPIRE_VAL, QCH_CON_MCT_QCH_ENABLE, QCH_CON_MCT_QCH_CLOCK_REQ, QCH_CON_MCT_QCH_EXPIRE_VAL, QCH_CON_OTP_CON_BIRA_QCH_ENABLE, QCH_CON_OTP_CON_BIRA_QCH_CLOCK_REQ, QCH_CON_OTP_CON_BIRA_QCH_EXPIRE_VAL, QCH_CON_OTP_CON_TOP_QCH_ENABLE, QCH_CON_OTP_CON_TOP_QCH_CLOCK_REQ, QCH_CON_OTP_CON_TOP_QCH_EXPIRE_VAL, QCH_CON_PERIS_CMU_PERIS_QCH_ENABLE, QCH_CON_PERIS_CMU_PERIS_QCH_CLOCK_REQ, QCH_CON_PERIS_CMU_PERIS_QCH_EXPIRE_VAL, QCH_CON_PMU_PERIS_QCH_ENABLE, QCH_CON_PMU_PERIS_QCH_CLOCK_REQ, QCH_CON_PMU_PERIS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_PERIS_QCH_ENABLE, QCH_CON_SYSREG_PERIS_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERIS_QCH_EXPIRE_VAL, QCH_CON_TZPC00_QCH_ENABLE, QCH_CON_TZPC00_QCH_CLOCK_REQ, QCH_CON_TZPC00_QCH_EXPIRE_VAL, QCH_CON_TZPC01_QCH_ENABLE, QCH_CON_TZPC01_QCH_CLOCK_REQ, QCH_CON_TZPC01_QCH_EXPIRE_VAL, QCH_CON_TZPC02_QCH_ENABLE, QCH_CON_TZPC02_QCH_CLOCK_REQ, QCH_CON_TZPC02_QCH_EXPIRE_VAL, QCH_CON_TZPC03_QCH_ENABLE, QCH_CON_TZPC03_QCH_CLOCK_REQ, QCH_CON_TZPC03_QCH_EXPIRE_VAL, QCH_CON_TZPC04_QCH_ENABLE, QCH_CON_TZPC04_QCH_CLOCK_REQ, QCH_CON_TZPC04_QCH_EXPIRE_VAL, QCH_CON_TZPC05_QCH_ENABLE, QCH_CON_TZPC05_QCH_CLOCK_REQ, QCH_CON_TZPC05_QCH_EXPIRE_VAL, QCH_CON_TZPC06_QCH_ENABLE, QCH_CON_TZPC06_QCH_CLOCK_REQ, QCH_CON_TZPC06_QCH_EXPIRE_VAL, QCH_CON_TZPC07_QCH_ENABLE, QCH_CON_TZPC07_QCH_CLOCK_REQ, QCH_CON_TZPC07_QCH_EXPIRE_VAL, QCH_CON_TZPC08_QCH_ENABLE, QCH_CON_TZPC08_QCH_CLOCK_REQ, QCH_CON_TZPC08_QCH_EXPIRE_VAL, QCH_CON_TZPC09_QCH_ENABLE, QCH_CON_TZPC09_QCH_CLOCK_REQ, QCH_CON_TZPC09_QCH_EXPIRE_VAL, QCH_CON_TZPC10_QCH_ENABLE, QCH_CON_TZPC10_QCH_CLOCK_REQ, QCH_CON_TZPC10_QCH_EXPIRE_VAL, QCH_CON_TZPC11_QCH_ENABLE, QCH_CON_TZPC11_QCH_CLOCK_REQ, QCH_CON_TZPC11_QCH_EXPIRE_VAL, QCH_CON_TZPC12_QCH_ENABLE, QCH_CON_TZPC12_QCH_CLOCK_REQ, QCH_CON_TZPC12_QCH_EXPIRE_VAL, QCH_CON_TZPC13_QCH_ENABLE, QCH_CON_TZPC13_QCH_CLOCK_REQ, QCH_CON_TZPC13_QCH_EXPIRE_VAL, QCH_CON_TZPC14_QCH_ENABLE, QCH_CON_TZPC14_QCH_CLOCK_REQ, QCH_CON_TZPC14_QCH_EXPIRE_VAL, QCH_CON_TZPC15_QCH_ENABLE, QCH_CON_TZPC15_QCH_CLOCK_REQ, QCH_CON_TZPC15_QCH_EXPIRE_VAL, QCH_CON_WDT_CLUSTER0_QCH_ENABLE, QCH_CON_WDT_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_WDT_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_WDT_CLUSTER1_QCH_ENABLE, QCH_CON_WDT_CLUSTER1_QCH_CLOCK_REQ, QCH_CON_WDT_CLUSTER1_QCH_EXPIRE_VAL, PLL_CON0_MUX_CLKCMU_SRDZ_IMGD_USER_BUSY, PLL_CON0_MUX_CLKCMU_SRDZ_IMGD_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_SRDZ_IMGD_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_SRDZ_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_SRDZ_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_SRDZ_BUSP_DIVRATIO, PLL_CON0_MUX_CLKCMU_SRDZ_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_SRDZ_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_SRDZ_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_SRDZ_UID_SRDZ_CMU_SRDZ_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SRDZ_UID_SRDZ_CMU_SRDZ_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_SRDZ_UID_SRDZ_CMU_SRDZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_IMGD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_IMGD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_IMGD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SRDZ_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SRDZ_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SRDZ_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PMU_SRDZ_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PMU_SRDZ_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PMU_SRDZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SYSREG_SRDZ_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SYSREG_SRDZ_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SYSREG_SRDZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_SYS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_SYS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_SYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_D_SRDZ_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_D_SRDZ_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_D_SRDZ_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_P_SRDZ_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_P_SRDZ_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_P_SRDZ_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_NONSECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_NONSECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_P_SRDZ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_P_SRDZ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_P_SRDZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_D_SRDZ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_D_SRDZ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_D_SRDZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_ATB_SRDZCAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_ATB_SRDZCAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_ATB_SRDZCAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_ATB_DCAMSRDZ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_ATB_DCAMSRDZ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_ATB_DCAMSRDZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBM_1TO2_SRDZ_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBM_1TO2_SRDZ_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBM_1TO2_SRDZ_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBS_SRDZ_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBS_SRDZ_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBS_SRDZ_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BTM_SRDZ_QCH_ENABLE, QCH_CON_BTM_SRDZ_QCH_CLOCK_REQ, QCH_CON_BTM_SRDZ_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_DCAMSRDZ_QCH_ENABLE, QCH_CON_LHM_ATB_DCAMSRDZ_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_DCAMSRDZ_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_DCAMSRDZ_QCH_ENABLE, QCH_CON_LHM_AXI_D_DCAMSRDZ_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_DCAMSRDZ_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_SRDZ_QCH_ENABLE, QCH_CON_LHM_AXI_P_SRDZ_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_SRDZ_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_SRDZCAM_QCH_ENABLE, QCH_CON_LHS_ATB_SRDZCAM_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_SRDZCAM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_SRDZ_QCH_ENABLE, QCH_CON_LHS_AXI_D_SRDZ_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_SRDZ_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_SRDZDCAM_QCH_ENABLE, QCH_CON_LHS_AXI_P_SRDZDCAM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_SRDZDCAM_QCH_EXPIRE_VAL, QCH_CON_PMU_SRDZ_QCH_ENABLE, QCH_CON_PMU_SRDZ_QCH_CLOCK_REQ, QCH_CON_PMU_SRDZ_QCH_EXPIRE_VAL, QCH_CON_BCM_SRDZ_QCH_ENABLE, QCH_CON_BCM_SRDZ_QCH_CLOCK_REQ, QCH_CON_BCM_SRDZ_QCH_EXPIRE_VAL, QCH_CON_SMMU_SRDZ_QCH_ENABLE, QCH_CON_SMMU_SRDZ_QCH_CLOCK_REQ, QCH_CON_SMMU_SRDZ_QCH_EXPIRE_VAL, QCH_CON_SRDZ_QCH_ENABLE, QCH_CON_SRDZ_QCH_CLOCK_REQ, QCH_CON_SRDZ_QCH_EXPIRE_VAL, QCH_CON_SRDZ_CMU_SRDZ_QCH_ENABLE, QCH_CON_SRDZ_CMU_SRDZ_QCH_CLOCK_REQ, QCH_CON_SRDZ_CMU_SRDZ_QCH_EXPIRE_VAL, QCH_CON_SYSREG_SRDZ_QCH_ENABLE, QCH_CON_SYSREG_SRDZ_QCH_CLOCK_REQ, QCH_CON_SYSREG_SRDZ_QCH_EXPIRE_VAL, CLK_CON_DIV_DIV_CLK_VPU_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_VPU_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_VPU_BUSP_DIVRATIO, PLL_CON0_MUX_CLKCMU_VPU_BUS_USER_BUSY, PLL_CON0_MUX_CLKCMU_VPU_BUS_USER_MUX_SEL, PLL_CON2_MUX_CLKCMU_VPU_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_VPU_UID_VPU_CMU_VPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VPU_UID_VPU_CMU_VPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VPU_UID_VPU_CMU_VPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VPU_UID_PMU_VPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_PMU_VPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_PMU_VPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VPU_UID_SYSREG_VPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_SYSREG_VPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_SYSREG_VPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2APB_VPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2APB_VPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2APB_VPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_P_VPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_P_VPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_P_VPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_NONSECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_NONSECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_VPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_VPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_VPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_ACEL_D_VPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_ACEL_D_VPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_ACEL_D_VPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_VPU_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_VPU_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_VPU_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2AHB_VPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2AHB_VPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2AHB_VPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_VPU_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_VPU_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_VPU_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_D_VPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_D_VPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_D_VPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_DSPVPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_DSPVPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_DSPVPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_AXI_D_VPUDSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_AXI_D_VPUDSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_AXI_D_VPUDSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_BTM_VPU_QCH_ENABLE, QCH_CON_BTM_VPU_QCH_CLOCK_REQ, QCH_CON_BTM_VPU_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_DSPVPU_QCH_ENABLE, QCH_CON_LHM_AXI_P_DSPVPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DSPVPU_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_VPU_QCH_ENABLE, QCH_CON_LHM_AXI_P_VPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_VPU_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_VPU_QCH_ENABLE, QCH_CON_LHS_ACEL_D_VPU_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_VPU_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_VPUDSP_QCH_ENABLE, QCH_CON_LHS_AXI_D_VPUDSP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_VPUDSP_QCH_EXPIRE_VAL, QCH_CON_PMU_VPU_QCH_ENABLE, QCH_CON_PMU_VPU_QCH_CLOCK_REQ, QCH_CON_PMU_VPU_QCH_EXPIRE_VAL, QCH_CON_BCM_VPU_QCH_ENABLE, QCH_CON_BCM_VPU_QCH_CLOCK_REQ, QCH_CON_BCM_VPU_QCH_EXPIRE_VAL, QCH_CON_SMMU_VPU_QCH_ENABLE, QCH_CON_SMMU_VPU_QCH_CLOCK_REQ, QCH_CON_SMMU_VPU_QCH_EXPIRE_VAL, QCH_CON_SYSREG_VPU_QCH_ENABLE, QCH_CON_SYSREG_VPU_QCH_CLOCK_REQ, QCH_CON_SYSREG_VPU_QCH_EXPIRE_VAL, QCH_CON_VPU_QCH_ENABLE, QCH_CON_VPU_QCH_CLOCK_REQ, QCH_CON_VPU_QCH_EXPIRE_VAL, QCH_CON_VPU_CMU_VPU_QCH_ENABLE, QCH_CON_VPU_CMU_VPU_QCH_CLOCK_REQ, QCH_CON_VPU_CMU_VPU_QCH_EXPIRE_VAL, CLK_CON_DIV_DIV_CLK_VTS_BUS_BUSY, CLK_CON_DIV_DIV_CLK_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_VTS_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_DMICIF_BUSY, CLK_CON_DIV_DIV_CLK_VTS_DMICIF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_VTS_DMICIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_DMIC_BUSY, CLK_CON_DIV_DIV_CLK_VTS_DMIC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIVRATIO, CLKOUT_CON_BLK_VTS_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_VTS_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_VTS_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, CLKOUT_CON_BLK_VTS_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_VTS_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_VTS_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_SYS_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_SYS_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_SYS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMICIF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMICIF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMICIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, OSC_CON2_OSC_VTS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_CPU_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_CPU_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_CPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2_BUSY, CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2_DIVRATIO, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMICIF_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMICIF_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMICIF_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_VTS2AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_VTS2AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_VTS2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_VTS_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_VTS_CMUREF_BUSY, CLK_CON_MUX_MUX_CLK_VTS_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_VTS_CMUREF_SELECT, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_DIV2_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_DIV2_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_CLK_ENABLE_AUTOMATIC_CLKGATING, DMYQCH_CON_CMU_VTS_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_VTS_CMUREF_QCH_CLOCK_REQ, QCH_CON_DMIC_AHB_QCH_PCLK_ENABLE, QCH_CON_DMIC_AHB_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AHB_QCH_PCLK_EXPIRE_VAL, DMYQCH_CON_DMIC_AHB_QCH_HCLK_ENABLE, DMYQCH_CON_DMIC_AHB_QCH_HCLK_CLOCK_REQ, QCH_CON_DMIC_IF_QCH_PCLK_ENABLE, QCH_CON_DMIC_IF_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_IF_QCH_PCLK_EXPIRE_VAL, DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK_ENABLE, DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK_CLOCK_REQ, QCH_CON_GPIO_VTS_QCH_ENABLE, QCH_CON_GPIO_VTS_QCH_CLOCK_REQ, QCH_CON_GPIO_VTS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_VTS_QCH_ENABLE, QCH_CON_LHM_AXI_P_VTS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_VTS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_VTS_QCH_ENABLE, QCH_CON_LHS_AXI_D_VTS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_VTS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_VTS2AP_QCH_ENABLE, QCH_CON_MAILBOX_VTS2AP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_VTS2AP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_VTS_QCH_ENABLE, QCH_CON_SYSREG_VTS_QCH_CLOCK_REQ, QCH_CON_SYSREG_VTS_QCH_EXPIRE_VAL, QCH_CON_VTS_QCH_CPU_ENABLE, QCH_CON_VTS_QCH_CPU_CLOCK_REQ, QCH_CON_VTS_QCH_CPU_EXPIRE_VAL, QCH_CON_VTS_QCH_SYS_ENABLE, QCH_CON_VTS_QCH_SYS_CLOCK_REQ, QCH_CON_VTS_QCH_SYS_EXPIRE_VAL, QCH_CON_VTS_QCH_SYS_DMIC_ENABLE, QCH_CON_VTS_QCH_SYS_DMIC_CLOCK_REQ, QCH_CON_VTS_QCH_SYS_DMIC_EXPIRE_VAL, QCH_CON_VTS_CMU_VTS_QCH_ENABLE, QCH_CON_VTS_CMU_VTS_QCH_CLOCK_REQ, QCH_CON_VTS_CMU_VTS_QCH_EXPIRE_VAL, QCH_CON_WDT_VTS_QCH_ENABLE, QCH_CON_WDT_VTS_QCH_CLOCK_REQ, QCH_CON_WDT_VTS_QCH_EXPIRE_VAL, /*====================The section of controller option SFR access===================*/ ABOX_ENABLE_POWER_MANAGEMENT, ABOX_ENABLE_AUTOMATIC_CLKGATING, APM_ENABLE_POWER_MANAGEMENT, APM_ENABLE_AUTOMATIC_CLKGATING, BUS1_ENABLE_POWER_MANAGEMENT, BUS1_ENABLE_AUTOMATIC_CLKGATING, BUSC_ENABLE_POWER_MANAGEMENT, BUSC_ENABLE_AUTOMATIC_CLKGATING, CAM_ENABLE_POWER_MANAGEMENT, CAM_ENABLE_AUTOMATIC_CLKGATING, CMU_ENABLE_POWER_MANAGEMENT, CMU_ENABLE_AUTOMATIC_CLKGATING, CORE_ENABLE_POWER_MANAGEMENT, CORE_ENABLE_AUTOMATIC_CLKGATING, CPUCL0_ENABLE_POWER_MANAGEMENT, CPUCL0_ENABLE_AUTOMATIC_CLKGATING, CPUCL1_ENABLE_POWER_MANAGEMENT, CPUCL1_ENABLE_AUTOMATIC_CLKGATING, DBG_ENABLE_POWER_MANAGEMENT, DBG_ENABLE_AUTOMATIC_CLKGATING, DCAM_ENABLE_POWER_MANAGEMENT, DCAM_ENABLE_AUTOMATIC_CLKGATING, DPU0_ENABLE_POWER_MANAGEMENT, DPU0_ENABLE_AUTOMATIC_CLKGATING, DPU1_ENABLE_POWER_MANAGEMENT, DPU1_ENABLE_AUTOMATIC_CLKGATING, DSP_ENABLE_POWER_MANAGEMENT, DSP_ENABLE_AUTOMATIC_CLKGATING, FSYS0_ENABLE_POWER_MANAGEMENT, FSYS0_ENABLE_AUTOMATIC_CLKGATING, FSYS1_ENABLE_POWER_MANAGEMENT, FSYS1_ENABLE_AUTOMATIC_CLKGATING, G2D_ENABLE_POWER_MANAGEMENT, G2D_ENABLE_AUTOMATIC_CLKGATING, G3D_ENABLE_POWER_MANAGEMENT, G3D_ENABLE_AUTOMATIC_CLKGATING, IMEM_ENABLE_POWER_MANAGEMENT, IMEM_ENABLE_AUTOMATIC_CLKGATING, ISPHQ_ENABLE_POWER_MANAGEMENT, ISPHQ_ENABLE_AUTOMATIC_CLKGATING, ISPLP_ENABLE_POWER_MANAGEMENT, ISPLP_ENABLE_AUTOMATIC_CLKGATING, IVA_ENABLE_POWER_MANAGEMENT, IVA_ENABLE_AUTOMATIC_CLKGATING, MFC_ENABLE_POWER_MANAGEMENT, MFC_ENABLE_AUTOMATIC_CLKGATING, MIF_ENABLE_POWER_MANAGEMENT, MIF_ENABLE_AUTOMATIC_CLKGATING, MIF1_ENABLE_POWER_MANAGEMENT, MIF1_ENABLE_AUTOMATIC_CLKGATING, MIF2_ENABLE_POWER_MANAGEMENT, MIF2_ENABLE_AUTOMATIC_CLKGATING, MIF3_ENABLE_POWER_MANAGEMENT, MIF3_ENABLE_AUTOMATIC_CLKGATING, PERIC0_ENABLE_POWER_MANAGEMENT, PERIC0_ENABLE_AUTOMATIC_CLKGATING, PERIC1_ENABLE_POWER_MANAGEMENT, PERIC1_ENABLE_AUTOMATIC_CLKGATING, PERIS_ENABLE_POWER_MANAGEMENT, PERIS_ENABLE_AUTOMATIC_CLKGATING, SRDZ_ENABLE_POWER_MANAGEMENT, SRDZ_ENABLE_AUTOMATIC_CLKGATING, VPU_ENABLE_POWER_MANAGEMENT, VPU_ENABLE_AUTOMATIC_CLKGATING, VTS_ENABLE_POWER_MANAGEMENT, VTS_ENABLE_AUTOMATIC_CLKGATING, end_of_sfr_access, num_of_sfr_access = end_of_sfr_access - SFR_ACCESS_TYPE, }; #endif