441 lines
11 KiB
C
441 lines
11 KiB
C
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/*
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* Copyright (c) 2017 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Header file for Samsung EXYNOS SoC MIPI-DSI Master driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __SAMSUNG_DSIM_H__
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#define __SAMSUNG_DSIM_H__
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/regulator/consumer.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <media/v4l2-subdev.h>
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#include "./panels/decon_lcd.h"
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#if defined(CONFIG_SOC_EXYNOS9610)
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#include "./cal_9610/regs-dsim.h"
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#include "./cal_9610/dsim_cal.h"
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#endif
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#if defined(CONFIG_EXYNOS_DECON_LCD_S6E3HA2K)
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#include "./panels/s6e3ha2k_param.h"
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#elif defined(CONFIG_EXYNOS_DECON_LCD_S6E3HF4)
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#include "./panels/s6e3hf4_param.h"
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#elif defined(CONFIG_EXYNOS_DECON_LCD_EMUL_DISP)
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#include "./panels/emul_disp_param.h"
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#elif defined(CONFIG_EXYNOS_DECON_LCD_S6E3HA6)
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#include "./panels/s6e3ha6_param.h"
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#elif defined(CONFIG_EXYNOS_DECON_LCD_S6E3AA2)
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#include "./panels/s6e3aa2_param.h"
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#elif defined(CONFIG_EXYNOS_DECON_LCD_S6E3FA0)
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#include "./panels/s6e3fa0_param.h"
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#endif
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extern int dsim_log_level;
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#define DSIM_MODULE_NAME "exynos-dsim"
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#define MAX_DSIM_CNT 2
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#define DSIM_DDI_ID_LEN 3
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#define DSIM_PIXEL_FORMAT_RGB24 0x3E
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#define DSIM_PIXEL_FORMAT_RGB18_PACKED 0x1E
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#define DSIM_PIXEL_FORMAT_RGB18 0x2E
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#define DSIM_PIXEL_FORMAT_RGB30_PACKED 0x0D
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#define DSIM_RX_FIFO_MAX_DEPTH 64
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#define MAX_DSIM_DATALANE_CNT 4
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#define MIPI_WR_TIMEOUT msecs_to_jiffies(50)
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#define MIPI_RD_TIMEOUT msecs_to_jiffies(100)
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#define dsim_err(fmt, ...) \
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do { \
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if (dsim_log_level >= 3) { \
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pr_err(pr_fmt("dsim: "fmt), ##__VA_ARGS__); \
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} \
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} while (0)
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#define dsim_warn(fmt, ...) \
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do { \
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if (dsim_log_level >= 4) { \
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pr_warn(pr_fmt("dsim: "fmt), ##__VA_ARGS__); \
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} \
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} while (0)
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#define dsim_info(fmt, ...) \
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do { \
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if (dsim_log_level >= 6) \
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pr_info(pr_fmt("dsim: "fmt), ##__VA_ARGS__); \
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} while (0)
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#define dsim_dbg(fmt, ...) \
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do { \
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if (dsim_log_level >= 7) \
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pr_info(pr_fmt("dsim: "fmt), ##__VA_ARGS__); \
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} while (0)
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#define call_panel_ops(q, op, args...) \
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(((q) && ((q)->panel_ops->op)) ? ((q)->panel_ops->op(args)) : 0)
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extern struct dsim_device *dsim_drvdata[MAX_DSIM_CNT];
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extern struct dsim_lcd_driver s6e3ha2k_mipi_lcd_driver;
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extern struct dsim_lcd_driver emul_disp_mipi_lcd_driver;
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extern struct dsim_lcd_driver s6e3hf4_mipi_lcd_driver;
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extern struct dsim_lcd_driver s6e3ha6_mipi_lcd_driver;
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extern struct dsim_lcd_driver s6e3ha8_mipi_lcd_driver;
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extern struct dsim_lcd_driver s6e3aa2_mipi_lcd_driver;
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extern struct dsim_lcd_driver s6e3fa0_mipi_lcd_driver;
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extern struct dsim_lcd_driver s6e3fa7_mipi_lcd_driver;
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extern struct dsim_lcd_driver ea8076_mipi_lcd_driver;
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/* define video timer interrupt */
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enum {
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DSIM_VBP = 0,
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DSIM_VSYNC,
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DSIM_V_ACTIVE,
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DSIM_VFP,
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};
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/* define dsi bist pattern */
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enum {
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DSIM_COLOR_BAR = 0,
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DSIM_GRAY_GRADATION,
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DSIM_USER_DEFINED,
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DSIM_PRB7_RANDOM,
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};
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/* define DSI lane types. */
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enum {
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DSIM_LANE_CLOCK = (1 << 0),
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DSIM_LANE_DATA0 = (1 << 1),
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DSIM_LANE_DATA1 = (1 << 2),
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DSIM_LANE_DATA2 = (1 << 3),
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DSIM_LANE_DATA3 = (1 << 4),
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};
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/* DSI Error report bit definitions */
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enum {
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MIPI_DSI_ERR_SOT = (1 << 0),
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MIPI_DSI_ERR_SOT_SYNC = (1 << 1),
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MIPI_DSI_ERR_EOT_SYNC = (1 << 2),
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MIPI_DSI_ERR_ESCAPE_MODE_ENTRY_CMD = (1 << 3),
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MIPI_DSI_ERR_LOW_POWER_TRANSMIT_SYNC = (1 << 4),
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MIPI_DSI_ERR_HS_RECEIVE_TIMEOUT = (1 << 5),
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MIPI_DSI_ERR_FALSE_CONTROL = (1 << 6),
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/* Bit 7 is reserved */
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MIPI_DSI_ERR_ECC_SINGLE_BIT = (1 << 8),
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MIPI_DSI_ERR_ECC_MULTI_BIT = (1 << 9),
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MIPI_DSI_ERR_CHECKSUM = (1 << 10),
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MIPI_DSI_ERR_DATA_TYPE_NOT_RECOGNIZED = (1 << 11),
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MIPI_DSI_ERR_VCHANNEL_ID_INVALID = (1 << 12),
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MIPI_DSI_ERR_INVALID_TRANSMIT_LENGTH = (1 << 13),
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/* Bit 14 is reserved */
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MIPI_DSI_ERR_PROTOCAL_VIOLATION = (1 << 15),
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/* DSI_PROTOCAL_VIOLATION[15] is for protocol violation that is caused EoTp
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* missing So this bit is egnored because of not supportung @S.LSI AP */
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/* FALSE_ERROR_CONTROL[6] is for detect invalid escape or turnaround sequence.
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* This bit is not supporting @S.LSI AP because of non standard
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* ULPS enter/exit sequence during power-gating */
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/* Bit [14],[7] is reserved */
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MIPI_DSI_ERR_BIT_MASK = (0x3f3f), /* Error_Range[13:0] */
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};
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/* operation state of dsim driver */
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enum dsim_state {
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DSIM_STATE_INIT,
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DSIM_STATE_ON, /* HS clock was enabled. */
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DSIM_STATE_DOZE, /* HS clock was enabled. */
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DSIM_STATE_ULPS, /* DSIM was entered ULPS state */
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DSIM_STATE_DOZE_SUSPEND, /* DSIM is suspend state */
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DSIM_STATE_OFF /* DSIM is suspend state */
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};
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enum dphy_charic_value {
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M_PLL_CTRL1,
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M_PLL_CTRL2,
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B_DPHY_CTRL2,
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B_DPHY_CTRL3,
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B_DPHY_CTRL4,
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M_DPHY_CTRL1,
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M_DPHY_CTRL2,
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M_DPHY_CTRL3,
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M_DPHY_CTRL4
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};
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struct dsim_pll_param {
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u32 p;
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u32 m;
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u32 s;
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u32 k;
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u32 pll_freq; /* in/out parameter: Mhz */
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};
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struct dphy_timing_value {
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u32 bps;
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u32 clk_prepare;
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u32 clk_zero;
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u32 clk_post;
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u32 clk_trail;
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u32 hs_prepare;
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u32 hs_zero;
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u32 hs_trail;
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u32 lpx;
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u32 hs_exit;
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u32 b_dphyctl;
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};
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struct dsim_resources {
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struct clk *pclk;
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struct clk *dphy_esc;
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struct clk *dphy_byte;
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struct clk *rgb_vclk0;
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struct clk *pclk_disp;
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struct clk *aclk;
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int lcd_power[3];
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int lcd_reset;
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int irq;
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void __iomem *regs;
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void __iomem *ss_regs;
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void __iomem *phy_regs;
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void __iomem *phy_regs_ex;
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struct regulator *regulator_1p8v;
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struct regulator *regulator_3p3v;
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};
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struct panel_private {
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unsigned int lcdconnected;
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void *par;
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};
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struct dsim_device {
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int id;
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enum dsim_state state;
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struct device *dev;
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struct dsim_resources res;
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unsigned int data_lane;
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u32 data_lane_cnt;
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struct phy *phy;
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struct phy *phy_ex;
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spinlock_t slock;
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struct dsim_lcd_driver *panel_ops;
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struct decon_lcd lcd_info;
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struct panel_private priv;
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struct v4l2_subdev sd;
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struct dsim_clks clks;
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struct timer_list cmd_timer;
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struct mutex cmd_lock;
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struct completion ph_wr_comp;
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struct completion rd_comp;
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int total_underrun_cnt;
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struct backlight_device *bd;
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int idle_ip_index;
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/* true - fb reserved */
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/* false - fb not reserved */
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bool fb_reservation;
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phys_addr_t phys_addr;
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phys_addr_t phys_size;
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#if defined(CONFIG_EXYNOS_READ_ESD_SOLUTION)
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//#define READ_ESD_SOLUTION_TEST
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int esd_test;
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bool esd_recovering;
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#endif
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int continuous_underrun_max;
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int continuous_underrun_cnt;
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};
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struct dsim_lcd_driver {
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char *name;
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int (*probe)(struct dsim_device *dsim);
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int (*suspend)(struct dsim_device *dsim);
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int (*displayon)(struct dsim_device *dsim);
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int (*resume)(struct dsim_device *dsim);
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int (*resume_early)(struct dsim_device *dsim);
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int (*dump)(struct dsim_device *dsim);
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int (*mres)(struct dsim_device *dsim, int mres_idx);
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int (*doze)(struct dsim_device *dsim);
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int (*doze_suspend)(struct dsim_device *dsim);
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int (*match)(void *maybe_unused);
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#if defined(CONFIG_LOGGING_BIGDATA_BUG)
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unsigned int (*get_buginfo)(struct dsim_device *dsim);
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#endif
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#if defined(CONFIG_SUPPORT_MASK_LAYER)
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int (*mask_brightness)(struct dsim_device *dsim);
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#endif
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#if defined(CONFIG_EXYNOS_READ_ESD_SOLUTION)
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int (*read_state)(struct dsim_device *dsim);
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#endif
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};
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int dsim_write_data(struct dsim_device *dsim, u32 id, unsigned long d0, u32 d1);
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int dsim_read_data(struct dsim_device *dsim, u32 id, u32 addr, u32 cnt, u8 *buf);
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int dsim_wait_for_cmd_done(struct dsim_device *dsim);
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int dsim_reset_panel(struct dsim_device *dsim);
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int dsim_set_panel_power(struct dsim_device *dsim, bool on);
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int dsim_set_panel_power_early(struct dsim_device *dsim);
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void dsim_to_regs_param(struct dsim_device *dsim, struct dsim_regs *regs);
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static inline struct dsim_device *get_dsim_drvdata(u32 id)
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{
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return dsim_drvdata[id];
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}
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static inline int dsim_rd_data(u32 id, u32 cmd_id, u32 addr, u32 size, u8 *buf)
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{
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int ret;
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struct dsim_device *dsim = get_dsim_drvdata(id);
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ret = dsim_read_data(dsim, cmd_id, addr, size, buf);
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if (ret)
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return ret;
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return 0;
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}
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static inline int dsim_wr_data(u32 id, u32 cmd_id, unsigned long d0, u32 d1)
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{
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int ret;
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struct dsim_device *dsim = get_dsim_drvdata(id);
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ret = dsim_write_data(dsim, cmd_id, d0, d1);
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if (ret)
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return ret;
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return 0;
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}
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static inline int dsim_wait_for_cmd_completion(u32 id)
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{
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int ret;
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struct dsim_device *dsim = get_dsim_drvdata(id);
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ret = dsim_wait_for_cmd_done(dsim);
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return ret;
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}
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/* register access subroutines */
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static inline u32 dsim_read(u32 id, u32 reg_id)
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{
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struct dsim_device *dsim = get_dsim_drvdata(id);
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return readl(dsim->res.regs + reg_id);
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}
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static inline u32 dsim_read_mask(u32 id, u32 reg_id, u32 mask)
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{
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u32 val = dsim_read(id, reg_id);
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val &= (mask);
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return val;
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}
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static inline void dsim_write(u32 id, u32 reg_id, u32 val)
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{
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struct dsim_device *dsim = get_dsim_drvdata(id);
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writel(val, dsim->res.regs + reg_id);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void dsim_write_mask(u32 id, u32 reg_id, u32 val, u32 mask)
|
||
|
|
{
|
||
|
|
struct dsim_device *dsim = get_dsim_drvdata(id);
|
||
|
|
u32 old = dsim_read(id, reg_id);
|
||
|
|
|
||
|
|
val = (val & mask) | (old & ~mask);
|
||
|
|
writel(val, dsim->res.regs + reg_id);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* DPHY register access subroutines */
|
||
|
|
static inline u32 dsim_phy_read(u32 id, u32 reg_id)
|
||
|
|
{
|
||
|
|
struct dsim_device *dsim = get_dsim_drvdata(id);
|
||
|
|
|
||
|
|
return readl(dsim->res.phy_regs + reg_id);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline u32 dsim_phy_read_mask(u32 id, u32 reg_id, u32 mask)
|
||
|
|
{
|
||
|
|
u32 val = dsim_phy_read(id, reg_id);
|
||
|
|
|
||
|
|
val &= (mask);
|
||
|
|
return val;
|
||
|
|
}
|
||
|
|
static inline void dsim_phy_extra_write(u32 id, u32 reg_id, u32 val)
|
||
|
|
{
|
||
|
|
struct dsim_device *dsim = get_dsim_drvdata(id);
|
||
|
|
|
||
|
|
writel(val, dsim->res.phy_regs_ex + reg_id);
|
||
|
|
}
|
||
|
|
static inline void dsim_phy_write(u32 id, u32 reg_id, u32 val)
|
||
|
|
{
|
||
|
|
struct dsim_device *dsim = get_dsim_drvdata(id);
|
||
|
|
|
||
|
|
writel(val, dsim->res.phy_regs + reg_id);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void dsim_phy_write_mask(u32 id, u32 reg_id, u32 val, u32 mask)
|
||
|
|
{
|
||
|
|
struct dsim_device *dsim = get_dsim_drvdata(id);
|
||
|
|
u32 old = dsim_phy_read(id, reg_id);
|
||
|
|
|
||
|
|
val = (val & mask) | (old & ~mask);
|
||
|
|
writel(val, dsim->res.phy_regs + reg_id);
|
||
|
|
/* printk("offset : 0x%8x, value : 0x%x\n", reg_id, val); */
|
||
|
|
}
|
||
|
|
|
||
|
|
/* DPHY loop back for test */
|
||
|
|
#ifdef DPHY_LOOP
|
||
|
|
void dsim_reg_set_dphy_loop_back_test(u32 id);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
static inline bool IS_DSIM_ON_STATE(struct dsim_device *dsim)
|
||
|
|
{
|
||
|
|
#ifdef CONFIG_EXYNOS_DOZE
|
||
|
|
return (dsim->state == DSIM_STATE_ON ||
|
||
|
|
dsim->state == DSIM_STATE_DOZE);
|
||
|
|
#else
|
||
|
|
return (dsim->state == DSIM_STATE_ON);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline bool IS_DSIM_OFF_STATE(struct dsim_device *dsim)
|
||
|
|
{
|
||
|
|
return (dsim->state == DSIM_STATE_ULPS ||
|
||
|
|
#ifdef CONFIG_EXYNOS_DOZE
|
||
|
|
dsim->state == DSIM_STATE_DOZE_SUSPEND ||
|
||
|
|
#endif
|
||
|
|
dsim->state == DSIM_STATE_OFF);
|
||
|
|
}
|
||
|
|
|
||
|
|
#define DSIM_IOC_ENTER_ULPS _IOW('D', 0, u32)
|
||
|
|
#define DSIM_IOC_GET_LCD_INFO _IOW('D', 5, struct decon_lcd *)
|
||
|
|
#define DSIM_IOC_DUMP _IOW('D', 8, u32)
|
||
|
|
#define DSIM_IOC_GET_WCLK _IOW('D', 9, u32)
|
||
|
|
#define DSIM_IOC_SET_CONFIG _IOW('D', 10, u32)
|
||
|
|
#define DSIM_IOC_FREE_FB_RES _IOW('D', 11, u32)
|
||
|
|
#define DSIM_IOC_DOZE _IOW('D', 20, u32)
|
||
|
|
#define DSIM_IOC_DOZE_SUSPEND _IOW('D', 21, u32)
|
||
|
|
|
||
|
|
#if defined(CONFIG_EXYNOS_READ_ESD_SOLUTION)
|
||
|
|
#define DSIM_ESD_OK 0
|
||
|
|
#define DSIM_ESD_ERROR 1
|
||
|
|
#define DSIM_ESD_CHECK_ERROR 2
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* __SAMSUNG_DSIM_H__ */
|