lineage_kernel_xcoverpro/drivers/soc/samsung/cal-if/exynos8895/cmucal-qch.c

#include "../cmucal.h"
#include "cmucal-sfr.h"
#include "cmucal-qch.h"

/*=================CMUCAL version: S5E8895================================*/

/*====================The section of QCH nodes===================*/
unsigned int cmucal_qch_size = 550;


struct cmucal_qch cmucal_qch_list[] = {
	CLK_QCH(ABOX_CMU_ABOX_QCH, QCH_CON_ABOX_CMU_ABOX_QCH_ENABLE, QCH_CON_ABOX_CMU_ABOX_QCH_CLOCK_REQ, QCH_CON_ABOX_CMU_ABOX_QCH_EXPIRE_VAL),
	CLK_QCH(ABOX_TOP_QCH, DMYQCH_CON_ABOX_TOP_QCH_ENABLE, DMYQCH_CON_ABOX_TOP_QCH_CLOCK_REQ, EMPTY_CAL_ID),
	CLK_QCH(BTM_ABOX_QCH, QCH_CON_BTM_ABOX_QCH_ENABLE, QCH_CON_BTM_ABOX_QCH_CLOCK_REQ, QCH_CON_BTM_ABOX_QCH_EXPIRE_VAL),
	CLK_QCH(DMIC_QCH, DMYQCH_CON_DMIC_QCH_ENABLE, DMYQCH_CON_DMIC_QCH_CLOCK_REQ, EMPTY_CAL_ID),
	CLK_QCH(GPIO_ABOX_QCH, QCH_CON_GPIO_ABOX_QCH_ENABLE, QCH_CON_GPIO_ABOX_QCH_CLOCK_REQ, QCH_CON_GPIO_ABOX_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_ABOX_QCH, QCH_CON_LHM_AXI_P_ABOX_QCH_ENABLE, QCH_CON_LHM_AXI_P_ABOX_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_ABOX_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_ATB_ABOX_QCH, QCH_CON_LHS_ATB_ABOX_QCH_ENABLE, QCH_CON_LHS_ATB_ABOX_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_ABOX_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_D_ABOX_QCH, QCH_CON_LHS_AXI_D_ABOX_QCH_ENABLE, QCH_CON_LHS_AXI_D_ABOX_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_ABOX_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_ABOX_QCH, QCH_CON_PMU_ABOX_QCH_ENABLE, QCH_CON_PMU_ABOX_QCH_CLOCK_REQ, QCH_CON_PMU_ABOX_QCH_EXPIRE_VAL),
	CLK_QCH(BCM_ABOX_QCH, QCH_CON_BCM_ABOX_QCH_ENABLE, QCH_CON_BCM_ABOX_QCH_CLOCK_REQ, QCH_CON_BCM_ABOX_QCH_EXPIRE_VAL),
	CLK_QCH(SMMU_ABOX_QCH, QCH_CON_SMMU_ABOX_QCH_ENABLE, QCH_CON_SMMU_ABOX_QCH_CLOCK_REQ, QCH_CON_SMMU_ABOX_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_ABOX_QCH, QCH_CON_SYSREG_ABOX_QCH_ENABLE, QCH_CON_SYSREG_ABOX_QCH_CLOCK_REQ, QCH_CON_SYSREG_ABOX_QCH_EXPIRE_VAL),
	CLK_QCH(TREX_ABOX_QCH, QCH_CON_TREX_ABOX_QCH_ENABLE, QCH_CON_TREX_ABOX_QCH_CLOCK_REQ, QCH_CON_TREX_ABOX_QCH_EXPIRE_VAL),
	CLK_QCH(WDT_ABOXCPU_QCH, QCH_CON_WDT_ABOXCPU_QCH_ENABLE, QCH_CON_WDT_ABOXCPU_QCH_CLOCK_REQ, QCH_CON_WDT_ABOXCPU_QCH_EXPIRE_VAL),
	CLK_QCH(APM_QCH_SYS, QCH_CON_APM_QCH_SYS_ENABLE, QCH_CON_APM_QCH_SYS_CLOCK_REQ, QCH_CON_APM_QCH_SYS_EXPIRE_VAL),
	CLK_QCH(APM_QCH_CPU, QCH_CON_APM_QCH_CPU_ENABLE, QCH_CON_APM_QCH_CPU_CLOCK_REQ, QCH_CON_APM_QCH_CPU_EXPIRE_VAL),
	CLK_QCH(APM_QCH_OSCCLK, DMYQCH_CON_APM_QCH_OSCCLK_ENABLE, DMYQCH_CON_APM_QCH_OSCCLK_CLOCK_REQ, EMPTY_CAL_ID),
	CLK_QCH(APM_CMU_APM_QCH, QCH_CON_APM_CMU_APM_QCH_ENABLE, QCH_CON_APM_CMU_APM_QCH_CLOCK_REQ, QCH_CON_APM_CMU_APM_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_ALIVE_QCH, QCH_CON_LHM_AXI_P_ALIVE_QCH_ENABLE, QCH_CON_LHM_AXI_P_ALIVE_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_ALIVE_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_D_ALIVE_QCH, QCH_CON_LHS_AXI_D_ALIVE_QCH_ENABLE, QCH_CON_LHS_AXI_D_ALIVE_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_ALIVE_QCH_EXPIRE_VAL),
	CLK_QCH(MAILBOX_APM2AP_QCH, QCH_CON_MAILBOX_APM2AP_QCH_ENABLE, QCH_CON_MAILBOX_APM2AP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM2AP_QCH_EXPIRE_VAL),
	CLK_QCH(MAILBOX_APM2CP_QCH, QCH_CON_MAILBOX_APM2CP_QCH_ENABLE, QCH_CON_MAILBOX_APM2CP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM2CP_QCH_EXPIRE_VAL),
	CLK_QCH(MAILBOX_APM2GNSS_QCH, QCH_CON_MAILBOX_APM2GNSS_QCH_ENABLE, QCH_CON_MAILBOX_APM2GNSS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM2GNSS_QCH_EXPIRE_VAL),
	CLK_QCH(SCAN2AXI_QCH, QCH_CON_SCAN2AXI_QCH_ENABLE, QCH_CON_SCAN2AXI_QCH_CLOCK_REQ, QCH_CON_SCAN2AXI_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_APM_QCH, QCH_CON_SYSREG_APM_QCH_ENABLE, QCH_CON_SYSREG_APM_QCH_CLOCK_REQ, QCH_CON_SYSREG_APM_QCH_EXPIRE_VAL),
	CLK_QCH(WDT_APM_QCH, QCH_CON_WDT_APM_QCH_ENABLE, QCH_CON_WDT_APM_QCH_CLOCK_REQ, QCH_CON_WDT_APM_QCH_EXPIRE_VAL),
	CLK_QCH(BUS1_CMU_BUS1_QCH, QCH_CON_BUS1_CMU_BUS1_QCH_ENABLE, QCH_CON_BUS1_CMU_BUS1_QCH_CLOCK_REQ, QCH_CON_BUS1_CMU_BUS1_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_ACEL_D_FSYS1_QCH, QCH_CON_LHM_ACEL_D_FSYS1_QCH_ENABLE, QCH_CON_LHM_ACEL_D_FSYS1_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_FSYS1_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_D_ALIVE_QCH, QCH_CON_LHM_AXI_D_ALIVE_QCH_ENABLE, QCH_CON_LHM_AXI_D_ALIVE_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_ALIVE_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_D_GNSS_QCH, QCH_CON_LHM_AXI_D_GNSS_QCH_ENABLE, QCH_CON_LHM_AXI_D_GNSS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_GNSS_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_ALIVE_QCH, QCH_CON_LHS_AXI_P_ALIVE_QCH_ENABLE, QCH_CON_LHS_AXI_P_ALIVE_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_ALIVE_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_FSYS1_QCH, QCH_CON_LHS_AXI_P_FSYS1_QCH_ENABLE, QCH_CON_LHS_AXI_P_FSYS1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_FSYS1_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_BUS1_QCH, QCH_CON_PMU_BUS1_QCH_ENABLE, QCH_CON_PMU_BUS1_QCH_CLOCK_REQ, QCH_CON_PMU_BUS1_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_BUS1_QCH, QCH_CON_SYSREG_BUS1_QCH_ENABLE, QCH_CON_SYSREG_BUS1_QCH_CLOCK_REQ, QCH_CON_SYSREG_BUS1_QCH_EXPIRE_VAL),
	CLK_QCH(TREX_D_BUS1_QCH, QCH_CON_TREX_D_BUS1_QCH_ENABLE, QCH_CON_TREX_D_BUS1_QCH_CLOCK_REQ, QCH_CON_TREX_D_BUS1_QCH_EXPIRE_VAL),
	CLK_QCH(TREX_P_BUS1_QCH, QCH_CON_TREX_P_BUS1_QCH_ENABLE, QCH_CON_TREX_P_BUS1_QCH_CLOCK_REQ, QCH_CON_TREX_P_BUS1_QCH_EXPIRE_VAL),
	CLK_QCH(ADCIF_BUSC_QCH_S0, QCH_CON_ADCIF_BUSC_QCH_S0_ENABLE, QCH_CON_ADCIF_BUSC_QCH_S0_CLOCK_REQ, QCH_CON_ADCIF_BUSC_QCH_S0_EXPIRE_VAL),
	CLK_QCH(ADCIF_BUSC_QCH_S1, QCH_CON_ADCIF_BUSC_QCH_S1_ENABLE, QCH_CON_ADCIF_BUSC_QCH_S1_CLOCK_REQ, QCH_CON_ADCIF_BUSC_QCH_S1_EXPIRE_VAL),
	CLK_QCH(BUSC_CMU_BUSC_QCH, QCH_CON_BUSC_CMU_BUSC_QCH_ENABLE, QCH_CON_BUSC_CMU_BUSC_QCH_CLOCK_REQ, QCH_CON_BUSC_CMU_BUSC_QCH_EXPIRE_VAL),
	CLK_QCH(BUSIF_CMUTOPC_QCH, QCH_CON_BUSIF_CMUTOPC_QCH_ENABLE, QCH_CON_BUSIF_CMUTOPC_QCH_CLOCK_REQ, QCH_CON_BUSIF_CMUTOPC_QCH_EXPIRE_VAL),
	CLK_QCH(GNSSMBOX_QCH, QCH_CON_GNSSMBOX_QCH_ENABLE, QCH_CON_GNSSMBOX_QCH_CLOCK_REQ, QCH_CON_GNSSMBOX_QCH_EXPIRE_VAL),
	CLK_QCH(GPIO_BUSC_QCH, QCH_CON_GPIO_BUSC_QCH_ENABLE, QCH_CON_GPIO_BUSC_QCH_CLOCK_REQ, QCH_CON_GPIO_BUSC_QCH_EXPIRE_VAL),
	CLK_QCH(HSI2CDF_QCH, QCH_CON_HSI2CDF_QCH_ENABLE, QCH_CON_HSI2CDF_QCH_CLOCK_REQ, QCH_CON_HSI2CDF_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_ACEL_D0_G2D_QCH, QCH_CON_LHM_ACEL_D0_G2D_QCH_ENABLE, QCH_CON_LHM_ACEL_D0_G2D_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D0_G2D_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_ACEL_D1_G2D_QCH, QCH_CON_LHM_ACEL_D1_G2D_QCH_ENABLE, QCH_CON_LHM_ACEL_D1_G2D_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D1_G2D_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_ACEL_D2_G2D_QCH, QCH_CON_LHM_ACEL_D2_G2D_QCH_ENABLE, QCH_CON_LHM_ACEL_D2_G2D_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D2_G2D_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_ACEL_D_DSP_QCH, QCH_CON_LHM_ACEL_D_DSP_QCH_ENABLE, QCH_CON_LHM_ACEL_D_DSP_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_DSP_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_ACEL_D_FSYS0_QCH, QCH_CON_LHM_ACEL_D_FSYS0_QCH_ENABLE, QCH_CON_LHM_ACEL_D_FSYS0_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_FSYS0_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_ACEL_D_IVA_QCH, QCH_CON_LHM_ACEL_D_IVA_QCH_ENABLE, QCH_CON_LHM_ACEL_D_IVA_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_IVA_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_ACEL_D_VPU_QCH, QCH_CON_LHM_ACEL_D_VPU_QCH_ENABLE, QCH_CON_LHM_ACEL_D_VPU_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_VPU_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_D0_CAM_QCH, QCH_CON_LHM_AXI_D0_CAM_QCH_ENABLE, QCH_CON_LHM_AXI_D0_CAM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_CAM_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_D0_DPU_QCH, QCH_CON_LHM_AXI_D0_DPU_QCH_ENABLE, QCH_CON_LHM_AXI_D0_DPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_DPU_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_D0_MFC_QCH, QCH_CON_LHM_AXI_D0_MFC_QCH_ENABLE, QCH_CON_LHM_AXI_D0_MFC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_MFC_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_D1_CAM_QCH, QCH_CON_LHM_AXI_D1_CAM_QCH_ENABLE, QCH_CON_LHM_AXI_D1_CAM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_CAM_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_D1_DPU_QCH, QCH_CON_LHM_AXI_D1_DPU_QCH_ENABLE, QCH_CON_LHM_AXI_D1_DPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_DPU_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_D1_MFC_QCH, QCH_CON_LHM_AXI_D1_MFC_QCH_ENABLE, QCH_CON_LHM_AXI_D1_MFC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_MFC_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_D2_DPU_QCH, QCH_CON_LHM_AXI_D2_DPU_QCH_ENABLE, QCH_CON_LHM_AXI_D2_DPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D2_DPU_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_D_ABOX_QCH, QCH_CON_LHM_AXI_D_ABOX_QCH_ENABLE, QCH_CON_LHM_AXI_D_ABOX_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_ABOX_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_D_ISPLP_QCH, QCH_CON_LHM_AXI_D_ISPLP_QCH_ENABLE, QCH_CON_LHM_AXI_D_ISPLP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_ISPLP_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_D_SRDZ_QCH, QCH_CON_LHM_AXI_D_SRDZ_QCH_ENABLE, QCH_CON_LHM_AXI_D_SRDZ_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_SRDZ_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_D_VTS_QCH, QCH_CON_LHM_AXI_D_VTS_QCH_ENABLE, QCH_CON_LHM_AXI_D_VTS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_VTS_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_G_CSSYS_QCH, QCH_CON_LHM_AXI_G_CSSYS_QCH_ENABLE, QCH_CON_LHM_AXI_G_CSSYS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_G_CSSYS_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_D_IVASC_QCH, QCH_CON_LHS_AXI_D_IVASC_QCH_ENABLE, QCH_CON_LHS_AXI_D_IVASC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_IVASC_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P0_DPU_QCH, QCH_CON_LHS_AXI_P0_DPU_QCH_ENABLE, QCH_CON_LHS_AXI_P0_DPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P0_DPU_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P1_DPU_QCH, QCH_CON_LHS_AXI_P1_DPU_QCH_ENABLE, QCH_CON_LHS_AXI_P1_DPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P1_DPU_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_ABOX_QCH, QCH_CON_LHS_AXI_P_ABOX_QCH_ENABLE, QCH_CON_LHS_AXI_P_ABOX_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_ABOX_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_CAM_QCH, QCH_CON_LHS_AXI_P_CAM_QCH_ENABLE, QCH_CON_LHS_AXI_P_CAM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_CAM_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_DSP_QCH, QCH_CON_LHS_AXI_P_DSP_QCH_ENABLE, QCH_CON_LHS_AXI_P_DSP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_DSP_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_FSYS0_QCH, QCH_CON_LHS_AXI_P_FSYS0_QCH_ENABLE, QCH_CON_LHS_AXI_P_FSYS0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_FSYS0_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_G2D_QCH, QCH_CON_LHS_AXI_P_G2D_QCH_ENABLE, QCH_CON_LHS_AXI_P_G2D_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_G2D_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_ISPHQ_QCH, QCH_CON_LHS_AXI_P_ISPHQ_QCH_ENABLE, QCH_CON_LHS_AXI_P_ISPHQ_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_ISPHQ_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_ISPLP_QCH, QCH_CON_LHS_AXI_P_ISPLP_QCH_ENABLE, QCH_CON_LHS_AXI_P_ISPLP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_ISPLP_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_IVA_QCH, QCH_CON_LHS_AXI_P_IVA_QCH_ENABLE, QCH_CON_LHS_AXI_P_IVA_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_IVA_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_MFC_QCH, QCH_CON_LHS_AXI_P_MFC_QCH_ENABLE, QCH_CON_LHS_AXI_P_MFC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MFC_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_MIF0_QCH, QCH_CON_LHS_AXI_P_MIF0_QCH_ENABLE, QCH_CON_LHS_AXI_P_MIF0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MIF0_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_MIF1_QCH, QCH_CON_LHS_AXI_P_MIF1_QCH_ENABLE, QCH_CON_LHS_AXI_P_MIF1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MIF1_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_MIF2_QCH, QCH_CON_LHS_AXI_P_MIF2_QCH_ENABLE, QCH_CON_LHS_AXI_P_MIF2_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MIF2_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_MIF3_QCH, QCH_CON_LHS_AXI_P_MIF3_QCH_ENABLE, QCH_CON_LHS_AXI_P_MIF3_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MIF3_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_PERIC0_QCH, QCH_CON_LHS_AXI_P_PERIC0_QCH_ENABLE, QCH_CON_LHS_AXI_P_PERIC0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_PERIC0_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_PERIC1_QCH, QCH_CON_LHS_AXI_P_PERIC1_QCH_ENABLE, QCH_CON_LHS_AXI_P_PERIC1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_PERIC1_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_PERIS_QCH, QCH_CON_LHS_AXI_P_PERIS_QCH_ENABLE, QCH_CON_LHS_AXI_P_PERIS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_PERIS_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_SRDZ_QCH, QCH_CON_LHS_AXI_P_SRDZ_QCH_ENABLE, QCH_CON_LHS_AXI_P_SRDZ_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_SRDZ_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_VPU_QCH, QCH_CON_LHS_AXI_P_VPU_QCH_ENABLE, QCH_CON_LHS_AXI_P_VPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_VPU_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_VTS_QCH, QCH_CON_LHS_AXI_P_VTS_QCH_ENABLE, QCH_CON_LHS_AXI_P_VTS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_VTS_QCH_EXPIRE_VAL),
	CLK_QCH(MBOX_QCH, QCH_CON_MBOX_QCH_ENABLE, QCH_CON_MBOX_QCH_CLOCK_REQ, QCH_CON_MBOX_QCH_EXPIRE_VAL),
	CLK_QCH(PDMA0_QCH, QCH_CON_PDMA0_QCH_ENABLE, QCH_CON_PDMA0_QCH_CLOCK_REQ, QCH_CON_PDMA0_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_BUSC_QCH, QCH_CON_PMU_BUSC_QCH_ENABLE, QCH_CON_PMU_BUSC_QCH_CLOCK_REQ, QCH_CON_PMU_BUSC_QCH_EXPIRE_VAL),
	CLK_QCH(SECMBOX_QCH, QCH_CON_SECMBOX_QCH_ENABLE, QCH_CON_SECMBOX_QCH_CLOCK_REQ, QCH_CON_SECMBOX_QCH_EXPIRE_VAL),
	CLK_QCH(SPDMA_QCH, QCH_CON_SPDMA_QCH_ENABLE, QCH_CON_SPDMA_QCH_CLOCK_REQ, QCH_CON_SPDMA_QCH_EXPIRE_VAL),
	CLK_QCH(SPEEDY_QCH, QCH_CON_SPEEDY_QCH_ENABLE, QCH_CON_SPEEDY_QCH_CLOCK_REQ, QCH_CON_SPEEDY_QCH_EXPIRE_VAL),
	CLK_QCH(SPEEDY_BATCHER_WRAP_QCH_BATCHER_SPEEDY, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_SPEEDY_ENABLE, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_SPEEDY_CLOCK_REQ, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_SPEEDY_EXPIRE_VAL),
	CLK_QCH(SPEEDY_BATCHER_WRAP_QCH_BATCHER_CP, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_CP_ENABLE, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_CP_CLOCK_REQ, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_CP_EXPIRE_VAL),
	CLK_QCH(SPEEDY_BATCHER_WRAP_QCH_BATCHER_AP, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_AP_ENABLE, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_AP_CLOCK_REQ, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_AP_EXPIRE_VAL),
	CLK_QCH(SYSREG_BUSC_QCH, QCH_CON_SYSREG_BUSC_QCH_ENABLE, QCH_CON_SYSREG_BUSC_QCH_CLOCK_REQ, QCH_CON_SYSREG_BUSC_QCH_EXPIRE_VAL),
	CLK_QCH(TREX_D_BUSC_QCH, QCH_CON_TREX_D_BUSC_QCH_ENABLE, QCH_CON_TREX_D_BUSC_QCH_CLOCK_REQ, QCH_CON_TREX_D_BUSC_QCH_EXPIRE_VAL),
	CLK_QCH(TREX_P_BUSC_QCH, QCH_CON_TREX_P_BUSC_QCH_ENABLE, QCH_CON_TREX_P_BUSC_QCH_CLOCK_REQ, QCH_CON_TREX_P_BUSC_QCH_EXPIRE_VAL),
	CLK_QCH(BTM_CAMD0_QCH, QCH_CON_BTM_CAMD0_QCH_ENABLE, QCH_CON_BTM_CAMD0_QCH_CLOCK_REQ, QCH_CON_BTM_CAMD0_QCH_EXPIRE_VAL),
	CLK_QCH(BTM_CAMD1_QCH, QCH_CON_BTM_CAMD1_QCH_ENABLE, QCH_CON_BTM_CAMD1_QCH_CLOCK_REQ, QCH_CON_BTM_CAMD1_QCH_EXPIRE_VAL),
	CLK_QCH(CAM_CMU_CAM_QCH, QCH_CON_CAM_CMU_CAM_QCH_ENABLE, QCH_CON_CAM_CMU_CAM_QCH_CLOCK_REQ, QCH_CON_CAM_CMU_CAM_QCH_EXPIRE_VAL),
	CLK_QCH(ISP_EWGEN_CAM_QCH, QCH_CON_ISP_EWGEN_CAM_QCH_ENABLE, QCH_CON_ISP_EWGEN_CAM_QCH_CLOCK_REQ, QCH_CON_ISP_EWGEN_CAM_QCH_EXPIRE_VAL),
	CLK_QCH(IS_CAM_QCH_CSIS0, QCH_CON_IS_CAM_QCH_CSIS0_ENABLE, QCH_CON_IS_CAM_QCH_CSIS0_CLOCK_REQ, QCH_CON_IS_CAM_QCH_CSIS0_EXPIRE_VAL),
	CLK_QCH(IS_CAM_QCH_CSIS1, QCH_CON_IS_CAM_QCH_CSIS1_ENABLE, QCH_CON_IS_CAM_QCH_CSIS1_CLOCK_REQ, QCH_CON_IS_CAM_QCH_CSIS1_EXPIRE_VAL),
	CLK_QCH(IS_CAM_QCH_CSIS2, QCH_CON_IS_CAM_QCH_CSIS2_ENABLE, QCH_CON_IS_CAM_QCH_CSIS2_CLOCK_REQ, QCH_CON_IS_CAM_QCH_CSIS2_EXPIRE_VAL),
	CLK_QCH(IS_CAM_QCH_CSIS3, QCH_CON_IS_CAM_QCH_CSIS3_ENABLE, QCH_CON_IS_CAM_QCH_CSIS3_CLOCK_REQ, QCH_CON_IS_CAM_QCH_CSIS3_EXPIRE_VAL),
	CLK_QCH(IS_CAM_QCH_MC_SCALER, QCH_CON_IS_CAM_QCH_MC_SCALER_ENABLE, QCH_CON_IS_CAM_QCH_MC_SCALER_CLOCK_REQ, QCH_CON_IS_CAM_QCH_MC_SCALER_EXPIRE_VAL),
	CLK_QCH(IS_CAM_QCH_CSISX4_DMA, QCH_CON_IS_CAM_QCH_CSISX4_DMA_ENABLE, QCH_CON_IS_CAM_QCH_CSISX4_DMA_CLOCK_REQ, QCH_CON_IS_CAM_QCH_CSISX4_DMA_EXPIRE_VAL),
	CLK_QCH(IS_CAM_QCH_SYSMMU_CAM0, QCH_CON_IS_CAM_QCH_SYSMMU_CAM0_ENABLE, QCH_CON_IS_CAM_QCH_SYSMMU_CAM0_CLOCK_REQ, QCH_CON_IS_CAM_QCH_SYSMMU_CAM0_EXPIRE_VAL),
	CLK_QCH(IS_CAM_QCH_SYSMMU_CAM1, QCH_CON_IS_CAM_QCH_SYSMMU_CAM1_ENABLE, QCH_CON_IS_CAM_QCH_SYSMMU_CAM1_CLOCK_REQ, QCH_CON_IS_CAM_QCH_SYSMMU_CAM1_EXPIRE_VAL),
	CLK_QCH(IS_CAM_QCH_BCM_CAM0, QCH_CON_IS_CAM_QCH_BCM_CAM0_ENABLE, QCH_CON_IS_CAM_QCH_BCM_CAM0_CLOCK_REQ, QCH_CON_IS_CAM_QCH_BCM_CAM0_EXPIRE_VAL),
	CLK_QCH(IS_CAM_QCH_BCM_CAM1, QCH_CON_IS_CAM_QCH_BCM_CAM1_ENABLE, QCH_CON_IS_CAM_QCH_BCM_CAM1_CLOCK_REQ, QCH_CON_IS_CAM_QCH_BCM_CAM1_EXPIRE_VAL),
	CLK_QCH(IS_CAM_QCH_TPU0, QCH_CON_IS_CAM_QCH_TPU0_ENABLE, QCH_CON_IS_CAM_QCH_TPU0_CLOCK_REQ, QCH_CON_IS_CAM_QCH_TPU0_EXPIRE_VAL),
	CLK_QCH(IS_CAM_QCH_VRA, QCH_CON_IS_CAM_QCH_VRA_ENABLE, QCH_CON_IS_CAM_QCH_VRA_CLOCK_REQ, QCH_CON_IS_CAM_QCH_VRA_EXPIRE_VAL),
	CLK_QCH(IS_CAM_QCH_QE_TPU0, QCH_CON_IS_CAM_QCH_QE_TPU0_ENABLE, QCH_CON_IS_CAM_QCH_QE_TPU0_CLOCK_REQ, QCH_CON_IS_CAM_QCH_QE_TPU0_EXPIRE_VAL),
	CLK_QCH(IS_CAM_QCH_QE_VRA, QCH_CON_IS_CAM_QCH_QE_VRA_ENABLE, QCH_CON_IS_CAM_QCH_QE_VRA_CLOCK_REQ, QCH_CON_IS_CAM_QCH_QE_VRA_EXPIRE_VAL),
	CLK_QCH(IS_CAM_QCH_BNS, QCH_CON_IS_CAM_QCH_BNS_ENABLE, QCH_CON_IS_CAM_QCH_BNS_CLOCK_REQ, QCH_CON_IS_CAM_QCH_BNS_EXPIRE_VAL),
	CLK_QCH(IS_CAM_QCH_QE_CSISX4, QCH_CON_IS_CAM_QCH_QE_CSISX4_ENABLE, QCH_CON_IS_CAM_QCH_QE_CSISX4_CLOCK_REQ, QCH_CON_IS_CAM_QCH_QE_CSISX4_EXPIRE_VAL),
	CLK_QCH(IS_CAM_QCH_QE_TPU1, QCH_CON_IS_CAM_QCH_QE_TPU1_ENABLE, QCH_CON_IS_CAM_QCH_QE_TPU1_CLOCK_REQ, QCH_CON_IS_CAM_QCH_QE_TPU1_EXPIRE_VAL),
	CLK_QCH(IS_CAM_QCH_TPU1, QCH_CON_IS_CAM_QCH_TPU1_ENABLE, QCH_CON_IS_CAM_QCH_TPU1_CLOCK_REQ, QCH_CON_IS_CAM_QCH_TPU1_EXPIRE_VAL),
	CLK_QCH(LHM_ATB_SRDZCAM_QCH, QCH_CON_LHM_ATB_SRDZCAM_QCH_ENABLE, QCH_CON_LHM_ATB_SRDZCAM_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_SRDZCAM_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_CAM_QCH, QCH_CON_LHM_AXI_P_CAM_QCH_ENABLE, QCH_CON_LHM_AXI_P_CAM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_CAM_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_D0_CAM_QCH, QCH_CON_LHS_AXI_D0_CAM_QCH_ENABLE, QCH_CON_LHS_AXI_D0_CAM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_CAM_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_D1_CAM_QCH, QCH_CON_LHS_AXI_D1_CAM_QCH_ENABLE, QCH_CON_LHS_AXI_D1_CAM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_CAM_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_CAM_QCH, QCH_CON_PMU_CAM_QCH_ENABLE, QCH_CON_PMU_CAM_QCH_CLOCK_REQ, QCH_CON_PMU_CAM_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_CAM_QCH, QCH_CON_SYSREG_CAM_QCH_ENABLE, QCH_CON_SYSREG_CAM_QCH_CLOCK_REQ, QCH_CON_SYSREG_CAM_QCH_EXPIRE_VAL),
	CLK_QCH(CMU_CMU_CMUREF_QCH, DMYQCH_CON_CMU_CMU_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CMU_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID),
	CLK_QCH(DFTMUX_TOP_QCH_CIS_CLK0, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_CLOCK_REQ, EMPTY_CAL_ID),
	CLK_QCH(DFTMUX_TOP_QCH_CIS_CLK1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_CLOCK_REQ, EMPTY_CAL_ID),
	CLK_QCH(DFTMUX_TOP_QCH_CIS_CLK2, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_CLOCK_REQ, EMPTY_CAL_ID),
	CLK_QCH(DFTMUX_TOP_QCH_CIS_CLK3, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_CLOCK_REQ, EMPTY_CAL_ID),
	CLK_QCH(APBBR_CCI_QCH, QCH_CON_APBBR_CCI_QCH_ENABLE, QCH_CON_APBBR_CCI_QCH_CLOCK_REQ, QCH_CON_APBBR_CCI_QCH_EXPIRE_VAL),
	CLK_QCH(BDU_QCH, QCH_CON_BDU_QCH_ENABLE, QCH_CON_BDU_QCH_CLOCK_REQ, QCH_CON_BDU_QCH_EXPIRE_VAL),
	CLK_QCH(BUSIF_HPMCORE_QCH, QCH_CON_BUSIF_HPMCORE_QCH_ENABLE, QCH_CON_BUSIF_HPMCORE_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMCORE_QCH_EXPIRE_VAL),
	CLK_QCH(CCI_QCH, DMYQCH_CON_CCI_QCH_ENABLE, DMYQCH_CON_CCI_QCH_CLOCK_REQ, EMPTY_CAL_ID),
	CLK_QCH(CORE_CMU_CORE_QCH, QCH_CON_CORE_CMU_CORE_QCH_ENABLE, QCH_CON_CORE_CMU_CORE_QCH_CLOCK_REQ, QCH_CON_CORE_CMU_CORE_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_ACE_D0_G3D_QCH, QCH_CON_LHM_ACE_D0_G3D_QCH_ENABLE, QCH_CON_LHM_ACE_D0_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D0_G3D_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_ACE_D1_G3D_QCH, QCH_CON_LHM_ACE_D1_G3D_QCH_ENABLE, QCH_CON_LHM_ACE_D1_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D1_G3D_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_ACE_D2_G3D_QCH, QCH_CON_LHM_ACE_D2_G3D_QCH_ENABLE, QCH_CON_LHM_ACE_D2_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D2_G3D_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_ACE_D3_G3D_QCH, QCH_CON_LHM_ACE_D3_G3D_QCH_ENABLE, QCH_CON_LHM_ACE_D3_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D3_G3D_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_ACE_D_CPUCL1_QCH, QCH_CON_LHM_ACE_D_CPUCL1_QCH_ENABLE, QCH_CON_LHM_ACE_D_CPUCL1_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D_CPUCL1_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_D_CP_QCH, QCH_CON_LHM_AXI_D_CP_QCH_ENABLE, QCH_CON_LHM_AXI_D_CP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_CP_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_CP_QCH, QCH_CON_LHM_AXI_P_CP_QCH_ENABLE, QCH_CON_LHM_AXI_P_CP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_CP_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_ATB_T_BDU_QCH, QCH_CON_LHS_ATB_T_BDU_QCH_ENABLE, QCH_CON_LHS_ATB_T_BDU_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T_BDU_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_CPUCL0_QCH, QCH_CON_LHS_AXI_P_CPUCL0_QCH_ENABLE, QCH_CON_LHS_AXI_P_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_CPUCL0_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_CPUCL1_QCH, QCH_CON_LHS_AXI_P_CPUCL1_QCH_ENABLE, QCH_CON_LHS_AXI_P_CPUCL1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_CPUCL1_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_DBG_QCH, QCH_CON_LHS_AXI_P_DBG_QCH_ENABLE, QCH_CON_LHS_AXI_P_DBG_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_DBG_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_G3D_QCH, QCH_CON_LHS_AXI_P_G3D_QCH_ENABLE, QCH_CON_LHS_AXI_P_G3D_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_G3D_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_IMEM_QCH, QCH_CON_LHS_AXI_P_IMEM_QCH_ENABLE, QCH_CON_LHS_AXI_P_IMEM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_IMEM_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_CORE_QCH, QCH_CON_PMU_CORE_QCH_ENABLE, QCH_CON_PMU_CORE_QCH_CLOCK_REQ, QCH_CON_PMU_CORE_QCH_EXPIRE_VAL),
	CLK_QCH(PPCFW_G3D_QCH, QCH_CON_PPCFW_G3D_QCH_ENABLE, QCH_CON_PPCFW_G3D_QCH_CLOCK_REQ, QCH_CON_PPCFW_G3D_QCH_EXPIRE_VAL),
	CLK_QCH(BCM_CPUCL0_QCH, QCH_CON_BCM_CPUCL0_QCH_ENABLE, QCH_CON_BCM_CPUCL0_QCH_CLOCK_REQ, QCH_CON_BCM_CPUCL0_QCH_EXPIRE_VAL),
	CLK_QCH(BCM_CPUCL1_QCH, QCH_CON_BCM_CPUCL1_QCH_ENABLE, QCH_CON_BCM_CPUCL1_QCH_CLOCK_REQ, QCH_CON_BCM_CPUCL1_QCH_EXPIRE_VAL),
	CLK_QCH(BCM_G3D0_QCH, QCH_CON_BCM_G3D0_QCH_ENABLE, QCH_CON_BCM_G3D0_QCH_CLOCK_REQ, QCH_CON_BCM_G3D0_QCH_EXPIRE_VAL),
	CLK_QCH(BCM_G3D1_QCH, QCH_CON_BCM_G3D1_QCH_ENABLE, QCH_CON_BCM_G3D1_QCH_CLOCK_REQ, QCH_CON_BCM_G3D1_QCH_EXPIRE_VAL),
	CLK_QCH(BCM_G3D2_QCH, QCH_CON_BCM_G3D2_QCH_ENABLE, QCH_CON_BCM_G3D2_QCH_CLOCK_REQ, QCH_CON_BCM_G3D2_QCH_EXPIRE_VAL),
	CLK_QCH(BCM_G3D3_QCH, QCH_CON_BCM_G3D3_QCH_ENABLE, QCH_CON_BCM_G3D3_QCH_CLOCK_REQ, QCH_CON_BCM_G3D3_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_CORE_QCH, QCH_CON_SYSREG_CORE_QCH_ENABLE, QCH_CON_SYSREG_CORE_QCH_CLOCK_REQ, QCH_CON_SYSREG_CORE_QCH_EXPIRE_VAL),
	CLK_QCH(TREX_D_CORE_QCH, QCH_CON_TREX_D_CORE_QCH_ENABLE, QCH_CON_TREX_D_CORE_QCH_CLOCK_REQ, QCH_CON_TREX_D_CORE_QCH_EXPIRE_VAL),
	CLK_QCH(TREX_P0_CORE_QCH, QCH_CON_TREX_P0_CORE_QCH_ENABLE, QCH_CON_TREX_P0_CORE_QCH_CLOCK_REQ, QCH_CON_TREX_P0_CORE_QCH_EXPIRE_VAL),
	CLK_QCH(TREX_P1_CORE_QCH, QCH_CON_TREX_P1_CORE_QCH_ENABLE, QCH_CON_TREX_P1_CORE_QCH_CLOCK_REQ, QCH_CON_TREX_P1_CORE_QCH_EXPIRE_VAL),
	CLK_QCH(BUSIF_DROOPDETECTOR_CPUCL0_QCH, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_ENABLE, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_CLOCK_REQ, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_EXPIRE_VAL),
	CLK_QCH(BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP0, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP0_ENABLE, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP0_CLOCK_REQ, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP0_EXPIRE_VAL),
	CLK_QCH(BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP1, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP1_ENABLE, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP1_CLOCK_REQ, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP1_EXPIRE_VAL),
	CLK_QCH(BUSIF_HPMCPUCL0_QCH, QCH_CON_BUSIF_HPMCPUCL0_QCH_ENABLE, QCH_CON_BUSIF_HPMCPUCL0_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMCPUCL0_QCH_EXPIRE_VAL),
	CLK_QCH(CLUSTER0_QCH, DMYQCH_CON_CLUSTER0_QCH_ENABLE, DMYQCH_CON_CLUSTER0_QCH_CLOCK_REQ, EMPTY_CAL_ID),
	CLK_QCH(CLUSTER0_QCH_LHS_ATB_T0_CLUSTER0, QCH_CON_CLUSTER0_QCH_LHS_ATB_T0_CLUSTER0_ENABLE, QCH_CON_CLUSTER0_QCH_LHS_ATB_T0_CLUSTER0_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_LHS_ATB_T0_CLUSTER0_EXPIRE_VAL),
	CLK_QCH(CLUSTER0_QCH_LHS_ATB_T1_CLUSTER0, QCH_CON_CLUSTER0_QCH_LHS_ATB_T1_CLUSTER0_ENABLE, QCH_CON_CLUSTER0_QCH_LHS_ATB_T1_CLUSTER0_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_LHS_ATB_T1_CLUSTER0_EXPIRE_VAL),
	CLK_QCH(CLUSTER0_QCH_LHS_ATB_T2_CLUSTER0, QCH_CON_CLUSTER0_QCH_LHS_ATB_T2_CLUSTER0_ENABLE, QCH_CON_CLUSTER0_QCH_LHS_ATB_T2_CLUSTER0_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_LHS_ATB_T2_CLUSTER0_EXPIRE_VAL),
	CLK_QCH(CLUSTER0_QCH_LHS_ATB_T3_CLUSTER0, QCH_CON_CLUSTER0_QCH_LHS_ATB_T3_CLUSTER0_ENABLE, QCH_CON_CLUSTER0_QCH_LHS_ATB_T3_CLUSTER0_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_LHS_ATB_T3_CLUSTER0_EXPIRE_VAL),
	CLK_QCH(CMU_CPUCL0_SHORTSTOP_QCH, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_EXPIRE_VAL),
	CLK_QCH(CPUCL0_CMU_CPUCL0_QCH, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_ENABLE, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_CLOCK_REQ, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_CPUCL0_QCH, QCH_CON_LHM_AXI_P_CPUCL0_QCH_ENABLE, QCH_CON_LHM_AXI_P_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_CPUCL0_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_CPUCL0_QCH, QCH_CON_PMU_CPUCL0_QCH_ENABLE, QCH_CON_PMU_CPUCL0_QCH_CLOCK_REQ, QCH_CON_PMU_CPUCL0_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_CPUCL0_QCH, QCH_CON_SYSREG_CPUCL0_QCH_ENABLE, QCH_CON_SYSREG_CPUCL0_QCH_CLOCK_REQ, QCH_CON_SYSREG_CPUCL0_QCH_EXPIRE_VAL),
	CLK_QCH(BUSIF_HPMCPUCL1_QCH, QCH_CON_BUSIF_HPMCPUCL1_QCH_ENABLE, QCH_CON_BUSIF_HPMCPUCL1_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMCPUCL1_QCH_EXPIRE_VAL),
	CLK_QCH(CLUSTER1_QCH_CPU, DMYQCH_CON_CLUSTER1_QCH_CPU_ENABLE, DMYQCH_CON_CLUSTER1_QCH_CPU_CLOCK_REQ, EMPTY_CAL_ID),
	CLK_QCH(CLUSTER1_QCH_DBG, DMYQCH_CON_CLUSTER1_QCH_DBG_ENABLE, DMYQCH_CON_CLUSTER1_QCH_DBG_CLOCK_REQ, EMPTY_CAL_ID),
	CLK_QCH(CLUSTER1_QCH_LHS_ACE_D_CPUCL1, QCH_CON_CLUSTER1_QCH_LHS_ACE_D_CPUCL1_ENABLE, QCH_CON_CLUSTER1_QCH_LHS_ACE_D_CPUCL1_CLOCK_REQ, QCH_CON_CLUSTER1_QCH_LHS_ACE_D_CPUCL1_EXPIRE_VAL),
	CLK_QCH(CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1_ENABLE, QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1_CLOCK_REQ, QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1_EXPIRE_VAL),
	CLK_QCH(CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1_ENABLE, QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1_CLOCK_REQ, QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1_EXPIRE_VAL),
	CLK_QCH(CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1_ENABLE, QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1_CLOCK_REQ, QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1_EXPIRE_VAL),
	CLK_QCH(CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1_ENABLE, QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1_CLOCK_REQ, QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1_EXPIRE_VAL),
	CLK_QCH(CMU_CPUCL1_SHORTSTOP_QCH, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_EXPIRE_VAL),
	CLK_QCH(CPUCL1_CMU_CPUCL1_QCH, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_ENABLE, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_CLOCK_REQ, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_CPUCL1_QCH, QCH_CON_LHM_AXI_P_CPUCL1_QCH_ENABLE, QCH_CON_LHM_AXI_P_CPUCL1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_CPUCL1_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_CPUCL1_QCH, QCH_CON_PMU_CPUCL1_QCH_ENABLE, QCH_CON_PMU_CPUCL1_QCH_CLOCK_REQ, QCH_CON_PMU_CPUCL1_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_CPUCL1_QCH, QCH_CON_SYSREG_CPUCL1_QCH_ENABLE, QCH_CON_SYSREG_CPUCL1_QCH_CLOCK_REQ, QCH_CON_SYSREG_CPUCL1_QCH_EXPIRE_VAL),
	CLK_QCH(CSSYS_QCH, QCH_CON_CSSYS_QCH_ENABLE, QCH_CON_CSSYS_QCH_CLOCK_REQ, QCH_CON_CSSYS_QCH_EXPIRE_VAL),
	CLK_QCH(DBG_CMU_DBG_QCH, QCH_CON_DBG_CMU_DBG_QCH_ENABLE, QCH_CON_DBG_CMU_DBG_QCH_CLOCK_REQ, QCH_CON_DBG_CMU_DBG_QCH_EXPIRE_VAL),
	CLK_QCH(DUMPPC_CPUCL0_QCH, QCH_CON_DUMPPC_CPUCL0_QCH_ENABLE, QCH_CON_DUMPPC_CPUCL0_QCH_CLOCK_REQ, QCH_CON_DUMPPC_CPUCL0_QCH_EXPIRE_VAL),
	CLK_QCH(DUMPPC_CPUCL1_QCH, QCH_CON_DUMPPC_CPUCL1_QCH_ENABLE, QCH_CON_DUMPPC_CPUCL1_QCH_CLOCK_REQ, QCH_CON_DUMPPC_CPUCL1_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_ATB_T0_CLUSTER0_QCH, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_ATB_T0_CLUSTER1_QCH, QCH_CON_LHM_ATB_T0_CLUSTER1_QCH_ENABLE, QCH_CON_LHM_ATB_T0_CLUSTER1_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T0_CLUSTER1_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_ATB_T1_CLUSTER0_QCH, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_ATB_T1_CLUSTER1_QCH, QCH_CON_LHM_ATB_T1_CLUSTER1_QCH_ENABLE, QCH_CON_LHM_ATB_T1_CLUSTER1_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T1_CLUSTER1_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_ATB_T2_CLUSTER0_QCH, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_ATB_T2_CLUSTER1_QCH, QCH_CON_LHM_ATB_T2_CLUSTER1_QCH_ENABLE, QCH_CON_LHM_ATB_T2_CLUSTER1_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T2_CLUSTER1_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_ATB_T3_CLUSTER0_QCH, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_ATB_T3_CLUSTER1_QCH, QCH_CON_LHM_ATB_T3_CLUSTER1_QCH_ENABLE, QCH_CON_LHM_ATB_T3_CLUSTER1_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T3_CLUSTER1_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_ATB_T_AUD_QCH, QCH_CON_LHM_ATB_T_AUD_QCH_ENABLE, QCH_CON_LHM_ATB_T_AUD_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T_AUD_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_ATB_T_BDU_QCH, QCH_CON_LHM_ATB_T_BDU_QCH_ENABLE, QCH_CON_LHM_ATB_T_BDU_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T_BDU_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_DBG_QCH, QCH_CON_LHM_AXI_P_DBG_QCH_ENABLE, QCH_CON_LHM_AXI_P_DBG_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DBG_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_G_CSSYS_QCH, QCH_CON_LHS_AXI_G_CSSYS_QCH_ENABLE, QCH_CON_LHS_AXI_G_CSSYS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G_CSSYS_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_G_ETR_QCH, QCH_CON_LHS_AXI_G_ETR_QCH_ENABLE, QCH_CON_LHS_AXI_G_ETR_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G_ETR_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_DBG_QCH, QCH_CON_PMU_DBG_QCH_ENABLE, QCH_CON_PMU_DBG_QCH_CLOCK_REQ, QCH_CON_PMU_DBG_QCH_EXPIRE_VAL),
	CLK_QCH(SECJTAG_QCH, QCH_CON_SECJTAG_QCH_ENABLE, QCH_CON_SECJTAG_QCH_CLOCK_REQ, QCH_CON_SECJTAG_QCH_EXPIRE_VAL),
	CLK_QCH(STM_TXACTOR_QCH, QCH_CON_STM_TXACTOR_QCH_ENABLE, QCH_CON_STM_TXACTOR_QCH_CLOCK_REQ, QCH_CON_STM_TXACTOR_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_DBG_QCH, QCH_CON_SYSREG_DBG_QCH_ENABLE, QCH_CON_SYSREG_DBG_QCH_CLOCK_REQ, QCH_CON_SYSREG_DBG_QCH_EXPIRE_VAL),
	CLK_QCH(BTM_DCAM_QCH, QCH_CON_BTM_DCAM_QCH_ENABLE, QCH_CON_BTM_DCAM_QCH_CLOCK_REQ, QCH_CON_BTM_DCAM_QCH_EXPIRE_VAL),
	CLK_QCH(DCAM_CMU_DCAM_QCH, QCH_CON_DCAM_CMU_DCAM_QCH_ENABLE, QCH_CON_DCAM_CMU_DCAM_QCH_CLOCK_REQ, QCH_CON_DCAM_CMU_DCAM_QCH_EXPIRE_VAL),
	CLK_QCH(DCP_QCH, QCH_CON_DCP_QCH_ENABLE, QCH_CON_DCP_QCH_CLOCK_REQ, QCH_CON_DCP_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_SRDZDCAM_QCH, QCH_CON_LHM_AXI_P_SRDZDCAM_QCH_ENABLE, QCH_CON_LHM_AXI_P_SRDZDCAM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_SRDZDCAM_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_ATB_DCAMSRDZ_QCH, QCH_CON_LHS_ATB_DCAMSRDZ_QCH_ENABLE, QCH_CON_LHS_ATB_DCAMSRDZ_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_DCAMSRDZ_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_D_DCAMSRDZ_QCH, QCH_CON_LHS_AXI_D_DCAMSRDZ_QCH_ENABLE, QCH_CON_LHS_AXI_D_DCAMSRDZ_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_DCAMSRDZ_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_DCAM_QCH, QCH_CON_PMU_DCAM_QCH_ENABLE, QCH_CON_PMU_DCAM_QCH_CLOCK_REQ, QCH_CON_PMU_DCAM_QCH_EXPIRE_VAL),
	CLK_QCH(BCM_DCAM_QCH, QCH_CON_BCM_DCAM_QCH_ENABLE, QCH_CON_BCM_DCAM_QCH_CLOCK_REQ, QCH_CON_BCM_DCAM_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_DCAM_QCH, QCH_CON_SYSREG_DCAM_QCH_ENABLE, QCH_CON_SYSREG_DCAM_QCH_CLOCK_REQ, QCH_CON_SYSREG_DCAM_QCH_EXPIRE_VAL),
	CLK_QCH(BTM_DPUD0_QCH, QCH_CON_BTM_DPUD0_QCH_ENABLE, QCH_CON_BTM_DPUD0_QCH_CLOCK_REQ, QCH_CON_BTM_DPUD0_QCH_EXPIRE_VAL),
	CLK_QCH(BTM_DPUD1_QCH, QCH_CON_BTM_DPUD1_QCH_ENABLE, QCH_CON_BTM_DPUD1_QCH_CLOCK_REQ, QCH_CON_BTM_DPUD1_QCH_EXPIRE_VAL),
	CLK_QCH(BTM_DPUD2_QCH, QCH_CON_BTM_DPUD2_QCH_ENABLE, QCH_CON_BTM_DPUD2_QCH_CLOCK_REQ, QCH_CON_BTM_DPUD2_QCH_EXPIRE_VAL),
	CLK_QCH(DECON0_QCH, QCH_CON_DECON0_QCH_ENABLE, QCH_CON_DECON0_QCH_CLOCK_REQ, QCH_CON_DECON0_QCH_EXPIRE_VAL),
	CLK_QCH(DPP_QCH_DPP_G0, QCH_CON_DPP_QCH_DPP_G0_ENABLE, QCH_CON_DPP_QCH_DPP_G0_CLOCK_REQ, QCH_CON_DPP_QCH_DPP_G0_EXPIRE_VAL),
	CLK_QCH(DPP_QCH_DPP_G1, QCH_CON_DPP_QCH_DPP_G1_ENABLE, QCH_CON_DPP_QCH_DPP_G1_CLOCK_REQ, QCH_CON_DPP_QCH_DPP_G1_EXPIRE_VAL),
	CLK_QCH(DPP_QCH_DPP_VGR, QCH_CON_DPP_QCH_DPP_VGR_ENABLE, QCH_CON_DPP_QCH_DPP_VGR_CLOCK_REQ, QCH_CON_DPP_QCH_DPP_VGR_EXPIRE_VAL),
	CLK_QCH(DPU0_CMU_DPU0_QCH, QCH_CON_DPU0_CMU_DPU0_QCH_ENABLE, QCH_CON_DPU0_CMU_DPU0_QCH_CLOCK_REQ, QCH_CON_DPU0_CMU_DPU0_QCH_EXPIRE_VAL),
	CLK_QCH(DPU_DMA_QCH, QCH_CON_DPU_DMA_QCH_ENABLE, QCH_CON_DPU_DMA_QCH_CLOCK_REQ, QCH_CON_DPU_DMA_QCH_EXPIRE_VAL),
	CLK_QCH(DPU_WB_MUX_QCH, QCH_CON_DPU_WB_MUX_QCH_ENABLE, QCH_CON_DPU_WB_MUX_QCH_CLOCK_REQ, QCH_CON_DPU_WB_MUX_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P0_DPU_QCH, QCH_CON_LHM_AXI_P0_DPU_QCH_ENABLE, QCH_CON_LHM_AXI_P0_DPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P0_DPU_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_D0_DPU_QCH, QCH_CON_LHS_AXI_D0_DPU_QCH_ENABLE, QCH_CON_LHS_AXI_D0_DPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_DPU_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_D1_DPU_QCH, QCH_CON_LHS_AXI_D1_DPU_QCH_ENABLE, QCH_CON_LHS_AXI_D1_DPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_DPU_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_D2_DPU_QCH, QCH_CON_LHS_AXI_D2_DPU_QCH_ENABLE, QCH_CON_LHS_AXI_D2_DPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D2_DPU_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_D_USBTV_QCH, QCH_CON_LHS_AXI_D_USBTV_QCH_ENABLE, QCH_CON_LHS_AXI_D_USBTV_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_USBTV_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_DPU0_QCH, QCH_CON_PMU_DPU0_QCH_ENABLE, QCH_CON_PMU_DPU0_QCH_CLOCK_REQ, QCH_CON_PMU_DPU0_QCH_EXPIRE_VAL),
	CLK_QCH(BCM_DPUD0_QCH, QCH_CON_BCM_DPUD0_QCH_ENABLE, QCH_CON_BCM_DPUD0_QCH_CLOCK_REQ, QCH_CON_BCM_DPUD0_QCH_EXPIRE_VAL),
	CLK_QCH(BCM_DPUD1_QCH, QCH_CON_BCM_DPUD1_QCH_ENABLE, QCH_CON_BCM_DPUD1_QCH_CLOCK_REQ, QCH_CON_BCM_DPUD1_QCH_EXPIRE_VAL),
	CLK_QCH(BCM_DPUD2_QCH, QCH_CON_BCM_DPUD2_QCH_ENABLE, QCH_CON_BCM_DPUD2_QCH_CLOCK_REQ, QCH_CON_BCM_DPUD2_QCH_EXPIRE_VAL),
	CLK_QCH(SYSMMU_DPUD0_QCH, QCH_CON_SYSMMU_DPUD0_QCH_ENABLE, QCH_CON_SYSMMU_DPUD0_QCH_CLOCK_REQ, QCH_CON_SYSMMU_DPUD0_QCH_EXPIRE_VAL),
	CLK_QCH(SYSMMU_DPUD1_QCH, QCH_CON_SYSMMU_DPUD1_QCH_ENABLE, QCH_CON_SYSMMU_DPUD1_QCH_CLOCK_REQ, QCH_CON_SYSMMU_DPUD1_QCH_EXPIRE_VAL),
	CLK_QCH(SYSMMU_DPUD2_QCH, QCH_CON_SYSMMU_DPUD2_QCH_ENABLE, QCH_CON_SYSMMU_DPUD2_QCH_CLOCK_REQ, QCH_CON_SYSMMU_DPUD2_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_DPU0_QCH, QCH_CON_SYSREG_DPU0_QCH_ENABLE, QCH_CON_SYSREG_DPU0_QCH_CLOCK_REQ, QCH_CON_SYSREG_DPU0_QCH_EXPIRE_VAL),
	CLK_QCH(DECON1_QCH, QCH_CON_DECON1_QCH_ENABLE, QCH_CON_DECON1_QCH_CLOCK_REQ, QCH_CON_DECON1_QCH_EXPIRE_VAL),
	CLK_QCH(DECON2_QCH_ACLK, QCH_CON_DECON2_QCH_ACLK_ENABLE, QCH_CON_DECON2_QCH_ACLK_CLOCK_REQ, QCH_CON_DECON2_QCH_ACLK_EXPIRE_VAL),
	CLK_QCH(DECON2_QCH_VCLK, QCH_CON_DECON2_QCH_VCLK_ENABLE, QCH_CON_DECON2_QCH_VCLK_CLOCK_REQ, QCH_CON_DECON2_QCH_VCLK_EXPIRE_VAL),
	CLK_QCH(DPU1_CMU_DPU1_QCH, QCH_CON_DPU1_CMU_DPU1_QCH_ENABLE, QCH_CON_DPU1_CMU_DPU1_QCH_CLOCK_REQ, QCH_CON_DPU1_CMU_DPU1_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_DPU1_QCH, QCH_CON_LHM_AXI_P_DPU1_QCH_ENABLE, QCH_CON_LHM_AXI_P_DPU1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DPU1_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_ATB_DPTX_QCH, QCH_CON_LHS_ATB_DPTX_QCH_ENABLE, QCH_CON_LHS_ATB_DPTX_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_DPTX_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_DPU1_QCH, QCH_CON_PMU_DPU1_QCH_ENABLE, QCH_CON_PMU_DPU1_QCH_CLOCK_REQ, QCH_CON_PMU_DPU1_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_DPU1_QCH, QCH_CON_SYSREG_DPU1_QCH_ENABLE, QCH_CON_SYSREG_DPU1_QCH_CLOCK_REQ, QCH_CON_SYSREG_DPU1_QCH_EXPIRE_VAL),
	CLK_QCH(BTM_SCORE_QCH, QCH_CON_BTM_SCORE_QCH_ENABLE, QCH_CON_BTM_SCORE_QCH_CLOCK_REQ, QCH_CON_BTM_SCORE_QCH_EXPIRE_VAL),
	CLK_QCH(DSP_CMU_DSP_QCH, QCH_CON_DSP_CMU_DSP_QCH_ENABLE, QCH_CON_DSP_CMU_DSP_QCH_CLOCK_REQ, QCH_CON_DSP_CMU_DSP_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_D_IVADSP_QCH, QCH_CON_LHM_AXI_D_IVADSP_QCH_ENABLE, QCH_CON_LHM_AXI_D_IVADSP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_IVADSP_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_D_VPUDSP_QCH, QCH_CON_LHM_AXI_D_VPUDSP_QCH_ENABLE, QCH_CON_LHM_AXI_D_VPUDSP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_VPUDSP_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_DSP_QCH, QCH_CON_LHM_AXI_P_DSP_QCH_ENABLE, QCH_CON_LHM_AXI_P_DSP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DSP_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_IVADSP_QCH, QCH_CON_LHM_AXI_P_IVADSP_QCH_ENABLE, QCH_CON_LHM_AXI_P_IVADSP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_IVADSP_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_ACEL_D_DSP_QCH, QCH_CON_LHS_ACEL_D_DSP_QCH_ENABLE, QCH_CON_LHS_ACEL_D_DSP_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_DSP_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_DSPIVA_QCH, QCH_CON_LHS_AXI_P_DSPIVA_QCH_ENABLE, QCH_CON_LHS_AXI_P_DSPIVA_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_DSPIVA_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_DSPVPU_QCH, QCH_CON_LHS_AXI_P_DSPVPU_QCH_ENABLE, QCH_CON_LHS_AXI_P_DSPVPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_DSPVPU_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_DSP_QCH, QCH_CON_PMU_DSP_QCH_ENABLE, QCH_CON_PMU_DSP_QCH_CLOCK_REQ, QCH_CON_PMU_DSP_QCH_EXPIRE_VAL),
	CLK_QCH(BCM_SCORE_QCH, QCH_CON_BCM_SCORE_QCH_ENABLE, QCH_CON_BCM_SCORE_QCH_CLOCK_REQ, QCH_CON_BCM_SCORE_QCH_EXPIRE_VAL),
	CLK_QCH(SCORE_QCH, QCH_CON_SCORE_QCH_ENABLE, QCH_CON_SCORE_QCH_CLOCK_REQ, QCH_CON_SCORE_QCH_EXPIRE_VAL),
	CLK_QCH(SMMU_SCORE_QCH, QCH_CON_SMMU_SCORE_QCH_ENABLE, QCH_CON_SMMU_SCORE_QCH_CLOCK_REQ, QCH_CON_SMMU_SCORE_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_DSP_QCH, QCH_CON_SYSREG_DSP_QCH_ENABLE, QCH_CON_SYSREG_DSP_QCH_CLOCK_REQ, QCH_CON_SYSREG_DSP_QCH_EXPIRE_VAL),
	CLK_QCH(BTM_FSYS0_QCH, QCH_CON_BTM_FSYS0_QCH_ENABLE, QCH_CON_BTM_FSYS0_QCH_CLOCK_REQ, QCH_CON_BTM_FSYS0_QCH_EXPIRE_VAL),
	CLK_QCH(DP_LINK_QCH, QCH_CON_DP_LINK_QCH_ENABLE, QCH_CON_DP_LINK_QCH_CLOCK_REQ, QCH_CON_DP_LINK_QCH_EXPIRE_VAL),
	CLK_QCH(ETR_MIU_QCH_PCLK, QCH_CON_ETR_MIU_QCH_PCLK_ENABLE, QCH_CON_ETR_MIU_QCH_PCLK_CLOCK_REQ, QCH_CON_ETR_MIU_QCH_PCLK_EXPIRE_VAL),
	CLK_QCH(ETR_MIU_QCH_ACLK, QCH_CON_ETR_MIU_QCH_ACLK_ENABLE, QCH_CON_ETR_MIU_QCH_ACLK_CLOCK_REQ, QCH_CON_ETR_MIU_QCH_ACLK_EXPIRE_VAL),
	CLK_QCH(FSYS0_CMU_FSYS0_QCH, QCH_CON_FSYS0_CMU_FSYS0_QCH_ENABLE, QCH_CON_FSYS0_CMU_FSYS0_QCH_CLOCK_REQ, QCH_CON_FSYS0_CMU_FSYS0_QCH_EXPIRE_VAL),
	CLK_QCH(GPIO_FSYS0_QCH, QCH_CON_GPIO_FSYS0_QCH_ENABLE, QCH_CON_GPIO_FSYS0_QCH_CLOCK_REQ, QCH_CON_GPIO_FSYS0_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_D_USBTV_QCH, QCH_CON_LHM_AXI_D_USBTV_QCH_ENABLE, QCH_CON_LHM_AXI_D_USBTV_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_USBTV_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_G_ETR_QCH, QCH_CON_LHM_AXI_G_ETR_QCH_ENABLE, QCH_CON_LHM_AXI_G_ETR_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_G_ETR_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_FSYS0_QCH, QCH_CON_LHM_AXI_P_FSYS0_QCH_ENABLE, QCH_CON_LHM_AXI_P_FSYS0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_FSYS0_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_ACEL_D_FSYS0_QCH, QCH_CON_LHS_ACEL_D_FSYS0_QCH_ENABLE, QCH_CON_LHS_ACEL_D_FSYS0_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_FSYS0_QCH_EXPIRE_VAL),
	CLK_QCH(MMC_EMBD_QCH, QCH_CON_MMC_EMBD_QCH_ENABLE, QCH_CON_MMC_EMBD_QCH_CLOCK_REQ, QCH_CON_MMC_EMBD_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_FSYS0_QCH, QCH_CON_PMU_FSYS0_QCH_ENABLE, QCH_CON_PMU_FSYS0_QCH_CLOCK_REQ, QCH_CON_PMU_FSYS0_QCH_EXPIRE_VAL),
	CLK_QCH(BCM_FSYS0_QCH, QCH_CON_BCM_FSYS0_QCH_ENABLE, QCH_CON_BCM_FSYS0_QCH_CLOCK_REQ, QCH_CON_BCM_FSYS0_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_FSYS0_QCH, QCH_CON_SYSREG_FSYS0_QCH_ENABLE, QCH_CON_SYSREG_FSYS0_QCH_CLOCK_REQ, QCH_CON_SYSREG_FSYS0_QCH_EXPIRE_VAL),
	CLK_QCH(UFS_EMBD_QCH, QCH_CON_UFS_EMBD_QCH_ENABLE, QCH_CON_UFS_EMBD_QCH_CLOCK_REQ, QCH_CON_UFS_EMBD_QCH_EXPIRE_VAL),
	CLK_QCH(UFS_EMBD_QCH_FMP, QCH_CON_UFS_EMBD_QCH_FMP_ENABLE, QCH_CON_UFS_EMBD_QCH_FMP_CLOCK_REQ, QCH_CON_UFS_EMBD_QCH_FMP_EXPIRE_VAL),
	CLK_QCH(USBTV_QCH_USB30DRD_LINK, QCH_CON_USBTV_QCH_USB30DRD_LINK_ENABLE, QCH_CON_USBTV_QCH_USB30DRD_LINK_CLOCK_REQ, QCH_CON_USBTV_QCH_USB30DRD_LINK_EXPIRE_VAL),
	CLK_QCH(USBTV_QCH_USBTV_HOST, QCH_CON_USBTV_QCH_USBTV_HOST_ENABLE, QCH_CON_USBTV_QCH_USBTV_HOST_CLOCK_REQ, QCH_CON_USBTV_QCH_USBTV_HOST_EXPIRE_VAL),
	CLK_QCH(ADM_AHB_SSS_QCH, QCH_CON_ADM_AHB_SSS_QCH_ENABLE, QCH_CON_ADM_AHB_SSS_QCH_CLOCK_REQ, QCH_CON_ADM_AHB_SSS_QCH_EXPIRE_VAL),
	CLK_QCH(BTM_FSYS1_QCH, QCH_CON_BTM_FSYS1_QCH_ENABLE, QCH_CON_BTM_FSYS1_QCH_CLOCK_REQ, QCH_CON_BTM_FSYS1_QCH_EXPIRE_VAL),
	CLK_QCH(FSYS1_CMU_FSYS1_QCH, QCH_CON_FSYS1_CMU_FSYS1_QCH_ENABLE, QCH_CON_FSYS1_CMU_FSYS1_QCH_CLOCK_REQ, QCH_CON_FSYS1_CMU_FSYS1_QCH_EXPIRE_VAL),
	CLK_QCH(GPIO_FSYS1_QCH, QCH_CON_GPIO_FSYS1_QCH_ENABLE, QCH_CON_GPIO_FSYS1_QCH_CLOCK_REQ, QCH_CON_GPIO_FSYS1_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_FSYS1_QCH, QCH_CON_LHM_AXI_P_FSYS1_QCH_ENABLE, QCH_CON_LHM_AXI_P_FSYS1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_FSYS1_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_ACEL_D_FSYS1_QCH, QCH_CON_LHS_ACEL_D_FSYS1_QCH_ENABLE, QCH_CON_LHS_ACEL_D_FSYS1_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_FSYS1_QCH_EXPIRE_VAL),
	CLK_QCH(MMC_CARD_QCH, QCH_CON_MMC_CARD_QCH_ENABLE, QCH_CON_MMC_CARD_QCH_CLOCK_REQ, QCH_CON_MMC_CARD_QCH_EXPIRE_VAL),
	CLK_QCH(PCIE_QCH_PCIE0_MSTR, QCH_CON_PCIE_QCH_PCIE0_MSTR_ENABLE, QCH_CON_PCIE_QCH_PCIE0_MSTR_CLOCK_REQ, QCH_CON_PCIE_QCH_PCIE0_MSTR_EXPIRE_VAL),
	CLK_QCH(PCIE_QCH_PCIE_PCS, QCH_CON_PCIE_QCH_PCIE_PCS_ENABLE, QCH_CON_PCIE_QCH_PCIE_PCS_CLOCK_REQ, QCH_CON_PCIE_QCH_PCIE_PCS_EXPIRE_VAL),
	CLK_QCH(PCIE_QCH_PCIE_PHY, QCH_CON_PCIE_QCH_PCIE_PHY_ENABLE, QCH_CON_PCIE_QCH_PCIE_PHY_CLOCK_REQ, QCH_CON_PCIE_QCH_PCIE_PHY_EXPIRE_VAL),
	CLK_QCH(PCIE_QCH_PCIE0_DBI, QCH_CON_PCIE_QCH_PCIE0_DBI_ENABLE, QCH_CON_PCIE_QCH_PCIE0_DBI_CLOCK_REQ, QCH_CON_PCIE_QCH_PCIE0_DBI_EXPIRE_VAL),
	CLK_QCH(PCIE_QCH_PCIE0_APB, QCH_CON_PCIE_QCH_PCIE0_APB_ENABLE, QCH_CON_PCIE_QCH_PCIE0_APB_CLOCK_REQ, QCH_CON_PCIE_QCH_PCIE0_APB_EXPIRE_VAL),
	CLK_QCH(PCIE_QCH_PCIE_SOCPLL, DMYQCH_CON_PCIE_QCH_PCIE_SOCPLL_ENABLE, DMYQCH_CON_PCIE_QCH_PCIE_SOCPLL_CLOCK_REQ, EMPTY_CAL_ID),
	CLK_QCH(PCIE_QCH_PCIE1_MSTR, QCH_CON_PCIE_QCH_PCIE1_MSTR_ENABLE, QCH_CON_PCIE_QCH_PCIE1_MSTR_CLOCK_REQ, QCH_CON_PCIE_QCH_PCIE1_MSTR_EXPIRE_VAL),
	CLK_QCH(PCIE_QCH_PCIE1_DBI, QCH_CON_PCIE_QCH_PCIE1_DBI_ENABLE, QCH_CON_PCIE_QCH_PCIE1_DBI_CLOCK_REQ, QCH_CON_PCIE_QCH_PCIE1_DBI_EXPIRE_VAL),
	CLK_QCH(PCIE_QCH_PCIE1_APB, QCH_CON_PCIE_QCH_PCIE1_APB_ENABLE, QCH_CON_PCIE_QCH_PCIE1_APB_CLOCK_REQ, QCH_CON_PCIE_QCH_PCIE1_APB_EXPIRE_VAL),
	CLK_QCH(PMU_FSYS1_QCH, QCH_CON_PMU_FSYS1_QCH_ENABLE, QCH_CON_PMU_FSYS1_QCH_CLOCK_REQ, QCH_CON_PMU_FSYS1_QCH_EXPIRE_VAL),
	CLK_QCH(BCM_FSYS1_QCH, QCH_CON_BCM_FSYS1_QCH_ENABLE, QCH_CON_BCM_FSYS1_QCH_CLOCK_REQ, QCH_CON_BCM_FSYS1_QCH_EXPIRE_VAL),
	CLK_QCH(RTIC_QCH, QCH_CON_RTIC_QCH_ENABLE, QCH_CON_RTIC_QCH_CLOCK_REQ, QCH_CON_RTIC_QCH_EXPIRE_VAL),
	CLK_QCH(SSS_QCH, QCH_CON_SSS_QCH_ENABLE, QCH_CON_SSS_QCH_CLOCK_REQ, QCH_CON_SSS_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_FSYS1_QCH, QCH_CON_SYSREG_FSYS1_QCH_ENABLE, QCH_CON_SYSREG_FSYS1_QCH_CLOCK_REQ, QCH_CON_SYSREG_FSYS1_QCH_EXPIRE_VAL),
	CLK_QCH(TOE_WIFI0_QCH, QCH_CON_TOE_WIFI0_QCH_ENABLE, QCH_CON_TOE_WIFI0_QCH_CLOCK_REQ, QCH_CON_TOE_WIFI0_QCH_EXPIRE_VAL),
	CLK_QCH(TOE_WIFI1_QCH, QCH_CON_TOE_WIFI1_QCH_ENABLE, QCH_CON_TOE_WIFI1_QCH_CLOCK_REQ, QCH_CON_TOE_WIFI1_QCH_EXPIRE_VAL),
	CLK_QCH(UFS_CARD_QCH, QCH_CON_UFS_CARD_QCH_ENABLE, QCH_CON_UFS_CARD_QCH_CLOCK_REQ, QCH_CON_UFS_CARD_QCH_EXPIRE_VAL),
	CLK_QCH(UFS_CARD_QCH_FMP, QCH_CON_UFS_CARD_QCH_FMP_ENABLE, QCH_CON_UFS_CARD_QCH_FMP_CLOCK_REQ, QCH_CON_UFS_CARD_QCH_FMP_EXPIRE_VAL),
	CLK_QCH(BTM_G2DD0_QCH, QCH_CON_BTM_G2DD0_QCH_ENABLE, QCH_CON_BTM_G2DD0_QCH_CLOCK_REQ, QCH_CON_BTM_G2DD0_QCH_EXPIRE_VAL),
	CLK_QCH(BTM_G2DD1_QCH, QCH_CON_BTM_G2DD1_QCH_ENABLE, QCH_CON_BTM_G2DD1_QCH_CLOCK_REQ, QCH_CON_BTM_G2DD1_QCH_EXPIRE_VAL),
	CLK_QCH(BTM_G2DD2_QCH, QCH_CON_BTM_G2DD2_QCH_ENABLE, QCH_CON_BTM_G2DD2_QCH_CLOCK_REQ, QCH_CON_BTM_G2DD2_QCH_EXPIRE_VAL),
	CLK_QCH(G2D_QCH, QCH_CON_G2D_QCH_ENABLE, QCH_CON_G2D_QCH_CLOCK_REQ, QCH_CON_G2D_QCH_EXPIRE_VAL),
	CLK_QCH(G2D_CMU_G2D_QCH, QCH_CON_G2D_CMU_G2D_QCH_ENABLE, QCH_CON_G2D_CMU_G2D_QCH_CLOCK_REQ, QCH_CON_G2D_CMU_G2D_QCH_EXPIRE_VAL),
	CLK_QCH(JPEG_QCH, QCH_CON_JPEG_QCH_ENABLE, QCH_CON_JPEG_QCH_CLOCK_REQ, QCH_CON_JPEG_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_G2D_QCH, QCH_CON_LHM_AXI_P_G2D_QCH_ENABLE, QCH_CON_LHM_AXI_P_G2D_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_G2D_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_ACEL_D0_G2D_QCH, QCH_CON_LHS_ACEL_D0_G2D_QCH_ENABLE, QCH_CON_LHS_ACEL_D0_G2D_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D0_G2D_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_ACEL_D1_G2D_QCH, QCH_CON_LHS_ACEL_D1_G2D_QCH_ENABLE, QCH_CON_LHS_ACEL_D1_G2D_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D1_G2D_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_ACEL_D2_G2D_QCH, QCH_CON_LHS_ACEL_D2_G2D_QCH_ENABLE, QCH_CON_LHS_ACEL_D2_G2D_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D2_G2D_QCH_EXPIRE_VAL),
	CLK_QCH(M2MSCALER_QCH, QCH_CON_M2MSCALER_QCH_ENABLE, QCH_CON_M2MSCALER_QCH_CLOCK_REQ, QCH_CON_M2MSCALER_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_G2D_QCH, QCH_CON_PMU_G2D_QCH_ENABLE, QCH_CON_PMU_G2D_QCH_CLOCK_REQ, QCH_CON_PMU_G2D_QCH_EXPIRE_VAL),
	CLK_QCH(BCM_G2DD0_QCH, QCH_CON_BCM_G2DD0_QCH_ENABLE, QCH_CON_BCM_G2DD0_QCH_CLOCK_REQ, QCH_CON_BCM_G2DD0_QCH_EXPIRE_VAL),
	CLK_QCH(BCM_G2DD1_QCH, QCH_CON_BCM_G2DD1_QCH_ENABLE, QCH_CON_BCM_G2DD1_QCH_CLOCK_REQ, QCH_CON_BCM_G2DD1_QCH_EXPIRE_VAL),
	CLK_QCH(BCM_G2DD2_QCH, QCH_CON_BCM_G2DD2_QCH_ENABLE, QCH_CON_BCM_G2DD2_QCH_CLOCK_REQ, QCH_CON_BCM_G2DD2_QCH_EXPIRE_VAL),
	CLK_QCH(QE_JPEG_QCH, QCH_CON_QE_JPEG_QCH_ENABLE, QCH_CON_QE_JPEG_QCH_CLOCK_REQ, QCH_CON_QE_JPEG_QCH_EXPIRE_VAL),
	CLK_QCH(QE_M2MSCALER_QCH, QCH_CON_QE_M2MSCALER_QCH_ENABLE, QCH_CON_QE_M2MSCALER_QCH_CLOCK_REQ, QCH_CON_QE_M2MSCALER_QCH_EXPIRE_VAL),
	CLK_QCH(SMMU_G2DD0_QCH, QCH_CON_SMMU_G2DD0_QCH_ENABLE, QCH_CON_SMMU_G2DD0_QCH_CLOCK_REQ, QCH_CON_SMMU_G2DD0_QCH_EXPIRE_VAL),
	CLK_QCH(SMMU_G2DD1_QCH, QCH_CON_SMMU_G2DD1_QCH_ENABLE, QCH_CON_SMMU_G2DD1_QCH_CLOCK_REQ, QCH_CON_SMMU_G2DD1_QCH_EXPIRE_VAL),
	CLK_QCH(SMMU_G2DD2_QCH, QCH_CON_SMMU_G2DD2_QCH_ENABLE, QCH_CON_SMMU_G2DD2_QCH_CLOCK_REQ, QCH_CON_SMMU_G2DD2_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_G2D_QCH, QCH_CON_SYSREG_G2D_QCH_ENABLE, QCH_CON_SYSREG_G2D_QCH_CLOCK_REQ, QCH_CON_SYSREG_G2D_QCH_EXPIRE_VAL),
	CLK_QCH(AGPU_QCH_G3D, QCH_CON_AGPU_QCH_G3D_ENABLE, QCH_CON_AGPU_QCH_G3D_CLOCK_REQ, QCH_CON_AGPU_QCH_G3D_EXPIRE_VAL),
	CLK_QCH(AGPU_QCH_LHM_AXI_G3DSFR, QCH_CON_AGPU_QCH_LHM_AXI_G3DSFR_ENABLE, QCH_CON_AGPU_QCH_LHM_AXI_G3DSFR_CLOCK_REQ, QCH_CON_AGPU_QCH_LHM_AXI_G3DSFR_EXPIRE_VAL),
	CLK_QCH(AGPU_QCH_LHS_ACE_D0_G3D, QCH_CON_AGPU_QCH_LHS_ACE_D0_G3D_ENABLE, QCH_CON_AGPU_QCH_LHS_ACE_D0_G3D_CLOCK_REQ, QCH_CON_AGPU_QCH_LHS_ACE_D0_G3D_EXPIRE_VAL),
	CLK_QCH(AGPU_QCH_LHS_ACE_D1_G3D, QCH_CON_AGPU_QCH_LHS_ACE_D1_G3D_ENABLE, QCH_CON_AGPU_QCH_LHS_ACE_D1_G3D_CLOCK_REQ, QCH_CON_AGPU_QCH_LHS_ACE_D1_G3D_EXPIRE_VAL),
	CLK_QCH(AGPU_QCH_LHS_ACE_D2_G3D, QCH_CON_AGPU_QCH_LHS_ACE_D2_G3D_ENABLE, QCH_CON_AGPU_QCH_LHS_ACE_D2_G3D_CLOCK_REQ, QCH_CON_AGPU_QCH_LHS_ACE_D2_G3D_EXPIRE_VAL),
	CLK_QCH(AGPU_QCH_LHS_ACE_D3_G3D, QCH_CON_AGPU_QCH_LHS_ACE_D3_G3D_ENABLE, QCH_CON_AGPU_QCH_LHS_ACE_D3_G3D_CLOCK_REQ, QCH_CON_AGPU_QCH_LHS_ACE_D3_G3D_EXPIRE_VAL),
	CLK_QCH(BUSIF_HPMG3D_QCH, QCH_CON_BUSIF_HPMG3D_QCH_ENABLE, QCH_CON_BUSIF_HPMG3D_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMG3D_QCH_EXPIRE_VAL),
	CLK_QCH(G3D_CMU_G3D_QCH, QCH_CON_G3D_CMU_G3D_QCH_ENABLE, QCH_CON_G3D_CMU_G3D_QCH_CLOCK_REQ, QCH_CON_G3D_CMU_G3D_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_G3D_QCH, QCH_CON_LHM_AXI_P_G3D_QCH_ENABLE, QCH_CON_LHM_AXI_P_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_G3D_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_G3DSFR_QCH, QCH_CON_LHS_AXI_G3DSFR_QCH_ENABLE, QCH_CON_LHS_AXI_G3DSFR_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G3DSFR_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_G3D_QCH, QCH_CON_PMU_G3D_QCH_ENABLE, QCH_CON_PMU_G3D_QCH_CLOCK_REQ, QCH_CON_PMU_G3D_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_G3D_QCH, QCH_CON_SYSREG_G3D_QCH_ENABLE, QCH_CON_SYSREG_G3D_QCH_CLOCK_REQ, QCH_CON_SYSREG_G3D_QCH_EXPIRE_VAL),
	CLK_QCH(IMEM_CMU_IMEM_QCH, QCH_CON_IMEM_CMU_IMEM_QCH_ENABLE, QCH_CON_IMEM_CMU_IMEM_QCH_CLOCK_REQ, QCH_CON_IMEM_CMU_IMEM_QCH_EXPIRE_VAL),
	CLK_QCH(INTMEM_QCH, QCH_CON_INTMEM_QCH_ENABLE, QCH_CON_INTMEM_QCH_CLOCK_REQ, QCH_CON_INTMEM_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_IMEM_QCH, QCH_CON_LHM_AXI_P_IMEM_QCH_ENABLE, QCH_CON_LHM_AXI_P_IMEM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_IMEM_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_IMEM_QCH, QCH_CON_PMU_IMEM_QCH_ENABLE, QCH_CON_PMU_IMEM_QCH_CLOCK_REQ, QCH_CON_PMU_IMEM_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_IMEM_QCH, QCH_CON_SYSREG_IMEM_QCH_ENABLE, QCH_CON_SYSREG_IMEM_QCH_CLOCK_REQ, QCH_CON_SYSREG_IMEM_QCH_EXPIRE_VAL),
	CLK_QCH(ISPHQ_CMU_ISPHQ_QCH, QCH_CON_ISPHQ_CMU_ISPHQ_QCH_ENABLE, QCH_CON_ISPHQ_CMU_ISPHQ_QCH_CLOCK_REQ, QCH_CON_ISPHQ_CMU_ISPHQ_QCH_EXPIRE_VAL),
	CLK_QCH(ISP_EWGEN_ISPHQ_QCH, QCH_CON_ISP_EWGEN_ISPHQ_QCH_ENABLE, QCH_CON_ISP_EWGEN_ISPHQ_QCH_CLOCK_REQ, QCH_CON_ISP_EWGEN_ISPHQ_QCH_EXPIRE_VAL),
	CLK_QCH(IS_ISPHQ_QCH_3AA, QCH_CON_IS_ISPHQ_QCH_3AA_ENABLE, QCH_CON_IS_ISPHQ_QCH_3AA_CLOCK_REQ, QCH_CON_IS_ISPHQ_QCH_3AA_EXPIRE_VAL),
	CLK_QCH(IS_ISPHQ_QCH_ISPHQ, QCH_CON_IS_ISPHQ_QCH_ISPHQ_ENABLE, QCH_CON_IS_ISPHQ_QCH_ISPHQ_CLOCK_REQ, QCH_CON_IS_ISPHQ_QCH_ISPHQ_EXPIRE_VAL),
	CLK_QCH(IS_ISPHQ_QCH_QE_3AA, QCH_CON_IS_ISPHQ_QCH_QE_3AA_ENABLE, QCH_CON_IS_ISPHQ_QCH_QE_3AA_CLOCK_REQ, QCH_CON_IS_ISPHQ_QCH_QE_3AA_EXPIRE_VAL),
	CLK_QCH(IS_ISPHQ_QCH_QE_ISPHQ, QCH_CON_IS_ISPHQ_QCH_QE_ISPHQ_ENABLE, QCH_CON_IS_ISPHQ_QCH_QE_ISPHQ_CLOCK_REQ, QCH_CON_IS_ISPHQ_QCH_QE_ISPHQ_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_ISPHQ_QCH, QCH_CON_LHM_AXI_P_ISPHQ_QCH_ENABLE, QCH_CON_LHM_AXI_P_ISPHQ_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_ISPHQ_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_LD_ISPHQ_QCH, QCH_CON_LHS_AXI_LD_ISPHQ_QCH_ENABLE, QCH_CON_LHS_AXI_LD_ISPHQ_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_LD_ISPHQ_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_ISPHQ_QCH, QCH_CON_PMU_ISPHQ_QCH_ENABLE, QCH_CON_PMU_ISPHQ_QCH_CLOCK_REQ, QCH_CON_PMU_ISPHQ_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_ISPHQ_QCH, QCH_CON_SYSREG_ISPHQ_QCH_ENABLE, QCH_CON_SYSREG_ISPHQ_QCH_CLOCK_REQ, QCH_CON_SYSREG_ISPHQ_QCH_EXPIRE_VAL),
	CLK_QCH(BTM_ISPLP_QCH, QCH_CON_BTM_ISPLP_QCH_ENABLE, QCH_CON_BTM_ISPLP_QCH_CLOCK_REQ, QCH_CON_BTM_ISPLP_QCH_EXPIRE_VAL),
	CLK_QCH(ISPLP_CMU_ISPLP_QCH, QCH_CON_ISPLP_CMU_ISPLP_QCH_ENABLE, QCH_CON_ISPLP_CMU_ISPLP_QCH_CLOCK_REQ, QCH_CON_ISPLP_CMU_ISPLP_QCH_EXPIRE_VAL),
	CLK_QCH(ISP_EWGEN_ISPLP_QCH, QCH_CON_ISP_EWGEN_ISPLP_QCH_ENABLE, QCH_CON_ISP_EWGEN_ISPLP_QCH_CLOCK_REQ, QCH_CON_ISP_EWGEN_ISPLP_QCH_EXPIRE_VAL),
	CLK_QCH(IS_ISPLP_QCH_3AAW, QCH_CON_IS_ISPLP_QCH_3AAW_ENABLE, QCH_CON_IS_ISPLP_QCH_3AAW_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_3AAW_EXPIRE_VAL),
	CLK_QCH(IS_ISPLP_QCH_ISPLP, QCH_CON_IS_ISPLP_QCH_ISPLP_ENABLE, QCH_CON_IS_ISPLP_QCH_ISPLP_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_ISPLP_EXPIRE_VAL),
	CLK_QCH(IS_ISPLP_QCH_QE_3AAW, QCH_CON_IS_ISPLP_QCH_QE_3AAW_ENABLE, QCH_CON_IS_ISPLP_QCH_QE_3AAW_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_QE_3AAW_EXPIRE_VAL),
	CLK_QCH(IS_ISPLP_QCH_QE_ISPLP, QCH_CON_IS_ISPLP_QCH_QE_ISPLP_ENABLE, QCH_CON_IS_ISPLP_QCH_QE_ISPLP_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_QE_ISPLP_EXPIRE_VAL),
	CLK_QCH(IS_ISPLP_QCH_SMMU_ISPLP, QCH_CON_IS_ISPLP_QCH_SMMU_ISPLP_ENABLE, QCH_CON_IS_ISPLP_QCH_SMMU_ISPLP_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_SMMU_ISPLP_EXPIRE_VAL),
	CLK_QCH(IS_ISPLP_QCH_BCM_ISPLP, QCH_CON_IS_ISPLP_QCH_BCM_ISPLP_ENABLE, QCH_CON_IS_ISPLP_QCH_BCM_ISPLP_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_BCM_ISPLP_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_LD_ISPHQ_QCH, QCH_CON_LHM_AXI_LD_ISPHQ_QCH_ENABLE, QCH_CON_LHM_AXI_LD_ISPHQ_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_LD_ISPHQ_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_ISPLP_QCH, QCH_CON_LHM_AXI_P_ISPLP_QCH_ENABLE, QCH_CON_LHM_AXI_P_ISPLP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_ISPLP_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_D_ISPLP_QCH, QCH_CON_LHS_AXI_D_ISPLP_QCH_ENABLE, QCH_CON_LHS_AXI_D_ISPLP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_ISPLP_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_ISPLP_QCH, QCH_CON_PMU_ISPLP_QCH_ENABLE, QCH_CON_PMU_ISPLP_QCH_CLOCK_REQ, QCH_CON_PMU_ISPLP_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_ISPLP_QCH, QCH_CON_SYSREG_ISPLP_QCH_ENABLE, QCH_CON_SYSREG_ISPLP_QCH_CLOCK_REQ, QCH_CON_SYSREG_ISPLP_QCH_EXPIRE_VAL),
	CLK_QCH(BTM_IVA_QCH, QCH_CON_BTM_IVA_QCH_ENABLE, QCH_CON_BTM_IVA_QCH_CLOCK_REQ, QCH_CON_BTM_IVA_QCH_EXPIRE_VAL),
	CLK_QCH(IVA_QCH, QCH_CON_IVA_QCH_ENABLE, QCH_CON_IVA_QCH_CLOCK_REQ, QCH_CON_IVA_QCH_EXPIRE_VAL),
	CLK_QCH(IVA_CMU_IVA_QCH, QCH_CON_IVA_CMU_IVA_QCH_ENABLE, QCH_CON_IVA_CMU_IVA_QCH_CLOCK_REQ, QCH_CON_IVA_CMU_IVA_QCH_EXPIRE_VAL),
	CLK_QCH(IVA_INTMEM_QCH, QCH_CON_IVA_INTMEM_QCH_ENABLE, QCH_CON_IVA_INTMEM_QCH_CLOCK_REQ, QCH_CON_IVA_INTMEM_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_D_IVASC_QCH, QCH_CON_LHM_AXI_D_IVASC_QCH_ENABLE, QCH_CON_LHM_AXI_D_IVASC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_IVASC_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_DSPIVA_QCH, QCH_CON_LHM_AXI_P_DSPIVA_QCH_ENABLE, QCH_CON_LHM_AXI_P_DSPIVA_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DSPIVA_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_IVA_QCH, QCH_CON_LHM_AXI_P_IVA_QCH_ENABLE, QCH_CON_LHM_AXI_P_IVA_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_IVA_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_ACEL_D_IVA_QCH, QCH_CON_LHS_ACEL_D_IVA_QCH_ENABLE, QCH_CON_LHS_ACEL_D_IVA_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_IVA_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_D_IVADSP_QCH, QCH_CON_LHS_AXI_D_IVADSP_QCH_ENABLE, QCH_CON_LHS_AXI_D_IVADSP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_IVADSP_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_IVADSP_QCH, QCH_CON_LHS_AXI_P_IVADSP_QCH_ENABLE, QCH_CON_LHS_AXI_P_IVADSP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_IVADSP_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_IVA_QCH, QCH_CON_PMU_IVA_QCH_ENABLE, QCH_CON_PMU_IVA_QCH_CLOCK_REQ, QCH_CON_PMU_IVA_QCH_EXPIRE_VAL),
	CLK_QCH(BCM_IVA_QCH, QCH_CON_BCM_IVA_QCH_ENABLE, QCH_CON_BCM_IVA_QCH_CLOCK_REQ, QCH_CON_BCM_IVA_QCH_EXPIRE_VAL),
	CLK_QCH(SMMU_IVA_QCH, QCH_CON_SMMU_IVA_QCH_ENABLE, QCH_CON_SMMU_IVA_QCH_CLOCK_REQ, QCH_CON_SMMU_IVA_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_IVA_QCH, QCH_CON_SYSREG_IVA_QCH_ENABLE, QCH_CON_SYSREG_IVA_QCH_CLOCK_REQ, QCH_CON_SYSREG_IVA_QCH_EXPIRE_VAL),
	CLK_QCH(BTM_MFCD0_QCH, QCH_CON_BTM_MFCD0_QCH_ENABLE, QCH_CON_BTM_MFCD0_QCH_CLOCK_REQ, QCH_CON_BTM_MFCD0_QCH_EXPIRE_VAL),
	CLK_QCH(BTM_MFCD1_QCH, QCH_CON_BTM_MFCD1_QCH_ENABLE, QCH_CON_BTM_MFCD1_QCH_CLOCK_REQ, QCH_CON_BTM_MFCD1_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_MFC_QCH, QCH_CON_LHM_AXI_P_MFC_QCH_ENABLE, QCH_CON_LHM_AXI_P_MFC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MFC_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_D0_MFC_QCH, QCH_CON_LHS_AXI_D0_MFC_QCH_ENABLE, QCH_CON_LHS_AXI_D0_MFC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_MFC_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_D1_MFC_QCH, QCH_CON_LHS_AXI_D1_MFC_QCH_ENABLE, QCH_CON_LHS_AXI_D1_MFC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_MFC_QCH_EXPIRE_VAL),
	CLK_QCH(MFC_QCH, QCH_CON_MFC_QCH_ENABLE, QCH_CON_MFC_QCH_CLOCK_REQ, QCH_CON_MFC_QCH_EXPIRE_VAL),
	CLK_QCH(MFC_CMU_MFC_QCH, QCH_CON_MFC_CMU_MFC_QCH_ENABLE, QCH_CON_MFC_CMU_MFC_QCH_CLOCK_REQ, QCH_CON_MFC_CMU_MFC_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_MFC_QCH, QCH_CON_PMU_MFC_QCH_ENABLE, QCH_CON_PMU_MFC_QCH_CLOCK_REQ, QCH_CON_PMU_MFC_QCH_EXPIRE_VAL),
	CLK_QCH(BCM_MFCD0_QCH, QCH_CON_BCM_MFCD0_QCH_ENABLE, QCH_CON_BCM_MFCD0_QCH_CLOCK_REQ, QCH_CON_BCM_MFCD0_QCH_EXPIRE_VAL),
	CLK_QCH(BCM_MFCD1_QCH, QCH_CON_BCM_MFCD1_QCH_ENABLE, QCH_CON_BCM_MFCD1_QCH_CLOCK_REQ, QCH_CON_BCM_MFCD1_QCH_EXPIRE_VAL),
	CLK_QCH(SMMU_MFCD0_QCH, QCH_CON_SMMU_MFCD0_QCH_ENABLE, QCH_CON_SMMU_MFCD0_QCH_CLOCK_REQ, QCH_CON_SMMU_MFCD0_QCH_EXPIRE_VAL),
	CLK_QCH(SMMU_MFCD1_QCH, QCH_CON_SMMU_MFCD1_QCH_ENABLE, QCH_CON_SMMU_MFCD1_QCH_CLOCK_REQ, QCH_CON_SMMU_MFCD1_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_MFC_QCH, QCH_CON_SYSREG_MFC_QCH_ENABLE, QCH_CON_SYSREG_MFC_QCH_CLOCK_REQ, QCH_CON_SYSREG_MFC_QCH_EXPIRE_VAL),
	CLK_QCH(APBBR_DDRPHY_QCH, QCH_CON_APBBR_DDRPHY_QCH_ENABLE, QCH_CON_APBBR_DDRPHY_QCH_CLOCK_REQ, QCH_CON_APBBR_DDRPHY_QCH_EXPIRE_VAL),
	CLK_QCH(APBBR_DMC_QCH, QCH_CON_APBBR_DMC_QCH_ENABLE, QCH_CON_APBBR_DMC_QCH_CLOCK_REQ, QCH_CON_APBBR_DMC_QCH_EXPIRE_VAL),
	CLK_QCH(APBBR_DMCTZ_QCH, QCH_CON_APBBR_DMCTZ_QCH_ENABLE, QCH_CON_APBBR_DMCTZ_QCH_CLOCK_REQ, QCH_CON_APBBR_DMCTZ_QCH_EXPIRE_VAL),
	CLK_QCH(BUSIF_HPMMIF_QCH, QCH_CON_BUSIF_HPMMIF_QCH_ENABLE, QCH_CON_BUSIF_HPMMIF_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMMIF_QCH_EXPIRE_VAL),
	CLK_QCH(CMU_MIF_CMUREF_QCH, DMYQCH_CON_CMU_MIF_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_MIF_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID),
	CLK_QCH(DDRPHY_QCH, QCH_CON_DDRPHY_QCH_ENABLE, QCH_CON_DDRPHY_QCH_CLOCK_REQ, QCH_CON_DDRPHY_QCH_EXPIRE_VAL),
	CLK_QCH(DMC_QCH, QCH_CON_DMC_QCH_ENABLE, QCH_CON_DMC_QCH_CLOCK_REQ, QCH_CON_DMC_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_MIF_QCH, QCH_CON_LHM_AXI_P_MIF_QCH_ENABLE, QCH_CON_LHM_AXI_P_MIF_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MIF_QCH_EXPIRE_VAL),
	CLK_QCH(MIF_CMU_MIF_QCH, QCH_CON_MIF_CMU_MIF_QCH_ENABLE, QCH_CON_MIF_CMU_MIF_QCH_CLOCK_REQ, QCH_CON_MIF_CMU_MIF_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_MIF_QCH, QCH_CON_PMU_MIF_QCH_ENABLE, QCH_CON_PMU_MIF_QCH_CLOCK_REQ, QCH_CON_PMU_MIF_QCH_EXPIRE_VAL),
	CLK_QCH(BCMPPC_DEBUG_QCH, QCH_CON_BCMPPC_DEBUG_QCH_ENABLE, QCH_CON_BCMPPC_DEBUG_QCH_CLOCK_REQ, QCH_CON_BCMPPC_DEBUG_QCH_EXPIRE_VAL),
	CLK_QCH(BCMPPC_DVFS_QCH, QCH_CON_BCMPPC_DVFS_QCH_ENABLE, QCH_CON_BCMPPC_DVFS_QCH_CLOCK_REQ, QCH_CON_BCMPPC_DVFS_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_MIF_QCH, QCH_CON_SYSREG_MIF_QCH_ENABLE, QCH_CON_SYSREG_MIF_QCH_CLOCK_REQ, QCH_CON_SYSREG_MIF_QCH_EXPIRE_VAL),
	CLK_QCH(APBBR_DDRPHY1_QCH, QCH_CON_APBBR_DDRPHY1_QCH_ENABLE, QCH_CON_APBBR_DDRPHY1_QCH_CLOCK_REQ, QCH_CON_APBBR_DDRPHY1_QCH_EXPIRE_VAL),
	CLK_QCH(APBBR_DMC1_QCH, QCH_CON_APBBR_DMC1_QCH_ENABLE, QCH_CON_APBBR_DMC1_QCH_CLOCK_REQ, QCH_CON_APBBR_DMC1_QCH_EXPIRE_VAL),
	CLK_QCH(APBBR_DMCTZ1_QCH, QCH_CON_APBBR_DMCTZ1_QCH_ENABLE, QCH_CON_APBBR_DMCTZ1_QCH_CLOCK_REQ, QCH_CON_APBBR_DMCTZ1_QCH_EXPIRE_VAL),
	CLK_QCH(BUSIF_HPMMIF1_QCH, QCH_CON_BUSIF_HPMMIF1_QCH_ENABLE, QCH_CON_BUSIF_HPMMIF1_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMMIF1_QCH_EXPIRE_VAL),
	CLK_QCH(CMU_MIF1_CMUREF_QCH, DMYQCH_CON_CMU_MIF1_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_MIF1_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID),
	CLK_QCH(DDRPHY1_QCH, QCH_CON_DDRPHY1_QCH_ENABLE, QCH_CON_DDRPHY1_QCH_CLOCK_REQ, QCH_CON_DDRPHY1_QCH_EXPIRE_VAL),
	CLK_QCH(DMC1_QCH, QCH_CON_DMC1_QCH_ENABLE, QCH_CON_DMC1_QCH_CLOCK_REQ, QCH_CON_DMC1_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_MIF1_QCH, QCH_CON_LHM_AXI_P_MIF1_QCH_ENABLE, QCH_CON_LHM_AXI_P_MIF1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MIF1_QCH_EXPIRE_VAL),
	CLK_QCH(MIF1_CMU_MIF1_QCH, QCH_CON_MIF1_CMU_MIF1_QCH_ENABLE, QCH_CON_MIF1_CMU_MIF1_QCH_CLOCK_REQ, QCH_CON_MIF1_CMU_MIF1_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_MIF1_QCH, QCH_CON_PMU_MIF1_QCH_ENABLE, QCH_CON_PMU_MIF1_QCH_CLOCK_REQ, QCH_CON_PMU_MIF1_QCH_EXPIRE_VAL),
	CLK_QCH(BCMPPC_DEBUG1_QCH, QCH_CON_BCMPPC_DEBUG1_QCH_ENABLE, QCH_CON_BCMPPC_DEBUG1_QCH_CLOCK_REQ, QCH_CON_BCMPPC_DEBUG1_QCH_EXPIRE_VAL),
	CLK_QCH(BCMPPC_DVFS1_QCH, QCH_CON_BCMPPC_DVFS1_QCH_ENABLE, QCH_CON_BCMPPC_DVFS1_QCH_CLOCK_REQ, QCH_CON_BCMPPC_DVFS1_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_MIF1_QCH, QCH_CON_SYSREG_MIF1_QCH_ENABLE, QCH_CON_SYSREG_MIF1_QCH_CLOCK_REQ, QCH_CON_SYSREG_MIF1_QCH_EXPIRE_VAL),
	CLK_QCH(APBBR_DDRPHY2_QCH, QCH_CON_APBBR_DDRPHY2_QCH_ENABLE, QCH_CON_APBBR_DDRPHY2_QCH_CLOCK_REQ, QCH_CON_APBBR_DDRPHY2_QCH_EXPIRE_VAL),
	CLK_QCH(APBBR_DMC2_QCH, QCH_CON_APBBR_DMC2_QCH_ENABLE, QCH_CON_APBBR_DMC2_QCH_CLOCK_REQ, QCH_CON_APBBR_DMC2_QCH_EXPIRE_VAL),
	CLK_QCH(APBBR_DMCTZ2_QCH, QCH_CON_APBBR_DMCTZ2_QCH_ENABLE, QCH_CON_APBBR_DMCTZ2_QCH_CLOCK_REQ, QCH_CON_APBBR_DMCTZ2_QCH_EXPIRE_VAL),
	CLK_QCH(BUSIF_HPMMIF2_QCH, QCH_CON_BUSIF_HPMMIF2_QCH_ENABLE, QCH_CON_BUSIF_HPMMIF2_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMMIF2_QCH_EXPIRE_VAL),
	CLK_QCH(CMU_MIF2_CMUREF_QCH, DMYQCH_CON_CMU_MIF2_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_MIF2_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID),
	CLK_QCH(DDRPHY2_QCH, QCH_CON_DDRPHY2_QCH_ENABLE, QCH_CON_DDRPHY2_QCH_CLOCK_REQ, QCH_CON_DDRPHY2_QCH_EXPIRE_VAL),
	CLK_QCH(DMC2_QCH, QCH_CON_DMC2_QCH_ENABLE, QCH_CON_DMC2_QCH_CLOCK_REQ, QCH_CON_DMC2_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_MIF2_QCH, QCH_CON_LHM_AXI_P_MIF2_QCH_ENABLE, QCH_CON_LHM_AXI_P_MIF2_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MIF2_QCH_EXPIRE_VAL),
	CLK_QCH(MIF2_CMU_MIF2_QCH, QCH_CON_MIF2_CMU_MIF2_QCH_ENABLE, QCH_CON_MIF2_CMU_MIF2_QCH_CLOCK_REQ, QCH_CON_MIF2_CMU_MIF2_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_MIF2_QCH, QCH_CON_PMU_MIF2_QCH_ENABLE, QCH_CON_PMU_MIF2_QCH_CLOCK_REQ, QCH_CON_PMU_MIF2_QCH_EXPIRE_VAL),
	CLK_QCH(BCMPPC_DEBUG2_QCH, QCH_CON_BCMPPC_DEBUG2_QCH_ENABLE, QCH_CON_BCMPPC_DEBUG2_QCH_CLOCK_REQ, QCH_CON_BCMPPC_DEBUG2_QCH_EXPIRE_VAL),
	CLK_QCH(BCMPPC_DVFS2_QCH, QCH_CON_BCMPPC_DVFS2_QCH_ENABLE, QCH_CON_BCMPPC_DVFS2_QCH_CLOCK_REQ, QCH_CON_BCMPPC_DVFS2_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_MIF2_QCH, QCH_CON_SYSREG_MIF2_QCH_ENABLE, QCH_CON_SYSREG_MIF2_QCH_CLOCK_REQ, QCH_CON_SYSREG_MIF2_QCH_EXPIRE_VAL),
	CLK_QCH(APBBR_DDRPHY3_QCH, QCH_CON_APBBR_DDRPHY3_QCH_ENABLE, QCH_CON_APBBR_DDRPHY3_QCH_CLOCK_REQ, QCH_CON_APBBR_DDRPHY3_QCH_EXPIRE_VAL),
	CLK_QCH(APBBR_DMC3_QCH, QCH_CON_APBBR_DMC3_QCH_ENABLE, QCH_CON_APBBR_DMC3_QCH_CLOCK_REQ, QCH_CON_APBBR_DMC3_QCH_EXPIRE_VAL),
	CLK_QCH(APBBR_DMCTZ3_QCH, QCH_CON_APBBR_DMCTZ3_QCH_ENABLE, QCH_CON_APBBR_DMCTZ3_QCH_CLOCK_REQ, QCH_CON_APBBR_DMCTZ3_QCH_EXPIRE_VAL),
	CLK_QCH(BUSIF_HPMMIF3_QCH, QCH_CON_BUSIF_HPMMIF3_QCH_ENABLE, QCH_CON_BUSIF_HPMMIF3_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMMIF3_QCH_EXPIRE_VAL),
	CLK_QCH(CMU_MIF3_CMUREF_QCH, DMYQCH_CON_CMU_MIF3_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_MIF3_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID),
	CLK_QCH(DDRPHY3_QCH, QCH_CON_DDRPHY3_QCH_ENABLE, QCH_CON_DDRPHY3_QCH_CLOCK_REQ, QCH_CON_DDRPHY3_QCH_EXPIRE_VAL),
	CLK_QCH(DMC3_QCH, QCH_CON_DMC3_QCH_ENABLE, QCH_CON_DMC3_QCH_CLOCK_REQ, QCH_CON_DMC3_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_MIF3_QCH, QCH_CON_LHM_AXI_P_MIF3_QCH_ENABLE, QCH_CON_LHM_AXI_P_MIF3_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MIF3_QCH_EXPIRE_VAL),
	CLK_QCH(MIF3_CMU_MIF3_QCH, QCH_CON_MIF3_CMU_MIF3_QCH_ENABLE, QCH_CON_MIF3_CMU_MIF3_QCH_CLOCK_REQ, QCH_CON_MIF3_CMU_MIF3_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_MIF3_QCH, QCH_CON_PMU_MIF3_QCH_ENABLE, QCH_CON_PMU_MIF3_QCH_CLOCK_REQ, QCH_CON_PMU_MIF3_QCH_EXPIRE_VAL),
	CLK_QCH(BCMPPC_DEBUG3_QCH, QCH_CON_BCMPPC_DEBUG3_QCH_ENABLE, QCH_CON_BCMPPC_DEBUG3_QCH_CLOCK_REQ, QCH_CON_BCMPPC_DEBUG3_QCH_EXPIRE_VAL),
	CLK_QCH(BCMPPC_DVFS3_QCH, QCH_CON_BCMPPC_DVFS3_QCH_ENABLE, QCH_CON_BCMPPC_DVFS3_QCH_CLOCK_REQ, QCH_CON_BCMPPC_DVFS3_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_MIF3_QCH, QCH_CON_SYSREG_MIF3_QCH_ENABLE, QCH_CON_SYSREG_MIF3_QCH_CLOCK_REQ, QCH_CON_SYSREG_MIF3_QCH_EXPIRE_VAL),
	CLK_QCH(GPIO_PERIC0_QCH, QCH_CON_GPIO_PERIC0_QCH_ENABLE, QCH_CON_GPIO_PERIC0_QCH_CLOCK_REQ, QCH_CON_GPIO_PERIC0_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_PERIC0_QCH, QCH_CON_LHM_AXI_P_PERIC0_QCH_ENABLE, QCH_CON_LHM_AXI_P_PERIC0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_PERIC0_QCH_EXPIRE_VAL),
	CLK_QCH(PERIC0_CMU_PERIC0_QCH, QCH_CON_PERIC0_CMU_PERIC0_QCH_ENABLE, QCH_CON_PERIC0_CMU_PERIC0_QCH_CLOCK_REQ, QCH_CON_PERIC0_CMU_PERIC0_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_PERIC0_QCH, QCH_CON_PMU_PERIC0_QCH_ENABLE, QCH_CON_PMU_PERIC0_QCH_CLOCK_REQ, QCH_CON_PMU_PERIC0_QCH_EXPIRE_VAL),
	CLK_QCH(PWM_QCH, QCH_CON_PWM_QCH_ENABLE, QCH_CON_PWM_QCH_CLOCK_REQ, QCH_CON_PWM_QCH_EXPIRE_VAL),
	CLK_QCH(SPEEDY2_TSP_QCH, QCH_CON_SPEEDY2_TSP_QCH_ENABLE, QCH_CON_SPEEDY2_TSP_QCH_CLOCK_REQ, QCH_CON_SPEEDY2_TSP_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_PERIC0_QCH, QCH_CON_SYSREG_PERIC0_QCH_ENABLE, QCH_CON_SYSREG_PERIC0_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERIC0_QCH_EXPIRE_VAL),
	CLK_QCH(UART_DBG_QCH, QCH_CON_UART_DBG_QCH_ENABLE, QCH_CON_UART_DBG_QCH_CLOCK_REQ, QCH_CON_UART_DBG_QCH_EXPIRE_VAL),
	CLK_QCH(USI00_QCH, QCH_CON_USI00_QCH_ENABLE, QCH_CON_USI00_QCH_CLOCK_REQ, QCH_CON_USI00_QCH_EXPIRE_VAL),
	CLK_QCH(USI01_QCH, QCH_CON_USI01_QCH_ENABLE, QCH_CON_USI01_QCH_CLOCK_REQ, QCH_CON_USI01_QCH_EXPIRE_VAL),
	CLK_QCH(USI02_QCH, QCH_CON_USI02_QCH_ENABLE, QCH_CON_USI02_QCH_CLOCK_REQ, QCH_CON_USI02_QCH_EXPIRE_VAL),
	CLK_QCH(USI03_QCH, QCH_CON_USI03_QCH_ENABLE, QCH_CON_USI03_QCH_CLOCK_REQ, QCH_CON_USI03_QCH_EXPIRE_VAL),
	CLK_QCH(GPIO_PERIC1_QCH, QCH_CON_GPIO_PERIC1_QCH_ENABLE, QCH_CON_GPIO_PERIC1_QCH_CLOCK_REQ, QCH_CON_GPIO_PERIC1_QCH_EXPIRE_VAL),
	CLK_QCH(HSI2C_CAM0_QCH, QCH_CON_HSI2C_CAM0_QCH_ENABLE, QCH_CON_HSI2C_CAM0_QCH_CLOCK_REQ, QCH_CON_HSI2C_CAM0_QCH_EXPIRE_VAL),
	CLK_QCH(HSI2C_CAM1_QCH, QCH_CON_HSI2C_CAM1_QCH_ENABLE, QCH_CON_HSI2C_CAM1_QCH_CLOCK_REQ, QCH_CON_HSI2C_CAM1_QCH_EXPIRE_VAL),
	CLK_QCH(HSI2C_CAM2_QCH, QCH_CON_HSI2C_CAM2_QCH_ENABLE, QCH_CON_HSI2C_CAM2_QCH_CLOCK_REQ, QCH_CON_HSI2C_CAM2_QCH_EXPIRE_VAL),
	CLK_QCH(HSI2C_CAM3_QCH, QCH_CON_HSI2C_CAM3_QCH_ENABLE, QCH_CON_HSI2C_CAM3_QCH_CLOCK_REQ, QCH_CON_HSI2C_CAM3_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_PERIC1_QCH, QCH_CON_LHM_AXI_P_PERIC1_QCH_ENABLE, QCH_CON_LHM_AXI_P_PERIC1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_PERIC1_QCH_EXPIRE_VAL),
	CLK_QCH(PERIC1_CMU_PERIC1_QCH, QCH_CON_PERIC1_CMU_PERIC1_QCH_ENABLE, QCH_CON_PERIC1_CMU_PERIC1_QCH_CLOCK_REQ, QCH_CON_PERIC1_CMU_PERIC1_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_PERIC1_QCH, QCH_CON_PMU_PERIC1_QCH_ENABLE, QCH_CON_PMU_PERIC1_QCH_CLOCK_REQ, QCH_CON_PMU_PERIC1_QCH_EXPIRE_VAL),
	CLK_QCH(SPEEDY2_DDI_QCH, QCH_CON_SPEEDY2_DDI_QCH_ENABLE, QCH_CON_SPEEDY2_DDI_QCH_CLOCK_REQ, QCH_CON_SPEEDY2_DDI_QCH_EXPIRE_VAL),
	CLK_QCH(SPEEDY2_DDI1_QCH, QCH_CON_SPEEDY2_DDI1_QCH_ENABLE, QCH_CON_SPEEDY2_DDI1_QCH_CLOCK_REQ, QCH_CON_SPEEDY2_DDI1_QCH_EXPIRE_VAL),
	CLK_QCH(SPEEDY2_DDI2_QCH, QCH_CON_SPEEDY2_DDI2_QCH_ENABLE, QCH_CON_SPEEDY2_DDI2_QCH_CLOCK_REQ, QCH_CON_SPEEDY2_DDI2_QCH_EXPIRE_VAL),
	CLK_QCH(SPEEDY2_TSP1_QCH, QCH_CON_SPEEDY2_TSP1_QCH_ENABLE, QCH_CON_SPEEDY2_TSP1_QCH_CLOCK_REQ, QCH_CON_SPEEDY2_TSP1_QCH_EXPIRE_VAL),
	CLK_QCH(SPEEDY2_TSP2_QCH, QCH_CON_SPEEDY2_TSP2_QCH_ENABLE, QCH_CON_SPEEDY2_TSP2_QCH_CLOCK_REQ, QCH_CON_SPEEDY2_TSP2_QCH_EXPIRE_VAL),
	CLK_QCH(SPI_CAM0_QCH, QCH_CON_SPI_CAM0_QCH_ENABLE, QCH_CON_SPI_CAM0_QCH_CLOCK_REQ, QCH_CON_SPI_CAM0_QCH_EXPIRE_VAL),
	CLK_QCH(SPI_CAM1_QCH, QCH_CON_SPI_CAM1_QCH_ENABLE, QCH_CON_SPI_CAM1_QCH_CLOCK_REQ, QCH_CON_SPI_CAM1_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_PERIC1_QCH, QCH_CON_SYSREG_PERIC1_QCH_ENABLE, QCH_CON_SYSREG_PERIC1_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERIC1_QCH_EXPIRE_VAL),
	CLK_QCH(UART_BT_QCH, QCH_CON_UART_BT_QCH_ENABLE, QCH_CON_UART_BT_QCH_CLOCK_REQ, QCH_CON_UART_BT_QCH_EXPIRE_VAL),
	CLK_QCH(USI04_QCH, QCH_CON_USI04_QCH_ENABLE, QCH_CON_USI04_QCH_CLOCK_REQ, QCH_CON_USI04_QCH_EXPIRE_VAL),
	CLK_QCH(USI05_QCH, QCH_CON_USI05_QCH_ENABLE, QCH_CON_USI05_QCH_CLOCK_REQ, QCH_CON_USI05_QCH_EXPIRE_VAL),
	CLK_QCH(USI06_QCH, QCH_CON_USI06_QCH_ENABLE, QCH_CON_USI06_QCH_CLOCK_REQ, QCH_CON_USI06_QCH_EXPIRE_VAL),
	CLK_QCH(USI07_QCH, QCH_CON_USI07_QCH_ENABLE, QCH_CON_USI07_QCH_CLOCK_REQ, QCH_CON_USI07_QCH_EXPIRE_VAL),
	CLK_QCH(USI08_QCH, QCH_CON_USI08_QCH_ENABLE, QCH_CON_USI08_QCH_CLOCK_REQ, QCH_CON_USI08_QCH_EXPIRE_VAL),
	CLK_QCH(USI09_QCH, QCH_CON_USI09_QCH_ENABLE, QCH_CON_USI09_QCH_CLOCK_REQ, QCH_CON_USI09_QCH_EXPIRE_VAL),
	CLK_QCH(USI10_QCH, QCH_CON_USI10_QCH_ENABLE, QCH_CON_USI10_QCH_CLOCK_REQ, QCH_CON_USI10_QCH_EXPIRE_VAL),
	CLK_QCH(USI11_QCH, QCH_CON_USI11_QCH_ENABLE, QCH_CON_USI11_QCH_CLOCK_REQ, QCH_CON_USI11_QCH_EXPIRE_VAL),
	CLK_QCH(USI12_QCH, QCH_CON_USI12_QCH_ENABLE, QCH_CON_USI12_QCH_CLOCK_REQ, QCH_CON_USI12_QCH_EXPIRE_VAL),
	CLK_QCH(USI13_QCH, QCH_CON_USI13_QCH_ENABLE, QCH_CON_USI13_QCH_CLOCK_REQ, QCH_CON_USI13_QCH_EXPIRE_VAL),
	CLK_QCH(BUSIF_TMU_QCH, QCH_CON_BUSIF_TMU_QCH_ENABLE, QCH_CON_BUSIF_TMU_QCH_CLOCK_REQ, QCH_CON_BUSIF_TMU_QCH_EXPIRE_VAL),
	CLK_QCH(GIC_QCH, QCH_CON_GIC_QCH_ENABLE, QCH_CON_GIC_QCH_CLOCK_REQ, QCH_CON_GIC_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_PERIS_QCH, QCH_CON_LHM_AXI_P_PERIS_QCH_ENABLE, QCH_CON_LHM_AXI_P_PERIS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_PERIS_QCH_EXPIRE_VAL),
	CLK_QCH(MCT_QCH, QCH_CON_MCT_QCH_ENABLE, QCH_CON_MCT_QCH_CLOCK_REQ, QCH_CON_MCT_QCH_EXPIRE_VAL),
	CLK_QCH(OTP_CON_BIRA_QCH, QCH_CON_OTP_CON_BIRA_QCH_ENABLE, QCH_CON_OTP_CON_BIRA_QCH_CLOCK_REQ, QCH_CON_OTP_CON_BIRA_QCH_EXPIRE_VAL),
	CLK_QCH(OTP_CON_TOP_QCH, QCH_CON_OTP_CON_TOP_QCH_ENABLE, QCH_CON_OTP_CON_TOP_QCH_CLOCK_REQ, QCH_CON_OTP_CON_TOP_QCH_EXPIRE_VAL),
	CLK_QCH(PERIS_CMU_PERIS_QCH, QCH_CON_PERIS_CMU_PERIS_QCH_ENABLE, QCH_CON_PERIS_CMU_PERIS_QCH_CLOCK_REQ, QCH_CON_PERIS_CMU_PERIS_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_PERIS_QCH, QCH_CON_PMU_PERIS_QCH_ENABLE, QCH_CON_PMU_PERIS_QCH_CLOCK_REQ, QCH_CON_PMU_PERIS_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_PERIS_QCH, QCH_CON_SYSREG_PERIS_QCH_ENABLE, QCH_CON_SYSREG_PERIS_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERIS_QCH_EXPIRE_VAL),
	CLK_QCH(TZPC00_QCH, QCH_CON_TZPC00_QCH_ENABLE, QCH_CON_TZPC00_QCH_CLOCK_REQ, QCH_CON_TZPC00_QCH_EXPIRE_VAL),
	CLK_QCH(TZPC01_QCH, QCH_CON_TZPC01_QCH_ENABLE, QCH_CON_TZPC01_QCH_CLOCK_REQ, QCH_CON_TZPC01_QCH_EXPIRE_VAL),
	CLK_QCH(TZPC02_QCH, QCH_CON_TZPC02_QCH_ENABLE, QCH_CON_TZPC02_QCH_CLOCK_REQ, QCH_CON_TZPC02_QCH_EXPIRE_VAL),
	CLK_QCH(TZPC03_QCH, QCH_CON_TZPC03_QCH_ENABLE, QCH_CON_TZPC03_QCH_CLOCK_REQ, QCH_CON_TZPC03_QCH_EXPIRE_VAL),
	CLK_QCH(TZPC04_QCH, QCH_CON_TZPC04_QCH_ENABLE, QCH_CON_TZPC04_QCH_CLOCK_REQ, QCH_CON_TZPC04_QCH_EXPIRE_VAL),
	CLK_QCH(TZPC05_QCH, QCH_CON_TZPC05_QCH_ENABLE, QCH_CON_TZPC05_QCH_CLOCK_REQ, QCH_CON_TZPC05_QCH_EXPIRE_VAL),
	CLK_QCH(TZPC06_QCH, QCH_CON_TZPC06_QCH_ENABLE, QCH_CON_TZPC06_QCH_CLOCK_REQ, QCH_CON_TZPC06_QCH_EXPIRE_VAL),
	CLK_QCH(TZPC07_QCH, QCH_CON_TZPC07_QCH_ENABLE, QCH_CON_TZPC07_QCH_CLOCK_REQ, QCH_CON_TZPC07_QCH_EXPIRE_VAL),
	CLK_QCH(TZPC08_QCH, QCH_CON_TZPC08_QCH_ENABLE, QCH_CON_TZPC08_QCH_CLOCK_REQ, QCH_CON_TZPC08_QCH_EXPIRE_VAL),
	CLK_QCH(TZPC09_QCH, QCH_CON_TZPC09_QCH_ENABLE, QCH_CON_TZPC09_QCH_CLOCK_REQ, QCH_CON_TZPC09_QCH_EXPIRE_VAL),
	CLK_QCH(TZPC10_QCH, QCH_CON_TZPC10_QCH_ENABLE, QCH_CON_TZPC10_QCH_CLOCK_REQ, QCH_CON_TZPC10_QCH_EXPIRE_VAL),
	CLK_QCH(TZPC11_QCH, QCH_CON_TZPC11_QCH_ENABLE, QCH_CON_TZPC11_QCH_CLOCK_REQ, QCH_CON_TZPC11_QCH_EXPIRE_VAL),
	CLK_QCH(TZPC12_QCH, QCH_CON_TZPC12_QCH_ENABLE, QCH_CON_TZPC12_QCH_CLOCK_REQ, QCH_CON_TZPC12_QCH_EXPIRE_VAL),
	CLK_QCH(TZPC13_QCH, QCH_CON_TZPC13_QCH_ENABLE, QCH_CON_TZPC13_QCH_CLOCK_REQ, QCH_CON_TZPC13_QCH_EXPIRE_VAL),
	CLK_QCH(TZPC14_QCH, QCH_CON_TZPC14_QCH_ENABLE, QCH_CON_TZPC14_QCH_CLOCK_REQ, QCH_CON_TZPC14_QCH_EXPIRE_VAL),
	CLK_QCH(TZPC15_QCH, QCH_CON_TZPC15_QCH_ENABLE, QCH_CON_TZPC15_QCH_CLOCK_REQ, QCH_CON_TZPC15_QCH_EXPIRE_VAL),
	CLK_QCH(WDT_CLUSTER0_QCH, QCH_CON_WDT_CLUSTER0_QCH_ENABLE, QCH_CON_WDT_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_WDT_CLUSTER0_QCH_EXPIRE_VAL),
	CLK_QCH(WDT_CLUSTER1_QCH, QCH_CON_WDT_CLUSTER1_QCH_ENABLE, QCH_CON_WDT_CLUSTER1_QCH_CLOCK_REQ, QCH_CON_WDT_CLUSTER1_QCH_EXPIRE_VAL),
	CLK_QCH(BTM_SRDZ_QCH, QCH_CON_BTM_SRDZ_QCH_ENABLE, QCH_CON_BTM_SRDZ_QCH_CLOCK_REQ, QCH_CON_BTM_SRDZ_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_ATB_DCAMSRDZ_QCH, QCH_CON_LHM_ATB_DCAMSRDZ_QCH_ENABLE, QCH_CON_LHM_ATB_DCAMSRDZ_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_DCAMSRDZ_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_D_DCAMSRDZ_QCH, QCH_CON_LHM_AXI_D_DCAMSRDZ_QCH_ENABLE, QCH_CON_LHM_AXI_D_DCAMSRDZ_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_DCAMSRDZ_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_SRDZ_QCH, QCH_CON_LHM_AXI_P_SRDZ_QCH_ENABLE, QCH_CON_LHM_AXI_P_SRDZ_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_SRDZ_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_ATB_SRDZCAM_QCH, QCH_CON_LHS_ATB_SRDZCAM_QCH_ENABLE, QCH_CON_LHS_ATB_SRDZCAM_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_SRDZCAM_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_D_SRDZ_QCH, QCH_CON_LHS_AXI_D_SRDZ_QCH_ENABLE, QCH_CON_LHS_AXI_D_SRDZ_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_SRDZ_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_P_SRDZDCAM_QCH, QCH_CON_LHS_AXI_P_SRDZDCAM_QCH_ENABLE, QCH_CON_LHS_AXI_P_SRDZDCAM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_SRDZDCAM_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_SRDZ_QCH, QCH_CON_PMU_SRDZ_QCH_ENABLE, QCH_CON_PMU_SRDZ_QCH_CLOCK_REQ, QCH_CON_PMU_SRDZ_QCH_EXPIRE_VAL),
	CLK_QCH(BCM_SRDZ_QCH, QCH_CON_BCM_SRDZ_QCH_ENABLE, QCH_CON_BCM_SRDZ_QCH_CLOCK_REQ, QCH_CON_BCM_SRDZ_QCH_EXPIRE_VAL),
	CLK_QCH(SMMU_SRDZ_QCH, QCH_CON_SMMU_SRDZ_QCH_ENABLE, QCH_CON_SMMU_SRDZ_QCH_CLOCK_REQ, QCH_CON_SMMU_SRDZ_QCH_EXPIRE_VAL),
	CLK_QCH(SRDZ_QCH, QCH_CON_SRDZ_QCH_ENABLE, QCH_CON_SRDZ_QCH_CLOCK_REQ, QCH_CON_SRDZ_QCH_EXPIRE_VAL),
	CLK_QCH(SRDZ_CMU_SRDZ_QCH, QCH_CON_SRDZ_CMU_SRDZ_QCH_ENABLE, QCH_CON_SRDZ_CMU_SRDZ_QCH_CLOCK_REQ, QCH_CON_SRDZ_CMU_SRDZ_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_SRDZ_QCH, QCH_CON_SYSREG_SRDZ_QCH_ENABLE, QCH_CON_SYSREG_SRDZ_QCH_CLOCK_REQ, QCH_CON_SYSREG_SRDZ_QCH_EXPIRE_VAL),
	CLK_QCH(BTM_VPU_QCH, QCH_CON_BTM_VPU_QCH_ENABLE, QCH_CON_BTM_VPU_QCH_CLOCK_REQ, QCH_CON_BTM_VPU_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_DSPVPU_QCH, QCH_CON_LHM_AXI_P_DSPVPU_QCH_ENABLE, QCH_CON_LHM_AXI_P_DSPVPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DSPVPU_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_VPU_QCH, QCH_CON_LHM_AXI_P_VPU_QCH_ENABLE, QCH_CON_LHM_AXI_P_VPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_VPU_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_ACEL_D_VPU_QCH, QCH_CON_LHS_ACEL_D_VPU_QCH_ENABLE, QCH_CON_LHS_ACEL_D_VPU_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_VPU_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_D_VPUDSP_QCH, QCH_CON_LHS_AXI_D_VPUDSP_QCH_ENABLE, QCH_CON_LHS_AXI_D_VPUDSP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_VPUDSP_QCH_EXPIRE_VAL),
	CLK_QCH(PMU_VPU_QCH, QCH_CON_PMU_VPU_QCH_ENABLE, QCH_CON_PMU_VPU_QCH_CLOCK_REQ, QCH_CON_PMU_VPU_QCH_EXPIRE_VAL),
	CLK_QCH(BCM_VPU_QCH, QCH_CON_BCM_VPU_QCH_ENABLE, QCH_CON_BCM_VPU_QCH_CLOCK_REQ, QCH_CON_BCM_VPU_QCH_EXPIRE_VAL),
	CLK_QCH(SMMU_VPU_QCH, QCH_CON_SMMU_VPU_QCH_ENABLE, QCH_CON_SMMU_VPU_QCH_CLOCK_REQ, QCH_CON_SMMU_VPU_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_VPU_QCH, QCH_CON_SYSREG_VPU_QCH_ENABLE, QCH_CON_SYSREG_VPU_QCH_CLOCK_REQ, QCH_CON_SYSREG_VPU_QCH_EXPIRE_VAL),
	CLK_QCH(VPU_QCH, QCH_CON_VPU_QCH_ENABLE, QCH_CON_VPU_QCH_CLOCK_REQ, QCH_CON_VPU_QCH_EXPIRE_VAL),
	CLK_QCH(VPU_CMU_VPU_QCH, QCH_CON_VPU_CMU_VPU_QCH_ENABLE, QCH_CON_VPU_CMU_VPU_QCH_CLOCK_REQ, QCH_CON_VPU_CMU_VPU_QCH_EXPIRE_VAL),
	CLK_QCH(CMU_VTS_CMUREF_QCH, DMYQCH_CON_CMU_VTS_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_VTS_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID),
	CLK_QCH(DMIC_AHB_QCH_PCLK, QCH_CON_DMIC_AHB_QCH_PCLK_ENABLE, QCH_CON_DMIC_AHB_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AHB_QCH_PCLK_EXPIRE_VAL),
	CLK_QCH(DMIC_AHB_QCH_HCLK, DMYQCH_CON_DMIC_AHB_QCH_HCLK_ENABLE, DMYQCH_CON_DMIC_AHB_QCH_HCLK_CLOCK_REQ, EMPTY_CAL_ID),
	CLK_QCH(DMIC_IF_QCH_PCLK, QCH_CON_DMIC_IF_QCH_PCLK_ENABLE, QCH_CON_DMIC_IF_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_IF_QCH_PCLK_EXPIRE_VAL),
	CLK_QCH(DMIC_IF_QCH_DMIC_CLK, DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK_ENABLE, DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK_CLOCK_REQ, EMPTY_CAL_ID),
	CLK_QCH(GPIO_VTS_QCH, QCH_CON_GPIO_VTS_QCH_ENABLE, QCH_CON_GPIO_VTS_QCH_CLOCK_REQ, QCH_CON_GPIO_VTS_QCH_EXPIRE_VAL),
	CLK_QCH(LHM_AXI_P_VTS_QCH, QCH_CON_LHM_AXI_P_VTS_QCH_ENABLE, QCH_CON_LHM_AXI_P_VTS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_VTS_QCH_EXPIRE_VAL),
	CLK_QCH(LHS_AXI_D_VTS_QCH, QCH_CON_LHS_AXI_D_VTS_QCH_ENABLE, QCH_CON_LHS_AXI_D_VTS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_VTS_QCH_EXPIRE_VAL),
	CLK_QCH(MAILBOX_VTS2AP_QCH, QCH_CON_MAILBOX_VTS2AP_QCH_ENABLE, QCH_CON_MAILBOX_VTS2AP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_VTS2AP_QCH_EXPIRE_VAL),
	CLK_QCH(SYSREG_VTS_QCH, QCH_CON_SYSREG_VTS_QCH_ENABLE, QCH_CON_SYSREG_VTS_QCH_CLOCK_REQ, QCH_CON_SYSREG_VTS_QCH_EXPIRE_VAL),
	CLK_QCH(VTS_QCH_CPU, QCH_CON_VTS_QCH_CPU_ENABLE, QCH_CON_VTS_QCH_CPU_CLOCK_REQ, QCH_CON_VTS_QCH_CPU_EXPIRE_VAL),
	CLK_QCH(VTS_QCH_SYS, QCH_CON_VTS_QCH_SYS_ENABLE, QCH_CON_VTS_QCH_SYS_CLOCK_REQ, QCH_CON_VTS_QCH_SYS_EXPIRE_VAL),
	CLK_QCH(VTS_QCH_SYS_DMIC, QCH_CON_VTS_QCH_SYS_DMIC_ENABLE, QCH_CON_VTS_QCH_SYS_DMIC_CLOCK_REQ, QCH_CON_VTS_QCH_SYS_DMIC_EXPIRE_VAL),
	CLK_QCH(VTS_CMU_VTS_QCH, QCH_CON_VTS_CMU_VTS_QCH_ENABLE, QCH_CON_VTS_CMU_VTS_QCH_CLOCK_REQ, QCH_CON_VTS_CMU_VTS_QCH_EXPIRE_VAL),
	CLK_QCH(WDT_VTS_QCH, QCH_CON_WDT_VTS_QCH_ENABLE, QCH_CON_WDT_VTS_QCH_CLOCK_REQ, QCH_CON_WDT_VTS_QCH_EXPIRE_VAL),
};

/*====================The section of controller option nodes===================*/
unsigned int cmucal_option_size=33;


struct cmucal_option cmucal_option_list[]={
	CLK_OPTION(CTRL_OPTION_BLK_ABOX, ABOX_ENABLE_POWER_MANAGEMENT, ABOX_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_APM, APM_ENABLE_POWER_MANAGEMENT, APM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_BUS1, BUS1_ENABLE_POWER_MANAGEMENT, BUS1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_BUSC, BUSC_ENABLE_POWER_MANAGEMENT, BUSC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_CAM, CAM_ENABLE_POWER_MANAGEMENT, CAM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_CMU, CMU_ENABLE_POWER_MANAGEMENT, CMU_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_CORE, CORE_ENABLE_POWER_MANAGEMENT, CORE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_CPUCL0, CPUCL0_ENABLE_POWER_MANAGEMENT, CPUCL0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_CPUCL1, CPUCL1_ENABLE_POWER_MANAGEMENT, CPUCL1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_DBG, DBG_ENABLE_POWER_MANAGEMENT, DBG_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_DCAM, DCAM_ENABLE_POWER_MANAGEMENT, DCAM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_DPU0, DPU0_ENABLE_POWER_MANAGEMENT, DPU0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_DPU1, DPU1_ENABLE_POWER_MANAGEMENT, DPU1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_DSP, DSP_ENABLE_POWER_MANAGEMENT, DSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_FSYS0, FSYS0_ENABLE_POWER_MANAGEMENT, FSYS0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_FSYS1, FSYS1_ENABLE_POWER_MANAGEMENT, FSYS1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_G2D, G2D_ENABLE_POWER_MANAGEMENT, G2D_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_G3D, G3D_ENABLE_POWER_MANAGEMENT, G3D_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_IMEM, IMEM_ENABLE_POWER_MANAGEMENT, IMEM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_ISPHQ, ISPHQ_ENABLE_POWER_MANAGEMENT, ISPHQ_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_ISPLP, ISPLP_ENABLE_POWER_MANAGEMENT, ISPLP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_IVA, IVA_ENABLE_POWER_MANAGEMENT, IVA_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_MFC, MFC_ENABLE_POWER_MANAGEMENT, MFC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_MIF, MIF_ENABLE_POWER_MANAGEMENT, MIF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_MIF1, MIF1_ENABLE_POWER_MANAGEMENT, MIF1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_MIF2, MIF2_ENABLE_POWER_MANAGEMENT, MIF2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_MIF3, MIF3_ENABLE_POWER_MANAGEMENT, MIF3_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_PERIC0, PERIC0_ENABLE_POWER_MANAGEMENT, PERIC0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_PERIC1, PERIC1_ENABLE_POWER_MANAGEMENT, PERIC1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_PERIS, PERIS_ENABLE_POWER_MANAGEMENT, PERIS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_SRDZ, SRDZ_ENABLE_POWER_MANAGEMENT, SRDZ_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_VPU, VPU_ENABLE_POWER_MANAGEMENT, VPU_ENABLE_AUTOMATIC_CLKGATING),
	CLK_OPTION(CTRL_OPTION_BLK_VTS, VTS_ENABLE_POWER_MANAGEMENT, VTS_ENABLE_AUTOMATIC_CLKGATING),
};