1499 lines
59 KiB
C
1499 lines
59 KiB
C
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#ifndef __CMUCAL_NODE_H__
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#define __CMUCAL_NODE_H__
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#include "../cmucal.h"
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/*=================CMUCAL version: S5E8895================================*/
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enum clk_id {
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OSCCLK_ABOX = FIXED_RATE_TYPE,
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CLKIO_ABOX_UAIF0,
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CLKIO_ABOX_UAIF1,
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CLKIO_ABOX_UAIF2,
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CLKIO_ABOX_UAIF3,
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CLKIO_ABOX_UAIF4,
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OSCCLK_APM,
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OSCCLK_BUS1,
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OSCCLK_BUSC,
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OSCCLK_CAM,
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OSCCLK_CMU,
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OSCCLK_CORE,
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OSCCLK_CPUCL0,
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CLUSTER0_ACLKOUT,
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CLUSTER0_ATCLKOUT,
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OSCCLK_EMBEDDED_CPUCL0,
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OSCCLK_CPUCL1,
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CLK_CLUSTER1_DIV_ACLK,
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CLK_CLUSTER1_DIV_ATCLK,
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CLK_CLUSTER1_DIV_CNTCLK,
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CLK_CLUSTER1_DIV_PCLKDBG,
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OSCCLK_EMBEDDED_CPUCL1,
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OSCCLK_DBG,
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OSCCLK_DCAM,
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OSCCLK_DPU0,
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CLK_DEBUG_DECON0,
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OSCCLK_DPU1,
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CLK_DEBUG_DECON1,
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CLK_DEBUG_DECON2,
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OSCCLK_DSP,
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OSCCLK_FSYS0,
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OSCCLK_FSYS1,
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OSCCLK_G2D,
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OSCCLK_G3D,
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OSCCLK_EMBEDDED_G3D,
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OSCCLK_IMEM,
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OSCCLK_ISPHQ,
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OSCCLK_ISPLP,
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OSCCLK_IVA,
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OSCCLK_MFC,
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OSCCLK_MIF,
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OSCCLK_MIF1,
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OSCCLK_MIF2,
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OSCCLK_MIF3,
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OSCCLK_PERIC0,
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OSCCLK_PERIC1,
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OSCCLK_PERIS,
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OSCCLK_SRDZ,
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OSCCLK_VPU,
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OSCCLK_VTS,
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RTCCLK_VTS,
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OSC_VTS,
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CP2AP_MIF_CLK,
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end_of_fixed_rate,
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num_of_fixed_rate = end_of_fixed_rate - FIXED_RATE_TYPE,
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DIV_CLK_CAM_BUSD_DIV2 = FIXED_FACTOR_TYPE,
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DIV_PLL_SHARED0_DIV2,
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DIV_PLL_SHARED1_DIV2,
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DIV_PLL_SHARED2_DIV2,
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DIV_PLL_SHARED3_DIV2,
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DIV_PLL_SHARED4_DIV2,
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DIV_PLL_SHARED0_DIV4,
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CLKCMU_FSYS1_PCIE,
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CLKCMU_OTP,
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DIV_PLL_SHARED1_DIV4,
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DIV_CP2AP_MIF_CLK_DIV2,
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CLK_MIF_BUSD,
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CLK_MIF1_BUSD,
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CLK_MIF2_BUSD,
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CLK_MIF3_BUSD,
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DIV_CLK_VTS_CMUREF,
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end_of_fixed_factor,
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num_of_fixed_factor = end_of_fixed_factor - FIXED_FACTOR_TYPE,
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PLL_AUD = PLL_TYPE,
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PLL_SHARED1,
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PLL_SHARED4,
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PLL_SHARED3,
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PLL_SHARED2,
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PLL_SHARED0,
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PLL_CPUCL0,
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PLL_CPUCL1,
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PLL_DPU,
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PLL_G3D,
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PLL_MIF,
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PLL_MIF1,
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PLL_MIF2,
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PLL_MIF3,
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end_of_pll,
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num_of_pll = end_of_pll - PLL_TYPE,
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MUX_CLK_ABOX_UAIF3 = MUX_TYPE,
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MUX_CLK_ABOX_UAIF2,
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MUX_CLK_ABOX_UAIF1,
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MUX_CLK_ABOX_UAIF0,
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MUX_CLK_ABOX_CPU,
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MUX_CLK_ABOX_UAIF4,
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MUX_CLKCMU_DPU_BUS,
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MUX_CLKCMU_BUS1_BUS,
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MUX_CLKCMU_MFC_BUS,
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MUX_CLKCMU_FSYS0_USBDRD30,
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MUX_CLKCMU_FSYS0_UFS_EMBD,
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MUX_CLKCMU_VPU_BUS,
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MUX_CLKCMU_PERIC0_UART_DBG,
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MUX_CLKCMU_PERIC0_USI00,
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MUX_CLKCMU_PERIC0_USI02,
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MUX_CLKCMU_PERIC0_USI03,
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MUX_CLKCMU_PERIC1_USI04,
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MUX_CLKCMU_PERIC1_USI05,
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MUX_CLKCMU_PERIC1_UART_BT,
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MUX_CLKCMU_PERIC1_USI06,
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MUX_CLKCMU_PERIC1_USI07,
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MUX_CLKCMU_PERIC1_USI08,
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MUX_CLKCMU_PERIC1_USI09,
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MUX_CLKCMU_PERIC1_USI10,
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MUX_CLKCMU_PERIC1_USI11,
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MUX_CLKCMU_PERIC1_USI12,
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MUX_CLKCMU_PERIC1_USI13,
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MUX_CLKCMU_BUSC_BUS,
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MUX_CLKCMU_G2D_G2D,
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MUX_CLKCMU_PERIC0_USI01,
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MUX_CLKCMU_FSYS1_MMC_CARD,
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MUX_CLKCMU_DSP_BUS,
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MUX_CLKCMU_FSYS0_MMC_EMBD,
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MUX_CLKCMU_CPUCL0_SWITCH,
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MUX_CLKCMU_CORE_BUS,
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MUX_CLKCMU_MIF_SWITCH,
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MUX_CLKCMU_CAM_BUS,
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MUX_CLKCMU_CAM_TPU0,
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MUX_CLKCMU_CAM_TPU1,
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MUX_CLKCMU_ISPLP_BUS,
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MUX_CLKCMU_ISPHQ_BUS,
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MUX_CLKCMU_ABOX_CPUABOX,
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MUX_CLKCMU_G2D_JPEG,
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MUX_CLKCMU_HPM,
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MUX_CLKCMU_DBG_BUS,
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MUX_CLKCMU_PERIC1_SPI_CAM0,
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MUX_CLKCMU_PERIC1_SPI_CAM1,
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MUX_CLKCMU_DROOPDETECTOR,
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MUX_CLKCMU_FSYS0_BUS,
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MUX_CLKCMU_CIS_CLK0,
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MUX_CLKCMU_CIS_CLK1,
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MUX_CLKCMU_CIS_CLK2,
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MUX_CLKCMU_CIS_CLK3,
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MUX_CLKCMU_IVA_BUS,
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MUX_CLKCMU_FSYS1_UFS_CARD,
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MUX_CMU_CMUREF,
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MUX_CLKCMU_BUSC_BUSPHSI2C,
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MUX_CLKCMU_CAM_VRA,
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MUX_CLKCMU_PERIC0_BUS,
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MUX_CLKCMU_PERIC1_BUS,
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MUX_CLKCMU_PERIS_BUS,
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MUX_CLKCMU_DCAM_BUS,
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MUX_CLKCMU_IMEM_BUS,
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MUX_CLKCMU_FSYS0_DPGTC,
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MUX_CLKCMU_FSYS1_PCIE,
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MUX_CLKCMU_SRDZ_BUS,
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MUX_CLKCMU_SRDZ_IMGD,
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MUX_CLKCMU_DCAM_IMGD,
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MUX_CLKCMU_PERIC1_SPEEDY2,
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MUX_CLKCMU_APM_BUS,
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MUX_CLKCMU_FSYS1_BUS,
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MUX_CLK_CMU_CMUREF,
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MUX_CLKCMU_CPUCL1_SWITCH,
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MUX_CLK_CPUCL0_PLL,
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MUX_CLK_CPUCL1_PLL,
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MUX_CLK_G3D_BUSD,
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CLKMUX_MIF_DDRPHY2X,
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MUX_MIF_CMUREF,
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MUX_MIF1_CMUREF,
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CLKMUX_MIF1_DDRPHY2X,
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MUX_MIF2_CMUREF,
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CLKMUX_MIF2_DDRPHY2X,
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MUX_MIF3_CMUREF,
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CLKMUX_MIF3_DDRPHY2X,
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MUX_CLK_VTS_CMUREF,
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ABOX_CMU_CLKOUT0,
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ABOX_CMU_CLKOUT1,
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APM_CMU_CLKOUT0,
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APM_CMU_CLKOUT1,
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BUS1_CMU_CLKOUT0,
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BUS1_CMU_CLKOUT1,
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BUSC_CMU_CLKOUT0,
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BUSC_CMU_CLKOUT1,
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CAM_CMU_CLKOUT0,
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CAM_CMU_CLKOUT1,
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CMU_CMU_CLKOUT0,
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CMU_CMU_CLKOUT1,
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CORE_CMU_CLKOUT0,
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CORE_CMU_CLKOUT1,
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CPUCL0_CMU_CLKOUT0,
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CPUCL0_CMU_CLKOUT1,
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CPUCL0_EMBEDDED_CMU_CLKOUT0,
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CPUCL0_EMBEDDED_CMU_CLKOUT1,
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CPUCL1_CMU_CLKOUT0,
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CPUCL1_CMU_CLKOUT1,
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CPUCL1_EMBEDDED_CMU_CLKOUT0,
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CPUCL1_EMBEDDED_CMU_CLKOUT1,
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DBG_CMU_CLKOUT0,
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DBG_CMU_CLKOUT1,
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DCAM_CMU_CLKOUT0,
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DCAM_CMU_CLKOUT1,
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DPU0_CMU_CLKOUT0,
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DPU0_CMU_CLKOUT1,
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DPU1_CMU_CLKOUT0,
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DPU1_CMU_CLKOUT1,
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DSP_CMU_CLKOUT0,
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DSP_CMU_CLKOUT1,
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FSYS0_CMU_CLKOUT0,
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FSYS0_CMU_CLKOUT1,
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FSYS1_CMU_CLKOUT0,
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FSYS1_CMU_CLKOUT1,
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G2D_CMU_CLKOUT0,
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G2D_CMU_CLKOUT1,
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G3D_CMU_CLKOUT0,
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G3D_CMU_CLKOUT1,
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G3D_EMBEDDED_CMU_CLKOUT0,
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G3D_EMBEDDED_CMU_CLKOUT1,
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IMEM_CMU_CLKOUT0,
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IMEM_CMU_CLKOUT1,
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ISPHQ_CMU_CLKOUT0,
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ISPHQ_CMU_CLKOUT1,
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ISPLP_CMU_CLKOUT0,
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ISPLP_CMU_CLKOUT1,
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IVA_CMU_CLKOUT0,
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IVA_CMU_CLKOUT1,
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MFC_CMU_CLKOUT0,
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MFC_CMU_CLKOUT1,
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MIF_CMU_CLKOUT0,
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MIF_CMU_CLKOUT1,
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MIF1_CMU_CLKOUT0,
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MIF1_CMU_CLKOUT1,
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MIF2_CMU_CLKOUT0,
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MIF2_CMU_CLKOUT1,
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MIF3_CMU_CLKOUT0,
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MIF3_CMU_CLKOUT1,
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PERIC0_CMU_CLKOUT0,
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PERIC0_CMU_CLKOUT1,
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PERIC1_CMU_CLKOUT0,
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PERIC1_CMU_CLKOUT1,
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PERIS_CMU_CLKOUT0,
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PERIS_CMU_CLKOUT1,
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SRDZ_CMU_CLKOUT0,
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SRDZ_CMU_CLKOUT1,
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VPU_CMU_CLKOUT0,
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VPU_CMU_CLKOUT1,
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VTS_CMU_CLKOUT0,
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VTS_CMU_CLKOUT1,
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MUX_CLK_PERIS_GIC = ((MASK_OF_ID & VTS_CMU_CLKOUT1) | CONST_MUX_TYPE) + 1,
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MUX_CLKCMU_ABOX_CPUABOX_USER = ((MASK_OF_ID & MUX_CLK_PERIS_GIC) | USER_MUX_TYPE) + 1,
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MUX_CLKCMU_APM_BUS_USER,
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MUX_CLKCMU_BUS1_BUS_USER,
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MUX_CLKCMU_BUSC_BUS_USER,
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MUX_CLKCMU_BUSC_BUSPHSI2C_USER,
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MUX_CLKCMU_CAM_BUS_USER,
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MUX_CLKCMU_CAM_TPU0_USER,
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MUX_CLKCMU_CAM_VRA_USER,
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MUX_CLKCMU_CAM_TPU1_USER,
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MUX_CP2AP_MIF_CLK_USER,
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MUX_CLKCMU_CORE_BUS_USER,
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MUX_CLKCMU_CPUCL0_SWITCH_USER,
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MUX_CLKCMU_CPUCL1_SWITCH_USER,
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MUX_CLKCMU_DBG_BUS_USER,
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MUX_CLKCMU_DCAM_BUS_USER,
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MUX_CLKCMU_DCAM_IMGD_USER,
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MUX_CLKCMU_DPU_BUS_USER,
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MUX_CLKCMU_DPU1_BUSD_USER,
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MUX_CLKCMU_DPU1_BUSP_USER,
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MUX_CLKCMU_DSP_BUS_USER,
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MUX_CLKCMU_FSYS0_UFS_EMBD_USER,
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MUX_CLKCMU_FSYS0_MMC_EMBD_USER,
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MUX_CLKCMU_FSYS0_BUS_USER,
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MUX_CLKCMU_FSYS0_USBDRD30_USER,
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MUX_CLKCMU_FSYS0_DPGTC_USER,
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MUX_CLKCMU_FSYS1_BUS_USER,
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MUX_CLKCMU_FSYS1_MMC_CARD_USER,
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MUX_CLKCMU_FSYS1_PCIE_USER,
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MUX_CLKCMU_FSYS1_UFS_CARD_USER,
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MUX_CLKCMU_G2D_G2D_USER,
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MUX_CLKCMU_G2D_JPEG_USER,
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MUX_CLKCMU_G3D_SWITCH_USER,
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MUX_CLKCMU_IMEM_BUS_USER,
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MUX_CLKCMU_ISPHQ_BUS_USER,
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MUX_CLKCMU_ISPLP_BUS_USER,
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MUX_CLKCMU_IVA_BUS_USER,
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MUX_CLKCMU_MFC_BUS_USER,
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MUX_CLKCMU_PERIC0_BUS_USER,
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MUX_CLKCMU_PERIC0_UART_DBG_USER,
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MUX_CLKCMU_PERIC0_USI00_USER,
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MUX_CLKCMU_PERIC0_USI01_USER,
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MUX_CLKCMU_PERIC0_USI02_USER,
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MUX_CLKCMU_PERIC0_USI03_USER,
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MUX_CLKCMU_PERIC1_UART_BT_USER,
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MUX_CLKCMU_PERIC1_USI05_USER,
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MUX_CLKCMU_PERIC1_USI06_USER,
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MUX_CLKCMU_PERIC1_USI07_USER,
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MUX_CLKCMU_PERIC1_USI08_USER,
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MUX_CLKCMU_PERIC1_USI09_USER,
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MUX_CLKCMU_PERIC1_USI10_USER,
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MUX_CLKCMU_PERIC1_USI11_USER,
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MUX_CLKCMU_PERIC1_USI12_USER,
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MUX_CLKCMU_PERIC1_USI13_USER,
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MUX_CLKCMU_PERIC1_BUS_USER,
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MUX_CLKCMU_PERIC1_USI04_USER,
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||
|
|
MUX_CLKCMU_PERIC1_SPI_CAM0_USER,
|
||
|
|
MUX_CLKCMU_PERIC1_SPI_CAM1_USER,
|
||
|
|
MUX_CLKCMU_PERIC1_SPEEDY2_USER,
|
||
|
|
MUX_CLKCMU_PERIS_BUS_USER,
|
||
|
|
MUX_CLKCMU_SRDZ_IMGD_USER,
|
||
|
|
MUX_CLKCMU_SRDZ_BUS_USER,
|
||
|
|
MUX_CLKCMU_VPU_BUS_USER,
|
||
|
|
end_of_mux,
|
||
|
|
num_of_mux = (end_of_mux - MUX_TYPE) & MASK_OF_ID,
|
||
|
|
|
||
|
|
DIV_CLK_ABOX_PLL = DIV_TYPE,
|
||
|
|
DIV_CLK_ABOX_AUDIF,
|
||
|
|
DIV_CLK_ABOX_CPU_ATCLK,
|
||
|
|
DIV_CLK_ABOX_CPU_PCLKDBG,
|
||
|
|
DIV_CLK_ABOX_DSIF,
|
||
|
|
DIV_CLK_ABOX_UAIF0,
|
||
|
|
DIV_CLK_ABOX_UAIF1,
|
||
|
|
DIV_CLK_ABOX_UAIF2,
|
||
|
|
DIV_CLK_ABOX_UAIF3,
|
||
|
|
DIV_CLK_ABOX_CPU_ACLK,
|
||
|
|
DIV_CLK_ABOX_BUS,
|
||
|
|
DIV_CLK_ABOX_BUSP,
|
||
|
|
DIV_CLK_ABOX_DMIC,
|
||
|
|
DIV_CLK_ABOX_UAIF4,
|
||
|
|
DIV_CLK_BUS1_BUSP,
|
||
|
|
DIV_CLK_BUSC_BUSP,
|
||
|
|
DIV_CLK_CAM_BUSP,
|
||
|
|
CLKCMU_APM_BUS,
|
||
|
|
CLKCMU_G3D_SWITCH,
|
||
|
|
CLKCMU_PERIC0_BUS,
|
||
|
|
CLKCMU_PERIS_BUS,
|
||
|
|
CLKCMU_FSYS0_BUS,
|
||
|
|
CLKCMU_DPU_BUS,
|
||
|
|
CLKCMU_BUS1_BUS,
|
||
|
|
CLKCMU_PERIC0_USI00,
|
||
|
|
CLKCMU_PERIC0_UART_DBG,
|
||
|
|
CLKCMU_PERIC0_USI01,
|
||
|
|
CLKCMU_PERIC0_USI02,
|
||
|
|
CLKCMU_PERIC0_USI03,
|
||
|
|
CLKCMU_MFC_BUS,
|
||
|
|
CLKCMU_G2D_G2D,
|
||
|
|
CLKCMU_FSYS0_USBDRD30,
|
||
|
|
CLKCMU_FSYS0_MMC_EMBD,
|
||
|
|
CLKCMU_FSYS0_UFS_EMBD,
|
||
|
|
CLKCMU_FSYS1_MMC_CARD,
|
||
|
|
CLKCMU_FSYS1_BUS,
|
||
|
|
CLKCMU_VPU_BUS,
|
||
|
|
CLKCMU_DSP_BUS,
|
||
|
|
CLKCMU_PERIC1_BUS,
|
||
|
|
CLKCMU_PERIC1_UART_BT,
|
||
|
|
CLKCMU_PERIC1_USI05,
|
||
|
|
CLKCMU_PERIC1_USI06,
|
||
|
|
CLKCMU_PERIC1_USI07,
|
||
|
|
CLKCMU_PERIC1_USI08,
|
||
|
|
CLKCMU_PERIC1_USI09,
|
||
|
|
CLKCMU_PERIC1_USI10,
|
||
|
|
CLKCMU_PERIC1_USI11,
|
||
|
|
CLKCMU_PERIC1_USI12,
|
||
|
|
CLKCMU_PERIC1_USI13,
|
||
|
|
CLKCMU_BUSC_BUS,
|
||
|
|
CLKCMU_PERIC1_USI04,
|
||
|
|
CLKCMU_CPUCL1_SWITCH,
|
||
|
|
CLKCMU_CPUCL0_SWITCH,
|
||
|
|
CLKCMU_CORE_BUS,
|
||
|
|
CLKCMU_CAM_BUS,
|
||
|
|
CLKCMU_CAM_TPU0,
|
||
|
|
CLKCMU_CAM_TPU1,
|
||
|
|
CLKCMU_ISPLP_BUS,
|
||
|
|
CLKCMU_ISPHQ_BUS,
|
||
|
|
CLKCMU_ABOX_CPUABOX,
|
||
|
|
CLKCMU_G2D_JPEG,
|
||
|
|
CLKCMU_HPM,
|
||
|
|
CLKCMU_DBG_BUS,
|
||
|
|
CLKCMU_PERIC1_SPI_CAM0,
|
||
|
|
CLKCMU_PERIC1_SPI_CAM1,
|
||
|
|
CLKCMU_CIS_CLK0,
|
||
|
|
CLKCMU_CIS_CLK1,
|
||
|
|
CLKCMU_CIS_CLK2,
|
||
|
|
CLKCMU_CIS_CLK3,
|
||
|
|
CLKCMU_IVA_BUS,
|
||
|
|
CLKCMU_FSYS1_UFS_CARD,
|
||
|
|
CLKCMU_BUSC_BUSPHSI2C,
|
||
|
|
CLKCMU_CAM_VRA,
|
||
|
|
CLKCMU_PERIC1_SPEEDY2,
|
||
|
|
CLKCMU_FSYS0_DPGTC,
|
||
|
|
CLKCMU_MODEM_SHARED0,
|
||
|
|
CLKCMU_MODEM_SHARED1,
|
||
|
|
CLKCMU_DCAM_BUS,
|
||
|
|
CLKCMU_IMEM_BUS,
|
||
|
|
DIV_CLK_CMU_CMUREF,
|
||
|
|
CLKCMU_SRDZ_IMGD,
|
||
|
|
CLKCMU_SRDZ_BUS,
|
||
|
|
CLKCMU_DCAM_IMGD,
|
||
|
|
DIV_CLK_CORE_BUSP,
|
||
|
|
DIV_CLK_CPUCL0_CMUREF,
|
||
|
|
DIV_CLK_CPUCL0_PCLK,
|
||
|
|
DIV_CLK_CLUSTER0_ACLK,
|
||
|
|
DIV_CLK_CLUSTER0_ATCLK,
|
||
|
|
DIV_CLK_CPUCL0_PCLKDBG,
|
||
|
|
DIV_CLK_CPUCL1_CMUREF,
|
||
|
|
DIV_CLK_CPUCL1_PCLK,
|
||
|
|
DIV_CLK_CLUSTER1_PCLKDBG,
|
||
|
|
DIV_CLK_CLUSTER1_CNTCLK,
|
||
|
|
DIV_CLK_CLUSTER1_ACLK,
|
||
|
|
DIV_CLK_CLUSTER1_ATCLK,
|
||
|
|
DIV_CLK_DBG_PCLKDBG,
|
||
|
|
DIV_CLK_DCAM_BUSP,
|
||
|
|
DIV_CLK_DPU0_BUSP,
|
||
|
|
DIV_CLKCMU_DPU1_DECON2,
|
||
|
|
DIV_CLK_DSP_BUSP,
|
||
|
|
DIV_CLK_G2D_BUSP,
|
||
|
|
DIV_CLK_G3D_BUSP,
|
||
|
|
DIV_CLK_ISPHQ_BUSP,
|
||
|
|
DIV_CLK_ISPLP_BUSP,
|
||
|
|
DIV_CLK_IVA_BUSP,
|
||
|
|
DIV_CLK_MFC_BUSP,
|
||
|
|
DIV_CLK_MIF_PRE,
|
||
|
|
DIV_CLK_MIF_BUSP,
|
||
|
|
DIV_CLK_MIF1_PRE,
|
||
|
|
DIV_CLK_MIF1_BUSP,
|
||
|
|
DIV_CLK_MIF2_PRE,
|
||
|
|
DIV_CLK_MIF2_BUSP,
|
||
|
|
DIV_CLK_MIF3_PRE,
|
||
|
|
DIV_CLK_MIF3_BUSP,
|
||
|
|
DIV_CLK_SRDZ_BUSP,
|
||
|
|
DIV_CLK_VPU_BUSP,
|
||
|
|
DIV_CLK_VTS_BUS,
|
||
|
|
DIV_CLK_VTS_DMICIF,
|
||
|
|
DIV_CLK_VTS_DMIC,
|
||
|
|
DIV_CLK_VTS_DMIC_DIV2,
|
||
|
|
|
||
|
|
DIV_CLK_CPUCL0_CPU = (DIV_CLK_VTS_DMIC_DIV2 | CONST_DIV_TYPE) + 1,
|
||
|
|
DIV_CLK_CPUCL1_CPU,
|
||
|
|
end_of_div,
|
||
|
|
num_of_div = (end_of_div - DIV_TYPE) & MASK_OF_ID,
|
||
|
|
|
||
|
|
CLK_BLK_ABOX_UID_ABOX_CMU_ABOX_IPCLKPORT_PCLK = GATE_TYPE,
|
||
|
|
GOUT_BLK_ABOX_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_ABOX_UID_PMU_ABOX_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_ABOX_UID_SYSREG_ABOX_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF0,
|
||
|
|
GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF1,
|
||
|
|
GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF3,
|
||
|
|
GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_DSIF,
|
||
|
|
GOUT_BLK_ABOX_UID_LHS_ATB_ABOX_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_ABOX_UID_GPIO_ABOX_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_ABOX_UID_AXI_US_32to128_IPCLKPORT_aclk,
|
||
|
|
GOUT_BLK_ABOX_UID_RSTnSYNC_CLK_ABOX_BUS_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_ABOX_UID_RSTnSYNC_CLK_ABOX_CPU_ATCLK_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_ABOX_UID_RSTnSYNC_CLK_ABOX_CPU_PCLKDBG_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_ABOX_UID_RSTnSYNC_CLK_ABOX_DSIF_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_ABOX_UID_RSTnSYNC_CLK_ABOX_UAIF0_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_ABOX_UID_RSTnSYNC_CLK_ABOX_UAIF1_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_ABOX_UID_RSTnSYNC_CLK_ABOX_UAIF2_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_ABOX_UID_RSTnSYNC_CLK_ABOX_UAIF3_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_ACLK,
|
||
|
|
GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ASB,
|
||
|
|
GOUT_BLK_ABOX_UID_RSTnSYNC_CLK_ABOX_CPU_ACLK_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_CA7,
|
||
|
|
GOUT_BLK_ABOX_UID_RSTnSYNC_CLK_ABOX_CPU_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM,
|
||
|
|
GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF2,
|
||
|
|
GOUT_BLK_ABOX_UID_LHM_AXI_P_ABOX_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS,
|
||
|
|
GOUT_BLK_ABOX_UID_RSTnSYNC_CLK_ABOX_BUSP_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_ABOX_UID_WDT_ABOXCPU_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ABOX_UID_DMIC_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ATB,
|
||
|
|
GOUT_BLK_ABOX_UID_ABOX_DAP_IPCLKPORT_dapclk,
|
||
|
|
GOUT_BLK_ABOX_UID_TREX_ABOX_IPCLKPORT_clk,
|
||
|
|
GOUT_BLK_ABOX_UID_WRAP2_CONV_ABOX_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ABOX_UID_DFTMUX_ABOX_IPCLKPORT_AUD_CODEC_MCLK,
|
||
|
|
GOUT_BLK_ABOX_UID_RSTnSYNC_CLK_ABOX_UAIF4_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF4,
|
||
|
|
CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU,
|
||
|
|
GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS,
|
||
|
|
GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_XIU_D_ALIVE,
|
||
|
|
GOUT_BLK_APM_UID_RSTnSYNC_CLK_APM_BUS_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_APM_UID_SCAN2AXI_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_BUS1_UID_LHM_ACEL_D_FSYS1_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUS1_UID_LHS_AXI_P_FSYS1_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_pclk,
|
||
|
|
GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1,
|
||
|
|
GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_pclk,
|
||
|
|
GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_BUS1_UID_PMU_BUS1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_BUS1_UID_LHM_AXI_D_ALIVE_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUS1_UID_LHS_AXI_P_ALIVE_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUS1_UID_RSTnSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_BUS1_UID_RSTnSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_BUSC_UID_AXI2APB_BUSCP0_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_BUSC_UID_AXI2APB_BUSCP1_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_BUSC_UID_AXI2APB_BUSC_TDP_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_BUSC_UID_GPIO_BUSC_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_BUSC_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_BUSC_UID_PMU_BUSC_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_BUSC_UID_SECMBOX_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_BUSC_UID_MBOX_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S0,
|
||
|
|
GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S1,
|
||
|
|
GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_pclk,
|
||
|
|
GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_pclk,
|
||
|
|
GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_BUSC,
|
||
|
|
GOUT_BLK_BUSC_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_BUSC_UID_RSTnSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_RSTnSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_GNSSMBOX_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_BUSC_UID_SPEEDY_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_PCLK_BATCHER_SPEEDY,
|
||
|
|
GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_i_pclk_BATCHER_AP,
|
||
|
|
GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_i_pclk_BATCHER_CP,
|
||
|
|
GOUT_BLK_BUSC_UID_HSI2CDF_IPCLKPORT_iPCLK,
|
||
|
|
GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKS,
|
||
|
|
GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKM,
|
||
|
|
GOUT_BLK_BUSC_UID_RSTnSYNC_CLK_BUSC_BUSPHSI2C_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SCI_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHS_AXI_D_IVASC_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_PDMA0_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_BUSC_UID_SPDMA_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS,
|
||
|
|
GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM,
|
||
|
|
GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS,
|
||
|
|
GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM,
|
||
|
|
GOUT_BLK_BUSC_UID_LHM_ACEL_D0_G2D_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHM_ACEL_D1_G2D_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHM_ACEL_D2_G2D_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHM_ACEL_D_DSP_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHM_ACEL_D_FSYS0_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHM_ACEL_D_IVA_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHM_ACEL_D_VPU_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHM_AXI_D0_CAM_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHM_AXI_D0_DPU_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHM_AXI_D0_MFC_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHM_AXI_D1_CAM_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHM_AXI_D1_DPU_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHM_AXI_D1_MFC_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHM_AXI_D2_DPU_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHM_AXI_D_SRDZ_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHM_AXI_D_ISPLP_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHS_AXI_P0_DPU_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHS_AXI_P1_DPU_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHS_AXI_P_ABOX_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHS_AXI_P_SRDZ_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHS_AXI_P_DSP_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHS_AXI_P_FSYS0_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPHQ_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPLP_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHS_AXI_P_IVA_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHS_AXI_P_VPU_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_ACLK_BUSC,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_BNS,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSISX4_DMA,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_MC_SCALER,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU0,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_VRA,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_CFW_CAM,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM0,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM1,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_CSISX4,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU0,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_VRA,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM0,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM1,
|
||
|
|
GOUT_BLK_CAM_UID_LHS_AXI_D0_CAM_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CAM_UID_LHS_AXI_D1_CAM_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_ACLK,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_MC_SCALER,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM0,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM0,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM1,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_CSISX4,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU0,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_VRA,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU0_MCSC,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU0,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPLP,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPHQ,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU0,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2to1_ISP_TPU0,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1to2_TPU0_MCSC,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_VRA,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2to1_VRA,
|
||
|
|
GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_DIV2,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_DIV2,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_DIV2,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_DIV2,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU0,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_VRA,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_0,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_1,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM1,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU0,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_VRA,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_D_CAM0_4x1,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_P_CAM_1x2,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_MC_SCALER,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSISX4_DMA,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_MCSC_VRA,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPLP_CAM,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPHQ_CAM,
|
||
|
|
GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU0,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_VRA,
|
||
|
|
GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_ACLK,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BNS,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_BNS,
|
||
|
|
GOUT_BLK_CAM_UID_RSTnSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_CAM_UID_RSTnSYNC_CLK_CAM_BUSD_DIV2_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_CAM_UID_RSTnSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_CAM_UID_RSTnSYNC_CLK_CAM_TPU0_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_CAM_UID_RSTnSYNC_CLK_CAM_VRA_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSISX4_DMA,
|
||
|
|
CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU1,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU1,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU1,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU1,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU1_MCSC,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU1,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU1,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2to1_ISP_TPU1,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1to2_TPU1_MCSC,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU1,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU1,
|
||
|
|
GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_CAM_UID_RSTnSYNC_CLK_CAM_TPU1_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS0,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS1,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS3,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS2,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS0,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS1,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS2,
|
||
|
|
GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS3,
|
||
|
|
GOUT_BLK_CAM_UID_PMU_CAM_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_CAM_UID_LHM_ATB_SRDZCAM_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CAM_UID_ISP_EWGEN_CAM_IPCLKPORT_I_PCLK,
|
||
|
|
GATE_CLKCMU_APM_BUS,
|
||
|
|
GATE_CLKCMU_FSYS0_BUS,
|
||
|
|
CLKCMU_MIF_SWITCH,
|
||
|
|
GATE_CLKCMU_MFC_BUS,
|
||
|
|
GATE_CLKCMU_G2D_G2D,
|
||
|
|
GATE_CLKCMU_FSYS0_USBDRD30,
|
||
|
|
GATE_CLKCMU_FSYS0_MMC_EMBD,
|
||
|
|
GATE_CLKCMU_FSYS0_UFS_EMBD,
|
||
|
|
GATE_CLKCMU_FSYS1_BUS,
|
||
|
|
GATE_CLKCMU_FSYS1_MMC_CARD,
|
||
|
|
GATE_CLKCMU_DPU_BUS,
|
||
|
|
GATE_CLKCMU_G3D_SWITCH,
|
||
|
|
GATE_CLKCMU_PERIS_BUS,
|
||
|
|
GATE_CLKCMU_VPU_BUS,
|
||
|
|
GATE_CLKCMU_DSP_BUS,
|
||
|
|
GATE_CLKCMU_PERIC0_BUS,
|
||
|
|
GATE_CLKCMU_PERIC0_UART_DBG,
|
||
|
|
GATE_CLKCMU_PERIC0_USI00,
|
||
|
|
GATE_CLKCMU_PERIC0_USI01,
|
||
|
|
GATE_CLKCMU_PERIC0_USI02,
|
||
|
|
GATE_CLKCMU_PERIC1_USI05,
|
||
|
|
GATE_CLKCMU_PERIC1_UART_BT,
|
||
|
|
GATE_CLKCMU_PERIC1_USI04,
|
||
|
|
GATE_CLKCMU_PERIC1_BUS,
|
||
|
|
GATE_CLKCMU_PERIC1_USI06,
|
||
|
|
GATE_CLKCMU_PERIC1_USI10,
|
||
|
|
GATE_CLKCMU_PERIC1_USI11,
|
||
|
|
GATE_CLKCMU_PERIC1_USI12,
|
||
|
|
GATE_CLKCMU_PERIC1_USI13,
|
||
|
|
GATE_CLKCMU_BUSC_BUS,
|
||
|
|
GATE_CLKCMU_PERIC1_USI08,
|
||
|
|
GATE_CLKCMU_PERIC1_USI07,
|
||
|
|
GATE_CLKCMU_PERIC0_USI03,
|
||
|
|
GATE_CLKCMU_BUS1_BUS,
|
||
|
|
GATE_CLKCMU_PERIC1_USI09,
|
||
|
|
GATE_CLKCMU_CPUCL1_SWITCH,
|
||
|
|
GATE_CLKCMU_CPUCL0_SWITCH,
|
||
|
|
GATE_CLKCMU_CORE_BUS,
|
||
|
|
GATE_CLKCMU_CAM_BUS,
|
||
|
|
GATE_CLKCMU_CAM_TPU0,
|
||
|
|
GATE_CLKCMU_CAM_TPU1,
|
||
|
|
GATE_CLKCMU_ISPLP_BUS,
|
||
|
|
GATE_CLKCMU_ISPHQ_BUS,
|
||
|
|
GATE_CLKCMU_ABOX_CPUABOX,
|
||
|
|
GATE_CLKCMU_G2D_JPEG,
|
||
|
|
GATE_CLKCMU_HPM,
|
||
|
|
GATE_CLKCMU_FSYS1_PCIE,
|
||
|
|
GATE_CLKCMU_DBG_BUS,
|
||
|
|
GATE_CLKCMU_PERIC1_SPI_CAM0,
|
||
|
|
GATE_CLKCMU_PERIC1_SPI_CAM1,
|
||
|
|
CLKCMU_DROOPDETECTOR,
|
||
|
|
GATE_CLKCMU_CIS_CLK0,
|
||
|
|
GATE_CLKCMU_CIS_CLK1,
|
||
|
|
GATE_CLKCMU_CIS_CLK3,
|
||
|
|
GATE_CLKCMU_CIS_CLK2,
|
||
|
|
GATE_CLKCMU_IVA_BUS,
|
||
|
|
GATE_CLKCMU_FSYS1_UFS_CARD,
|
||
|
|
GATE_CLKCMU_BUSC_BUSPHSI2C,
|
||
|
|
GATE_CLKCMU_CAM_VRA,
|
||
|
|
GATE_CLKCMU_PERIC1_SPEEDY2,
|
||
|
|
GATE_CLKCMU_FSYS0_DPGTC,
|
||
|
|
GATE_CLKCMU_MODEM_SHARED0,
|
||
|
|
GATE_CLKCMU_MODEM_SHARED1,
|
||
|
|
GATE_CLKCMU_DCAM_BUS,
|
||
|
|
GATE_CLKCMU_IMEM_BUS,
|
||
|
|
GATE_CLKCMU_SRDZ_IMGD,
|
||
|
|
GATE_CLKCMU_SRDZ_BUS,
|
||
|
|
GATE_CLKCMU_DCAM_IMGD,
|
||
|
|
CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_CORE_UID_PMU_CORE_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE,
|
||
|
|
GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE,
|
||
|
|
GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_pclk,
|
||
|
|
GOUT_BLK_CORE_UID_CCI_IPCLKPORT_clk,
|
||
|
|
GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_LHM_CPACE_D_CPUCL0_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF0_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF1_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF2_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF3_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_LHM_DBG_G0_DMC_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_LHM_DBG_G1_DMC_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_LHM_DBG_G2_DMC_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_LHM_DBG_G3_DMC_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM,
|
||
|
|
GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_CORE_UID_APBBR_CCI_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_pclk,
|
||
|
|
GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE,
|
||
|
|
GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_CORE_UID_LHS_AXI_P_DBG_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_LHS_AXI_P_IMEM_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_pclk,
|
||
|
|
CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_hpm_targetclk_c,
|
||
|
|
GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_CPUCL0_UID_BUSIF_DROOPDETECTOR_CPUCL0_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_hpm_targetclk_c,
|
||
|
|
GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP0_IPCLKPORT_CK_IN,
|
||
|
|
CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP1_IPCLKPORT_CK_IN,
|
||
|
|
GATE_CLK_CPUCL0_CPU,
|
||
|
|
GOUT_BLK_CPUCL0_UID_RSTnSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_CPUCL1_UID_PMU_CPUCL1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_hpm_targetclk_c,
|
||
|
|
GATE_CLK_CPUCL1_CPU,
|
||
|
|
GOUT_BLK_CPUCL1_UID_RSTnSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DBG_UID_DBG_CMU_DBG_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_DBG_UID_LHM_AXI_P_DBG_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DBG_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DBG_UID_AXI2APB_CORESIGHT_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_DBG_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_ATCLK,
|
||
|
|
GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_ATCLK,
|
||
|
|
GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_PCLKDBG,
|
||
|
|
GOUT_BLK_DBG_UID_SECJTAG_IPCLKPORT_i_clk,
|
||
|
|
GOUT_BLK_DBG_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DBG_UID_PMU_DBG_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_DBG_UID_SYSREG_DBG_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_DBG_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DBG_UID_RSTnSYNC_CLK_DBG_ATCLK_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_DBG_UID_RSTnSYNC_CLK_DBG_PCLKDBG_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_DBG_UID_DUMPPC_CPUCL0_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_DBG_UID_DUMPPC_CPUCL1_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_DCAM_UID_DCAM_CMU_DCAM_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_DCAM_UID_DCP_IPCLKPORT_Clk,
|
||
|
|
GOUT_BLK_DCAM_UID_PMU_DCAM_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_DCAM_UID_SYSREG_DCAM_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_DCAM_UID_AXI2APB_DCAM_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_DCAM_UID_AXI2APB_DCAM_SYS_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKS,
|
||
|
|
GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKM,
|
||
|
|
GOUT_BLK_DCAM_UID_XIU_P_DCAM_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_DCAM_UID_LHM_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DCAM_UID_LHS_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DCAM_UID_PXL_ASBM_DCAM_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_DCAM_UID_RSTnSYNC_CLK_DCAM_BUSD_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_DCAM_UID_RSTnSYNC_CLK_DCAM_BUSP_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_DCAM_UID_PXL_ASBS_DCAM_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_DCAM_UID_LHS_ATB_DCAMSRDZ_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DCAM_UID_RSTnSYNC_CLK_DCAM_IMGD_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_ACLK,
|
||
|
|
GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_PCLK,
|
||
|
|
CLKCMU_DPU1_BUSD,
|
||
|
|
CLKCMU_DPU1_BUSP,
|
||
|
|
CLK_BLK_DPU0_UID_DPU0_CMU_DPU0_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_DPU0_UID_DECON0_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_ACLK,
|
||
|
|
GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_ACLK,
|
||
|
|
GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_DPU0_UID_PMU_DPU0_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_DPU0_UID_SYSREG_DPU0_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_DPU0_UID_AXI2APB_DPU0P1_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_DPU0_UID_AXI2APB_DPU0P0_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_SECURE,
|
||
|
|
GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_NONSECURE,
|
||
|
|
GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_SECURE,
|
||
|
|
GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_NONSECURE,
|
||
|
|
GOUT_BLK_DPU0_UID_LHM_AXI_P0_DPU_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DPU0_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DPU0_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DPU0_UID_XIU_P0_DPU_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKS,
|
||
|
|
GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKM,
|
||
|
|
GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS,
|
||
|
|
GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM,
|
||
|
|
GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS,
|
||
|
|
GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS,
|
||
|
|
GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKS,
|
||
|
|
GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKM,
|
||
|
|
GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKS,
|
||
|
|
GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKM,
|
||
|
|
GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_VGR_ACLK,
|
||
|
|
GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G0_ACLK,
|
||
|
|
GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G1_ACLK,
|
||
|
|
GOUT_BLK_DPU0_UID_DPU_WB_MUX_IPCLKPORT_DPP_G1_ACLK,
|
||
|
|
GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH0,
|
||
|
|
GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH1,
|
||
|
|
GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH2,
|
||
|
|
GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_WB,
|
||
|
|
GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH_INTF,
|
||
|
|
GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_SFR,
|
||
|
|
GOUT_BLK_DPU0_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DPU0_UID_LHS_AXI_D_USBTV_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_ACLK,
|
||
|
|
GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_SECURE,
|
||
|
|
GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_NONSECURE,
|
||
|
|
GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM,
|
||
|
|
GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS,
|
||
|
|
GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM,
|
||
|
|
GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS,
|
||
|
|
GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKM,
|
||
|
|
GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS,
|
||
|
|
GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_DPU0_UID_RSTnSYNC_CLK_DPU0_BUSD_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_DPU0_UID_RSTnSYNC_CLK_DPU0_BUSP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DPU1_UID_DPU1_CMU_DPU1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_DPU1_UID_DECON1_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_DPU1_UID_SYSREG_DPU1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_DPU1_UID_PMU_DPU1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_DPU1_UID_AXI2APB_DPU1P0_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_DPU1_UID_LHM_AXI_P_DPU1_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKS,
|
||
|
|
GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKM,
|
||
|
|
GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKS,
|
||
|
|
GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKM,
|
||
|
|
GOUT_BLK_DPU1_UID_RSTnSYNC_CLK_DPU1_BUSD_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_DPU1_UID_RSTnSYNC_CLK_DPU1_BUSP_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_DPU1_UID_RSTnSYNC_CLK_DPU1_DECON2_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_VCLK,
|
||
|
|
CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_DSP_UID_SCORE_IPCLKPORT_clk,
|
||
|
|
GOUT_BLK_DSP_UID_PMU_DSP_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_DSP_UID_AXI2APB_DSP_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKS,
|
||
|
|
GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKM,
|
||
|
|
GOUT_BLK_DSP_UID_XIU_D_DSP0_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_NONSECURE,
|
||
|
|
GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_ACLK,
|
||
|
|
GOUT_BLK_DSP_UID_LHM_AXI_P_DSP_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_SECURE,
|
||
|
|
GOUT_BLK_DSP_UID_LHS_ACEL_D_DSP_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DSP_UID_RSTnSYNC_CLK_DSP_BUSD_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_DSP_UID_RSTnSYNC_CLK_DSP_BUSP_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_DSP_UID_XIU_D_DSP1_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_DSP_UID_XIU_P_DSP_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_DSP_UID_LHM_AXI_D_IVADSP_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DSP_UID_LHM_AXI_D_VPUDSP_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DSP_UID_LHM_AXI_P_IVADSP_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DSP_UID_LHS_AXI_P_DSPIVA_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DSP_UID_LHS_AXI_P_DSPVPU_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_DSP_UID_WRAP2_CONV_DSP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_LHS_ACEL_D_FSYS0_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_AHBBR_FSYS0_IPCLKPORT_HCLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_LHM_AXI_G_ETR_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_LHM_AXI_P_FSYS0_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_LHM_AXI_D_USBTV_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_US_D_FSYS0_USB_IPCLKPORT_aclk,
|
||
|
|
GOUT_BLK_FSYS0_UID_AXI2AHB_FSYS0_IPCLKPORT_aclk,
|
||
|
|
GOUT_BLK_FSYS0_UID_AXI2AHB_USB_FSYS0_IPCLKPORT_aclk,
|
||
|
|
GOUT_BLK_FSYS0_UID_AXI2APB_FSYS0_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_ACLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_GPIO_FSYS0_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_I_ACLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_SDCLKIN,
|
||
|
|
GOUT_BLK_FSYS0_UID_PMU_FSYS0_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_SYSREG_FSYS0_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
|
||
|
|
GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_USB_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_XIU_P_FSYS0_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_CORE_CLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_SUSPEND_CLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_REF_CLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_ACLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_AHB_CLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_XIU_CLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_ACLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_RSTnSYNC_CLK_FSYS0_BUS_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_GTC_EXT_CLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
|
||
|
|
GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_ieee1500_wrapper_for_pcie_phy_lc_x2_inst_0_i_scl_apb_pclk,
|
||
|
|
GOUT_BLK_FSYS1_UID_TOE_WIFI0_IPCLKPORT_i_CLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_TOE_WIFI1_IPCLKPORT_i_CLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_i_ACLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_i_PCLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_i_PCLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_i_ACLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_PMU_FSYS1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_aclk,
|
||
|
|
GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_FSYS1_UID_PCIE_IPCLKPORT_phy_ref_clk_in,
|
||
|
|
GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_slv_aclk_0,
|
||
|
|
GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_mstr_aclk_0,
|
||
|
|
GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_dbi_aclk_0,
|
||
|
|
GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_pcie_sub_ctrl_inst_0_i_driver_apb_clk,
|
||
|
|
GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_pipe2_digital_x2_wrap_inst_0_i_apb_pclk_scl,
|
||
|
|
GOUT_BLK_FSYS1_UID_RSTnSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_mstr_aclk_1,
|
||
|
|
GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_slv_aclk_1,
|
||
|
|
GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_dbi_aclk_1,
|
||
|
|
GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_pcie_sub_ctrl_inst_1_i_driver_apb_clk,
|
||
|
|
GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK,
|
||
|
|
GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO,
|
||
|
|
GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM,
|
||
|
|
CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_NONSECURE,
|
||
|
|
GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_G2D_UID_LHS_ACEL_D0_G2D_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_G2D_UID_LHS_ACEL_D1_G2D_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKM,
|
||
|
|
GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKS,
|
||
|
|
GOUT_BLK_G2D_UID_AXI2APB_G2DP0_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_G2D_UID_G2D_IPCLKPORT_Clk,
|
||
|
|
GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_NONSECURE,
|
||
|
|
GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_G2D_UID_PMU_G2D_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_ACLK,
|
||
|
|
GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_ACLK,
|
||
|
|
GOUT_BLK_G2D_UID_XIU_P_G2D_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_G2D_UID_AXI2APB_G2DP1_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK,
|
||
|
|
GOUT_BLK_G2D_UID_M2MSCALER_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_ACLK,
|
||
|
|
GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_NONSECURE,
|
||
|
|
GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_G2D_UID_LHS_ACEL_D2_G2D_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKM,
|
||
|
|
GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKS,
|
||
|
|
GOUT_BLK_G2D_UID_XIU_D_G2D_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_SECURE,
|
||
|
|
GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_SECURE,
|
||
|
|
GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_SECURE,
|
||
|
|
GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKS,
|
||
|
|
GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKM,
|
||
|
|
GOUT_BLK_G2D_UID_RSTnSYNC_CLK_G2D_G2D_BUSD_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_G2D_UID_RSTnSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_G2D_UID_RSTnSYNC_CLK_G2D_JPEG_BUSD_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_hpm_targetclk_c,
|
||
|
|
GOUT_BLK_G3D_UID_PMU_G3D_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_G3D_UID_RSTnSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK,
|
||
|
|
GATE_CLK_G3D_AGPU,
|
||
|
|
GOUT_BLK_IMEM_UID_LHM_AXI_P_IMEM_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_IMEM_UID_RSTnSYNC_CLK_IMEM_BUS_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_IMEM_UID_AXI2APB_IMEM_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_IMEM_UID_XIU_P_IMEM_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_IMEM_UID_SYSREG_IMEM_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_IMEM_UID_PMU_IMEM_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_IMEM_UID_IMEM_CMU_IMEM_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_IMEM_UID_IntMEM_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_TAA_ACLK,
|
||
|
|
GOUT_BLK_ISPHQ_UID_LHM_AXI_P_ISPHQ_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_ISPHQ_UID_LHS_AXI_LD_ISPHQ_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_ISPHQ_ACLK,
|
||
|
|
GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_ACLK,
|
||
|
|
GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_ACLK,
|
||
|
|
GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_XIU_D_ISPHQ_ACLK,
|
||
|
|
GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_AXI2APB_BRIDGE_ISPHQ_ACLK,
|
||
|
|
GOUT_BLK_ISPHQ_UID_RSTnSYNC_CLK_ISPHQ_BUSD_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_ISPHQ_UID_RSTnSYNC_CLK_ISPHQ_BUSP_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKM,
|
||
|
|
GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKM,
|
||
|
|
GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKS,
|
||
|
|
GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKS,
|
||
|
|
GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_PCLK,
|
||
|
|
GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_PCLK,
|
||
|
|
GOUT_BLK_ISPHQ_UID_PMU_ISPHQ_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_ISPHQ_UID_SYSREG_ISPHQ_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ISPHQ_UID_ISPHQ_CMU_ISPHQ_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_ISPHQ_UID_ISP_EWGEN_ISPHQ_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_TAAW_ACLK,
|
||
|
|
GOUT_BLK_ISPLP_UID_LHM_AXI_P_ISPLP_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_ISPLP_UID_LHS_AXI_D_ISPLP_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_ACLK,
|
||
|
|
GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_ISPLP_ACLK,
|
||
|
|
GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_ACLK,
|
||
|
|
GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_XIU_D_ISPLP_ACLK,
|
||
|
|
GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_ACLK,
|
||
|
|
GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_ACLK,
|
||
|
|
GOUT_BLK_ISPLP_UID_RSTnSYNC_CLK_ISPLP_BUSD_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_ISPLP_UID_RSTnSYNC_CLK_ISPLP_BUSP_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKM,
|
||
|
|
GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKM,
|
||
|
|
GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKS,
|
||
|
|
GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKS,
|
||
|
|
GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_PCLK,
|
||
|
|
GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_PCLK,
|
||
|
|
GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_PCLK,
|
||
|
|
GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_NONSECURE,
|
||
|
|
GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_SECURE,
|
||
|
|
GOUT_BLK_ISPLP_UID_PMU_ISPLP_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_ISPLP_UID_SYSREG_ISPLP_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_AXI2APB_BRIDGE_ISPLP_ACLK,
|
||
|
|
CLK_BLK_ISPLP_UID_ISPLP_CMU_ISPLP_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_ISPLP_UID_LHM_AXI_LD_ISPHQ_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_ISPLP_UID_ISP_EWGEN_ISPLP_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_ACLK,
|
||
|
|
CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_IVA_UID_LHS_ACEL_D_IVA_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_IVA_UID_LHS_AXI_D_IVADSP_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_IVA_UID_LHS_AXI_P_IVADSP_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_IVA_UID_LHM_AXI_P_DSPIVA_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_ACLK,
|
||
|
|
GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_IVA_UID_XIU_D_IVA_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKS,
|
||
|
|
GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKM,
|
||
|
|
GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_IVA_UID_PMU_IVA_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_IVA_UID_IVA_IPCLKPORT_clk_a,
|
||
|
|
GOUT_BLK_IVA_UID_RSTnSYNC_CLK_IVA_BUSD_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_IVA_UID_RSTnSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_IVA_UID_IVA_IntMEM_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_IVA_UID_LHM_AXI_D_IVASC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MFC_UID_MFC_IPCLKPORT_Clk,
|
||
|
|
GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKS,
|
||
|
|
GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKM,
|
||
|
|
GOUT_BLK_MFC_UID_AXI2APB_MFC_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_MFC_UID_PMU_MFC_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MFC_UID_LHS_AXI_D0_MFC_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_MFC_UID_LHS_AXI_D1_MFC_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_SECURE,
|
||
|
|
GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_SECURE,
|
||
|
|
GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK,
|
||
|
|
GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK,
|
||
|
|
GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_NONSECURE,
|
||
|
|
GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_NONSECURE,
|
||
|
|
GOUT_BLK_MFC_UID_RSTnSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_MFC_UID_RSTnSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF_UID_PMU_MIF_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_MIF_UID_AXI2APB_MIF_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF_UID_APBBR_DMCTZ_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_hpm_targetclk_c,
|
||
|
|
GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK1,
|
||
|
|
GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK2,
|
||
|
|
CLK_BLK_MIF_UID_DMC_IPCLKPORT_soc_clk,
|
||
|
|
CLK_BLK_MIF_UID_LHM_PSCDC_D_MIF_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_clk,
|
||
|
|
CLK_BLK_MIF_UID_RSTnSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_MIF_UID_RSTnSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_hpm_targetclk_c,
|
||
|
|
CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF1_UID_APBBR_DDRPHY1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF1_UID_APBBR_DMC1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF1_UID_APBBR_DMCTZ1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF1_UID_AXI2APB_MIF1_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF1_UID_DDRPHY1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK1,
|
||
|
|
GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK2,
|
||
|
|
GOUT_BLK_MIF1_UID_LHM_AXI_P_MIF1_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_MIF1_UID_PMU_MIF1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF1_UID_SYSREG_MIF1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF1_UID_RSTnSYNC_CLK_MIF_BUSP1_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MIF1_UID_DMC1_IPCLKPORT_soc_clk,
|
||
|
|
CLK_BLK_MIF1_UID_LHM_PSCDC_D_MIF1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_clk,
|
||
|
|
CLK_BLK_MIF1_UID_RSTnSYNC_CLK_MIF_BUSD1_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MIF2_UID_MIF2_CMU_MIF2_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MIF2_UID_HPM_MIF2_IPCLKPORT_hpm_targetclk_c,
|
||
|
|
GOUT_BLK_MIF2_UID_APBBR_DDRPHY2_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF2_UID_APBBR_DMC2_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF2_UID_APBBR_DMCTZ2_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF2_UID_AXI2APB_MIF2_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_MIF2_UID_BUSIF_HPMMIF2_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF2_UID_DDRPHY2_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK1,
|
||
|
|
GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK2,
|
||
|
|
GOUT_BLK_MIF2_UID_LHM_AXI_P_MIF2_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_MIF2_UID_PMU_MIF2_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF2_UID_RSTnSYNC_CLK_MIF_BUSP2_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_MIF2_UID_SYSREG_MIF2_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MIF2_UID_DMC2_IPCLKPORT_soc_clk,
|
||
|
|
CLK_BLK_MIF2_UID_LHM_PSCDC_D_MIF2_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_clk,
|
||
|
|
CLK_BLK_MIF2_UID_RSTnSYNC_CLK_MIF_BUSD2_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MIF3_UID_HPM_MIF3_IPCLKPORT_hpm_targetclk_c,
|
||
|
|
GOUT_BLK_MIF3_UID_APBBR_DDRPHY3_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF3_UID_APBBR_DMC3_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF3_UID_APBBR_DMCTZ3_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF3_UID_AXI2APB_MIF3_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_MIF3_UID_BUSIF_HPMMIF3_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF3_UID_DDRPHY3_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK1,
|
||
|
|
GOUT_BLK_MIF3_UID_LHM_AXI_P_MIF3_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_MIF3_UID_PMU_MIF3_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF3_UID_RSTnSYNC_CLK_MIF_BUSP3_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_MIF3_UID_SYSREG_MIF3_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK2,
|
||
|
|
CLK_BLK_MIF3_UID_MIF3_CMU_MIF3_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MIF3_UID_DMC3_IPCLKPORT_soc_clk,
|
||
|
|
CLK_BLK_MIF3_UID_LHM_PSCDC_D_MIF3_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_clk,
|
||
|
|
GOUT_BLK_MIF3_UID_RSTnSYNC_CLK_MIF_BUSD3_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIC0_UID_PMU_PERIC0_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_i_PCLK_S0,
|
||
|
|
GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_EXT_UCLK,
|
||
|
|
GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_i_PCLK,
|
||
|
|
GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_i_SCLK_USI,
|
||
|
|
GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_i_PCLK,
|
||
|
|
GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_i_SCLK_USI,
|
||
|
|
GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_i_PCLK,
|
||
|
|
GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_i_SCLK_USI,
|
||
|
|
GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_i_PCLK,
|
||
|
|
GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_i_SCLK_USI,
|
||
|
|
GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_PERIC0_UID_SPEEDY2_TSP_IPCLKPORT_clk,
|
||
|
|
GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_PMU_PERIC1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_i_PCLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_i_PCLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_i_PCLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_i_PCLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_i_PCLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_i_PCLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_i_PCLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_i_PCLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_i_PCLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_EXT_UCLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_i_SCLK_USI,
|
||
|
|
GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_i_SCLK_USI,
|
||
|
|
GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_i_SCLK_USI,
|
||
|
|
GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_i_SCLK_USI,
|
||
|
|
GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_i_SCLK_USI,
|
||
|
|
GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_i_SCLK_USI,
|
||
|
|
GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_i_SCLK_USI,
|
||
|
|
GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_i_SCLK_USI,
|
||
|
|
GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_i_SCLK_USI,
|
||
|
|
GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_i_SCLK_USI,
|
||
|
|
CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_HSI2C_CAM2_IPCLKPORT_iPCLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_HSI2C_CAM3_IPCLKPORT_iPCLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_SPI_EXT_CLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_SPI_EXT_CLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_i_PCLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_HSI2C_CAM1_IPCLKPORT_iPCLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_HSI2C_CAM0_IPCLKPORT_iPCLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_clk,
|
||
|
|
GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_sclk,
|
||
|
|
CLK_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_SPEEDY2_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_clk,
|
||
|
|
GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_sclk,
|
||
|
|
GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_clk,
|
||
|
|
GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_sclk,
|
||
|
|
GOUT_BLK_PERIC1_UID_SPEEDY2_TSP1_IPCLKPORT_clk,
|
||
|
|
GOUT_BLK_PERIC1_UID_SPEEDY2_TSP2_IPCLKPORT_clk,
|
||
|
|
GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P2_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_PERIS_UID_AXI2APB_PERISP0_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_PERIS_UID_AXI2APB_PERISP1_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIS_UID_PMU_PERIS_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIS_UID_TZPC00_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIS_UID_TZPC01_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIS_UID_TZPC10_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIS_UID_TZPC11_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIS_UID_TZPC12_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIS_UID_TZPC13_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIS_UID_TZPC14_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIS_UID_TZPC15_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIS_UID_TZPC02_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIS_UID_TZPC03_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIS_UID_TZPC04_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIS_UID_TZPC05_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIS_UID_TZPC06_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIS_UID_TZPC07_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIS_UID_TZPC08_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIS_UID_TZPC09_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIS_UID_RSTnSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_PERIS_UID_RSTnSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS,
|
||
|
|
GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM,
|
||
|
|
GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_SRDZ_UID_SRDZ_CMU_SRDZ_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_SRDZ_UID_RSTnSYNC_CLK_SRDZ_BUSD_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_SRDZ_UID_RSTnSYNC_CLK_SRDZ_BUSP_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_SRDZ_UID_RSTnSYNC_CLK_SRDZ_IMGD_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_SRDZ_UID_SRDZ_IPCLKPORT_Clk,
|
||
|
|
GOUT_BLK_SRDZ_UID_PMU_SRDZ_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_SRDZ_UID_SYSREG_SRDZ_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_SYS_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKS,
|
||
|
|
GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKM,
|
||
|
|
GOUT_BLK_SRDZ_UID_XIU_D_SRDZ_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_SRDZ_UID_XIU_P_SRDZ_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_NONSECURE,
|
||
|
|
GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_SECURE,
|
||
|
|
GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_ACLK,
|
||
|
|
GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_SRDZ_UID_LHM_AXI_P_SRDZ_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_SRDZ_UID_LHS_AXI_D_SRDZ_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_SRDZ_UID_LHS_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_SRDZ_UID_LHM_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_SRDZ_UID_LHS_ATB_SRDZCAM_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_SRDZ_UID_LHM_ATB_DCAMSRDZ_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_SRDZ_UID_PXL_ASBM_1to2_SRDZ_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_SRDZ_UID_PXL_ASBS_SRDZ_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_VPU_UID_VPU_CMU_VPU_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_VPU_UID_VPU_IPCLKPORT_HCLK,
|
||
|
|
GOUT_BLK_VPU_UID_VPU_IPCLKPORT_Clk,
|
||
|
|
GOUT_BLK_VPU_UID_PMU_VPU_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_VPU_UID_SYSREG_VPU_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_VPU_UID_AXI2APB_VPU_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_VPU_UID_XIU_P_VPU_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_NONSECURE,
|
||
|
|
GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_ACLK,
|
||
|
|
GOUT_BLK_VPU_UID_LHM_AXI_P_VPU_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_VPU_UID_LHS_ACEL_D_VPU_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_PCLK,
|
||
|
|
GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_SECURE,
|
||
|
|
GOUT_BLK_VPU_UID_AXI2AHB_VPU_IPCLKPORT_aclk,
|
||
|
|
GOUT_BLK_VPU_UID_RSTnSYNC_CLK_VPU_BUSD_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_VPU_UID_RSTnSYNC_CLK_VPU_BUSP_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_VPU_UID_XIU_D_VPU_IPCLKPORT_ACLK,
|
||
|
|
GOUT_BLK_VPU_UID_LHM_AXI_P_DSPVPU_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_VPU_UID_LHS_AXI_D_VPUDSP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK,
|
||
|
|
GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_SYS,
|
||
|
|
GOUT_BLK_VTS_UID_RSTnSYNC_CLK_VTS_BUS_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_VTS_UID_RSTnSYNC_CLK_VTS_DMICIF_IPCLKPORT_CLK,
|
||
|
|
GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_CPU,
|
||
|
|
GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMICIF_CLK,
|
||
|
|
GOUT_BLK_VTS_UID_MAILBOX_VTS2AP_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_HCLK,
|
||
|
|
GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK,
|
||
|
|
GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_DIV2_CLK,
|
||
|
|
CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_CLK,
|
||
|
|
end_of_gate,
|
||
|
|
num_of_gate = end_of_gate - GATE_TYPE,
|
||
|
|
};
|
||
|
|
|
||
|
|
#endif
|