lineage_kernel_xcoverpro/drivers/soc/samsung/cal-if/exynos8895/cmucal-node.c

#include "../cmucal.h"
#include "cmucal-node.h"
#include "cmucal-sfr.h"

/*=================CMUCAL version: S5E8895================================*/

/*====================The section of PLL rate tables===================*/
struct cmucal_pll_table pll_shared1_rate_table[] = {
	PLL_RATE_MPS(1865500000, 287, 4, 0),
};

struct cmucal_pll_table pll_shared4_rate_table[] = {
	PLL_RATE_MPS(667333313, 154, 6, 0),
};

struct cmucal_pll_table pll_shared3_rate_table[] = {
	PLL_RATE_MPS(630000000, 315, 13, 0),
};

struct cmucal_pll_table pll_shared2_rate_table[] = {
	PLL_RATE_MPS(800000000, 400, 13, 0),
};

struct cmucal_pll_table pll_shared0_rate_table[] = {
	PLL_RATE_MPS(2132000000, 328, 4, 0),
};

struct cmucal_pll_table pll_dpu_rate_table[] = {
	PLL_RATE_MPS(600000000, 300, 13, 0),
};

struct cmucal_pll_table pll_mif_rate_table[] = {
	PLL_RATE_MPS(4264000000, 492, 3, 0),
	PLL_RATE_MPS(3731000000, 574, 4, 0),
	PLL_RATE_MPS(2576599854, 991, 5, 1),
	PLL_RATE_MPS(1418000000, 709, 13, 0),
};

struct cmucal_pll_table pll_mif1_rate_table[] = {
	PLL_RATE_MPS(26000000, 0, 0, 0),
};

struct cmucal_pll_table pll_mif2_rate_table[] = {
	PLL_RATE_MPS(26000000, 0, 0, 0),
};

struct cmucal_pll_table pll_mif3_rate_table[] = {
	PLL_RATE_MPS(26000000, 0, 0, 0),
};

struct cmucal_pll_table pll_g3d_rate_table[] = {
	PLL_RATE_MPS(860000000, 430, 13, 0),
	PLL_RATE_MPS(600000000, 300, 13, 0),
	PLL_RATE_MPS(300000000, 150, 13, 0),
};

struct cmucal_pll_table pll_cpucl0_rate_table[] = {
	PLL_RATE_MPS(2860000000, 330, 3, 0),
	PLL_RATE_MPS(2160599854, 831, 5, 1),
	PLL_RATE_MPS(1924000000, 444, 3, 1),
	PLL_RATE_MPS(1066000000, 492, 3, 2),
	PLL_RATE_MPS(400000000, 200, 13, 0),
};

struct cmucal_pll_table pll_cpucl1_rate_table[] = {
	PLL_RATE_MPS(1906666666, 220, 3, 0),
	PLL_RATE_MPS(1449500000, 223, 4, 0),
	PLL_RATE_MPS(970666666, 224, 3, 1),
	PLL_RATE_MPS(600000000, 300, 13, 0),
	PLL_RATE_MPS(300000000, 150, 13, 0),
};

struct cmucal_pll_table pll_aud_rate_table[] = {
	PLL_RATE_MPSK(1179648000, 45, 1, 0, 24319),
	PLL_RATE_MPSK(1083801600, 42, 1, 0, -20665),
};

/*====================The section of PLLs===================*/
unsigned int cmucal_pll_size = 14;

struct cmucal_pll cmucal_pll_list[] = {
	CLK_PLL(PLL_1061X, PLL_AUD, OSCCLK_ABOX, PLL_LOCKTIME_PLL_AUD_PLL_LOCK_TIME, PLL_CON0_PLL_AUD_ENABLE, PLL_CON0_PLL_AUD_STABLE, PLL_CON0_PLL_AUD_DIV_P, PLL_CON0_PLL_AUD_DIV_M, PLL_CON0_PLL_AUD_DIV_S, PLL_CON3_PLL_AUD_DIV_K, pll_aud_rate_table, 150, 1500),
	CLK_PLL(PLL_1051X, PLL_SHARED1, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED1_PLL_LOCK_TIME, PLL_CON0_PLL_SHARED1_ENABLE, PLL_CON0_PLL_SHARED1_STABLE, PLL_CON0_PLL_SHARED1_DIV_P, PLL_CON0_PLL_SHARED1_DIV_M, PLL_CON0_PLL_SHARED1_DIV_S, EMPTY_CAL_ID, pll_shared1_rate_table, 150, 0),
	CLK_PLL(PLL_1052X, PLL_SHARED4, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED4_PLL_LOCK_TIME, PLL_CON0_PLL_SHARED4_ENABLE, PLL_CON0_PLL_SHARED4_STABLE, PLL_CON0_PLL_SHARED4_DIV_P, PLL_CON0_PLL_SHARED4_DIV_M, PLL_CON0_PLL_SHARED4_DIV_S, EMPTY_CAL_ID, pll_shared4_rate_table, 150, 0),
	CLK_PLL(PLL_1052X, PLL_SHARED3, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED3_PLL_LOCK_TIME, PLL_CON0_PLL_SHARED3_ENABLE, PLL_CON0_PLL_SHARED3_STABLE, PLL_CON0_PLL_SHARED3_DIV_P, PLL_CON0_PLL_SHARED3_DIV_M, PLL_CON0_PLL_SHARED3_DIV_S, EMPTY_CAL_ID, pll_shared3_rate_table, 150, 0),
	CLK_PLL(PLL_1052X, PLL_SHARED2, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED2_PLL_LOCK_TIME, PLL_CON0_PLL_SHARED2_ENABLE, PLL_CON0_PLL_SHARED2_STABLE, PLL_CON0_PLL_SHARED2_DIV_P, PLL_CON0_PLL_SHARED2_DIV_M, PLL_CON0_PLL_SHARED2_DIV_S, EMPTY_CAL_ID, pll_shared2_rate_table, 150, 0),
	CLK_PLL(PLL_1051X, PLL_SHARED0, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED0_PLL_LOCK_TIME, PLL_CON0_PLL_SHARED0_ENABLE, PLL_CON0_PLL_SHARED0_STABLE, PLL_CON0_PLL_SHARED0_DIV_P, PLL_CON0_PLL_SHARED0_DIV_M, PLL_CON0_PLL_SHARED0_DIV_S, EMPTY_CAL_ID, pll_shared0_rate_table, 150, 0),
	CLK_PLL(PLL_1050X, PLL_CPUCL0, OSCCLK_CPUCL0, PLL_LOCKTIME_PLL_CPUCL0_PLL_LOCK_TIME, PLL_CON0_PLL_CPUCL0_ENABLE, PLL_CON0_PLL_CPUCL0_STABLE, PLL_CON0_PLL_CPUCL0_DIV_P, PLL_CON0_PLL_CPUCL0_DIV_M, PLL_CON0_PLL_CPUCL0_DIV_S, EMPTY_CAL_ID, pll_cpucl0_rate_table, 150, 0),
	CLK_PLL(PLL_1051X, PLL_CPUCL1, OSCCLK_CPUCL1, PLL_LOCKTIME_PLL_CPUCL1_PLL_LOCK_TIME, PLL_CON0_PLL_CPUCL1_ENABLE, PLL_CON0_PLL_CPUCL1_STABLE, PLL_CON0_PLL_CPUCL1_DIV_P, PLL_CON0_PLL_CPUCL1_DIV_M, PLL_CON0_PLL_CPUCL1_DIV_S, EMPTY_CAL_ID, pll_cpucl1_rate_table, 150, 0),
	CLK_PLL(PLL_1052X, PLL_DPU, OSCCLK_DPU1, PLL_LOCKTIME_PLL_DPU_PLL_LOCK_TIME, PLL_CON0_PLL_DPU_ENABLE, PLL_CON0_PLL_DPU_STABLE, PLL_CON0_PLL_DPU_DIV_P, PLL_CON0_PLL_DPU_DIV_M, PLL_CON0_PLL_DPU_DIV_S, EMPTY_CAL_ID, pll_dpu_rate_table, 150, 0),
	CLK_PLL(PLL_1052X, PLL_G3D, OSCCLK_G3D, PLL_LOCKTIME_PLL_G3D_PLL_LOCK_TIME, PLL_CON0_PLL_G3D_ENABLE, PLL_CON0_PLL_G3D_STABLE, PLL_CON0_PLL_G3D_DIV_P, PLL_CON0_PLL_G3D_DIV_M, PLL_CON0_PLL_G3D_DIV_S, EMPTY_CAL_ID, pll_g3d_rate_table, 150, 0),
	CLK_PLL(PLL_1050X, PLL_MIF, OSCCLK_MIF, PLL_LOCKTIME_PLL_MIF_PLL_LOCK_TIME, PLL_CON0_PLL_MIF_ENABLE, PLL_CON0_PLL_MIF_STABLE, PLL_CON0_PLL_MIF_DIV_P, PLL_CON0_PLL_MIF_DIV_M, PLL_CON0_PLL_MIF_DIV_S, EMPTY_CAL_ID, pll_mif_rate_table, 150, 0),
	CLK_PLL(PLL_1050X, PLL_MIF1, OSCCLK_MIF1, PLL_LOCKTIME_PLL_MIF1_PLL_LOCK_TIME, PLL_CON0_PLL_MIF1_ENABLE, PLL_CON0_PLL_MIF1_STABLE, PLL_CON0_PLL_MIF1_DIV_P, PLL_CON0_PLL_MIF1_DIV_M, PLL_CON0_PLL_MIF1_DIV_S, EMPTY_CAL_ID, pll_mif1_rate_table, 150, 0),
	CLK_PLL(PLL_1050X, PLL_MIF2, OSCCLK_MIF2, PLL_LOCKTIME_PLL_MIF2_PLL_LOCK_TIME, PLL_CON0_PLL_MIF2_ENABLE, PLL_CON0_PLL_MIF2_STABLE, PLL_CON0_PLL_MIF2_DIV_P, PLL_CON0_PLL_MIF2_DIV_M, PLL_CON0_PLL_MIF2_DIV_S, EMPTY_CAL_ID, pll_mif2_rate_table, 150, 0),
	CLK_PLL(PLL_1050X, PLL_MIF3, OSCCLK_MIF3, PLL_LOCKTIME_PLL_MIF3_PLL_LOCK_TIME, PLL_CON0_PLL_MIF3_ENABLE, PLL_CON0_PLL_MIF3_STABLE, PLL_CON0_PLL_MIF3_DIV_P, PLL_CON0_PLL_MIF3_DIV_M, PLL_CON0_PLL_MIF3_DIV_S, EMPTY_CAL_ID, pll_mif3_rate_table, 150, 0),
};

/*====================The section of MUXs' parents===================*/
enum clk_id cmucal_mux_clk_abox_uaif3_parents[] = {
	DIV_CLK_ABOX_UAIF3,
	CLKIO_ABOX_UAIF3,
};
enum clk_id cmucal_mux_clk_abox_uaif2_parents[] = {
	DIV_CLK_ABOX_UAIF2,
	CLKIO_ABOX_UAIF2,
};
enum clk_id cmucal_mux_clk_abox_uaif1_parents[] = {
	DIV_CLK_ABOX_UAIF1,
	CLKIO_ABOX_UAIF1,
};
enum clk_id cmucal_mux_clk_abox_uaif0_parents[] = {
	DIV_CLK_ABOX_UAIF0,
	CLKIO_ABOX_UAIF0,
};
enum clk_id cmucal_mux_clk_abox_cpu_parents[] = {
	DIV_CLK_ABOX_PLL,
	MUX_CLKCMU_ABOX_CPUABOX_USER,
};
enum clk_id cmucal_mux_clk_abox_uaif4_parents[] = {
	DIV_CLK_ABOX_UAIF4,
	CLKIO_ABOX_UAIF4,
};
enum clk_id cmucal_mux_clkcmu_dpu_bus_parents[] = {
	DIV_PLL_SHARED0_DIV2,
	PLL_SHARED3,
	PLL_SHARED4,
	DIV_PLL_SHARED1_DIV4,
	DIV_PLL_SHARED2_DIV2,
	OSCCLK_CMU,
	OSCCLK_CMU,
	OSCCLK_CMU,
};
enum clk_id cmucal_mux_clkcmu_bus1_bus_parents[] = {
	PLL_SHARED4,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED1_DIV4,
	DIV_PLL_SHARED2_DIV2,
};
enum clk_id cmucal_mux_clkcmu_mfc_bus_parents[] = {
	PLL_SHARED4,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED1_DIV4,
	DIV_PLL_SHARED2_DIV2,
};
enum clk_id cmucal_mux_clkcmu_fsys0_usbdrd30_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_fsys0_ufs_embd_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_vpu_bus_parents[] = {
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED1_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_peric0_uart_dbg_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_peric0_usi00_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_peric0_usi02_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_peric0_usi03_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_peric1_usi04_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_peric1_usi05_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_peric1_uart_bt_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_peric1_usi06_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_peric1_usi07_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_peric1_usi08_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_peric1_usi09_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_peric1_usi10_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_peric1_usi11_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_peric1_usi12_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_peric1_usi13_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_busc_bus_parents[] = {
	PLL_SHARED4,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED1_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_CP2AP_MIF_CLK_DIV2,
	OSCCLK_CMU,
	OSCCLK_CMU,
	OSCCLK_CMU,
};
enum clk_id cmucal_mux_clkcmu_g2d_g2d_parents[] = {
	PLL_SHARED4,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED1_DIV4,
	DIV_PLL_SHARED2_DIV2,
};
enum clk_id cmucal_mux_clkcmu_peric0_usi01_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_fsys1_mmc_card_parents[] = {
	OSCCLK_CMU,
	PLL_SHARED2,
	PLL_SHARED4,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED1_DIV4,
	OSCCLK_CMU,
	OSCCLK_CMU,
	OSCCLK_CMU,
};
enum clk_id cmucal_mux_clkcmu_dsp_bus_parents[] = {
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED1_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_fsys0_mmc_embd_parents[] = {
	OSCCLK_CMU,
	PLL_SHARED2,
	PLL_SHARED4,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED1_DIV4,
	OSCCLK_CMU,
	OSCCLK_CMU,
	OSCCLK_CMU,
};
enum clk_id cmucal_mux_clkcmu_cpucl0_switch_parents[] = {
	DIV_PLL_SHARED0_DIV2,
	DIV_PLL_SHARED1_DIV2,
	PLL_SHARED2,
	PLL_SHARED4,
};
enum clk_id cmucal_mux_clkcmu_core_bus_parents[] = {
	DIV_PLL_SHARED0_DIV2,
	DIV_PLL_SHARED1_DIV2,
	PLL_SHARED2,
	PLL_SHARED4,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED1_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_CP2AP_MIF_CLK_DIV2,
};
enum clk_id cmucal_mux_clkcmu_mif_switch_parents[] = {
	PLL_SHARED0,
	PLL_SHARED1,
	DIV_PLL_SHARED0_DIV2,
	DIV_PLL_SHARED1_DIV2,
	PLL_SHARED2,
	MUX_CP2AP_MIF_CLK_USER,
	OSCCLK_CMU,
	OSCCLK_CMU,
};
enum clk_id cmucal_mux_clkcmu_cam_bus_parents[] = {
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED1_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_cam_tpu0_parents[] = {
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED1_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_cam_tpu1_parents[] = {
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED1_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_isplp_bus_parents[] = {
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED1_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_isphq_bus_parents[] = {
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED1_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_abox_cpuabox_parents[] = {
	DIV_PLL_SHARED0_DIV2,
	DIV_PLL_SHARED1_DIV2,
	PLL_SHARED2,
	PLL_SHARED4,
};
enum clk_id cmucal_mux_clkcmu_g2d_jpeg_parents[] = {
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED1_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_hpm_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED1_DIV4,
	DIV_PLL_SHARED2_DIV2,
};
enum clk_id cmucal_mux_clkcmu_dbg_bus_parents[] = {
	PLL_SHARED2,
	PLL_SHARED4,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED1_DIV4,
};
enum clk_id cmucal_mux_clkcmu_peric1_spi_cam0_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_peric1_spi_cam1_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_droopdetector_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV2,
	DIV_PLL_SHARED1_DIV2,
	PLL_SHARED2,
};
enum clk_id cmucal_mux_clkcmu_fsys0_bus_parents[] = {
	DIV_PLL_SHARED1_DIV2,
	PLL_SHARED2,
	PLL_SHARED4,
	DIV_PLL_SHARED0_DIV4,
};
enum clk_id cmucal_mux_clkcmu_cis_clk0_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED2_DIV2,
};
enum clk_id cmucal_mux_clkcmu_cis_clk1_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED2_DIV2,
};
enum clk_id cmucal_mux_clkcmu_cis_clk2_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED2_DIV2,
};
enum clk_id cmucal_mux_clkcmu_cis_clk3_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED2_DIV2,
};
enum clk_id cmucal_mux_clkcmu_iva_bus_parents[] = {
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED1_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_fsys1_ufs_card_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_cmu_cmuref_parents[] = {
	OSCCLK_CMU,
	DIV_CLK_CMU_CMUREF,
};
enum clk_id cmucal_mux_clkcmu_busc_busphsi2c_parents[] = {
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_CP2AP_MIF_CLK_DIV2,
	OSCCLK_CMU,
};
enum clk_id cmucal_mux_clkcmu_cam_vra_parents[] = {
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED1_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_peric0_bus_parents[] = {
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
};
enum clk_id cmucal_mux_clkcmu_peric1_bus_parents[] = {
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
};
enum clk_id cmucal_mux_clkcmu_peris_bus_parents[] = {
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
};
enum clk_id cmucal_mux_clkcmu_dcam_bus_parents[] = {
	PLL_SHARED4,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED1_DIV4,
	DIV_PLL_SHARED2_DIV2,
};
enum clk_id cmucal_mux_clkcmu_imem_bus_parents[] = {
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED1_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_fsys0_dpgtc_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_fsys1_pcie_parents[] = {
	OSCCLK_CMU,
	PLL_SHARED2,
};
enum clk_id cmucal_mux_clkcmu_srdz_bus_parents[] = {
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED1_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_srdz_imgd_parents[] = {
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED1_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_dcam_imgd_parents[] = {
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED1_DIV4,
	DIV_PLL_SHARED2_DIV2,
	DIV_PLL_SHARED4_DIV2,
};
enum clk_id cmucal_mux_clkcmu_peric1_speedy2_parents[] = {
	OSCCLK_CMU,
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
	OSCCLK_CMU,
};
enum clk_id cmucal_mux_clkcmu_apm_bus_parents[] = {
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
};
enum clk_id cmucal_mux_clkcmu_fsys1_bus_parents[] = {
	PLL_SHARED2,
	DIV_PLL_SHARED0_DIV4,
};
enum clk_id cmucal_mux_clk_cmu_cmuref_parents[] = {
	DIV_PLL_SHARED0_DIV4,
	DIV_PLL_SHARED2_DIV2,
};
enum clk_id cmucal_mux_clkcmu_cpucl1_switch_parents[] = {
	DIV_PLL_SHARED0_DIV2,
	DIV_PLL_SHARED1_DIV2,
	PLL_SHARED2,
	PLL_SHARED4,
};
enum clk_id cmucal_mux_clk_cpucl0_pll_parents[] = {
	PLL_CPUCL0,
	MUX_CLKCMU_CPUCL0_SWITCH_USER,
};
enum clk_id cmucal_mux_clk_cpucl1_pll_parents[] = {
	PLL_CPUCL1,
	MUX_CLKCMU_CPUCL1_SWITCH_USER,
};
enum clk_id cmucal_mux_clk_g3d_busd_parents[] = {
	PLL_G3D,
	MUX_CLKCMU_G3D_SWITCH_USER,
};
enum clk_id cmucal_clkmux_mif_ddrphy2x_parents[] = {
	PLL_MIF,
	CLKCMU_MIF_SWITCH,
};
enum clk_id cmucal_mux_mif_cmuref_parents[] = {
	OSCCLK_MIF,
	DIV_CLK_MIF_BUSP,
};
enum clk_id cmucal_mux_mif1_cmuref_parents[] = {
	OSCCLK_MIF1,
	DIV_CLK_MIF1_BUSP,
};
enum clk_id cmucal_clkmux_mif1_ddrphy2x_parents[] = {
	PLL_MIF1,
	CLKCMU_MIF_SWITCH,
};
enum clk_id cmucal_mux_mif2_cmuref_parents[] = {
	OSCCLK_MIF2,
	DIV_CLK_MIF2_BUSP,
};
enum clk_id cmucal_clkmux_mif2_ddrphy2x_parents[] = {
	PLL_MIF2,
	CLKCMU_MIF_SWITCH,
};
enum clk_id cmucal_mux_mif3_cmuref_parents[] = {
	OSCCLK_MIF3,
	DIV_CLK_MIF3_BUSP,
};
enum clk_id cmucal_clkmux_mif3_ddrphy2x_parents[] = {
	PLL_MIF3,
	CLKCMU_MIF_SWITCH,
};
enum clk_id cmucal_mux_clk_peris_gic_parents[] = {
	MUX_CLKCMU_PERIS_BUS_USER,
	OSCCLK_PERIS,
};
enum clk_id cmucal_mux_clk_vts_cmuref_parents[] = {
	OSCCLK_VTS,
	DIV_CLK_VTS_CMUREF,
};
enum clk_id cmucal_mux_clkcmu_abox_cpuabox_user_parents[] = {
	OSCCLK_ABOX,
	CLKCMU_ABOX_CPUABOX,
};
enum clk_id cmucal_mux_clkcmu_apm_bus_user_parents[] = {
	OSCCLK_APM,
	CLKCMU_APM_BUS,
};
enum clk_id cmucal_mux_clkcmu_bus1_bus_user_parents[] = {
	OSCCLK_BUS1,
	CLKCMU_BUS1_BUS,
};
enum clk_id cmucal_mux_clkcmu_busc_bus_user_parents[] = {
	OSCCLK_BUSC,
	CLKCMU_BUSC_BUS,
};
enum clk_id cmucal_mux_clkcmu_busc_busphsi2c_user_parents[] = {
	OSCCLK_BUSC,
	CLKCMU_BUSC_BUSPHSI2C,
};
enum clk_id cmucal_mux_clkcmu_cam_bus_user_parents[] = {
	OSCCLK_CAM,
	CLKCMU_CAM_BUS,
};
enum clk_id cmucal_mux_clkcmu_cam_tpu0_user_parents[] = {
	OSCCLK_CAM,
	CLKCMU_CAM_TPU0,
};
enum clk_id cmucal_mux_clkcmu_cam_vra_user_parents[] = {
	OSCCLK_CAM,
	CLKCMU_CAM_VRA,
};
enum clk_id cmucal_mux_clkcmu_cam_tpu1_user_parents[] = {
	OSCCLK_CAM,
	CLKCMU_CAM_TPU1,
};
enum clk_id cmucal_mux_cp2ap_mif_clk_user_parents[] = {
	OSCCLK_CMU,
	CP2AP_MIF_CLK,
};
enum clk_id cmucal_mux_clkcmu_core_bus_user_parents[] = {
	OSCCLK_CORE,
	CLKCMU_CORE_BUS,
};
enum clk_id cmucal_mux_clkcmu_cpucl0_switch_user_parents[] = {
	OSCCLK_CPUCL0,
	CLKCMU_CPUCL0_SWITCH,
};
enum clk_id cmucal_mux_clkcmu_cpucl1_switch_user_parents[] = {
	OSCCLK_CPUCL1,
	CLKCMU_CPUCL1_SWITCH,
};
enum clk_id cmucal_mux_clkcmu_dbg_bus_user_parents[] = {
	OSCCLK_DBG,
	CLKCMU_DBG_BUS,
};
enum clk_id cmucal_mux_clkcmu_dcam_bus_user_parents[] = {
	OSCCLK_DCAM,
	CLKCMU_DCAM_BUS,
};
enum clk_id cmucal_mux_clkcmu_dcam_imgd_user_parents[] = {
	OSCCLK_DCAM,
	CLKCMU_DCAM_IMGD,
};
enum clk_id cmucal_mux_clkcmu_dpu_bus_user_parents[] = {
	OSCCLK_DPU0,
	CLKCMU_DPU_BUS,
};
enum clk_id cmucal_mux_clkcmu_dpu1_busd_user_parents[] = {
	OSCCLK_DPU1,
	CLKCMU_DPU1_BUSD,
};
enum clk_id cmucal_mux_clkcmu_dpu1_busp_user_parents[] = {
	OSCCLK_DPU1,
	CLKCMU_DPU1_BUSP,
};
enum clk_id cmucal_mux_clkcmu_dsp_bus_user_parents[] = {
	OSCCLK_DSP,
	CLKCMU_DSP_BUS,
};
enum clk_id cmucal_mux_clkcmu_fsys0_ufs_embd_user_parents[] = {
	OSCCLK_FSYS0,
	CLKCMU_FSYS0_UFS_EMBD,
};
enum clk_id cmucal_mux_clkcmu_fsys0_mmc_embd_user_parents[] = {
	OSCCLK_FSYS0,
	CLKCMU_FSYS0_MMC_EMBD,
};
enum clk_id cmucal_mux_clkcmu_fsys0_bus_user_parents[] = {
	OSCCLK_FSYS0,
	CLKCMU_FSYS0_BUS,
};
enum clk_id cmucal_mux_clkcmu_fsys0_usbdrd30_user_parents[] = {
	OSCCLK_FSYS0,
	CLKCMU_FSYS0_USBDRD30,
};
enum clk_id cmucal_mux_clkcmu_fsys0_dpgtc_user_parents[] = {
	OSCCLK_FSYS0,
	CLKCMU_FSYS0_DPGTC,
};
enum clk_id cmucal_mux_clkcmu_fsys1_bus_user_parents[] = {
	OSCCLK_FSYS1,
	CLKCMU_FSYS1_BUS,
};
enum clk_id cmucal_mux_clkcmu_fsys1_mmc_card_user_parents[] = {
	OSCCLK_FSYS1,
	CLKCMU_FSYS1_MMC_CARD,
};
enum clk_id cmucal_mux_clkcmu_fsys1_pcie_user_parents[] = {
	OSCCLK_FSYS1,
	CLKCMU_FSYS1_PCIE,
};
enum clk_id cmucal_mux_clkcmu_fsys1_ufs_card_user_parents[] = {
	OSCCLK_FSYS1,
	CLKCMU_FSYS1_UFS_CARD,
};
enum clk_id cmucal_mux_clkcmu_g2d_g2d_user_parents[] = {
	OSCCLK_G2D,
	CLKCMU_G2D_G2D,
};
enum clk_id cmucal_mux_clkcmu_g2d_jpeg_user_parents[] = {
	OSCCLK_G2D,
	CLKCMU_G2D_JPEG,
};
enum clk_id cmucal_mux_clkcmu_g3d_switch_user_parents[] = {
	OSCCLK_G3D,
	CLKCMU_G3D_SWITCH,
};
enum clk_id cmucal_mux_clkcmu_imem_bus_user_parents[] = {
	OSCCLK_IMEM,
	CLKCMU_IMEM_BUS,
};
enum clk_id cmucal_mux_clkcmu_isphq_bus_user_parents[] = {
	OSCCLK_ISPHQ,
	CLKCMU_ISPHQ_BUS,
};
enum clk_id cmucal_mux_clkcmu_isplp_bus_user_parents[] = {
	OSCCLK_ISPLP,
	CLKCMU_ISPLP_BUS,
};
enum clk_id cmucal_mux_clkcmu_iva_bus_user_parents[] = {
	OSCCLK_IVA,
	CLKCMU_IVA_BUS,
};
enum clk_id cmucal_mux_clkcmu_mfc_bus_user_parents[] = {
	OSCCLK_MFC,
	CLKCMU_MFC_BUS,
};
enum clk_id cmucal_mux_clkcmu_peric0_bus_user_parents[] = {
	OSCCLK_PERIC0,
	CLKCMU_PERIC0_BUS,
};
enum clk_id cmucal_mux_clkcmu_peric0_uart_dbg_user_parents[] = {
	OSCCLK_PERIC0,
	CLKCMU_PERIC0_UART_DBG,
};
enum clk_id cmucal_mux_clkcmu_peric0_usi00_user_parents[] = {
	OSCCLK_PERIC0,
	CLKCMU_PERIC0_USI00,
};
enum clk_id cmucal_mux_clkcmu_peric0_usi01_user_parents[] = {
	OSCCLK_PERIC0,
	CLKCMU_PERIC0_USI01,
};
enum clk_id cmucal_mux_clkcmu_peric0_usi02_user_parents[] = {
	OSCCLK_PERIC0,
	CLKCMU_PERIC0_USI02,
};
enum clk_id cmucal_mux_clkcmu_peric0_usi03_user_parents[] = {
	OSCCLK_PERIC0,
	CLKCMU_PERIC0_USI03,
};
enum clk_id cmucal_mux_clkcmu_peric1_uart_bt_user_parents[] = {
	OSCCLK_PERIC1,
	CLKCMU_PERIC1_UART_BT,
};
enum clk_id cmucal_mux_clkcmu_peric1_usi05_user_parents[] = {
	OSCCLK_PERIC1,
	CLKCMU_PERIC1_USI05,
};
enum clk_id cmucal_mux_clkcmu_peric1_usi06_user_parents[] = {
	OSCCLK_PERIC1,
	CLKCMU_PERIC1_USI06,
};
enum clk_id cmucal_mux_clkcmu_peric1_usi07_user_parents[] = {
	OSCCLK_PERIC1,
	CLKCMU_PERIC1_USI07,
};
enum clk_id cmucal_mux_clkcmu_peric1_usi08_user_parents[] = {
	OSCCLK_PERIC1,
	CLKCMU_PERIC1_USI08,
};
enum clk_id cmucal_mux_clkcmu_peric1_usi09_user_parents[] = {
	OSCCLK_PERIC1,
	CLKCMU_PERIC1_USI09,
};
enum clk_id cmucal_mux_clkcmu_peric1_usi10_user_parents[] = {
	OSCCLK_PERIC1,
	CLKCMU_PERIC1_USI10,
};
enum clk_id cmucal_mux_clkcmu_peric1_usi11_user_parents[] = {
	OSCCLK_PERIC1,
	CLKCMU_PERIC1_USI11,
};
enum clk_id cmucal_mux_clkcmu_peric1_usi12_user_parents[] = {
	OSCCLK_PERIC1,
	CLKCMU_PERIC1_USI12,
};
enum clk_id cmucal_mux_clkcmu_peric1_usi13_user_parents[] = {
	OSCCLK_PERIC1,
	CLKCMU_PERIC1_USI13,
};
enum clk_id cmucal_mux_clkcmu_peric1_bus_user_parents[] = {
	OSCCLK_PERIC1,
	CLKCMU_PERIC1_BUS,
};
enum clk_id cmucal_mux_clkcmu_peric1_usi04_user_parents[] = {
	OSCCLK_PERIC1,
	CLKCMU_PERIC1_USI04,
};
enum clk_id cmucal_mux_clkcmu_peric1_spi_cam0_user_parents[] = {
	OSCCLK_PERIC1,
	CLKCMU_PERIC1_SPI_CAM0,
};
enum clk_id cmucal_mux_clkcmu_peric1_spi_cam1_user_parents[] = {
	OSCCLK_PERIC1,
	CLKCMU_PERIC1_SPI_CAM1,
};
enum clk_id cmucal_mux_clkcmu_peric1_speedy2_user_parents[] = {
	OSCCLK_PERIC1,
	CLKCMU_PERIC1_SPEEDY2,
};
enum clk_id cmucal_mux_clkcmu_peris_bus_user_parents[] = {
	OSCCLK_PERIS,
	CLKCMU_PERIS_BUS,
};
enum clk_id cmucal_mux_clkcmu_srdz_imgd_user_parents[] = {
	OSCCLK_SRDZ,
	CLKCMU_SRDZ_IMGD,
};
enum clk_id cmucal_mux_clkcmu_srdz_bus_user_parents[] = {
	OSCCLK_SRDZ,
	CLKCMU_SRDZ_BUS,
};
enum clk_id cmucal_mux_clkcmu_vpu_bus_user_parents[] = {
	OSCCLK_VPU,
	CLKCMU_VPU_BUS,
};


/*====================The section of MUXs===================*/
unsigned int cmucal_mux_size = 220;


struct cmucal_mux cmucal_mux_list[] = {
	CLK_MUX(MUX_CLK_ABOX_UAIF3, cmucal_mux_clk_abox_uaif3_parents, CLK_CON_MUX_MUX_CLK_ABOX_UAIF3_SELECT, CLK_CON_MUX_MUX_CLK_ABOX_UAIF3_BUSY, CLK_CON_MUX_MUX_CLK_ABOX_UAIF3_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_ABOX_UAIF2, cmucal_mux_clk_abox_uaif2_parents, CLK_CON_MUX_MUX_CLK_ABOX_UAIF2_SELECT, CLK_CON_MUX_MUX_CLK_ABOX_UAIF2_BUSY, CLK_CON_MUX_MUX_CLK_ABOX_UAIF2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_ABOX_UAIF1, cmucal_mux_clk_abox_uaif1_parents, CLK_CON_MUX_MUX_CLK_ABOX_UAIF1_SELECT, CLK_CON_MUX_MUX_CLK_ABOX_UAIF1_BUSY, CLK_CON_MUX_MUX_CLK_ABOX_UAIF1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_ABOX_UAIF0, cmucal_mux_clk_abox_uaif0_parents, CLK_CON_MUX_MUX_CLK_ABOX_UAIF0_SELECT, CLK_CON_MUX_MUX_CLK_ABOX_UAIF0_BUSY, CLK_CON_MUX_MUX_CLK_ABOX_UAIF0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_ABOX_CPU, cmucal_mux_clk_abox_cpu_parents, CLK_CON_MUX_MUX_CLK_ABOX_CPU_SELECT, CLK_CON_MUX_MUX_CLK_ABOX_CPU_BUSY, CLK_CON_MUX_MUX_CLK_ABOX_CPU_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_ABOX_UAIF4, cmucal_mux_clk_abox_uaif4_parents, CLK_CON_MUX_MUX_CLK_ABOX_UAIF4_SELECT, CLK_CON_MUX_MUX_CLK_ABOX_UAIF4_BUSY, CLK_CON_MUX_MUX_CLK_ABOX_UAIF4_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_DPU_BUS, cmucal_mux_clkcmu_dpu_bus_parents, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_BUS1_BUS, cmucal_mux_clkcmu_bus1_bus_parents, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_MFC_BUS, cmucal_mux_clkcmu_mfc_bus_parents, CLK_CON_MUX_MUX_CLKCMU_MFC_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_MFC_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_MFC_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_FSYS0_USBDRD30, cmucal_mux_clkcmu_fsys0_usbdrd30_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDRD30_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDRD30_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDRD30_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_FSYS0_UFS_EMBD, cmucal_mux_clkcmu_fsys0_ufs_embd_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_VPU_BUS, cmucal_mux_clkcmu_vpu_bus_parents, CLK_CON_MUX_MUX_CLKCMU_VPU_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_VPU_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_VPU_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC0_UART_DBG, cmucal_mux_clkcmu_peric0_uart_dbg_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC0_UART_DBG_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC0_UART_DBG_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC0_UART_DBG_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC0_USI00, cmucal_mux_clkcmu_peric0_usi00_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI00_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI00_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI00_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC0_USI02, cmucal_mux_clkcmu_peric0_usi02_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI02_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI02_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI02_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC0_USI03, cmucal_mux_clkcmu_peric0_usi03_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI03_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI03_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI03_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_USI04, cmucal_mux_clkcmu_peric1_usi04_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI04_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI04_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI04_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_USI05, cmucal_mux_clkcmu_peric1_usi05_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI05_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI05_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI05_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_UART_BT, cmucal_mux_clkcmu_peric1_uart_bt_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_UART_BT_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_UART_BT_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_USI06, cmucal_mux_clkcmu_peric1_usi06_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI06_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI06_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI06_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_USI07, cmucal_mux_clkcmu_peric1_usi07_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI07_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI07_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI07_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_USI08, cmucal_mux_clkcmu_peric1_usi08_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI08_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI08_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI08_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_USI09, cmucal_mux_clkcmu_peric1_usi09_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI09_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI09_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI09_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_USI10, cmucal_mux_clkcmu_peric1_usi10_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI10_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI10_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI10_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_USI11, cmucal_mux_clkcmu_peric1_usi11_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI11_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI11_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI11_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_USI12, cmucal_mux_clkcmu_peric1_usi12_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI12_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI12_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI12_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_USI13, cmucal_mux_clkcmu_peric1_usi13_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI13_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI13_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI13_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_BUSC_BUS, cmucal_mux_clkcmu_busc_bus_parents, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_G2D_G2D, cmucal_mux_clkcmu_g2d_g2d_parents, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_SELECT, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_BUSY, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC0_USI01, cmucal_mux_clkcmu_peric0_usi01_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI01_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI01_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI01_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_FSYS1_MMC_CARD, cmucal_mux_clkcmu_fsys1_mmc_card_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_DSP_BUS, cmucal_mux_clkcmu_dsp_bus_parents, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_FSYS0_MMC_EMBD, cmucal_mux_clkcmu_fsys0_mmc_embd_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS0_MMC_EMBD_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS0_MMC_EMBD_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS0_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CPUCL0_SWITCH, cmucal_mux_clkcmu_cpucl0_switch_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CORE_BUS, cmucal_mux_clkcmu_core_bus_parents, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_MIF_SWITCH, cmucal_mux_clkcmu_mif_switch_parents, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CAM_BUS, cmucal_mux_clkcmu_cam_bus_parents, CLK_CON_MUX_MUX_CLKCMU_CAM_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CAM_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CAM_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CAM_TPU0, cmucal_mux_clkcmu_cam_tpu0_parents, CLK_CON_MUX_MUX_CLKCMU_CAM_TPU0_SELECT, CLK_CON_MUX_MUX_CLKCMU_CAM_TPU0_BUSY, CLK_CON_MUX_MUX_CLKCMU_CAM_TPU0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CAM_TPU1, cmucal_mux_clkcmu_cam_tpu1_parents, CLK_CON_MUX_MUX_CLKCMU_CAM_TPU1_SELECT, CLK_CON_MUX_MUX_CLKCMU_CAM_TPU1_BUSY, CLK_CON_MUX_MUX_CLKCMU_CAM_TPU1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_ISPLP_BUS, cmucal_mux_clkcmu_isplp_bus_parents, CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_ISPHQ_BUS, cmucal_mux_clkcmu_isphq_bus_parents, CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_ABOX_CPUABOX, cmucal_mux_clkcmu_abox_cpuabox_parents, CLK_CON_MUX_MUX_CLKCMU_ABOX_CPUABOX_SELECT, CLK_CON_MUX_MUX_CLKCMU_ABOX_CPUABOX_BUSY, CLK_CON_MUX_MUX_CLKCMU_ABOX_CPUABOX_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_G2D_JPEG, cmucal_mux_clkcmu_g2d_jpeg_parents, CLK_CON_MUX_MUX_CLKCMU_G2D_JPEG_SELECT, CLK_CON_MUX_MUX_CLKCMU_G2D_JPEG_BUSY, CLK_CON_MUX_MUX_CLKCMU_G2D_JPEG_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_HPM, cmucal_mux_clkcmu_hpm_parents, CLK_CON_MUX_MUX_CLKCMU_HPM_SELECT, CLK_CON_MUX_MUX_CLKCMU_HPM_BUSY, CLK_CON_MUX_MUX_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_DBG_BUS, cmucal_mux_clkcmu_dbg_bus_parents, CLK_CON_MUX_MUX_CLKCMU_DBG_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_DBG_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_SPI_CAM0, cmucal_mux_clkcmu_peric1_spi_cam0_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM0_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM0_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_SPI_CAM1, cmucal_mux_clkcmu_peric1_spi_cam1_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM1_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM1_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_DROOPDETECTOR, cmucal_mux_clkcmu_droopdetector_parents, CLK_CON_MUX_MUX_CLKCMU_DROOPDETECTOR_SELECT, CLK_CON_MUX_MUX_CLKCMU_DROOPDETECTOR_BUSY, CLK_CON_MUX_MUX_CLKCMU_DROOPDETECTOR_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_FSYS0_BUS, cmucal_mux_clkcmu_fsys0_bus_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CIS_CLK0, cmucal_mux_clkcmu_cis_clk0_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CIS_CLK1, cmucal_mux_clkcmu_cis_clk1_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CIS_CLK2, cmucal_mux_clkcmu_cis_clk2_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CIS_CLK3, cmucal_mux_clkcmu_cis_clk3_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_IVA_BUS, cmucal_mux_clkcmu_iva_bus_parents, CLK_CON_MUX_MUX_CLKCMU_IVA_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_IVA_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_IVA_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_FSYS1_UFS_CARD, cmucal_mux_clkcmu_fsys1_ufs_card_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CMU_CMUREF, cmucal_mux_cmu_cmuref_parents, CLK_CON_MUX_MUX_CMU_CMUREF_SELECT, CLK_CON_MUX_MUX_CMU_CMUREF_BUSY, CLK_CON_MUX_MUX_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_BUSC_BUSPHSI2C, cmucal_mux_clkcmu_busc_busphsi2c_parents, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUSPHSI2C_SELECT, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUSPHSI2C_BUSY, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUSPHSI2C_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CAM_VRA, cmucal_mux_clkcmu_cam_vra_parents, CLK_CON_MUX_MUX_CLKCMU_CAM_VRA_SELECT, CLK_CON_MUX_MUX_CLKCMU_CAM_VRA_BUSY, CLK_CON_MUX_MUX_CLKCMU_CAM_VRA_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC0_BUS, cmucal_mux_clkcmu_peric0_bus_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_BUS, cmucal_mux_clkcmu_peric1_bus_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIS_BUS, cmucal_mux_clkcmu_peris_bus_parents, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_DCAM_BUS, cmucal_mux_clkcmu_dcam_bus_parents, CLK_CON_MUX_MUX_CLKCMU_DCAM_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_DCAM_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_DCAM_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_IMEM_BUS, cmucal_mux_clkcmu_imem_bus_parents, CLK_CON_MUX_MUX_CLKCMU_IMEM_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_IMEM_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_IMEM_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_FSYS0_DPGTC, cmucal_mux_clkcmu_fsys0_dpgtc_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_FSYS1_PCIE, cmucal_mux_clkcmu_fsys1_pcie_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_SRDZ_BUS, cmucal_mux_clkcmu_srdz_bus_parents, CLK_CON_MUX_MUX_CLKCMU_SRDZ_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_SRDZ_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_SRDZ_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_SRDZ_IMGD, cmucal_mux_clkcmu_srdz_imgd_parents, CLK_CON_MUX_MUX_CLKCMU_SRDZ_IMGD_SELECT, CLK_CON_MUX_MUX_CLKCMU_SRDZ_IMGD_BUSY, CLK_CON_MUX_MUX_CLKCMU_SRDZ_IMGD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_DCAM_IMGD, cmucal_mux_clkcmu_dcam_imgd_parents, CLK_CON_MUX_MUX_CLKCMU_DCAM_IMGD_SELECT, CLK_CON_MUX_MUX_CLKCMU_DCAM_IMGD_BUSY, CLK_CON_MUX_MUX_CLKCMU_DCAM_IMGD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_SPEEDY2, cmucal_mux_clkcmu_peric1_speedy2_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPEEDY2_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPEEDY2_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPEEDY2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_APM_BUS, cmucal_mux_clkcmu_apm_bus_parents, CLK_CON_MUX_MUX_CLKCMU_APM_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_APM_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_FSYS1_BUS, cmucal_mux_clkcmu_fsys1_bus_parents, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_CMU_CMUREF, cmucal_mux_clk_cmu_cmuref_parents, CLK_CON_MUX_MUX_CLK_CMU_CMUREF_SELECT, CLK_CON_MUX_MUX_CLK_CMU_CMUREF_BUSY, CLK_CON_MUX_MUX_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CPUCL1_SWITCH, cmucal_mux_clkcmu_cpucl1_switch_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_CPUCL0_PLL, cmucal_mux_clk_cpucl0_pll_parents, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_CPUCL1_PLL, cmucal_mux_clk_cpucl1_pll_parents, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_G3D_BUSD, cmucal_mux_clk_g3d_busd_parents, CLK_CON_MUX_MUX_CLK_G3D_BUSD_SELECT, CLK_CON_MUX_MUX_CLK_G3D_BUSD_BUSY, CLK_CON_MUX_MUX_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(CLKMUX_MIF_DDRPHY2X, cmucal_clkmux_mif_ddrphy2x_parents, CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X_SELECT, CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X_BUSY, CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_MIF_CMUREF, cmucal_mux_mif_cmuref_parents, CLK_CON_MUX_MUX_MIF_CMUREF_SELECT, CLK_CON_MUX_MUX_MIF_CMUREF_BUSY, CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_MIF1_CMUREF, cmucal_mux_mif1_cmuref_parents, CLK_CON_MUX_MUX_MIF1_CMUREF_SELECT, CLK_CON_MUX_MUX_MIF1_CMUREF_BUSY, CLK_CON_MUX_MUX_MIF1_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(CLKMUX_MIF1_DDRPHY2X, cmucal_clkmux_mif1_ddrphy2x_parents, CLK_CON_MUX_CLKMUX_MIF1_DDRPHY2X_SELECT, CLK_CON_MUX_CLKMUX_MIF1_DDRPHY2X_BUSY, CLK_CON_MUX_CLKMUX_MIF1_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_MIF2_CMUREF, cmucal_mux_mif2_cmuref_parents, CLK_CON_MUX_MUX_MIF2_CMUREF_SELECT, CLK_CON_MUX_MUX_MIF2_CMUREF_BUSY, CLK_CON_MUX_MUX_MIF2_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(CLKMUX_MIF2_DDRPHY2X, cmucal_clkmux_mif2_ddrphy2x_parents, CLK_CON_MUX_CLKMUX_MIF2_DDRPHY2X_SELECT, CLK_CON_MUX_CLKMUX_MIF2_DDRPHY2X_BUSY, CLK_CON_MUX_CLKMUX_MIF2_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_MIF3_CMUREF, cmucal_mux_mif3_cmuref_parents, CLK_CON_MUX_MUX_MIF3_CMUREF_SELECT, CLK_CON_MUX_MUX_MIF3_CMUREF_BUSY, CLK_CON_MUX_MUX_MIF3_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(CLKMUX_MIF3_DDRPHY2X, cmucal_clkmux_mif3_ddrphy2x_parents, CLK_CON_MUX_CLKMUX_MIF3_DDRPHY2X_SELECT, CLK_CON_MUX_CLKMUX_MIF3_DDRPHY2X_BUSY, CLK_CON_MUX_CLKMUX_MIF3_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_PERIS_GIC, cmucal_mux_clk_peris_gic_parents, CLK_CON_MUX_MUX_CLK_PERIS_GIC_SELECT, CLK_CON_MUX_MUX_CLK_PERIS_GIC_BUSY, CLK_CON_MUX_MUX_CLK_PERIS_GIC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_VTS_CMUREF, cmucal_mux_clk_vts_cmuref_parents, CLK_CON_MUX_MUX_CLK_VTS_CMUREF_SELECT, CLK_CON_MUX_MUX_CLK_VTS_CMUREF_BUSY, CLK_CON_MUX_MUX_CLK_VTS_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(ABOX_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_ABOX_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_ABOX_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_ABOX_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(ABOX_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_ABOX_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_ABOX_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_ABOX_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(APM_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_APM_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_APM_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_APM_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(APM_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_APM_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_APM_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_APM_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(BUS1_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_BUS1_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_BUS1_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_BUS1_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(BUS1_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_BUS1_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_BUS1_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_BUS1_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(BUSC_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_BUSC_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_BUSC_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_BUSC_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(BUSC_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_BUSC_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_BUSC_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_BUSC_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(CAM_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_CAM_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_CAM_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_CAM_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(CAM_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_CAM_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_CAM_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_CAM_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(CMU_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_CMU_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_CMU_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_CMU_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(CMU_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_CMU_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_CMU_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_CMU_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(CORE_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_CORE_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_CORE_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_CORE_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(CORE_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_CORE_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_CORE_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_CORE_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(CPUCL0_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(CPUCL0_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(CPUCL0_EMBEDDED_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(CPUCL0_EMBEDDED_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(CPUCL1_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(CPUCL1_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(CPUCL1_EMBEDDED_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(CPUCL1_EMBEDDED_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(DBG_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_DBG_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_DBG_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_DBG_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(DBG_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_DBG_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_DBG_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_DBG_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(DCAM_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_DCAM_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_DCAM_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_DCAM_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(DCAM_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_DCAM_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_DCAM_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_DCAM_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(DPU0_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_DPU0_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_DPU0_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_DPU0_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(DPU0_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_DPU0_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_DPU0_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_DPU0_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(DPU1_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_DPU1_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_DPU1_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_DPU1_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(DPU1_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_DPU1_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_DPU1_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_DPU1_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(DSP_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_DSP_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_DSP_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_DSP_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(DSP_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_DSP_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_DSP_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_DSP_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(FSYS0_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(FSYS0_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(FSYS1_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(FSYS1_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(G2D_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_G2D_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_G2D_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_G2D_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(G2D_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_G2D_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_G2D_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_G2D_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(G3D_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_G3D_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_G3D_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_G3D_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(G3D_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_G3D_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_G3D_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_G3D_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(G3D_EMBEDDED_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(G3D_EMBEDDED_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(IMEM_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_IMEM_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_IMEM_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_IMEM_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(IMEM_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_IMEM_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_IMEM_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_IMEM_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(ISPHQ_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(ISPHQ_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(ISPLP_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(ISPLP_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(IVA_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_IVA_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_IVA_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_IVA_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(IVA_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_IVA_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_IVA_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_IVA_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MFC_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_MFC_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_MFC_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_MFC_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MFC_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_MFC_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_MFC_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_MFC_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MIF_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_MIF_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_MIF_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_MIF_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MIF_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_MIF_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_MIF_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_MIF_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MIF1_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_MIF1_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_MIF1_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_MIF1_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MIF1_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_MIF1_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_MIF1_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_MIF1_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MIF2_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_MIF2_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_MIF2_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_MIF2_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MIF2_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_MIF2_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_MIF2_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_MIF2_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MIF3_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_MIF3_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_MIF3_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_MIF3_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MIF3_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_MIF3_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_MIF3_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_MIF3_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(PERIC0_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(PERIC0_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(PERIC1_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(PERIC1_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(PERIS_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_PERIS_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_PERIS_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_PERIS_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(PERIS_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_PERIS_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_PERIS_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_PERIS_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(SRDZ_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(SRDZ_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(VPU_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_VPU_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_VPU_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_VPU_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(VPU_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_VPU_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_VPU_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_VPU_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(VTS_CMU_CLKOUT0, NULL, CLKOUT_CON_BLK_VTS_CMU_CLKOUT0_SELECT, CLKOUT_CON_BLK_VTS_CMU_CLKOUT0_BUSY, CLKOUT_CON_BLK_VTS_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(VTS_CMU_CLKOUT1, NULL, CLKOUT_CON_BLK_VTS_CMU_CLKOUT1_SELECT, CLKOUT_CON_BLK_VTS_CMU_CLKOUT1_BUSY, CLKOUT_CON_BLK_VTS_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_ABOX_CPUABOX_USER, cmucal_mux_clkcmu_abox_cpuabox_user_parents, PLL_CON0_MUX_CLKCMU_ABOX_CPUABOX_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_ABOX_CPUABOX_USER_BUSY, PLL_CON2_MUX_CLKCMU_ABOX_CPUABOX_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_APM_BUS_USER, cmucal_mux_clkcmu_apm_bus_user_parents, PLL_CON0_MUX_CLKCMU_APM_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_APM_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_APM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_BUS1_BUS_USER, cmucal_mux_clkcmu_bus1_bus_user_parents, PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_BUS1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_BUSC_BUS_USER, cmucal_mux_clkcmu_busc_bus_user_parents, PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_BUSC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_BUSC_BUSPHSI2C_USER, cmucal_mux_clkcmu_busc_busphsi2c_user_parents, PLL_CON0_MUX_CLKCMU_BUSC_BUSPHSI2C_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_BUSC_BUSPHSI2C_USER_BUSY, PLL_CON2_MUX_CLKCMU_BUSC_BUSPHSI2C_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CAM_BUS_USER, cmucal_mux_clkcmu_cam_bus_user_parents, PLL_CON0_MUX_CLKCMU_CAM_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CAM_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_CAM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CAM_TPU0_USER, cmucal_mux_clkcmu_cam_tpu0_user_parents, PLL_CON0_MUX_CLKCMU_CAM_TPU0_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CAM_TPU0_USER_BUSY, PLL_CON2_MUX_CLKCMU_CAM_TPU0_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CAM_VRA_USER, cmucal_mux_clkcmu_cam_vra_user_parents, PLL_CON0_MUX_CLKCMU_CAM_VRA_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CAM_VRA_USER_BUSY, PLL_CON2_MUX_CLKCMU_CAM_VRA_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CAM_TPU1_USER, cmucal_mux_clkcmu_cam_tpu1_user_parents, PLL_CON0_MUX_CLKCMU_CAM_TPU1_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CAM_TPU1_USER_BUSY, PLL_CON2_MUX_CLKCMU_CAM_TPU1_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CP2AP_MIF_CLK_USER, cmucal_mux_cp2ap_mif_clk_user_parents, PLL_CON0_MUX_CP2AP_MIF_CLK_USER_MUX_SEL, PLL_CON0_MUX_CP2AP_MIF_CLK_USER_BUSY, PLL_CON2_MUX_CP2AP_MIF_CLK_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CORE_BUS_USER, cmucal_mux_clkcmu_core_bus_user_parents, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_CORE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CPUCL0_SWITCH_USER, cmucal_mux_clkcmu_cpucl0_switch_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_BUSY, PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CPUCL1_SWITCH_USER, cmucal_mux_clkcmu_cpucl1_switch_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_BUSY, PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_DBG_BUS_USER, cmucal_mux_clkcmu_dbg_bus_user_parents, PLL_CON0_MUX_CLKCMU_DBG_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DBG_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_DBG_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_DCAM_BUS_USER, cmucal_mux_clkcmu_dcam_bus_user_parents, PLL_CON0_MUX_CLKCMU_DCAM_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DCAM_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_DCAM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_DCAM_IMGD_USER, cmucal_mux_clkcmu_dcam_imgd_user_parents, PLL_CON0_MUX_CLKCMU_DCAM_IMGD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DCAM_IMGD_USER_BUSY, PLL_CON2_MUX_CLKCMU_DCAM_IMGD_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_DPU_BUS_USER, cmucal_mux_clkcmu_dpu_bus_user_parents, PLL_CON0_MUX_CLKCMU_DPU_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DPU_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_DPU_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_DPU1_BUSD_USER, cmucal_mux_clkcmu_dpu1_busd_user_parents, PLL_CON0_MUX_CLKCMU_DPU1_BUSD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DPU1_BUSD_USER_BUSY, PLL_CON2_MUX_CLKCMU_DPU1_BUSD_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_DPU1_BUSP_USER, cmucal_mux_clkcmu_dpu1_busp_user_parents, PLL_CON0_MUX_CLKCMU_DPU1_BUSP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DPU1_BUSP_USER_BUSY, PLL_CON2_MUX_CLKCMU_DPU1_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_DSP_BUS_USER, cmucal_mux_clkcmu_dsp_bus_user_parents, PLL_CON0_MUX_CLKCMU_DSP_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DSP_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_DSP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_FSYS0_UFS_EMBD_USER, cmucal_mux_clkcmu_fsys0_ufs_embd_user_parents, PLL_CON0_MUX_CLKCMU_FSYS0_UFS_EMBD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS0_UFS_EMBD_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS0_UFS_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_FSYS0_MMC_EMBD_USER, cmucal_mux_clkcmu_fsys0_mmc_embd_user_parents, PLL_CON0_MUX_CLKCMU_FSYS0_MMC_EMBD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS0_MMC_EMBD_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS0_MMC_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_FSYS0_BUS_USER, cmucal_mux_clkcmu_fsys0_bus_user_parents, PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_FSYS0_USBDRD30_USER, cmucal_mux_clkcmu_fsys0_usbdrd30_user_parents, PLL_CON0_MUX_CLKCMU_FSYS0_USBDRD30_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS0_USBDRD30_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS0_USBDRD30_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_FSYS0_DPGTC_USER, cmucal_mux_clkcmu_fsys0_dpgtc_user_parents, PLL_CON0_MUX_CLKCMU_FSYS0_DPGTC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS0_DPGTC_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS0_DPGTC_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_FSYS1_BUS_USER, cmucal_mux_clkcmu_fsys1_bus_user_parents, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_FSYS1_MMC_CARD_USER, cmucal_mux_clkcmu_fsys1_mmc_card_user_parents, PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS1_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_FSYS1_PCIE_USER, cmucal_mux_clkcmu_fsys1_pcie_user_parents, PLL_CON0_MUX_CLKCMU_FSYS1_PCIE_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS1_PCIE_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS1_PCIE_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_FSYS1_UFS_CARD_USER, cmucal_mux_clkcmu_fsys1_ufs_card_user_parents, PLL_CON0_MUX_CLKCMU_FSYS1_UFS_CARD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_FSYS1_UFS_CARD_USER_BUSY, PLL_CON2_MUX_CLKCMU_FSYS1_UFS_CARD_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_G2D_G2D_USER, cmucal_mux_clkcmu_g2d_g2d_user_parents, PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_BUSY, PLL_CON2_MUX_CLKCMU_G2D_G2D_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_G2D_JPEG_USER, cmucal_mux_clkcmu_g2d_jpeg_user_parents, PLL_CON0_MUX_CLKCMU_G2D_JPEG_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G2D_JPEG_USER_BUSY, PLL_CON2_MUX_CLKCMU_G2D_JPEG_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_G3D_SWITCH_USER, cmucal_mux_clkcmu_g3d_switch_user_parents, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_BUSY, PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_IMEM_BUS_USER, cmucal_mux_clkcmu_imem_bus_user_parents, PLL_CON0_MUX_CLKCMU_IMEM_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_IMEM_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_IMEM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_ISPHQ_BUS_USER, cmucal_mux_clkcmu_isphq_bus_user_parents, PLL_CON0_MUX_CLKCMU_ISPHQ_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_ISPHQ_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_ISPHQ_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_ISPLP_BUS_USER, cmucal_mux_clkcmu_isplp_bus_user_parents, PLL_CON0_MUX_CLKCMU_ISPLP_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_ISPLP_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_ISPLP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_IVA_BUS_USER, cmucal_mux_clkcmu_iva_bus_user_parents, PLL_CON0_MUX_CLKCMU_IVA_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_IVA_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_IVA_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_MFC_BUS_USER, cmucal_mux_clkcmu_mfc_bus_user_parents, PLL_CON0_MUX_CLKCMU_MFC_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MFC_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_MFC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC0_BUS_USER, cmucal_mux_clkcmu_peric0_bus_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC0_UART_DBG_USER, cmucal_mux_clkcmu_peric0_uart_dbg_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC0_UART_DBG_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC0_USI00_USER, cmucal_mux_clkcmu_peric0_usi00_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC0_USI00_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC0_USI01_USER, cmucal_mux_clkcmu_peric0_usi01_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC0_USI01_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC0_USI02_USER, cmucal_mux_clkcmu_peric0_usi02_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC0_USI02_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC0_USI03_USER, cmucal_mux_clkcmu_peric0_usi03_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC0_USI03_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_UART_BT_USER, cmucal_mux_clkcmu_peric1_uart_bt_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC1_UART_BT_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_USI05_USER, cmucal_mux_clkcmu_peric1_usi05_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_USI05_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_USI05_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC1_USI05_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_USI06_USER, cmucal_mux_clkcmu_peric1_usi06_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC1_USI06_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_USI07_USER, cmucal_mux_clkcmu_peric1_usi07_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC1_USI07_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_USI08_USER, cmucal_mux_clkcmu_peric1_usi08_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC1_USI08_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_USI09_USER, cmucal_mux_clkcmu_peric1_usi09_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC1_USI09_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_USI10_USER, cmucal_mux_clkcmu_peric1_usi10_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC1_USI10_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_USI11_USER, cmucal_mux_clkcmu_peric1_usi11_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC1_USI11_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_USI12_USER, cmucal_mux_clkcmu_peric1_usi12_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC1_USI12_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_USI13_USER, cmucal_mux_clkcmu_peric1_usi13_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC1_USI13_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_BUS_USER, cmucal_mux_clkcmu_peric1_bus_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_USI04_USER, cmucal_mux_clkcmu_peric1_usi04_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_USI04_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_USI04_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC1_USI04_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_SPI_CAM0_USER, cmucal_mux_clkcmu_peric1_spi_cam0_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM0_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM0_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC1_SPI_CAM0_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_SPI_CAM1_USER, cmucal_mux_clkcmu_peric1_spi_cam1_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM1_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM1_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC1_SPI_CAM1_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIC1_SPEEDY2_USER, cmucal_mux_clkcmu_peric1_speedy2_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_SPEEDY2_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_SPEEDY2_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIC1_SPEEDY2_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERIS_BUS_USER, cmucal_mux_clkcmu_peris_bus_user_parents, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_PERIS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_SRDZ_IMGD_USER, cmucal_mux_clkcmu_srdz_imgd_user_parents, PLL_CON0_MUX_CLKCMU_SRDZ_IMGD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_SRDZ_IMGD_USER_BUSY, PLL_CON2_MUX_CLKCMU_SRDZ_IMGD_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_SRDZ_BUS_USER, cmucal_mux_clkcmu_srdz_bus_user_parents, PLL_CON0_MUX_CLKCMU_SRDZ_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_SRDZ_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_SRDZ_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_VPU_BUS_USER, cmucal_mux_clkcmu_vpu_bus_user_parents, PLL_CON0_MUX_CLKCMU_VPU_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_VPU_BUS_USER_BUSY, PLL_CON2_MUX_CLKCMU_VPU_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
};

/*====================The section of DIVs===================*/
unsigned int cmucal_div_size = 122;


struct cmucal_div cmucal_div_list[] = {
	CLK_DIV(DIV_CLK_ABOX_PLL, PLL_AUD, CLK_CON_DIV_DIV_CLK_ABOX_PLL_DIVRATIO, CLK_CON_DIV_DIV_CLK_ABOX_PLL_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_PLL_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_ABOX_AUDIF, PLL_AUD, CLK_CON_DIV_DIV_CLK_ABOX_AUDIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_ABOX_AUDIF_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_AUDIF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_ABOX_CPU_ATCLK, MUX_CLK_ABOX_CPU, CLK_CON_DIV_DIV_CLK_ABOX_CPU_ATCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_ABOX_CPU_ATCLK_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_CPU_ATCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_ABOX_CPU_PCLKDBG, MUX_CLK_ABOX_CPU, CLK_CON_DIV_DIV_CLK_ABOX_CPU_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_ABOX_CPU_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_CPU_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_ABOX_DSIF, DIV_CLK_ABOX_AUDIF, CLK_CON_DIV_DIV_CLK_ABOX_DSIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_ABOX_DSIF_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_DSIF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_ABOX_UAIF0, DIV_CLK_ABOX_AUDIF, CLK_CON_DIV_DIV_CLK_ABOX_UAIF0_DIVRATIO, CLK_CON_DIV_DIV_CLK_ABOX_UAIF0_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_UAIF0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_ABOX_UAIF1, DIV_CLK_ABOX_AUDIF, CLK_CON_DIV_DIV_CLK_ABOX_UAIF1_DIVRATIO, CLK_CON_DIV_DIV_CLK_ABOX_UAIF1_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_UAIF1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_ABOX_UAIF2, DIV_CLK_ABOX_AUDIF, CLK_CON_DIV_DIV_CLK_ABOX_UAIF2_DIVRATIO, CLK_CON_DIV_DIV_CLK_ABOX_UAIF2_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_UAIF2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_ABOX_UAIF3, DIV_CLK_ABOX_AUDIF, CLK_CON_DIV_DIV_CLK_ABOX_UAIF3_DIVRATIO, CLK_CON_DIV_DIV_CLK_ABOX_UAIF3_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_UAIF3_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_ABOX_CPU_ACLK, MUX_CLK_ABOX_CPU, CLK_CON_DIV_DIV_CLK_ABOX_CPU_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_ABOX_CPU_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_CPU_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_ABOX_BUS, PLL_AUD, CLK_CON_DIV_DIV_CLK_ABOX_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_ABOX_BUS_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_ABOX_BUSP, DIV_CLK_ABOX_BUS, CLK_CON_DIV_DIV_CLK_ABOX_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_ABOX_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_ABOX_DMIC, DIV_CLK_ABOX_DSIF, CLK_CON_DIV_DIV_CLK_ABOX_DMIC_DIVRATIO, CLK_CON_DIV_DIV_CLK_ABOX_DMIC_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_DMIC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_ABOX_UAIF4, DIV_CLK_ABOX_AUDIF, CLK_CON_DIV_DIV_CLK_ABOX_UAIF4_DIVRATIO, CLK_CON_DIV_DIV_CLK_ABOX_UAIF4_BUSY, CLK_CON_DIV_DIV_CLK_ABOX_UAIF4_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_BUS1_BUSP, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_DIV_DIV_CLK_BUS1_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_BUS1_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_BUS1_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_BUSC_BUSP, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_DIV_DIV_CLK_BUSC_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_BUSC_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_BUSC_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CAM_BUSP, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_DIV_DIV_CLK_CAM_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_CAM_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_CAM_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_APM_BUS, GATE_CLKCMU_APM_BUS, CLK_CON_DIV_CLKCMU_APM_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_APM_BUS_BUSY, CLK_CON_DIV_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_G3D_SWITCH, GATE_CLKCMU_G3D_SWITCH, CLK_CON_DIV_CLKCMU_G3D_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_G3D_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERIC0_BUS, GATE_CLKCMU_PERIC0_BUS, CLK_CON_DIV_CLKCMU_PERIC0_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC0_BUS_BUSY, CLK_CON_DIV_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERIS_BUS, GATE_CLKCMU_PERIS_BUS, CLK_CON_DIV_CLKCMU_PERIS_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIS_BUS_BUSY, CLK_CON_DIV_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_FSYS0_BUS, GATE_CLKCMU_FSYS0_BUS, CLK_CON_DIV_CLKCMU_FSYS0_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS0_BUS_BUSY, CLK_CON_DIV_CLKCMU_FSYS0_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_DPU_BUS, GATE_CLKCMU_DPU_BUS, CLK_CON_DIV_CLKCMU_DPU_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_DPU_BUS_BUSY, CLK_CON_DIV_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_BUS1_BUS, GATE_CLKCMU_BUS1_BUS, CLK_CON_DIV_CLKCMU_BUS1_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_BUS1_BUS_BUSY, CLK_CON_DIV_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERIC0_USI00, GATE_CLKCMU_PERIC0_USI00, CLK_CON_DIV_CLKCMU_PERIC0_USI00_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC0_USI00_BUSY, CLK_CON_DIV_CLKCMU_PERIC0_USI00_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERIC0_UART_DBG, GATE_CLKCMU_PERIC0_UART_DBG, CLK_CON_DIV_CLKCMU_PERIC0_UART_DBG_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC0_UART_DBG_BUSY, CLK_CON_DIV_CLKCMU_PERIC0_UART_DBG_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERIC0_USI01, GATE_CLKCMU_PERIC0_USI01, CLK_CON_DIV_CLKCMU_PERIC0_USI01_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC0_USI01_BUSY, CLK_CON_DIV_CLKCMU_PERIC0_USI01_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERIC0_USI02, GATE_CLKCMU_PERIC0_USI02, CLK_CON_DIV_CLKCMU_PERIC0_USI02_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC0_USI02_BUSY, CLK_CON_DIV_CLKCMU_PERIC0_USI02_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERIC0_USI03, GATE_CLKCMU_PERIC0_USI03, CLK_CON_DIV_CLKCMU_PERIC0_USI03_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC0_USI03_BUSY, CLK_CON_DIV_CLKCMU_PERIC0_USI03_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_MFC_BUS, GATE_CLKCMU_MFC_BUS, CLK_CON_DIV_CLKCMU_MFC_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_MFC_BUS_BUSY, CLK_CON_DIV_CLKCMU_MFC_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_G2D_G2D, GATE_CLKCMU_G2D_G2D, CLK_CON_DIV_CLKCMU_G2D_G2D_DIVRATIO, CLK_CON_DIV_CLKCMU_G2D_G2D_BUSY, CLK_CON_DIV_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_FSYS0_USBDRD30, GATE_CLKCMU_FSYS0_USBDRD30, CLK_CON_DIV_CLKCMU_FSYS0_USBDRD30_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS0_USBDRD30_BUSY, CLK_CON_DIV_CLKCMU_FSYS0_USBDRD30_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_FSYS0_MMC_EMBD, GATE_CLKCMU_FSYS0_MMC_EMBD, CLK_CON_DIV_CLKCMU_FSYS0_MMC_EMBD_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS0_MMC_EMBD_BUSY, CLK_CON_DIV_CLKCMU_FSYS0_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_FSYS0_UFS_EMBD, GATE_CLKCMU_FSYS0_UFS_EMBD, CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD_BUSY, CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_FSYS1_MMC_CARD, GATE_CLKCMU_FSYS1_MMC_CARD, CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD_BUSY, CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_FSYS1_BUS, GATE_CLKCMU_FSYS1_BUS, CLK_CON_DIV_CLKCMU_FSYS1_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS1_BUS_BUSY, CLK_CON_DIV_CLKCMU_FSYS1_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_VPU_BUS, GATE_CLKCMU_VPU_BUS, CLK_CON_DIV_CLKCMU_VPU_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_VPU_BUS_BUSY, CLK_CON_DIV_CLKCMU_VPU_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_DSP_BUS, GATE_CLKCMU_DSP_BUS, CLK_CON_DIV_CLKCMU_DSP_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_DSP_BUS_BUSY, CLK_CON_DIV_CLKCMU_DSP_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERIC1_BUS, GATE_CLKCMU_PERIC1_BUS, CLK_CON_DIV_CLKCMU_PERIC1_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_BUS_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERIC1_UART_BT, GATE_CLKCMU_PERIC1_UART_BT, CLK_CON_DIV_CLKCMU_PERIC1_UART_BT_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_UART_BT_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERIC1_USI05, GATE_CLKCMU_PERIC1_USI05, CLK_CON_DIV_CLKCMU_PERIC1_USI05_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_USI05_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_USI05_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERIC1_USI06, GATE_CLKCMU_PERIC1_USI06, CLK_CON_DIV_CLKCMU_PERIC1_USI06_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_USI06_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_USI06_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERIC1_USI07, GATE_CLKCMU_PERIC1_USI07, CLK_CON_DIV_CLKCMU_PERIC1_USI07_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_USI07_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_USI07_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERIC1_USI08, GATE_CLKCMU_PERIC1_USI08, CLK_CON_DIV_CLKCMU_PERIC1_USI08_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_USI08_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_USI08_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERIC1_USI09, GATE_CLKCMU_PERIC1_USI09, CLK_CON_DIV_CLKCMU_PERIC1_USI09_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_USI09_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_USI09_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERIC1_USI10, GATE_CLKCMU_PERIC1_USI10, CLK_CON_DIV_CLKCMU_PERIC1_USI10_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_USI10_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_USI10_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERIC1_USI11, GATE_CLKCMU_PERIC1_USI11, CLK_CON_DIV_CLKCMU_PERIC1_USI11_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_USI11_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_USI11_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERIC1_USI12, GATE_CLKCMU_PERIC1_USI12, CLK_CON_DIV_CLKCMU_PERIC1_USI12_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_USI12_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_USI12_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERIC1_USI13, GATE_CLKCMU_PERIC1_USI13, CLK_CON_DIV_CLKCMU_PERIC1_USI13_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_USI13_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_USI13_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_BUSC_BUS, GATE_CLKCMU_BUSC_BUS, CLK_CON_DIV_CLKCMU_BUSC_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_BUSC_BUS_BUSY, CLK_CON_DIV_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERIC1_USI04, GATE_CLKCMU_PERIC1_USI04, CLK_CON_DIV_CLKCMU_PERIC1_USI04_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_USI04_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_USI04_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CPUCL1_SWITCH, GATE_CLKCMU_CPUCL1_SWITCH, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CPUCL0_SWITCH, GATE_CLKCMU_CPUCL0_SWITCH, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CORE_BUS, GATE_CLKCMU_CORE_BUS, CLK_CON_DIV_CLKCMU_CORE_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_CORE_BUS_BUSY, CLK_CON_DIV_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CAM_BUS, GATE_CLKCMU_CAM_BUS, CLK_CON_DIV_CLKCMU_CAM_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_CAM_BUS_BUSY, CLK_CON_DIV_CLKCMU_CAM_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CAM_TPU0, GATE_CLKCMU_CAM_TPU0, CLK_CON_DIV_CLKCMU_CAM_TPU0_DIVRATIO, CLK_CON_DIV_CLKCMU_CAM_TPU0_BUSY, CLK_CON_DIV_CLKCMU_CAM_TPU0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CAM_TPU1, GATE_CLKCMU_CAM_TPU1, CLK_CON_DIV_CLKCMU_CAM_TPU1_DIVRATIO, CLK_CON_DIV_CLKCMU_CAM_TPU1_BUSY, CLK_CON_DIV_CLKCMU_CAM_TPU1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_ISPLP_BUS, GATE_CLKCMU_ISPLP_BUS, CLK_CON_DIV_CLKCMU_ISPLP_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_ISPLP_BUS_BUSY, CLK_CON_DIV_CLKCMU_ISPLP_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_ISPHQ_BUS, GATE_CLKCMU_ISPHQ_BUS, CLK_CON_DIV_CLKCMU_ISPHQ_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_ISPHQ_BUS_BUSY, CLK_CON_DIV_CLKCMU_ISPHQ_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_ABOX_CPUABOX, GATE_CLKCMU_ABOX_CPUABOX, CLK_CON_DIV_CLKCMU_ABOX_CPUABOX_DIVRATIO, CLK_CON_DIV_CLKCMU_ABOX_CPUABOX_BUSY, CLK_CON_DIV_CLKCMU_ABOX_CPUABOX_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_G2D_JPEG, GATE_CLKCMU_G2D_JPEG, CLK_CON_DIV_CLKCMU_G2D_JPEG_DIVRATIO, CLK_CON_DIV_CLKCMU_G2D_JPEG_BUSY, CLK_CON_DIV_CLKCMU_G2D_JPEG_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_HPM, GATE_CLKCMU_HPM, CLK_CON_DIV_CLKCMU_HPM_DIVRATIO, CLK_CON_DIV_CLKCMU_HPM_BUSY, CLK_CON_DIV_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_DBG_BUS, GATE_CLKCMU_DBG_BUS, CLK_CON_DIV_CLKCMU_DBG_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_DBG_BUS_BUSY, CLK_CON_DIV_CLKCMU_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERIC1_SPI_CAM0, GATE_CLKCMU_PERIC1_SPI_CAM0, CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM0_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM0_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERIC1_SPI_CAM1, GATE_CLKCMU_PERIC1_SPI_CAM1, CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM1_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM1_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CIS_CLK0, GATE_CLKCMU_CIS_CLK0, CLK_CON_DIV_CLKCMU_CIS_CLK0_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK0_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CIS_CLK1, GATE_CLKCMU_CIS_CLK1, CLK_CON_DIV_CLKCMU_CIS_CLK1_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK1_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CIS_CLK2, GATE_CLKCMU_CIS_CLK2, CLK_CON_DIV_CLKCMU_CIS_CLK2_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK2_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CIS_CLK3, GATE_CLKCMU_CIS_CLK3, CLK_CON_DIV_CLKCMU_CIS_CLK3_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK3_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_IVA_BUS, GATE_CLKCMU_IVA_BUS, CLK_CON_DIV_CLKCMU_IVA_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_IVA_BUS_BUSY, CLK_CON_DIV_CLKCMU_IVA_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_FSYS1_UFS_CARD, GATE_CLKCMU_FSYS1_UFS_CARD, CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD_BUSY, CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_BUSC_BUSPHSI2C, GATE_CLKCMU_BUSC_BUSPHSI2C, CLK_CON_DIV_CLKCMU_BUSC_BUSPHSI2C_DIVRATIO, CLK_CON_DIV_CLKCMU_BUSC_BUSPHSI2C_BUSY, CLK_CON_DIV_CLKCMU_BUSC_BUSPHSI2C_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CAM_VRA, GATE_CLKCMU_CAM_VRA, CLK_CON_DIV_CLKCMU_CAM_VRA_DIVRATIO, CLK_CON_DIV_CLKCMU_CAM_VRA_BUSY, CLK_CON_DIV_CLKCMU_CAM_VRA_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERIC1_SPEEDY2, GATE_CLKCMU_PERIC1_SPEEDY2, CLK_CON_DIV_CLKCMU_PERIC1_SPEEDY2_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_SPEEDY2_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_SPEEDY2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_FSYS0_DPGTC, GATE_CLKCMU_FSYS0_DPGTC, CLK_CON_DIV_CLKCMU_FSYS0_DPGTC_DIVRATIO, CLK_CON_DIV_CLKCMU_FSYS0_DPGTC_BUSY, CLK_CON_DIV_CLKCMU_FSYS0_DPGTC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_MODEM_SHARED0, GATE_CLKCMU_MODEM_SHARED0, CLK_CON_DIV_CLKCMU_MODEM_SHARED0_DIVRATIO, CLK_CON_DIV_CLKCMU_MODEM_SHARED0_BUSY, CLK_CON_DIV_CLKCMU_MODEM_SHARED0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_MODEM_SHARED1, GATE_CLKCMU_MODEM_SHARED1, CLK_CON_DIV_CLKCMU_MODEM_SHARED1_DIVRATIO, CLK_CON_DIV_CLKCMU_MODEM_SHARED1_BUSY, CLK_CON_DIV_CLKCMU_MODEM_SHARED1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_DCAM_BUS, GATE_CLKCMU_DCAM_BUS, CLK_CON_DIV_CLKCMU_DCAM_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_DCAM_BUS_BUSY, CLK_CON_DIV_CLKCMU_DCAM_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_IMEM_BUS, GATE_CLKCMU_IMEM_BUS, CLK_CON_DIV_CLKCMU_IMEM_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_IMEM_BUS_BUSY, CLK_CON_DIV_CLKCMU_IMEM_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CMU_CMUREF, MUX_CLK_CMU_CMUREF, CLK_CON_DIV_DIV_CLK_CMU_CMUREF_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMU_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_SRDZ_IMGD, GATE_CLKCMU_SRDZ_IMGD, CLK_CON_DIV_CLKCMU_SRDZ_IMGD_DIVRATIO, CLK_CON_DIV_CLKCMU_SRDZ_IMGD_BUSY, CLK_CON_DIV_CLKCMU_SRDZ_IMGD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_SRDZ_BUS, GATE_CLKCMU_SRDZ_BUS, CLK_CON_DIV_CLKCMU_SRDZ_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_SRDZ_BUS_BUSY, CLK_CON_DIV_CLKCMU_SRDZ_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_DCAM_IMGD, GATE_CLKCMU_DCAM_IMGD, CLK_CON_DIV_CLKCMU_DCAM_IMGD_DIVRATIO, CLK_CON_DIV_CLKCMU_DCAM_IMGD_BUSY, CLK_CON_DIV_CLKCMU_DCAM_IMGD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CORE_BUSP, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_DIV_DIV_CLK_CORE_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_CORE_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_CORE_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CPUCL0_CMUREF, DIV_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CPUCL0_PCLK, DIV_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CLUSTER0_ACLK, GATE_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CLUSTER0_ATCLK, GATE_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CPUCL0_PCLKDBG, GATE_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CPUCL0_CPU, MUX_CLK_CPUCL0_PLL, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CPUCL1_CMUREF, DIV_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CPUCL1_PCLK, DIV_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CLUSTER1_PCLKDBG, GATE_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CLUSTER1_CNTCLK, GATE_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CLUSTER1_ACLK, GATE_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CLUSTER1_ATCLK, GATE_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CPUCL1_CPU, MUX_CLK_CPUCL1_PLL, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_DBG_PCLKDBG, MUX_CLKCMU_DBG_BUS_USER, CLK_CON_DIV_DIV_CLK_DBG_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_DBG_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_DBG_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_DCAM_BUSP, MUX_CLKCMU_DCAM_BUS_USER, CLK_CON_DIV_DIV_CLK_DCAM_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DCAM_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_DCAM_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_DPU0_BUSP, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_DIV_DIV_CLK_DPU0_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DPU0_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_DPU0_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLKCMU_DPU1_DECON2, PLL_DPU, CLK_CON_DIV_DIV_CLKCMU_DPU1_DECON2_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_DPU1_DECON2_BUSY, CLK_CON_DIV_DIV_CLKCMU_DPU1_DECON2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_DSP_BUSP, MUX_CLKCMU_DSP_BUS_USER, CLK_CON_DIV_DIV_CLK_DSP_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DSP_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_DSP_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_G2D_BUSP, MUX_CLKCMU_G2D_JPEG_USER, CLK_CON_DIV_DIV_CLK_G2D_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_G2D_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_G2D_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_G3D_BUSP, MUX_CLK_G3D_BUSD, CLK_CON_DIV_DIV_CLK_G3D_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_G3D_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_G3D_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_ISPHQ_BUSP, MUX_CLKCMU_ISPHQ_BUS_USER, CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_ISPLP_BUSP, MUX_CLKCMU_ISPLP_BUS_USER, CLK_CON_DIV_DIV_CLK_ISPLP_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_ISPLP_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_ISPLP_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_IVA_BUSP, MUX_CLKCMU_IVA_BUS_USER, CLK_CON_DIV_DIV_CLK_IVA_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_IVA_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_IVA_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_MFC_BUSP, MUX_CLKCMU_MFC_BUS_USER, CLK_CON_DIV_DIV_CLK_MFC_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MFC_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MFC_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_MIF_PRE, CLKCMU_MIF_SWITCH, CLK_CON_DIV_DIV_CLK_MIF_PRE_DIVRATIO, CLK_CON_DIV_DIV_CLK_MIF_PRE_BUSY, CLK_CON_DIV_DIV_CLK_MIF_PRE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_MIF_BUSP, DIV_CLK_MIF_PRE, CLK_CON_DIV_DIV_CLK_MIF_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MIF_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_MIF1_PRE, CLKCMU_MIF_SWITCH, CLK_CON_DIV_DIV_CLK_MIF1_PRE_DIVRATIO, CLK_CON_DIV_DIV_CLK_MIF1_PRE_BUSY, CLK_CON_DIV_DIV_CLK_MIF1_PRE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_MIF1_BUSP, DIV_CLK_MIF1_PRE, CLK_CON_DIV_DIV_CLK_MIF1_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MIF1_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MIF1_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_MIF2_PRE, CLKCMU_MIF_SWITCH, CLK_CON_DIV_DIV_CLK_MIF2_PRE_DIVRATIO, CLK_CON_DIV_DIV_CLK_MIF2_PRE_BUSY, CLK_CON_DIV_DIV_CLK_MIF2_PRE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_MIF2_BUSP, DIV_CLK_MIF2_PRE, CLK_CON_DIV_DIV_CLK_MIF2_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MIF2_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MIF2_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_MIF3_PRE, CLKCMU_MIF_SWITCH, CLK_CON_DIV_DIV_CLK_MIF3_PRE_DIVRATIO, CLK_CON_DIV_DIV_CLK_MIF3_PRE_BUSY, CLK_CON_DIV_DIV_CLK_MIF3_PRE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_MIF3_BUSP, DIV_CLK_MIF3_PRE, CLK_CON_DIV_DIV_CLK_MIF3_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MIF3_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MIF3_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_SRDZ_BUSP, MUX_CLKCMU_SRDZ_BUS_USER, CLK_CON_DIV_DIV_CLK_SRDZ_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_SRDZ_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_SRDZ_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_VPU_BUSP, MUX_CLKCMU_VPU_BUS_USER, CLK_CON_DIV_DIV_CLK_VPU_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_VPU_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_VPU_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_VTS_BUS, OSC_VTS, CLK_CON_DIV_DIV_CLK_VTS_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_BUS_BUSY, CLK_CON_DIV_DIV_CLK_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_VTS_DMICIF, OSC_VTS, CLK_CON_DIV_DIV_CLK_VTS_DMICIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_DMICIF_BUSY, CLK_CON_DIV_DIV_CLK_VTS_DMICIF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_VTS_DMIC, DIV_CLK_VTS_DMICIF, CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_DMIC_BUSY, CLK_CON_DIV_DIV_CLK_VTS_DMIC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_VTS_DMIC_DIV2, DIV_CLK_VTS_DMICIF, CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2_BUSY, CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2_ENABLE_AUTOMATIC_CLKGATING),
};

/*====================The section of GATEs===================*/
unsigned int cmucal_gate_size = 1042;


struct cmucal_gate cmucal_gate_list[] = {
	CLK_GATE(CLK_BLK_ABOX_UID_ABOX_CMU_ABOX_IPCLKPORT_PCLK, DIV_CLK_ABOX_BUS, CLK_CON_GAT_CLK_BLK_ABOX_UID_ABOX_CMU_ABOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ABOX_UID_ABOX_CMU_ABOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ABOX_UID_ABOX_CMU_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK, DIV_CLK_ABOX_BUS, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_PMU_ABOX_IPCLKPORT_PCLK, DIV_CLK_ABOX_BUS, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PMU_ABOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PMU_ABOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PMU_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_ACLK, DIV_CLK_ABOX_BUS, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_PCLK, DIV_CLK_ABOX_BUS, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_ACLK, DIV_CLK_ABOX_BUS, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_PCLK, DIV_CLK_ABOX_BUS, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_SYSREG_ABOX_IPCLKPORT_PCLK, DIV_CLK_ABOX_BUS, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SYSREG_ABOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SYSREG_ABOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SYSREG_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF0, MUX_CLK_ABOX_UAIF0, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF0_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF0_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF1, MUX_CLK_ABOX_UAIF1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF1_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF1_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF3, MUX_CLK_ABOX_UAIF3, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF3_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF3_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF3_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_DSIF, DIV_CLK_ABOX_DSIF, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_DSIF_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_DSIF_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_DSIF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_LHS_ATB_ABOX_IPCLKPORT_I_CLK, DIV_CLK_ABOX_CPU_ATCLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_ATB_ABOX_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_ATB_ABOX_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_ATB_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_ACLK, DIV_CLK_ABOX_BUS, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_GPIO_ABOX_IPCLKPORT_PCLK, DIV_CLK_ABOX_BUS, CLK_CON_GAT_GOUT_BLK_ABOX_UID_GPIO_ABOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_GPIO_ABOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_GPIO_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_AXI_US_32to128_IPCLKPORT_aclk, DIV_CLK_ABOX_BUS, CLK_CON_GAT_GOUT_BLK_ABOX_UID_AXI_US_32TO128_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_AXI_US_32TO128_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_AXI_US_32TO128_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_RSTnSYNC_CLK_ABOX_BUS_IPCLKPORT_CLK, DIV_CLK_ABOX_BUS, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_RSTnSYNC_CLK_ABOX_CPU_ATCLK_IPCLKPORT_CLK, DIV_CLK_ABOX_CPU_ATCLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ATCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ATCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_RSTnSYNC_CLK_ABOX_CPU_PCLKDBG_IPCLKPORT_CLK, DIV_CLK_ABOX_CPU_PCLKDBG, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_RSTnSYNC_CLK_ABOX_DSIF_IPCLKPORT_CLK, DIV_CLK_ABOX_DSIF, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_DSIF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_DSIF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_DSIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_RSTnSYNC_CLK_ABOX_UAIF0_IPCLKPORT_CLK, MUX_CLK_ABOX_UAIF0, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_RSTnSYNC_CLK_ABOX_UAIF1_IPCLKPORT_CLK, MUX_CLK_ABOX_UAIF1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_RSTnSYNC_CLK_ABOX_UAIF2_IPCLKPORT_CLK, MUX_CLK_ABOX_UAIF2, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_RSTnSYNC_CLK_ABOX_UAIF3_IPCLKPORT_CLK, MUX_CLK_ABOX_UAIF3, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF3_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF3_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_ACLK, DIV_CLK_ABOX_BUS, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_PCLK, DIV_CLK_ABOX_BUS, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ASB, DIV_CLK_ABOX_CPU_ACLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ASB_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ASB_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ASB_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_RSTnSYNC_CLK_ABOX_CPU_ACLK_IPCLKPORT_CLK, DIV_CLK_ABOX_CPU_ACLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ACLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ACLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_CA7, MUX_CLK_ABOX_CPU, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_CA7_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_CA7_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_CA7_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_RSTnSYNC_CLK_ABOX_CPU_IPCLKPORT_CLK, MUX_CLK_ABOX_CPU, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM, DIV_CLK_ABOX_BUS, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF2, MUX_CLK_ABOX_UAIF2, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF2_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF2_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_LHM_AXI_P_ABOX_IPCLKPORT_I_CLK, DIV_CLK_ABOX_BUSP, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHM_AXI_P_ABOX_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHM_AXI_P_ABOX_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHM_AXI_P_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS, DIV_CLK_ABOX_BUSP, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_RSTnSYNC_CLK_ABOX_BUSP_IPCLKPORT_CLK, DIV_CLK_ABOX_BUSP, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_PCLK, DIV_CLK_ABOX_BUS, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_WDT_ABOXCPU_IPCLKPORT_PCLK, DIV_CLK_ABOX_BUS, CLK_CON_GAT_GOUT_BLK_ABOX_UID_WDT_ABOXCPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_WDT_ABOXCPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_WDT_ABOXCPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_ABOX_UID_DMIC_IPCLKPORT_CLK, DIV_CLK_ABOX_DMIC, CLK_CON_GAT_CLK_BLK_ABOX_UID_DMIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ABOX_UID_DMIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ABOX_UID_DMIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ATB, DIV_CLK_ABOX_CPU_ATCLK, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ATB_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ATB_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ATB_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_ABOX_DAP_IPCLKPORT_dapclk, DIV_CLK_ABOX_CPU_PCLKDBG, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_DAP_IPCLKPORT_DAPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_DAP_IPCLKPORT_DAPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_DAP_IPCLKPORT_DAPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_TREX_ABOX_IPCLKPORT_clk, DIV_CLK_ABOX_BUS, CLK_CON_GAT_GOUT_BLK_ABOX_UID_TREX_ABOX_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_TREX_ABOX_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_TREX_ABOX_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_WRAP2_CONV_ABOX_IPCLKPORT_I_CLK, DIV_CLK_ABOX_BUS, CLK_CON_GAT_GOUT_BLK_ABOX_UID_WRAP2_CONV_ABOX_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_WRAP2_CONV_ABOX_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_WRAP2_CONV_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_ABOX_UID_DFTMUX_ABOX_IPCLKPORT_AUD_CODEC_MCLK, DIV_CLK_ABOX_AUDIF, CLK_CON_GAT_CLK_BLK_ABOX_UID_DFTMUX_ABOX_IPCLKPORT_AUD_CODEC_MCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ABOX_UID_DFTMUX_ABOX_IPCLKPORT_AUD_CODEC_MCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ABOX_UID_DFTMUX_ABOX_IPCLKPORT_AUD_CODEC_MCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_RSTnSYNC_CLK_ABOX_UAIF4_IPCLKPORT_CLK, MUX_CLK_ABOX_UAIF4, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF4_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF4_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF4_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF4, MUX_CLK_ABOX_UAIF4, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF4_CG_VAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF4_MANUAL, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF4_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_XIU_D_ALIVE, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_XIU_D_ALIVE_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_XIU_D_ALIVE_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_XIU_D_ALIVE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_APM_UID_RSTnSYNC_CLK_APM_BUS_IPCLKPORT_CLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_APM_UID_SCAN2AXI_IPCLKPORT_ACLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_SCAN2AXI_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SCAN2AXI_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SCAN2AXI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK, MUX_CLKCMU_APM_BUS_USER, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUS1_UID_LHM_ACEL_D_FSYS1_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_FSYS1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_FSYS1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_FSYS1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUS1_UID_LHS_AXI_P_FSYS1_IPCLKPORT_I_CLK, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_FSYS1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_FSYS1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_FSYS1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_pclk, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_pclk, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUS1_UID_PMU_BUS1_IPCLKPORT_PCLK, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_PMU_BUS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_PMU_BUS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_PMU_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUS1_UID_LHM_AXI_D_ALIVE_IPCLKPORT_I_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_ALIVE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_ALIVE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUS1_UID_LHS_AXI_P_ALIVE_IPCLKPORT_I_CLK, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_ALIVE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_ALIVE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUS1_UID_RSTnSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_BUS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUS1_UID_RSTnSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK, DIV_CLK_BUS1_BUSP, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_AXI2APB_BUSCP0_IPCLKPORT_ACLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_AXI2APB_BUSCP1_IPCLKPORT_ACLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_AXI2APB_BUSC_TDP_IPCLKPORT_ACLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSC_TDP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSC_TDP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSC_TDP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_GPIO_BUSC_IPCLKPORT_PCLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_GPIO_BUSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_GPIO_BUSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_GPIO_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_PMU_BUSC_IPCLKPORT_PCLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PMU_BUSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PMU_BUSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PMU_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_SECMBOX_IPCLKPORT_PCLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SECMBOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SECMBOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SECMBOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_MBOX_IPCLKPORT_PCLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_MBOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_MBOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_MBOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S0, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S0_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S0_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S1, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_pclk, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_pclk, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_BUSC, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_BUSC_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_BUSC_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_BUSC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_RSTnSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_RSTnSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_GNSSMBOX_IPCLKPORT_PCLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_GNSSMBOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_GNSSMBOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_GNSSMBOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_SPEEDY_IPCLKPORT_PCLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_PCLK_BATCHER_SPEEDY, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_PCLK_BATCHER_SPEEDY_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_PCLK_BATCHER_SPEEDY_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_PCLK_BATCHER_SPEEDY_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_i_pclk_BATCHER_AP, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_AP_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_AP_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_AP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_i_pclk_BATCHER_CP, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_CP_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_CP_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_CP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_HSI2CDF_IPCLKPORT_iPCLK, MUX_CLKCMU_BUSC_BUSPHSI2C_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_HSI2CDF_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_HSI2CDF_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_HSI2CDF_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKS, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKM, MUX_CLKCMU_BUSC_BUSPHSI2C_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_RSTnSYNC_CLK_BUSC_BUSPHSI2C_IPCLKPORT_CLK, MUX_CLKCMU_BUSC_BUSPHSI2C_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSPHSI2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSPHSI2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSPHSI2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SCI_IPCLKPORT_I_PCLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SCI_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SCI_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SCI_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHS_AXI_D_IVASC_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_D_IVASC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_D_IVASC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_D_IVASC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_PDMA0_IPCLKPORT_ACLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_SPDMA_IPCLKPORT_ACLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHM_ACEL_D0_G2D_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D0_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D0_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D0_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHM_ACEL_D1_G2D_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D1_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D1_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D1_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHM_ACEL_D2_G2D_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D2_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D2_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D2_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHM_ACEL_D_DSP_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_DSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_DSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_DSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHM_ACEL_D_FSYS0_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_FSYS0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_FSYS0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_FSYS0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHM_ACEL_D_IVA_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_IVA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_IVA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_IVA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHM_ACEL_D_VPU_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_VPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_VPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_VPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHM_AXI_D0_CAM_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_CAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_CAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHM_AXI_D0_DPU_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHM_AXI_D0_MFC_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHM_AXI_D1_CAM_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_CAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_CAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHM_AXI_D1_DPU_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHM_AXI_D1_MFC_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHM_AXI_D2_DPU_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D2_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D2_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D2_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHM_AXI_D_SRDZ_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_SRDZ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_SRDZ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_SRDZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHM_AXI_D_ISPLP_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ISPLP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ISPLP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ISPLP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHS_AXI_P0_DPU_IPCLKPORT_I_CLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P0_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P0_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P0_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHS_AXI_P1_DPU_IPCLKPORT_I_CLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P1_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P1_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P1_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHS_AXI_P_ABOX_IPCLKPORT_I_CLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ABOX_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ABOX_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHS_AXI_P_SRDZ_IPCLKPORT_I_CLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_SRDZ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_SRDZ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_SRDZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHS_AXI_P_DSP_IPCLKPORT_I_CLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_DSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_DSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_DSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHS_AXI_P_FSYS0_IPCLKPORT_I_CLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_FSYS0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_FSYS0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_FSYS0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPHQ_IPCLKPORT_I_CLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPHQ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPHQ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPHQ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPLP_IPCLKPORT_I_CLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPLP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPLP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPLP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHS_AXI_P_IVA_IPCLKPORT_I_CLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_IVA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_IVA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_IVA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHS_AXI_P_VPU_IPCLKPORT_I_CLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_ACLK_BUSC, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_ACLK_BUSC_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_ACLK_BUSC_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_ACLK_BUSC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_BNS, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_BNS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_BNS_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_BNS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSISX4_DMA, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSISX4_DMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSISX4_DMA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSISX4_DMA_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_MC_SCALER, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_MC_SCALER_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_MC_SCALER_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_MC_SCALER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU0, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_VRA, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_VRA_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_CFW_CAM, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_CFW_CAM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_CFW_CAM_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_CFW_CAM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM0, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM1, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_CSISX4, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_CSISX4_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_CSISX4_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_CSISX4_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU0, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_VRA, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_VRA_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM0, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM1, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_LHS_AXI_D0_CAM_IPCLKPORT_I_CLK, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D0_CAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D0_CAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D0_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_LHS_AXI_D1_CAM_IPCLKPORT_I_CLK, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D1_CAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D1_CAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D1_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_ACLK, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_MC_SCALER, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_MC_SCALER_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_MC_SCALER_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_MC_SCALER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM0, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM0, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM1, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_CSISX4, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_CSISX4_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_CSISX4_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_CSISX4_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU0, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_VRA, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_VRA_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU0_MCSC, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU0_MCSC_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU0_MCSC_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU0_MCSC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU0, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPLP, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPLP_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPLP_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPLP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPHQ, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPHQ_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPHQ_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPHQ_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU0, MUX_CLKCMU_CAM_TPU0_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2to1_ISP_TPU0, MUX_CLKCMU_CAM_TPU0_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1to2_TPU0_MCSC, MUX_CLKCMU_CAM_TPU0_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU0_MCSC_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU0_MCSC_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU0_MCSC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_VRA, MUX_CLKCMU_CAM_VRA_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_VRA_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2to1_VRA, MUX_CLKCMU_CAM_VRA_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_VRA_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_DIV2, DIV_CLK_CAM_BUSD_DIV2, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_DIV2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_DIV2_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_DIV2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_DIV2, DIV_CLK_CAM_BUSD_DIV2, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_DIV2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_DIV2_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_DIV2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_DIV2, DIV_CLK_CAM_BUSD_DIV2, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_DIV2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_DIV2_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_DIV2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_DIV2, DIV_CLK_CAM_BUSD_DIV2, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_DIV2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_DIV2_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_DIV2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU0, MUX_CLKCMU_CAM_TPU0_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_VRA, MUX_CLKCMU_CAM_VRA_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_VRA_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_0, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_1, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM1, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU0, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_VRA, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_VRA_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_D_CAM0_4x1, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_D_CAM0_4X1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_D_CAM0_4X1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_D_CAM0_4X1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_P_CAM_1x2, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_P_CAM_1X2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_P_CAM_1X2_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_P_CAM_1X2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_MC_SCALER, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_MC_SCALER_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_MC_SCALER_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_MC_SCALER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSISX4_DMA, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSISX4_DMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSISX4_DMA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSISX4_DMA_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_MCSC_VRA, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_MCSC_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_MCSC_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_MCSC_VRA_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPLP_CAM, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPLP_CAM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPLP_CAM_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPLP_CAM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPHQ_CAM, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPHQ_CAM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPHQ_CAM_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPHQ_CAM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU0, MUX_CLKCMU_CAM_TPU0_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_VRA, MUX_CLKCMU_CAM_VRA_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_VRA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_VRA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_VRA_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_ACLK, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BNS, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BNS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BNS_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BNS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_BNS, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_BNS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_BNS_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_BNS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_RSTnSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_RSTnSYNC_CLK_CAM_BUSD_DIV2_IPCLKPORT_CLK, DIV_CLK_CAM_BUSD_DIV2, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_DIV2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_DIV2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_DIV2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_RSTnSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_RSTnSYNC_CLK_CAM_TPU0_IPCLKPORT_CLK, MUX_CLKCMU_CAM_TPU0_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_RSTnSYNC_CLK_CAM_VRA_IPCLKPORT_CLK, MUX_CLKCMU_CAM_VRA_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_VRA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_VRA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_VRA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSISX4_DMA, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSISX4_DMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSISX4_DMA_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSISX4_DMA_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK, DIV_CLK_CAM_BUSP, CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU1, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU1, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU1, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU1, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU1_MCSC, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU1_MCSC_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU1_MCSC_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU1_MCSC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU1, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU1, MUX_CLKCMU_CAM_TPU1_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2to1_ISP_TPU1, MUX_CLKCMU_CAM_TPU1_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1to2_TPU1_MCSC, MUX_CLKCMU_CAM_TPU1_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU1_MCSC_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU1_MCSC_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU1_MCSC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU1, MUX_CLKCMU_CAM_TPU1_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU1, MUX_CLKCMU_CAM_TPU1_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_PCLK, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_PCLK, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_RSTnSYNC_CLK_CAM_TPU1_IPCLKPORT_CLK, MUX_CLKCMU_CAM_TPU1_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS0, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS1, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS3, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS3_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS3_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS3_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS2, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS2_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS0, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS0_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS1, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS1_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS2, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS2_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS3, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS3_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS3_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS3_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_PMU_CAM_IPCLKPORT_PCLK, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_PMU_CAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_PMU_CAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_PMU_CAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_LHM_ATB_SRDZCAM_IPCLKPORT_I_CLK, MUX_CLKCMU_CAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_ATB_SRDZCAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_ATB_SRDZCAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_ATB_SRDZCAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CAM_UID_ISP_EWGEN_CAM_IPCLKPORT_I_PCLK, DIV_CLK_CAM_BUSP, CLK_CON_GAT_GOUT_BLK_CAM_UID_ISP_EWGEN_CAM_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_ISP_EWGEN_CAM_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CAM_UID_ISP_EWGEN_CAM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_APM_BUS, MUX_CLKCMU_APM_BUS, CLK_CON_GAT_GATE_CLKCMU_APM_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_APM_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_FSYS0_BUS, MUX_CLKCMU_FSYS0_BUS, CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLKCMU_MIF_SWITCH, MUX_CLKCMU_MIF_SWITCH, CLK_CON_GAT_CLKCMU_MIF_SWITCH_CG_VAL, CLK_CON_GAT_CLKCMU_MIF_SWITCH_MANUAL, CLK_CON_GAT_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_MFC_BUS, MUX_CLKCMU_MFC_BUS, CLK_CON_GAT_GATE_CLKCMU_MFC_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MFC_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MFC_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_G2D_G2D, MUX_CLKCMU_G2D_G2D, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_FSYS0_USBDRD30, MUX_CLKCMU_FSYS0_USBDRD30, CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDRD30_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDRD30_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDRD30_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_FSYS0_MMC_EMBD, MUX_CLKCMU_FSYS0_MMC_EMBD, CLK_CON_GAT_GATE_CLKCMU_FSYS0_MMC_EMBD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_MMC_EMBD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_FSYS0_UFS_EMBD, MUX_CLKCMU_FSYS0_UFS_EMBD, CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_FSYS1_BUS, MUX_CLKCMU_FSYS1_BUS, CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_FSYS1_MMC_CARD, MUX_CLKCMU_FSYS1_MMC_CARD, CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_DPU_BUS, MUX_CLKCMU_DPU_BUS, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_G3D_SWITCH, PLL_SHARED2, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERIS_BUS, MUX_CLKCMU_PERIS_BUS, CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_VPU_BUS, MUX_CLKCMU_VPU_BUS, CLK_CON_GAT_GATE_CLKCMU_VPU_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_VPU_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_VPU_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_DSP_BUS, MUX_CLKCMU_DSP_BUS, CLK_CON_GAT_GATE_CLKCMU_DSP_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DSP_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DSP_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERIC0_BUS, MUX_CLKCMU_PERIC0_BUS, CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERIC0_UART_DBG, MUX_CLKCMU_PERIC0_UART_DBG, CLK_CON_GAT_GATE_CLKCMU_PERIC0_UART_DBG_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_UART_DBG_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_UART_DBG_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERIC0_USI00, MUX_CLKCMU_PERIC0_USI00, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI00_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI00_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI00_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERIC0_USI01, MUX_CLKCMU_PERIC0_USI01, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI01_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI01_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI01_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERIC0_USI02, MUX_CLKCMU_PERIC0_USI02, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI02_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI02_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI02_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERIC1_USI05, MUX_CLKCMU_PERIC1_USI05, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI05_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI05_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI05_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERIC1_UART_BT, MUX_CLKCMU_PERIC1_UART_BT, CLK_CON_GAT_GATE_CLKCMU_PERIC1_UART_BT_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_UART_BT_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERIC1_USI04, MUX_CLKCMU_PERIC1_USI04, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI04_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI04_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI04_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERIC1_BUS, MUX_CLKCMU_PERIC1_BUS, CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERIC1_USI06, MUX_CLKCMU_PERIC1_USI06, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI06_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI06_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI06_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERIC1_USI10, MUX_CLKCMU_PERIC1_USI10, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI10_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI10_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI10_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERIC1_USI11, MUX_CLKCMU_PERIC1_USI11, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI11_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI11_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI11_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERIC1_USI12, MUX_CLKCMU_PERIC1_USI12, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI12_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI12_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI12_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERIC1_USI13, MUX_CLKCMU_PERIC1_USI13, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI13_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI13_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI13_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_BUSC_BUS, MUX_CLKCMU_BUSC_BUS, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERIC1_USI08, MUX_CLKCMU_PERIC1_USI08, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI08_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI08_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI08_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERIC1_USI07, MUX_CLKCMU_PERIC1_USI07, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI07_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI07_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI07_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERIC0_USI03, MUX_CLKCMU_PERIC0_USI03, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI03_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI03_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI03_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_BUS1_BUS, MUX_CLKCMU_BUS1_BUS, CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERIC1_USI09, MUX_CLKCMU_PERIC1_USI09, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI09_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI09_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI09_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CPUCL1_SWITCH, MUX_CLKCMU_CPUCL1_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CPUCL0_SWITCH, MUX_CLKCMU_CPUCL0_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CORE_BUS, MUX_CLKCMU_CORE_BUS, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CAM_BUS, MUX_CLKCMU_CAM_BUS, CLK_CON_GAT_GATE_CLKCMU_CAM_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CAM_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CAM_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CAM_TPU0, MUX_CLKCMU_CAM_TPU0, CLK_CON_GAT_GATE_CLKCMU_CAM_TPU0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CAM_TPU0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CAM_TPU0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CAM_TPU1, MUX_CLKCMU_CAM_TPU1, CLK_CON_GAT_GATE_CLKCMU_CAM_TPU1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CAM_TPU1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CAM_TPU1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_ISPLP_BUS, MUX_CLKCMU_ISPLP_BUS, CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_ISPHQ_BUS, MUX_CLKCMU_ISPHQ_BUS, CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_ABOX_CPUABOX, MUX_CLKCMU_ABOX_CPUABOX, CLK_CON_GAT_GATE_CLKCMU_ABOX_CPUABOX_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ABOX_CPUABOX_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ABOX_CPUABOX_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_G2D_JPEG, MUX_CLKCMU_G2D_JPEG, CLK_CON_GAT_GATE_CLKCMU_G2D_JPEG_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G2D_JPEG_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G2D_JPEG_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_HPM, MUX_CLKCMU_HPM, CLK_CON_GAT_GATE_CLKCMU_HPM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HPM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_FSYS1_PCIE, MUX_CLKCMU_FSYS1_PCIE, CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_DBG_BUS, MUX_CLKCMU_DBG_BUS, CLK_CON_GAT_GATE_CLKCMU_DBG_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DBG_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERIC1_SPI_CAM0, MUX_CLKCMU_PERIC1_SPI_CAM0, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERIC1_SPI_CAM1, MUX_CLKCMU_PERIC1_SPI_CAM1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLKCMU_DROOPDETECTOR, MUX_CLKCMU_DROOPDETECTOR, CLK_CON_GAT_CLKCMU_DROOPDETECTOR_CG_VAL, CLK_CON_GAT_CLKCMU_DROOPDETECTOR_MANUAL, CLK_CON_GAT_CLKCMU_DROOPDETECTOR_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CIS_CLK0, MUX_CLKCMU_CIS_CLK0, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CIS_CLK1, MUX_CLKCMU_CIS_CLK1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CIS_CLK3, MUX_CLKCMU_CIS_CLK3, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CIS_CLK2, MUX_CLKCMU_CIS_CLK2, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_IVA_BUS, MUX_CLKCMU_IVA_BUS, CLK_CON_GAT_GATE_CLKCMU_IVA_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_IVA_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_IVA_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_FSYS1_UFS_CARD, MUX_CLKCMU_FSYS1_UFS_CARD, CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_BUSC_BUSPHSI2C, MUX_CLKCMU_BUSC_BUSPHSI2C, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUSPHSI2C_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUSPHSI2C_MANUAL, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUSPHSI2C_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CAM_VRA, MUX_CLKCMU_CAM_VRA, CLK_CON_GAT_GATE_CLKCMU_CAM_VRA_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CAM_VRA_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CAM_VRA_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERIC1_SPEEDY2, MUX_CLKCMU_PERIC1_SPEEDY2, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPEEDY2_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPEEDY2_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPEEDY2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_FSYS0_DPGTC, MUX_CLKCMU_FSYS0_DPGTC, CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_MODEM_SHARED0, DIV_PLL_SHARED0_DIV2, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_MODEM_SHARED1, PLL_SHARED2, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_DCAM_BUS, MUX_CLKCMU_DCAM_BUS, CLK_CON_GAT_GATE_CLKCMU_DCAM_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DCAM_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DCAM_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_IMEM_BUS, MUX_CLKCMU_IMEM_BUS, CLK_CON_GAT_GATE_CLKCMU_IMEM_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_IMEM_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_IMEM_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_SRDZ_IMGD, MUX_CLKCMU_SRDZ_IMGD, CLK_CON_GAT_GATE_CLKCMU_SRDZ_IMGD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_SRDZ_IMGD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_SRDZ_IMGD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_SRDZ_BUS, MUX_CLKCMU_SRDZ_BUS, CLK_CON_GAT_GATE_CLKCMU_SRDZ_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_SRDZ_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_SRDZ_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_DCAM_IMGD, MUX_CLKCMU_DCAM_IMGD, CLK_CON_GAT_GATE_CLKCMU_DCAM_IMGD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DCAM_IMGD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DCAM_IMGD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_PMU_CORE_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PMU_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PMU_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PMU_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_pclk, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_CCI_IPCLKPORT_clk, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LHM_CPACE_D_CPUCL0_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_CPACE_D_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_CPACE_D_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_CPACE_D_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF0_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF1_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF2_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF3_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF3_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF3_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_RSTnSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LHM_DBG_G0_DMC_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G0_DMC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G0_DMC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G0_DMC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LHM_DBG_G1_DMC_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G1_DMC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G1_DMC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G1_DMC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LHM_DBG_G2_DMC_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G2_DMC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G2_DMC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G2_DMC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LHM_DBG_G3_DMC_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G3_DMC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G3_DMC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G3_DMC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_APBBR_CCI_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_APBBR_CCI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_APBBR_CCI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_APBBR_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_pclk, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_DBG_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DBG_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DBG_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DBG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_IMEM_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_IMEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_IMEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_IMEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_pclk, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_UID_BUSIF_DROOPDETECTOR_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DROOPDETECTOR_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DROOPDETECTOR_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DROOPDETECTOR_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP0_IPCLKPORT_CK_IN, CLKCMU_DROOPDETECTOR, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP0_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP0_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP0_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP1_IPCLKPORT_CK_IN, CLKCMU_DROOPDETECTOR, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP1_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP1_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP1_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLK_CPUCL0_CPU, DIV_CLK_CPUCL0_CPU, CLK_CON_GAT_GATE_CLK_CPUCL0_CPU_CG_VAL, CLK_CON_GAT_GATE_CLK_CPUCL0_CPU_MANUAL, CLK_CON_GAT_GATE_CLK_CPUCL0_CPU_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_UID_RSTnSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL1_UID_PMU_CPUCL1_IPCLKPORT_PCLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_PMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_PMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_PMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLK_CPUCL1_CPU, DIV_CLK_CPUCL1_CPU, CLK_CON_GAT_GATE_CLK_CPUCL1_CPU_CG_VAL, CLK_CON_GAT_GATE_CLK_CPUCL1_CPU_MANUAL, CLK_CON_GAT_GATE_CLK_CPUCL1_CPU_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL1_UID_RSTnSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK, DIV_CLK_CPUCL1_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_DBG_UID_DBG_CMU_DBG_IPCLKPORT_PCLK, DIV_CLK_DBG_PCLKDBG, CLK_CON_GAT_CLK_BLK_DBG_UID_DBG_CMU_DBG_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DBG_UID_DBG_CMU_DBG_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DBG_UID_DBG_CMU_DBG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_LHM_AXI_P_DBG_IPCLKPORT_I_CLK, DIV_CLK_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_AXI_P_DBG_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_AXI_P_DBG_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_AXI_P_DBG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK, MUX_CLKCMU_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK, MUX_CLKCMU_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK, MUX_CLKCMU_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK, MUX_CLKCMU_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK, MUX_CLKCMU_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_AXI2APB_CORESIGHT_IPCLKPORT_ACLK, DIV_CLK_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_DBG_UID_AXI2APB_CORESIGHT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_AXI2APB_CORESIGHT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_AXI2APB_CORESIGHT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK, MUX_CLKCMU_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_PCLK, DIV_CLK_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_ATCLK, MUX_CLKCMU_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_ATCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_ATCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_ATCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_ATCLK, MUX_CLKCMU_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_ATCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_ATCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_PCLKDBG, DIV_CLK_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_PCLKDBG_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_PCLKDBG_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_SECJTAG_IPCLKPORT_i_clk, DIV_CLK_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_DBG_UID_SECJTAG_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_SECJTAG_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_SECJTAG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK, MUX_CLKCMU_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_PMU_DBG_IPCLKPORT_PCLK, DIV_CLK_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_DBG_UID_PMU_DBG_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_PMU_DBG_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_PMU_DBG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_SYSREG_DBG_IPCLKPORT_PCLK, DIV_CLK_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_DBG_UID_SYSREG_DBG_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_SYSREG_DBG_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_SYSREG_DBG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK, DIV_CLK_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_RSTnSYNC_CLK_DBG_ATCLK_IPCLKPORT_CLK, MUX_CLKCMU_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_ATCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_ATCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_RSTnSYNC_CLK_DBG_PCLKDBG_IPCLKPORT_CLK, DIV_CLK_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_DUMPPC_CPUCL0_IPCLKPORT_I_PCLK, DIV_CLK_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DBG_UID_DUMPPC_CPUCL1_IPCLKPORT_I_PCLK, DIV_CLK_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_DCAM_UID_DCAM_CMU_DCAM_IPCLKPORT_PCLK, DIV_CLK_DCAM_BUSP, CLK_CON_GAT_CLK_BLK_DCAM_UID_DCAM_CMU_DCAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DCAM_UID_DCAM_CMU_DCAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DCAM_UID_DCAM_CMU_DCAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DCAM_UID_DCP_IPCLKPORT_Clk, MUX_CLKCMU_DCAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DCAM_UID_DCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_DCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_DCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DCAM_UID_PMU_DCAM_IPCLKPORT_PCLK, DIV_CLK_DCAM_BUSP, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PMU_DCAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PMU_DCAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PMU_DCAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DCAM_UID_SYSREG_DCAM_IPCLKPORT_PCLK, DIV_CLK_DCAM_BUSP, CLK_CON_GAT_GOUT_BLK_DCAM_UID_SYSREG_DCAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_SYSREG_DCAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_SYSREG_DCAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DCAM_UID_AXI2APB_DCAM_IPCLKPORT_ACLK, DIV_CLK_DCAM_BUSP, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DCAM_UID_AXI2APB_DCAM_SYS_IPCLKPORT_ACLK, DIV_CLK_DCAM_BUSP, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_SYS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_SYS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_SYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKS, DIV_CLK_DCAM_BUSP, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKM, MUX_CLKCMU_DCAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DCAM_UID_XIU_P_DCAM_IPCLKPORT_ACLK, DIV_CLK_DCAM_BUSP, CLK_CON_GAT_GOUT_BLK_DCAM_UID_XIU_P_DCAM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_XIU_P_DCAM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_XIU_P_DCAM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_ACLK, MUX_CLKCMU_DCAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_PCLK, DIV_CLK_DCAM_BUSP, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DCAM_UID_LHM_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK, DIV_CLK_DCAM_BUSP, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHM_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHM_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHM_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DCAM_UID_LHS_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK, MUX_CLKCMU_DCAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DCAM_UID_PXL_ASBM_DCAM_IPCLKPORT_CLK, MUX_CLKCMU_DCAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBM_DCAM_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBM_DCAM_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBM_DCAM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DCAM_UID_RSTnSYNC_CLK_DCAM_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_DCAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DCAM_UID_RSTnSYNC_CLK_DCAM_BUSP_IPCLKPORT_CLK, DIV_CLK_DCAM_BUSP, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DCAM_UID_PXL_ASBS_DCAM_IPCLKPORT_CLK, MUX_CLKCMU_DCAM_IMGD_USER, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBS_DCAM_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBS_DCAM_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBS_DCAM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DCAM_UID_LHS_ATB_DCAMSRDZ_IPCLKPORT_I_CLK, MUX_CLKCMU_DCAM_IMGD_USER, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_ATB_DCAMSRDZ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_ATB_DCAMSRDZ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_ATB_DCAMSRDZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DCAM_UID_RSTnSYNC_CLK_DCAM_IMGD_IPCLKPORT_CLK, MUX_CLKCMU_DCAM_IMGD_USER, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_IMGD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_IMGD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_IMGD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_ACLK, MUX_CLKCMU_DCAM_BUS_USER, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_PCLK, DIV_CLK_DCAM_BUSP, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLKCMU_DPU1_BUSD, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_CLKCMU_DPU1_BUSD_CG_VAL, CLK_CON_GAT_CLKCMU_DPU1_BUSD_MANUAL, CLK_CON_GAT_CLKCMU_DPU1_BUSD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLKCMU_DPU1_BUSP, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_CLKCMU_DPU1_BUSP_CG_VAL, CLK_CON_GAT_CLKCMU_DPU1_BUSP_MANUAL, CLK_CON_GAT_CLKCMU_DPU1_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_DPU0_UID_DPU0_CMU_DPU0_IPCLKPORT_PCLK, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_CLK_BLK_DPU0_UID_DPU0_CMU_DPU0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPU0_UID_DPU0_CMU_DPU0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPU0_UID_DPU0_CMU_DPU0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_DECON0_IPCLKPORT_ACLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DECON0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DECON0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DECON0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_ACLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_PCLK, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_ACLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_PCLK, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_PMU_DPU0_IPCLKPORT_PCLK, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_PMU_DPU0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_PMU_DPU0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_PMU_DPU0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_SYSREG_DPU0_IPCLKPORT_PCLK, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSREG_DPU0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSREG_DPU0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSREG_DPU0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_AXI2APB_DPU0P1_IPCLKPORT_ACLK, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_AXI2APB_DPU0P0_IPCLKPORT_ACLK, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_SECURE, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_NONSECURE, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_NONSECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_NONSECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_ACLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_SECURE, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_NONSECURE, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_NONSECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_NONSECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_LHM_AXI_P0_DPU_IPCLKPORT_I_CLK, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHM_AXI_P0_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHM_AXI_P0_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHM_AXI_P0_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_XIU_P0_DPU_IPCLKPORT_ACLK, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_XIU_P0_DPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_XIU_P0_DPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_XIU_P0_DPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKS, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKM, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKS, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKM, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKS, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKM, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_VGR_ACLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_VGR_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_VGR_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_VGR_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G0_ACLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G0_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G0_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G0_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G1_ACLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G1_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G1_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G1_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_DPU_WB_MUX_IPCLKPORT_DPP_G1_ACLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_WB_MUX_IPCLKPORT_DPP_G1_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_WB_MUX_IPCLKPORT_DPP_G1_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_WB_MUX_IPCLKPORT_DPP_G1_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH0, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH0_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH0_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH1, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH1_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH1_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH2, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH2_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH2_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_WB, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_WB_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_WB_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_WB_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH_INTF, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH_INTF_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH_INTF_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH_INTF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_SFR, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_SFR_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_SFR_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_SFR_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_LHS_AXI_D_USBTV_IPCLKPORT_I_CLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D_USBTV_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D_USBTV_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D_USBTV_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_ACLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_PCLK, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_ACLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_SECURE, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_NONSECURE, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_NONSECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_NONSECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKM, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_ACLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_ACLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_PCLK, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_ACLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_PCLK, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_ACLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_PCLK, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_RSTnSYNC_CLK_DPU0_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU0_UID_RSTnSYNC_CLK_DPU0_BUSP_IPCLKPORT_CLK, DIV_CLK_DPU0_BUSP, CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_DPU1_UID_DPU1_CMU_DPU1_IPCLKPORT_PCLK, MUX_CLKCMU_DPU1_BUSP_USER, CLK_CON_GAT_CLK_BLK_DPU1_UID_DPU1_CMU_DPU1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPU1_UID_DPU1_CMU_DPU1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPU1_UID_DPU1_CMU_DPU1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU1_UID_DECON1_IPCLKPORT_ACLK, MUX_CLKCMU_DPU1_BUSD_USER, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_ACLK, MUX_CLKCMU_DPU1_BUSD_USER, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU1_UID_SYSREG_DPU1_IPCLKPORT_PCLK, MUX_CLKCMU_DPU1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_DPU1_UID_SYSREG_DPU1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_SYSREG_DPU1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_SYSREG_DPU1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU1_UID_PMU_DPU1_IPCLKPORT_PCLK, MUX_CLKCMU_DPU1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_DPU1_UID_PMU_DPU1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_PMU_DPU1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_PMU_DPU1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU1_UID_AXI2APB_DPU1P0_IPCLKPORT_ACLK, MUX_CLKCMU_DPU1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AXI2APB_DPU1P0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AXI2APB_DPU1P0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AXI2APB_DPU1P0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU1_UID_LHM_AXI_P_DPU1_IPCLKPORT_I_CLK, MUX_CLKCMU_DPU1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_DPU1_UID_LHM_AXI_P_DPU1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_LHM_AXI_P_DPU1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_LHM_AXI_P_DPU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKS, MUX_CLKCMU_DPU1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKM, MUX_CLKCMU_DPU1_BUSD_USER, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKS, MUX_CLKCMU_DPU1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKM, MUX_CLKCMU_DPU1_BUSD_USER, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU1_UID_RSTnSYNC_CLK_DPU1_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_DPU1_BUSD_USER, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU1_UID_RSTnSYNC_CLK_DPU1_BUSP_IPCLKPORT_CLK, MUX_CLKCMU_DPU1_BUSP_USER, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU1_UID_RSTnSYNC_CLK_DPU1_DECON2_IPCLKPORT_CLK, DIV_CLKCMU_DPU1_DECON2, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_DECON2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_DECON2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_DECON2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_VCLK, DIV_CLKCMU_DPU1_DECON2, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_VCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_VCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_VCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK, DIV_CLK_DSP_BUSP, CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_SCORE_IPCLKPORT_clk, MUX_CLKCMU_DSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSP_UID_SCORE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_SCORE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_SCORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_PMU_DSP_IPCLKPORT_PCLK, DIV_CLK_DSP_BUSP, CLK_CON_GAT_GOUT_BLK_DSP_UID_PMU_DSP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_PMU_DSP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_PMU_DSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK, DIV_CLK_DSP_BUSP, CLK_CON_GAT_GOUT_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_AXI2APB_DSP_IPCLKPORT_ACLK, DIV_CLK_DSP_BUSP, CLK_CON_GAT_GOUT_BLK_DSP_UID_AXI2APB_DSP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_AXI2APB_DSP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_AXI2APB_DSP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKS, DIV_CLK_DSP_BUSP, CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKM, MUX_CLKCMU_DSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_XIU_D_DSP0_IPCLKPORT_ACLK, MUX_CLKCMU_DSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_ACLK, MUX_CLKCMU_DSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_PCLK, DIV_CLK_DSP_BUSP, CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_ACLK, MUX_CLKCMU_DSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_NONSECURE, DIV_CLK_DSP_BUSP, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_NONSECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_NONSECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_ACLK, MUX_CLKCMU_DSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_LHM_AXI_P_DSP_IPCLKPORT_I_CLK, DIV_CLK_DSP_BUSP, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_DSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_DSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_DSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_PCLK, DIV_CLK_DSP_BUSP, CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_SECURE, DIV_CLK_DSP_BUSP, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_LHS_ACEL_D_DSP_IPCLKPORT_I_CLK, MUX_CLKCMU_DSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_ACEL_D_DSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_ACEL_D_DSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_ACEL_D_DSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_RSTnSYNC_CLK_DSP_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_DSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_RSTnSYNC_CLK_DSP_BUSP_IPCLKPORT_CLK, DIV_CLK_DSP_BUSP, CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_XIU_D_DSP1_IPCLKPORT_ACLK, MUX_CLKCMU_DSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_XIU_P_DSP_IPCLKPORT_ACLK, MUX_CLKCMU_DSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_P_DSP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_P_DSP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_P_DSP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_LHM_AXI_D_IVADSP_IPCLKPORT_I_CLK, MUX_CLKCMU_DSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_IVADSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_IVADSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_IVADSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_LHM_AXI_D_VPUDSP_IPCLKPORT_I_CLK, MUX_CLKCMU_DSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_VPUDSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_VPUDSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_VPUDSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_LHM_AXI_P_IVADSP_IPCLKPORT_I_CLK, MUX_CLKCMU_DSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_IVADSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_IVADSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_IVADSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_LHS_AXI_P_DSPIVA_IPCLKPORT_I_CLK, MUX_CLKCMU_DSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPIVA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPIVA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPIVA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_LHS_AXI_P_DSPVPU_IPCLKPORT_I_CLK, MUX_CLKCMU_DSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPVPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPVPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPVPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSP_UID_WRAP2_CONV_DSP_IPCLKPORT_I_CLK, MUX_CLKCMU_DSP_BUS_USER, CLK_CON_GAT_GOUT_BLK_DSP_UID_WRAP2_CONV_DSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_WRAP2_CONV_DSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSP_UID_WRAP2_CONV_DSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_LHS_ACEL_D_FSYS0_IPCLKPORT_I_CLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHS_ACEL_D_FSYS0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHS_ACEL_D_FSYS0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHS_ACEL_D_FSYS0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_AHBBR_FSYS0_IPCLKPORT_HCLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AHBBR_FSYS0_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AHBBR_FSYS0_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AHBBR_FSYS0_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_LHM_AXI_G_ETR_IPCLKPORT_I_CLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_G_ETR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_G_ETR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_G_ETR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_LHM_AXI_P_FSYS0_IPCLKPORT_I_CLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_P_FSYS0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_P_FSYS0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_P_FSYS0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_LHM_AXI_D_USBTV_IPCLKPORT_I_CLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_D_USBTV_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_D_USBTV_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_D_USBTV_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_US_D_FSYS0_USB_IPCLKPORT_aclk, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_US_D_FSYS0_USB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_US_D_FSYS0_USB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_US_D_FSYS0_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_AXI2AHB_FSYS0_IPCLKPORT_aclk, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_FSYS0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_FSYS0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_FSYS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_AXI2AHB_USB_FSYS0_IPCLKPORT_aclk, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_USB_FSYS0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_USB_FSYS0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_USB_FSYS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_AXI2APB_FSYS0_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2APB_FSYS0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2APB_FSYS0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2APB_FSYS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_ACLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_PCLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_GPIO_FSYS0_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_GPIO_FSYS0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_GPIO_FSYS0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_GPIO_FSYS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_I_ACLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_SDCLKIN, MUX_CLKCMU_FSYS0_MMC_EMBD_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_PMU_FSYS0_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PMU_FSYS0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PMU_FSYS0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PMU_FSYS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_SYSREG_FSYS0_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_SYSREG_FSYS0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_SYSREG_FSYS0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_SYSREG_FSYS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_ACLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, MUX_CLKCMU_FSYS0_UFS_EMBD_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_USB_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_USB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_USB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_XIU_P_FSYS0_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_P_FSYS0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_P_FSYS0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_P_FSYS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_CORE_CLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_CORE_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_CORE_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_CORE_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_SUSPEND_CLK, MUX_CLKCMU_FSYS0_USBDRD30_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_SUSPEND_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_SUSPEND_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_SUSPEND_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_REF_CLK, MUX_CLKCMU_FSYS0_USBDRD30_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_REF_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_REF_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_REF_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_ACLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_PCLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_AHB_CLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_AHB_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_AHB_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_AHB_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_XIU_CLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_XIU_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_XIU_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_XIU_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_ACLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_RSTnSYNC_CLK_FSYS0_BUS_IPCLKPORT_CLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_RSTNSYNC_CLK_FSYS0_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_RSTNSYNC_CLK_FSYS0_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_RSTNSYNC_CLK_FSYS0_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_PCLK, MUX_CLKCMU_FSYS0_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_GTC_EXT_CLK, MUX_CLKCMU_FSYS0_DPGTC_USER, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_GTC_EXT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_GTC_EXT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_GTC_EXT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN, MUX_CLKCMU_FSYS1_MMC_CARD_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_ieee1500_wrapper_for_pcie_phy_lc_x2_inst_0_i_scl_apb_pclk, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_TOE_WIFI0_IPCLKPORT_i_CLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_TOE_WIFI1_IPCLKPORT_i_CLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_i_ACLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_i_PCLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_i_PCLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_i_ACLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_PMU_FSYS1_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PMU_FSYS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PMU_FSYS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PMU_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_PCLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_aclk, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_FSYS1_UID_PCIE_IPCLKPORT_phy_ref_clk_in, MUX_CLKCMU_FSYS1_PCIE_USER, CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_IPCLKPORT_PHY_REF_CLK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_IPCLKPORT_PHY_REF_CLK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_IPCLKPORT_PHY_REF_CLK_IN_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_slv_aclk_0, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_0_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_0_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_mstr_aclk_0, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_0_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_0_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_dbi_aclk_0, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_0_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_0_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_pcie_sub_ctrl_inst_0_i_driver_apb_clk, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_pipe2_digital_x2_wrap_inst_0_i_apb_pclk_scl, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_RSTnSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_mstr_aclk_1, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_1_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_1_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_slv_aclk_1, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_1_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_1_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_dbi_aclk_1, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_1_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_1_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_pcie_sub_ctrl_inst_1_i_driver_apb_clk, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO, MUX_CLKCMU_FSYS1_UFS_CARD_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, MUX_CLKCMU_FSYS1_BUS_USER, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_PCLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_PCLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_NONSECURE, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_NONSECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_NONSECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_LHS_ACEL_D0_G2D_IPCLKPORT_I_CLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D0_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D0_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D0_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_LHS_ACEL_D1_G2D_IPCLKPORT_I_CLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D1_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D1_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D1_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKM, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKS, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_AXI2APB_G2DP0_IPCLKPORT_ACLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_G2D_IPCLKPORT_Clk, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_NONSECURE, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_NONSECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_NONSECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_PMU_G2D_IPCLKPORT_PCLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_PMU_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PMU_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PMU_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_ACLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_ACLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_XIU_P_G2D_IPCLKPORT_ACLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_P_G2D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_P_G2D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_P_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_AXI2APB_G2DP1_IPCLKPORT_ACLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_PCLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_PCLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK, MUX_CLKCMU_G2D_JPEG_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_M2MSCALER_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_JPEG_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_M2MSCALER_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_M2MSCALER_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_M2MSCALER_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_ACLK, MUX_CLKCMU_G2D_JPEG_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_PCLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_JPEG_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_PCLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_JPEG_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_PCLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_JPEG_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_NONSECURE, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_NONSECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_NONSECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_JPEG_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_PCLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_LHS_ACEL_D2_G2D_IPCLKPORT_I_CLK, MUX_CLKCMU_G2D_JPEG_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D2_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D2_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D2_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKM, MUX_CLKCMU_G2D_JPEG_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKS, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_XIU_D_G2D_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_JPEG_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_G2D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_G2D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_SECURE, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_SECURE, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_SECURE, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKS, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKM, MUX_CLKCMU_G2D_JPEG_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_RSTnSYNC_CLK_G2D_G2D_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_RSTnSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK, DIV_CLK_G2D_BUSP, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G2D_UID_RSTnSYNC_CLK_G2D_JPEG_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_G2D_JPEG_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_JPEG_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_JPEG_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_JPEG_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_PMU_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_PMU_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_PMU_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_PMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_RSTnSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLK_G3D_AGPU, MUX_CLK_G3D_BUSD, CLK_CON_GAT_GATE_CLK_G3D_AGPU_CG_VAL, CLK_CON_GAT_GATE_CLK_G3D_AGPU_MANUAL, CLK_CON_GAT_GATE_CLK_G3D_AGPU_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IMEM_UID_LHM_AXI_P_IMEM_IPCLKPORT_I_CLK, MUX_CLKCMU_IMEM_BUS_USER, CLK_CON_GAT_GOUT_BLK_IMEM_UID_LHM_AXI_P_IMEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_LHM_AXI_P_IMEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_LHM_AXI_P_IMEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IMEM_UID_RSTnSYNC_CLK_IMEM_BUS_IPCLKPORT_CLK, MUX_CLKCMU_IMEM_BUS_USER, CLK_CON_GAT_GOUT_BLK_IMEM_UID_RSTNSYNC_CLK_IMEM_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_RSTNSYNC_CLK_IMEM_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_RSTNSYNC_CLK_IMEM_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IMEM_UID_AXI2APB_IMEM_IPCLKPORT_ACLK, MUX_CLKCMU_IMEM_BUS_USER, CLK_CON_GAT_GOUT_BLK_IMEM_UID_AXI2APB_IMEM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_AXI2APB_IMEM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_AXI2APB_IMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IMEM_UID_XIU_P_IMEM_IPCLKPORT_ACLK, MUX_CLKCMU_IMEM_BUS_USER, CLK_CON_GAT_GOUT_BLK_IMEM_UID_XIU_P_IMEM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_XIU_P_IMEM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_XIU_P_IMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IMEM_UID_SYSREG_IMEM_IPCLKPORT_PCLK, MUX_CLKCMU_IMEM_BUS_USER, CLK_CON_GAT_GOUT_BLK_IMEM_UID_SYSREG_IMEM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_SYSREG_IMEM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_SYSREG_IMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IMEM_UID_PMU_IMEM_IPCLKPORT_PCLK, MUX_CLKCMU_IMEM_BUS_USER, CLK_CON_GAT_GOUT_BLK_IMEM_UID_PMU_IMEM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_PMU_IMEM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_PMU_IMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_IMEM_UID_IMEM_CMU_IMEM_IPCLKPORT_PCLK, MUX_CLKCMU_IMEM_BUS_USER, CLK_CON_GAT_CLK_BLK_IMEM_UID_IMEM_CMU_IMEM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_IMEM_UID_IMEM_CMU_IMEM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_IMEM_UID_IMEM_CMU_IMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IMEM_UID_IntMEM_IPCLKPORT_ACLK, MUX_CLKCMU_IMEM_BUS_USER, CLK_CON_GAT_GOUT_BLK_IMEM_UID_INTMEM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_INTMEM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IMEM_UID_INTMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_TAA_ACLK, MUX_CLKCMU_ISPHQ_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_TAA_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_TAA_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_TAA_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPHQ_UID_LHM_AXI_P_ISPHQ_IPCLKPORT_I_CLK, DIV_CLK_ISPHQ_BUSP, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHM_AXI_P_ISPHQ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHM_AXI_P_ISPHQ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHM_AXI_P_ISPHQ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPHQ_UID_LHS_AXI_LD_ISPHQ_IPCLKPORT_I_CLK, MUX_CLKCMU_ISPHQ_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHS_AXI_LD_ISPHQ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHS_AXI_LD_ISPHQ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHS_AXI_LD_ISPHQ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_ISPHQ_ACLK, MUX_CLKCMU_ISPHQ_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_ISPHQ_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_ISPHQ_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_ISPHQ_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_ACLK, MUX_CLKCMU_ISPHQ_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_ACLK, MUX_CLKCMU_ISPHQ_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_XIU_D_ISPHQ_ACLK, MUX_CLKCMU_ISPHQ_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_XIU_D_ISPHQ_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_XIU_D_ISPHQ_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_XIU_D_ISPHQ_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_AXI2APB_BRIDGE_ISPHQ_ACLK, DIV_CLK_ISPHQ_BUSP, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_AXI2APB_BRIDGE_ISPHQ_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_AXI2APB_BRIDGE_ISPHQ_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_AXI2APB_BRIDGE_ISPHQ_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPHQ_UID_RSTnSYNC_CLK_ISPHQ_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_ISPHQ_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPHQ_UID_RSTnSYNC_CLK_ISPHQ_BUSP_IPCLKPORT_CLK, DIV_CLK_ISPHQ_BUSP, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKM, MUX_CLKCMU_ISPHQ_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKM, MUX_CLKCMU_ISPHQ_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKS, DIV_CLK_ISPHQ_BUSP, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKS, DIV_CLK_ISPHQ_BUSP, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_PCLK, DIV_CLK_ISPHQ_BUSP, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_PCLK, DIV_CLK_ISPHQ_BUSP, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPHQ_UID_PMU_ISPHQ_IPCLKPORT_PCLK, DIV_CLK_ISPHQ_BUSP, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_PMU_ISPHQ_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_PMU_ISPHQ_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_PMU_ISPHQ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPHQ_UID_SYSREG_ISPHQ_IPCLKPORT_PCLK, DIV_CLK_ISPHQ_BUSP, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_SYSREG_ISPHQ_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_SYSREG_ISPHQ_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_SYSREG_ISPHQ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_ISPHQ_UID_ISPHQ_CMU_ISPHQ_IPCLKPORT_PCLK, DIV_CLK_ISPHQ_BUSP, CLK_CON_GAT_CLK_BLK_ISPHQ_UID_ISPHQ_CMU_ISPHQ_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ISPHQ_UID_ISPHQ_CMU_ISPHQ_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ISPHQ_UID_ISPHQ_CMU_ISPHQ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPHQ_UID_ISP_EWGEN_ISPHQ_IPCLKPORT_I_PCLK, DIV_CLK_ISPHQ_BUSP, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_ISP_EWGEN_ISPHQ_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_ISP_EWGEN_ISPHQ_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_ISP_EWGEN_ISPHQ_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_TAAW_ACLK, MUX_CLKCMU_ISPLP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_TAAW_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_TAAW_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_TAAW_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_LHM_AXI_P_ISPLP_IPCLKPORT_I_CLK, DIV_CLK_ISPLP_BUSP, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_P_ISPLP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_P_ISPLP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_P_ISPLP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_LHS_AXI_D_ISPLP_IPCLKPORT_I_CLK, MUX_CLKCMU_ISPLP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHS_AXI_D_ISPLP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHS_AXI_D_ISPLP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHS_AXI_D_ISPLP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_ACLK, MUX_CLKCMU_ISPLP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_ISPLP_ACLK, MUX_CLKCMU_ISPLP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_ISPLP_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_ISPLP_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_ISPLP_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_ACLK, MUX_CLKCMU_ISPLP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_XIU_D_ISPLP_ACLK, MUX_CLKCMU_ISPLP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_XIU_D_ISPLP_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_XIU_D_ISPLP_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_XIU_D_ISPLP_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_ACLK, MUX_CLKCMU_ISPLP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_ACLK, MUX_CLKCMU_ISPLP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_RSTnSYNC_CLK_ISPLP_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_ISPLP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_RSTnSYNC_CLK_ISPLP_BUSP_IPCLKPORT_CLK, DIV_CLK_ISPLP_BUSP, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKM, MUX_CLKCMU_ISPLP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKM, MUX_CLKCMU_ISPLP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_PCLK, DIV_CLK_ISPLP_BUSP, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKS, DIV_CLK_ISPLP_BUSP, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKS, DIV_CLK_ISPLP_BUSP, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_PCLK, DIV_CLK_ISPLP_BUSP, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_PCLK, DIV_CLK_ISPLP_BUSP, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_PCLK, DIV_CLK_ISPLP_BUSP, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_NONSECURE, DIV_CLK_ISPLP_BUSP, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_NONSECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_NONSECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_SECURE, DIV_CLK_ISPLP_BUSP, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_PMU_ISPLP_IPCLKPORT_PCLK, DIV_CLK_ISPLP_BUSP, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_PMU_ISPLP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_PMU_ISPLP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_PMU_ISPLP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_SYSREG_ISPLP_IPCLKPORT_PCLK, DIV_CLK_ISPLP_BUSP, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_SYSREG_ISPLP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_SYSREG_ISPLP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_SYSREG_ISPLP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_AXI2APB_BRIDGE_ISPLP_ACLK, DIV_CLK_ISPLP_BUSP, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_AXI2APB_BRIDGE_ISPLP_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_AXI2APB_BRIDGE_ISPLP_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_AXI2APB_BRIDGE_ISPLP_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_ISPLP_UID_ISPLP_CMU_ISPLP_IPCLKPORT_PCLK, DIV_CLK_ISPLP_BUSP, CLK_CON_GAT_CLK_BLK_ISPLP_UID_ISPLP_CMU_ISPLP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ISPLP_UID_ISPLP_CMU_ISPLP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ISPLP_UID_ISPLP_CMU_ISPLP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_LHM_AXI_LD_ISPHQ_IPCLKPORT_I_CLK, MUX_CLKCMU_ISPLP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_LD_ISPHQ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_LD_ISPHQ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_LD_ISPHQ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_ISP_EWGEN_ISPLP_IPCLKPORT_I_PCLK, DIV_CLK_ISPLP_BUSP, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_ISP_EWGEN_ISPLP_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_ISP_EWGEN_ISPLP_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_ISP_EWGEN_ISPLP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_ACLK, MUX_CLKCMU_ISPLP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK, DIV_CLK_IVA_BUSP, CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IVA_UID_LHS_ACEL_D_IVA_IPCLKPORT_I_CLK, MUX_CLKCMU_IVA_BUS_USER, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_ACEL_D_IVA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_ACEL_D_IVA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_ACEL_D_IVA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IVA_UID_LHS_AXI_D_IVADSP_IPCLKPORT_I_CLK, MUX_CLKCMU_IVA_BUS_USER, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_D_IVADSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_D_IVADSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_D_IVADSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IVA_UID_LHS_AXI_P_IVADSP_IPCLKPORT_I_CLK, MUX_CLKCMU_IVA_BUS_USER, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_P_IVADSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_P_IVADSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_P_IVADSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IVA_UID_LHM_AXI_P_DSPIVA_IPCLKPORT_I_CLK, MUX_CLKCMU_IVA_BUS_USER, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_DSPIVA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_DSPIVA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_DSPIVA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK, DIV_CLK_IVA_BUSP, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_ACLK, MUX_CLKCMU_IVA_BUS_USER, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK, DIV_CLK_IVA_BUSP, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_ACLK, MUX_CLKCMU_IVA_BUS_USER, CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_PCLK, DIV_CLK_IVA_BUSP, CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_ACLK, MUX_CLKCMU_IVA_BUS_USER, CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_PCLK, DIV_CLK_IVA_BUSP, CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IVA_UID_XIU_D_IVA_IPCLKPORT_ACLK, MUX_CLKCMU_IVA_BUS_USER, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_D_IVA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_D_IVA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_D_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK, DIV_CLK_IVA_BUSP, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKS, DIV_CLK_IVA_BUSP, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKM, MUX_CLKCMU_IVA_BUS_USER, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK, DIV_CLK_IVA_BUSP, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK, DIV_CLK_IVA_BUSP, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK, DIV_CLK_IVA_BUSP, CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IVA_UID_PMU_IVA_IPCLKPORT_PCLK, DIV_CLK_IVA_BUSP, CLK_CON_GAT_GOUT_BLK_IVA_UID_PMU_IVA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_PMU_IVA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_PMU_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IVA_UID_IVA_IPCLKPORT_clk_a, MUX_CLKCMU_IVA_BUS_USER, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_CLK_A_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_CLK_A_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_CLK_A_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IVA_UID_RSTnSYNC_CLK_IVA_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_IVA_BUS_USER, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IVA_UID_RSTnSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK, DIV_CLK_IVA_BUSP, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IVA_UID_IVA_IntMEM_IPCLKPORT_ACLK, MUX_CLKCMU_IVA_BUS_USER, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_INTMEM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_INTMEM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_INTMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_IVA_UID_LHM_AXI_D_IVASC_IPCLKPORT_I_CLK, MUX_CLKCMU_IVA_BUS_USER, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_D_IVASC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_D_IVASC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_D_IVASC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_MFC_IPCLKPORT_Clk, MUX_CLKCMU_MFC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKS, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKM, MUX_CLKCMU_MFC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_AXI2APB_MFC_IPCLKPORT_ACLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_AXI2APB_MFC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AXI2APB_MFC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AXI2APB_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_PMU_MFC_IPCLKPORT_PCLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_PMU_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PMU_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PMU_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_LHS_AXI_D0_MFC_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D0_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D0_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D0_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_LHS_AXI_D1_MFC_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D1_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D1_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D1_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_ACLK, MUX_CLKCMU_MFC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_SECURE, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_ACLK, MUX_CLKCMU_MFC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_SECURE, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_ACLK, MUX_CLKCMU_MFC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_PCLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_ACLK, MUX_CLKCMU_MFC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_PCLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK, MUX_CLKCMU_MFC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK, MUX_CLKCMU_MFC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_NONSECURE, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_NONSECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_NONSECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_NONSECURE, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_NONSECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_NONSECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_RSTnSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_MFC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_RSTnSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_PMU_MIF_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_PMU_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PMU_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PMU_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_AXI2APB_MIF_IPCLKPORT_ACLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_MIF_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_MIF_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_MIF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_APBBR_DMCTZ_IPCLKPORT_PCLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMCTZ_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMCTZ_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMCTZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK1, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK1_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK2, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK2_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF_UID_DMC_IPCLKPORT_soc_clk, CLK_MIF_BUSD, CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_SOC_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_SOC_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_SOC_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF_UID_LHM_PSCDC_D_MIF_IPCLKPORT_I_CLK, CLK_MIF_BUSD, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_PSCDC_D_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_PSCDC_D_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_PSCDC_D_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_ACLK, CLK_MIF_BUSD, CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_clk, CLK_MIF_BUSD, CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF_UID_RSTnSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK, CLK_MIF_BUSD, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_RSTnSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK, DIV_CLK_MIF_BUSP, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK, DIV_CLK_MIF1_BUSP, CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF1_UID_APBBR_DDRPHY1_IPCLKPORT_PCLK, DIV_CLK_MIF1_BUSP, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DDRPHY1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DDRPHY1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DDRPHY1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF1_UID_APBBR_DMC1_IPCLKPORT_PCLK, DIV_CLK_MIF1_BUSP, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF1_UID_APBBR_DMCTZ1_IPCLKPORT_PCLK, DIV_CLK_MIF1_BUSP, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMCTZ1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMCTZ1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMCTZ1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF1_UID_AXI2APB_MIF1_IPCLKPORT_ACLK, DIV_CLK_MIF1_BUSP, CLK_CON_GAT_GOUT_BLK_MIF1_UID_AXI2APB_MIF1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_AXI2APB_MIF1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_AXI2APB_MIF1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK, DIV_CLK_MIF1_BUSP, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF1_UID_DDRPHY1_IPCLKPORT_PCLK, DIV_CLK_MIF1_BUSP, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DDRPHY1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DDRPHY1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DDRPHY1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK1, DIV_CLK_MIF1_BUSP, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK1_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK2, DIV_CLK_MIF1_BUSP, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK2_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF1_UID_LHM_AXI_P_MIF1_IPCLKPORT_I_CLK, DIV_CLK_MIF1_BUSP, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_P_MIF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_P_MIF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_P_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF1_UID_PMU_MIF1_IPCLKPORT_PCLK, DIV_CLK_MIF1_BUSP, CLK_CON_GAT_GOUT_BLK_MIF1_UID_PMU_MIF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_PMU_MIF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_PMU_MIF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_PCLK, DIV_CLK_MIF1_BUSP, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_PCLK, DIV_CLK_MIF1_BUSP, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF1_UID_SYSREG_MIF1_IPCLKPORT_PCLK, DIV_CLK_MIF1_BUSP, CLK_CON_GAT_GOUT_BLK_MIF1_UID_SYSREG_MIF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_SYSREG_MIF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_SYSREG_MIF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF1_UID_RSTnSYNC_CLK_MIF_BUSP1_IPCLKPORT_CLK, DIV_CLK_MIF1_BUSP, CLK_CON_GAT_GOUT_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSP1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSP1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSP1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF1_UID_DMC1_IPCLKPORT_soc_clk, CLK_MIF1_BUSD, CLK_CON_GAT_CLK_BLK_MIF1_UID_DMC1_IPCLKPORT_SOC_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_DMC1_IPCLKPORT_SOC_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_DMC1_IPCLKPORT_SOC_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF1_UID_LHM_PSCDC_D_MIF1_IPCLKPORT_I_CLK, CLK_MIF1_BUSD, CLK_CON_GAT_CLK_BLK_MIF1_UID_LHM_PSCDC_D_MIF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_LHM_PSCDC_D_MIF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_LHM_PSCDC_D_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_ACLK, CLK_MIF1_BUSD, CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_clk, CLK_MIF1_BUSD, CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF1_UID_RSTnSYNC_CLK_MIF_BUSD1_IPCLKPORT_CLK, CLK_MIF1_BUSD, CLK_CON_GAT_CLK_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSD1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSD1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSD1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF2_UID_MIF2_CMU_MIF2_IPCLKPORT_PCLK, DIV_CLK_MIF2_BUSP, CLK_CON_GAT_CLK_BLK_MIF2_UID_MIF2_CMU_MIF2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_MIF2_CMU_MIF2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_MIF2_CMU_MIF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF2_UID_HPM_MIF2_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_MIF2_UID_HPM_MIF2_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_HPM_MIF2_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_HPM_MIF2_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF2_UID_APBBR_DDRPHY2_IPCLKPORT_PCLK, DIV_CLK_MIF2_BUSP, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DDRPHY2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DDRPHY2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DDRPHY2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF2_UID_APBBR_DMC2_IPCLKPORT_PCLK, DIV_CLK_MIF2_BUSP, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMC2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMC2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF2_UID_APBBR_DMCTZ2_IPCLKPORT_PCLK, DIV_CLK_MIF2_BUSP, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMCTZ2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMCTZ2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMCTZ2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF2_UID_AXI2APB_MIF2_IPCLKPORT_ACLK, DIV_CLK_MIF2_BUSP, CLK_CON_GAT_GOUT_BLK_MIF2_UID_AXI2APB_MIF2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_AXI2APB_MIF2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_AXI2APB_MIF2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF2_UID_BUSIF_HPMMIF2_IPCLKPORT_PCLK, DIV_CLK_MIF2_BUSP, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BUSIF_HPMMIF2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BUSIF_HPMMIF2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BUSIF_HPMMIF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF2_UID_DDRPHY2_IPCLKPORT_PCLK, DIV_CLK_MIF2_BUSP, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DDRPHY2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DDRPHY2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DDRPHY2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK1, DIV_CLK_MIF2_BUSP, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK1_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK2, DIV_CLK_MIF2_BUSP, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK2_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF2_UID_LHM_AXI_P_MIF2_IPCLKPORT_I_CLK, DIV_CLK_MIF2_BUSP, CLK_CON_GAT_GOUT_BLK_MIF2_UID_LHM_AXI_P_MIF2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_LHM_AXI_P_MIF2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_LHM_AXI_P_MIF2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF2_UID_PMU_MIF2_IPCLKPORT_PCLK, DIV_CLK_MIF2_BUSP, CLK_CON_GAT_GOUT_BLK_MIF2_UID_PMU_MIF2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_PMU_MIF2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_PMU_MIF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_PCLK, DIV_CLK_MIF2_BUSP, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_PCLK, DIV_CLK_MIF2_BUSP, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF2_UID_RSTnSYNC_CLK_MIF_BUSP2_IPCLKPORT_CLK, DIV_CLK_MIF2_BUSP, CLK_CON_GAT_GOUT_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSP2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSP2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSP2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF2_UID_SYSREG_MIF2_IPCLKPORT_PCLK, DIV_CLK_MIF2_BUSP, CLK_CON_GAT_GOUT_BLK_MIF2_UID_SYSREG_MIF2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_SYSREG_MIF2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF2_UID_SYSREG_MIF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF2_UID_DMC2_IPCLKPORT_soc_clk, CLK_MIF2_BUSD, CLK_CON_GAT_CLK_BLK_MIF2_UID_DMC2_IPCLKPORT_SOC_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_DMC2_IPCLKPORT_SOC_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_DMC2_IPCLKPORT_SOC_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF2_UID_LHM_PSCDC_D_MIF2_IPCLKPORT_I_CLK, CLK_MIF2_BUSD, CLK_CON_GAT_CLK_BLK_MIF2_UID_LHM_PSCDC_D_MIF2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_LHM_PSCDC_D_MIF2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_LHM_PSCDC_D_MIF2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_ACLK, CLK_MIF2_BUSD, CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_clk, CLK_MIF2_BUSD, CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF2_UID_RSTnSYNC_CLK_MIF_BUSD2_IPCLKPORT_CLK, CLK_MIF2_BUSD, CLK_CON_GAT_CLK_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSD2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSD2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSD2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF3_UID_HPM_MIF3_IPCLKPORT_hpm_targetclk_c, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_MIF3_UID_HPM_MIF3_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF3_UID_HPM_MIF3_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_MIF3_UID_HPM_MIF3_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF3_UID_APBBR_DDRPHY3_IPCLKPORT_PCLK, DIV_CLK_MIF3_BUSP, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DDRPHY3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DDRPHY3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DDRPHY3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF3_UID_APBBR_DMC3_IPCLKPORT_PCLK, DIV_CLK_MIF3_BUSP, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMC3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMC3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMC3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF3_UID_APBBR_DMCTZ3_IPCLKPORT_PCLK, DIV_CLK_MIF3_BUSP, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMCTZ3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMCTZ3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMCTZ3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF3_UID_AXI2APB_MIF3_IPCLKPORT_ACLK, DIV_CLK_MIF3_BUSP, CLK_CON_GAT_GOUT_BLK_MIF3_UID_AXI2APB_MIF3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_AXI2APB_MIF3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_AXI2APB_MIF3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF3_UID_BUSIF_HPMMIF3_IPCLKPORT_PCLK, DIV_CLK_MIF3_BUSP, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BUSIF_HPMMIF3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BUSIF_HPMMIF3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BUSIF_HPMMIF3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF3_UID_DDRPHY3_IPCLKPORT_PCLK, DIV_CLK_MIF3_BUSP, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DDRPHY3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DDRPHY3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DDRPHY3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK1, DIV_CLK_MIF3_BUSP, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK1_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF3_UID_LHM_AXI_P_MIF3_IPCLKPORT_I_CLK, DIV_CLK_MIF3_BUSP, CLK_CON_GAT_GOUT_BLK_MIF3_UID_LHM_AXI_P_MIF3_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_LHM_AXI_P_MIF3_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_LHM_AXI_P_MIF3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF3_UID_PMU_MIF3_IPCLKPORT_PCLK, DIV_CLK_MIF3_BUSP, CLK_CON_GAT_GOUT_BLK_MIF3_UID_PMU_MIF3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_PMU_MIF3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_PMU_MIF3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_PCLK, DIV_CLK_MIF3_BUSP, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_PCLK, DIV_CLK_MIF3_BUSP, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF3_UID_RSTnSYNC_CLK_MIF_BUSP3_IPCLKPORT_CLK, DIV_CLK_MIF3_BUSP, CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSP3_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSP3_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSP3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF3_UID_SYSREG_MIF3_IPCLKPORT_PCLK, DIV_CLK_MIF3_BUSP, CLK_CON_GAT_GOUT_BLK_MIF3_UID_SYSREG_MIF3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_SYSREG_MIF3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_SYSREG_MIF3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK2, DIV_CLK_MIF3_BUSP, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK2_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF3_UID_MIF3_CMU_MIF3_IPCLKPORT_PCLK, DIV_CLK_MIF3_BUSP, CLK_CON_GAT_CLK_BLK_MIF3_UID_MIF3_CMU_MIF3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF3_UID_MIF3_CMU_MIF3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF3_UID_MIF3_CMU_MIF3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF3_UID_DMC3_IPCLKPORT_soc_clk, CLK_MIF3_BUSD, CLK_CON_GAT_CLK_BLK_MIF3_UID_DMC3_IPCLKPORT_SOC_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF3_UID_DMC3_IPCLKPORT_SOC_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF3_UID_DMC3_IPCLKPORT_SOC_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF3_UID_LHM_PSCDC_D_MIF3_IPCLKPORT_I_CLK, CLK_MIF3_BUSD, CLK_CON_GAT_CLK_BLK_MIF3_UID_LHM_PSCDC_D_MIF3_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF3_UID_LHM_PSCDC_D_MIF3_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF3_UID_LHM_PSCDC_D_MIF3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_ACLK, CLK_MIF3_BUSD, CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_clk, CLK_MIF3_BUSD, CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF3_UID_RSTnSYNC_CLK_MIF_BUSD3_IPCLKPORT_CLK, CLK_MIF3_BUSD, CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSD3_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSD3_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSD3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC0_UID_PMU_PERIC0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PMU_PERIC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PMU_PERIC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PMU_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_i_PCLK_S0, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_EXT_UCLK, MUX_CLKCMU_PERIC0_UART_DBG_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_EXT_UCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_EXT_UCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_EXT_UCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_i_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_i_SCLK_USI, MUX_CLKCMU_PERIC0_USI00_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_i_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_i_SCLK_USI, MUX_CLKCMU_PERIC0_USI01_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_i_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_i_SCLK_USI, MUX_CLKCMU_PERIC0_USI02_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_i_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_i_SCLK_USI, MUX_CLKCMU_PERIC0_USI03_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0_IPCLKPORT_ACLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC0_UID_RSTnSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC0_UID_SPEEDY2_TSP_IPCLKPORT_clk, MUX_CLKCMU_PERIC0_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SPEEDY2_TSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SPEEDY2_TSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SPEEDY2_TSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_PMU_PERIC1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PMU_PERIC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PMU_PERIC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PMU_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_i_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_i_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_i_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_i_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_i_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_i_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_i_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_i_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_i_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_EXT_UCLK, MUX_CLKCMU_PERIC1_UART_BT_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_EXT_UCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_EXT_UCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_EXT_UCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_i_SCLK_USI, MUX_CLKCMU_PERIC1_USI10_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_i_SCLK_USI, MUX_CLKCMU_PERIC1_USI11_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_i_SCLK_USI, MUX_CLKCMU_PERIC1_USI12_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_i_SCLK_USI, MUX_CLKCMU_PERIC1_USI13_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_i_SCLK_USI, MUX_CLKCMU_PERIC1_USI04_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_i_SCLK_USI, MUX_CLKCMU_PERIC1_USI05_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_i_SCLK_USI, MUX_CLKCMU_PERIC1_USI06_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_i_SCLK_USI, MUX_CLKCMU_PERIC1_USI07_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_i_SCLK_USI, MUX_CLKCMU_PERIC1_USI08_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_i_SCLK_USI, MUX_CLKCMU_PERIC1_USI09_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_SCLK_USI_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_SCLK_USI_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_HSI2C_CAM2_IPCLKPORT_iPCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM2_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM2_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_HSI2C_CAM3_IPCLKPORT_iPCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM3_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM3_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_SPI_EXT_CLK, MUX_CLKCMU_PERIC1_SPI_CAM0_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_SPI_EXT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_SPI_EXT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_SPI_EXT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_SPI_EXT_CLK, MUX_CLKCMU_PERIC1_SPI_CAM1_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_SPI_EXT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_SPI_EXT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_SPI_EXT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_i_PCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_HSI2C_CAM1_IPCLKPORT_iPCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM1_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM1_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_HSI2C_CAM0_IPCLKPORT_iPCLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_clk, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_sclk, MUX_CLKCMU_PERIC1_SPEEDY2_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_SCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_SCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_PERIC1_UID_RSTnSYNC_CLK_PERIC1_SPEEDY2_IPCLKPORT_CLK, MUX_CLKCMU_PERIC1_SPEEDY2_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPEEDY2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPEEDY2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPEEDY2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_clk, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_sclk, MUX_CLKCMU_PERIC1_SPEEDY2_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_SCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_SCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_clk, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_sclk, MUX_CLKCMU_PERIC1_SPEEDY2_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_SCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_SCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_SPEEDY2_TSP1_IPCLKPORT_clk, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_SPEEDY2_TSP2_IPCLKPORT_clk, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P2_IPCLKPORT_ACLK, MUX_CLKCMU_PERIC1_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_AXI2APB_PERISP0_IPCLKPORT_ACLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_AXI2APB_PERISP1_IPCLKPORT_ACLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_PMU_PERIS_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_PMU_PERIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_PMU_PERIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_PMU_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_TZPC00_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC00_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC00_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_TZPC01_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC01_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC01_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC01_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_TZPC10_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC10_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC10_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC10_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_TZPC11_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC11_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC11_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC11_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_TZPC12_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC12_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC12_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC12_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_TZPC13_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC13_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC13_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC13_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_TZPC14_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC14_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC14_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC14_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_TZPC15_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC15_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC15_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC15_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_TZPC02_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC02_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC02_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC02_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_TZPC03_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC03_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC03_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC03_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_TZPC04_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC04_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC04_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC04_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_TZPC05_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC05_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC05_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC05_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_TZPC06_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC06_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC06_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC06_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_TZPC07_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC07_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC07_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC07_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_TZPC08_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC08_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC08_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC08_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_TZPC09_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC09_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC09_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC09_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_RSTnSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_RSTnSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK, MUX_CLK_PERIS_GIC, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM, MUX_CLK_PERIS_GIC, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK, MUX_CLK_PERIS_GIC, CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_SRDZ_UID_SRDZ_CMU_SRDZ_IPCLKPORT_PCLK, DIV_CLK_SRDZ_BUSP, CLK_CON_GAT_CLK_BLK_SRDZ_UID_SRDZ_CMU_SRDZ_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SRDZ_UID_SRDZ_CMU_SRDZ_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_SRDZ_UID_SRDZ_CMU_SRDZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_RSTnSYNC_CLK_SRDZ_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_SRDZ_BUS_USER, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_RSTnSYNC_CLK_SRDZ_BUSP_IPCLKPORT_CLK, DIV_CLK_SRDZ_BUSP, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_RSTnSYNC_CLK_SRDZ_IMGD_IPCLKPORT_CLK, MUX_CLKCMU_SRDZ_IMGD_USER, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_IMGD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_IMGD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_IMGD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_SRDZ_IPCLKPORT_Clk, MUX_CLKCMU_SRDZ_BUS_USER, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SRDZ_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SRDZ_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SRDZ_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_PMU_SRDZ_IPCLKPORT_PCLK, DIV_CLK_SRDZ_BUSP, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PMU_SRDZ_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PMU_SRDZ_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PMU_SRDZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_SYSREG_SRDZ_IPCLKPORT_PCLK, DIV_CLK_SRDZ_BUSP, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SYSREG_SRDZ_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SYSREG_SRDZ_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SYSREG_SRDZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_IPCLKPORT_ACLK, DIV_CLK_SRDZ_BUSP, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_SYS_IPCLKPORT_ACLK, DIV_CLK_SRDZ_BUSP, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_SYS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_SYS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_SYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKS, DIV_CLK_SRDZ_BUSP, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKM, MUX_CLKCMU_SRDZ_BUS_USER, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_XIU_D_SRDZ_IPCLKPORT_ACLK, MUX_CLKCMU_SRDZ_BUS_USER, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_D_SRDZ_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_D_SRDZ_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_D_SRDZ_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_XIU_P_SRDZ_IPCLKPORT_ACLK, DIV_CLK_SRDZ_BUSP, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_P_SRDZ_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_P_SRDZ_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_P_SRDZ_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_ACLK, MUX_CLKCMU_SRDZ_BUS_USER, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_PCLK, DIV_CLK_SRDZ_BUSP, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_ACLK, MUX_CLKCMU_SRDZ_BUS_USER, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_NONSECURE, DIV_CLK_SRDZ_BUSP, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_NONSECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_NONSECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_SECURE, DIV_CLK_SRDZ_BUSP, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_ACLK, MUX_CLKCMU_SRDZ_BUS_USER, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_PCLK, DIV_CLK_SRDZ_BUSP, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_LHM_AXI_P_SRDZ_IPCLKPORT_I_CLK, DIV_CLK_SRDZ_BUSP, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_P_SRDZ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_P_SRDZ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_P_SRDZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_LHS_AXI_D_SRDZ_IPCLKPORT_I_CLK, MUX_CLKCMU_SRDZ_BUS_USER, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_D_SRDZ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_D_SRDZ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_D_SRDZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_LHS_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK, DIV_CLK_SRDZ_BUSP, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_LHM_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK, MUX_CLKCMU_SRDZ_BUS_USER, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_LHS_ATB_SRDZCAM_IPCLKPORT_I_CLK, MUX_CLKCMU_SRDZ_IMGD_USER, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_ATB_SRDZCAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_ATB_SRDZCAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_ATB_SRDZCAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_LHM_ATB_DCAMSRDZ_IPCLKPORT_I_CLK, MUX_CLKCMU_SRDZ_BUS_USER, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_ATB_DCAMSRDZ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_ATB_DCAMSRDZ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_ATB_DCAMSRDZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_PXL_ASBM_1to2_SRDZ_IPCLKPORT_CLK, MUX_CLKCMU_SRDZ_BUS_USER, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBM_1TO2_SRDZ_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBM_1TO2_SRDZ_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBM_1TO2_SRDZ_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_SRDZ_UID_PXL_ASBS_SRDZ_IPCLKPORT_CLK, MUX_CLKCMU_SRDZ_IMGD_USER, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBS_SRDZ_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBS_SRDZ_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBS_SRDZ_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_VPU_UID_VPU_CMU_VPU_IPCLKPORT_PCLK, DIV_CLK_VPU_BUSP, CLK_CON_GAT_CLK_BLK_VPU_UID_VPU_CMU_VPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VPU_UID_VPU_CMU_VPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VPU_UID_VPU_CMU_VPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VPU_UID_VPU_IPCLKPORT_HCLK, DIV_CLK_VPU_BUSP, CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VPU_UID_VPU_IPCLKPORT_Clk, MUX_CLKCMU_VPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VPU_UID_PMU_VPU_IPCLKPORT_PCLK, DIV_CLK_VPU_BUSP, CLK_CON_GAT_GOUT_BLK_VPU_UID_PMU_VPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_PMU_VPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_PMU_VPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VPU_UID_SYSREG_VPU_IPCLKPORT_PCLK, DIV_CLK_VPU_BUSP, CLK_CON_GAT_GOUT_BLK_VPU_UID_SYSREG_VPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_SYSREG_VPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_SYSREG_VPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VPU_UID_AXI2APB_VPU_IPCLKPORT_ACLK, DIV_CLK_VPU_BUSP, CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2APB_VPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2APB_VPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2APB_VPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VPU_UID_XIU_P_VPU_IPCLKPORT_ACLK, DIV_CLK_VPU_BUSP, CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_P_VPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_P_VPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_P_VPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_ACLK, MUX_CLKCMU_VPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_PCLK, DIV_CLK_VPU_BUSP, CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_ACLK, MUX_CLKCMU_VPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_NONSECURE, DIV_CLK_VPU_BUSP, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_NONSECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_NONSECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_ACLK, MUX_CLKCMU_VPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VPU_UID_LHM_AXI_P_VPU_IPCLKPORT_I_CLK, DIV_CLK_VPU_BUSP, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_VPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_VPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_VPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VPU_UID_LHS_ACEL_D_VPU_IPCLKPORT_I_CLK, MUX_CLKCMU_VPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_ACEL_D_VPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_ACEL_D_VPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_ACEL_D_VPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_PCLK, DIV_CLK_VPU_BUSP, CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_SECURE, DIV_CLK_VPU_BUSP, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VPU_UID_AXI2AHB_VPU_IPCLKPORT_aclk, DIV_CLK_VPU_BUSP, CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2AHB_VPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2AHB_VPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2AHB_VPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VPU_UID_RSTnSYNC_CLK_VPU_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_VPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VPU_UID_RSTnSYNC_CLK_VPU_BUSP_IPCLKPORT_CLK, DIV_CLK_VPU_BUSP, CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VPU_UID_XIU_D_VPU_IPCLKPORT_ACLK, MUX_CLKCMU_VPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_D_VPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_D_VPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_D_VPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VPU_UID_LHM_AXI_P_DSPVPU_IPCLKPORT_I_CLK, DIV_CLK_VPU_BUSP, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_DSPVPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_DSPVPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_DSPVPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VPU_UID_LHS_AXI_D_VPUDSP_IPCLKPORT_I_CLK, MUX_CLKCMU_VPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_AXI_D_VPUDSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_AXI_D_VPUDSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_AXI_D_VPUDSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_SYS, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_SYS_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_SYS_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_SYS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_RSTnSYNC_CLK_VTS_BUS_IPCLKPORT_CLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_RSTnSYNC_CLK_VTS_DMICIF_IPCLKPORT_CLK, DIV_CLK_VTS_DMICIF, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMICIF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMICIF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMICIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_CPU, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_CPU_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_CPU_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_CPU_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMICIF_CLK, DIV_CLK_VTS_DMICIF, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMICIF_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMICIF_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMICIF_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_MAILBOX_VTS2AP_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_VTS2AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_VTS2AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_VTS2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_HCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_DIV2_CLK, DIV_CLK_VTS_DMIC_DIV2, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_DIV2_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_DIV2_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_CLK, DIV_CLK_VTS_DMIC, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_CLK_ENABLE_AUTOMATIC_CLKGATING),
};

/*====================The section of FIXED RATEs===================*/
unsigned int cmucal_fixed_rate_size = 53;


struct cmucal_clk_fixed_rate cmucal_fixed_rate_list[] = {
	FIXEDRATE(OSCCLK_ABOX, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(CLKIO_ABOX_UAIF0, 10000000, EMPTY_CAL_ID),
	FIXEDRATE(CLKIO_ABOX_UAIF1, 10000000, EMPTY_CAL_ID),
	FIXEDRATE(CLKIO_ABOX_UAIF2, 10000000, EMPTY_CAL_ID),
	FIXEDRATE(CLKIO_ABOX_UAIF3, 100000000, EMPTY_CAL_ID),
	FIXEDRATE(CLKIO_ABOX_UAIF4, 100000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_APM, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_BUS1, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_BUSC, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_CAM, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_CMU, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_CORE, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_CPUCL0, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(CLUSTER0_ACLKOUT, 100000000, EMPTY_CAL_ID),
	FIXEDRATE(CLUSTER0_ATCLKOUT, 100000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_EMBEDDED_CPUCL0, 100000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_CPUCL1, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(CLK_CLUSTER1_DIV_ACLK, 100000000, EMPTY_CAL_ID),
	FIXEDRATE(CLK_CLUSTER1_DIV_ATCLK, 100000000, EMPTY_CAL_ID),
	FIXEDRATE(CLK_CLUSTER1_DIV_CNTCLK, 100000000, EMPTY_CAL_ID),
	FIXEDRATE(CLK_CLUSTER1_DIV_PCLKDBG, 100000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_EMBEDDED_CPUCL1, 100000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_DBG, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_DCAM, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_DPU0, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(CLK_DEBUG_DECON0, 100000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_DPU1, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(CLK_DEBUG_DECON1, 100000000, EMPTY_CAL_ID),
	FIXEDRATE(CLK_DEBUG_DECON2, 100000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_DSP, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_FSYS0, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_FSYS1, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_G2D, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_G3D, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_EMBEDDED_G3D, 100000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_IMEM, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_ISPHQ, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_ISPLP, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_IVA, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_MFC, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_MIF, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_MIF1, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_MIF2, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_MIF3, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_PERIC0, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_PERIC1, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_PERIS, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_SRDZ, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_VPU, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_VTS, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(RTCCLK_VTS, 32767, EMPTY_CAL_ID),
	FIXEDRATE(OSC_VTS, 49152000, OSC_CON2_OSC_VTS_ENABLE_AUTOMATIC_CLKGATING),
	FIXEDRATE(CP2AP_MIF_CLK, 1066000000, EMPTY_CAL_ID),
};

/*====================The section of FIXED FACTORs===================*/
unsigned int cmucal_fixed_factor_size = 16;


struct cmucal_clk_fixed_factor cmucal_fixed_factor_list[] = {
	FIXEDFACTOR(DIV_CLK_CAM_BUSD_DIV2, MUX_CLKCMU_CAM_BUS_USER, 1, CLK_CON_DIV_DIV_CLK_CAM_BUSD_DIV2_ENABLE_AUTOMATIC_CLKGATING),
	FIXEDFACTOR(DIV_PLL_SHARED0_DIV2, PLL_SHARED0, 1, CLK_CON_DIV_DIV_PLL_SHARED0_DIV2_ENABLE_AUTOMATIC_CLKGATING),
	FIXEDFACTOR(DIV_PLL_SHARED1_DIV2, PLL_SHARED1, 1, CLK_CON_DIV_DIV_PLL_SHARED1_DIV2_ENABLE_AUTOMATIC_CLKGATING),
	FIXEDFACTOR(DIV_PLL_SHARED2_DIV2, PLL_SHARED2, 1, CLK_CON_DIV_DIV_PLL_SHARED2_DIV2_ENABLE_AUTOMATIC_CLKGATING),
	FIXEDFACTOR(DIV_PLL_SHARED3_DIV2, PLL_SHARED3, 1, CLK_CON_DIV_DIV_PLL_SHARED3_DIV2_ENABLE_AUTOMATIC_CLKGATING),
	FIXEDFACTOR(DIV_PLL_SHARED4_DIV2, PLL_SHARED4, 1, CLK_CON_DIV_DIV_PLL_SHARED4_DIV2_ENABLE_AUTOMATIC_CLKGATING),
	FIXEDFACTOR(DIV_PLL_SHARED0_DIV4, DIV_PLL_SHARED0_DIV2, 1, CLK_CON_DIV_DIV_PLL_SHARED0_DIV4_ENABLE_AUTOMATIC_CLKGATING),
	FIXEDFACTOR(CLKCMU_FSYS1_PCIE, GATE_CLKCMU_FSYS1_PCIE, 7, CLK_CON_DIV_CLKCMU_FSYS1_PCIE_ENABLE_AUTOMATIC_CLKGATING),
	FIXEDFACTOR(CLKCMU_OTP, OSCCLK_CMU, 7, CLK_CON_DIV_CLKCMU_OTP_ENABLE_AUTOMATIC_CLKGATING),
	FIXEDFACTOR(DIV_PLL_SHARED1_DIV4, DIV_PLL_SHARED1_DIV2, 1, CLK_CON_DIV_DIV_PLL_SHARED1_DIV4_ENABLE_AUTOMATIC_CLKGATING),
	FIXEDFACTOR(DIV_CP2AP_MIF_CLK_DIV2, MUX_CP2AP_MIF_CLK_USER, 1, CLK_CON_DIV_DIV_CP2AP_MIF_CLK_DIV2_ENABLE_AUTOMATIC_CLKGATING),
	FIXEDFACTOR(CLK_MIF_BUSD, CLKMUX_MIF_DDRPHY2X, 3, CLK_CON_DIV_CLK_MIF_BUSD_ENABLE_AUTOMATIC_CLKGATING),
	FIXEDFACTOR(CLK_MIF1_BUSD, CLKMUX_MIF1_DDRPHY2X, 3, CLK_CON_DIV_CLK_MIF1_BUSD_ENABLE_AUTOMATIC_CLKGATING),
	FIXEDFACTOR(CLK_MIF2_BUSD, CLKMUX_MIF2_DDRPHY2X, 3, CLK_CON_DIV_CLK_MIF2_BUSD_ENABLE_AUTOMATIC_CLKGATING),
	FIXEDFACTOR(CLK_MIF3_BUSD, CLKMUX_MIF3_DDRPHY2X, 3, CLK_CON_DIV_CLK_MIF3_BUSD_ENABLE_AUTOMATIC_CLKGATING),
	FIXEDFACTOR(DIV_CLK_VTS_CMUREF, OSC_VTS, 1, CLK_CON_DIV_DIV_CLK_VTS_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
};