272 lines
7.2 KiB
C
272 lines
7.2 KiB
C
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/*
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* PWM Controller Driver for HiSilicon BVT SoCs
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*
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* Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/reset.h>
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#define PWM_CFG0_ADDR(x) (((x) * 0x20) + 0x0)
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#define PWM_CFG1_ADDR(x) (((x) * 0x20) + 0x4)
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#define PWM_CFG2_ADDR(x) (((x) * 0x20) + 0x8)
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#define PWM_CTRL_ADDR(x) (((x) * 0x20) + 0xC)
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#define PWM_ENABLE_SHIFT 0
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#define PWM_ENABLE_MASK BIT(0)
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#define PWM_POLARITY_SHIFT 1
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#define PWM_POLARITY_MASK BIT(1)
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#define PWM_KEEP_SHIFT 2
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#define PWM_KEEP_MASK BIT(2)
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#define PWM_PERIOD_MASK GENMASK(31, 0)
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#define PWM_DUTY_MASK GENMASK(31, 0)
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struct hibvt_pwm_chip {
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struct pwm_chip chip;
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struct clk *clk;
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void __iomem *base;
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struct reset_control *rstc;
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};
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struct hibvt_pwm_soc {
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u32 num_pwms;
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};
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static const struct hibvt_pwm_soc pwm_soc[2] = {
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{ .num_pwms = 4 },
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{ .num_pwms = 8 },
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};
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static inline struct hibvt_pwm_chip *to_hibvt_pwm_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct hibvt_pwm_chip, chip);
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}
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static void hibvt_pwm_set_bits(void __iomem *base, u32 offset,
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u32 mask, u32 data)
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{
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void __iomem *address = base + offset;
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u32 value;
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value = readl(address);
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value &= ~mask;
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value |= (data & mask);
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writel(value, address);
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}
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static void hibvt_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
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hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
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PWM_ENABLE_MASK, 0x1);
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}
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static void hibvt_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
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hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
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PWM_ENABLE_MASK, 0x0);
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}
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static void hibvt_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_cycle_ns, int period_ns)
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{
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struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
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u32 freq, period, duty;
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freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000);
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period = div_u64(freq * period_ns, 1000);
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duty = div_u64(period * duty_cycle_ns, period_ns);
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hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm),
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PWM_PERIOD_MASK, period);
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hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm),
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PWM_DUTY_MASK, duty);
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}
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static void hibvt_pwm_set_polarity(struct pwm_chip *chip,
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struct pwm_device *pwm,
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enum pwm_polarity polarity)
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{
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struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
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if (polarity == PWM_POLARITY_INVERSED)
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hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
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PWM_POLARITY_MASK, (0x1 << PWM_POLARITY_SHIFT));
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else
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hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
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PWM_POLARITY_MASK, (0x0 << PWM_POLARITY_SHIFT));
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}
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static void hibvt_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
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void __iomem *base;
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u32 freq, value;
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freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000);
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base = hi_pwm_chip->base;
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value = readl(base + PWM_CFG0_ADDR(pwm->hwpwm));
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state->period = div_u64(value * 1000, freq);
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value = readl(base + PWM_CFG1_ADDR(pwm->hwpwm));
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state->duty_cycle = div_u64(value * 1000, freq);
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value = readl(base + PWM_CTRL_ADDR(pwm->hwpwm));
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state->enabled = (PWM_ENABLE_MASK & value);
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}
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static int hibvt_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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if (state->polarity != pwm->state.polarity)
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hibvt_pwm_set_polarity(chip, pwm, state->polarity);
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if (state->period != pwm->state.period ||
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state->duty_cycle != pwm->state.duty_cycle)
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hibvt_pwm_config(chip, pwm, state->duty_cycle, state->period);
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if (state->enabled != pwm->state.enabled) {
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if (state->enabled)
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hibvt_pwm_enable(chip, pwm);
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else
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hibvt_pwm_disable(chip, pwm);
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}
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return 0;
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}
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static const struct pwm_ops hibvt_pwm_ops = {
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.get_state = hibvt_pwm_get_state,
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.apply = hibvt_pwm_apply,
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.owner = THIS_MODULE,
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};
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static int hibvt_pwm_probe(struct platform_device *pdev)
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{
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const struct hibvt_pwm_soc *soc =
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of_device_get_match_data(&pdev->dev);
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struct hibvt_pwm_chip *pwm_chip;
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struct resource *res;
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int ret;
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int i;
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pwm_chip = devm_kzalloc(&pdev->dev, sizeof(*pwm_chip), GFP_KERNEL);
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if (pwm_chip == NULL)
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return -ENOMEM;
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pwm_chip->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(pwm_chip->clk)) {
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dev_err(&pdev->dev, "getting clock failed with %ld\n",
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PTR_ERR(pwm_chip->clk));
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return PTR_ERR(pwm_chip->clk);
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}
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pwm_chip->chip.ops = &hibvt_pwm_ops;
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pwm_chip->chip.dev = &pdev->dev;
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pwm_chip->chip.base = -1;
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pwm_chip->chip.npwm = soc->num_pwms;
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pwm_chip->chip.of_xlate = of_pwm_xlate_with_flags;
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pwm_chip->chip.of_pwm_n_cells = 3;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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pwm_chip->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(pwm_chip->base))
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return PTR_ERR(pwm_chip->base);
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ret = clk_prepare_enable(pwm_chip->clk);
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if (ret < 0)
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return ret;
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pwm_chip->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
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if (IS_ERR(pwm_chip->rstc)) {
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clk_disable_unprepare(pwm_chip->clk);
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return PTR_ERR(pwm_chip->rstc);
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}
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reset_control_assert(pwm_chip->rstc);
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msleep(30);
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reset_control_deassert(pwm_chip->rstc);
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ret = pwmchip_add(&pwm_chip->chip);
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if (ret < 0) {
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clk_disable_unprepare(pwm_chip->clk);
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return ret;
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}
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for (i = 0; i < pwm_chip->chip.npwm; i++) {
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hibvt_pwm_set_bits(pwm_chip->base, PWM_CTRL_ADDR(i),
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PWM_KEEP_MASK, (0x1 << PWM_KEEP_SHIFT));
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}
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platform_set_drvdata(pdev, pwm_chip);
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return 0;
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}
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static int hibvt_pwm_remove(struct platform_device *pdev)
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{
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struct hibvt_pwm_chip *pwm_chip;
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pwm_chip = platform_get_drvdata(pdev);
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reset_control_assert(pwm_chip->rstc);
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msleep(30);
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reset_control_deassert(pwm_chip->rstc);
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clk_disable_unprepare(pwm_chip->clk);
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return pwmchip_remove(&pwm_chip->chip);
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}
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static const struct of_device_id hibvt_pwm_of_match[] = {
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{ .compatible = "hisilicon,hi3516cv300-pwm", .data = &pwm_soc[0] },
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{ .compatible = "hisilicon,hi3519v100-pwm", .data = &pwm_soc[1] },
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{ }
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};
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MODULE_DEVICE_TABLE(of, hibvt_pwm_of_match);
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static struct platform_driver hibvt_pwm_driver = {
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.driver = {
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.name = "hibvt-pwm",
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.of_match_table = hibvt_pwm_of_match,
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},
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.probe = hibvt_pwm_probe,
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.remove = hibvt_pwm_remove,
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};
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module_platform_driver(hibvt_pwm_driver);
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MODULE_AUTHOR("Jian Yuan");
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MODULE_DESCRIPTION("HiSilicon BVT SoCs PWM driver");
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MODULE_LICENSE("GPL");
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