406 lines
14 KiB
C
406 lines
14 KiB
C
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/****************************************************************************
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*
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* Copyright (c) 2014 - 2020 Samsung Electronics Co., Ltd. All rights reserved
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*
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****************************************************************************/
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#ifndef __HIP4_H__
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#define __HIP4_H__
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/**
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* This header file is the public HIP4 interface, which will be accessible by
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* Wi-Fi service driver components.
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*
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* All struct and internal HIP functions shall be moved to a private header
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* file.
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*/
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#include <linux/interrupt.h>
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#include <linux/types.h>
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#include <linux/device.h>
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#include <linux/skbuff.h>
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#include <scsc/scsc_mifram.h>
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#include <scsc/scsc_mx.h>
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#ifdef CONFIG_SCSC_WLAN_RX_NAPI
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#include <linux/netdevice.h>
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#endif
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#ifdef CONFIG_SCSC_WLAN_ANDROID
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#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0))
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#include <scsc/scsc_wakelock.h>
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#else
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#include <linux/wakelock.h>
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#endif
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#endif
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#include "mbulk.h"
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#ifdef CONFIG_SCSC_SMAPPER
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#include "hip4_smapper.h"
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#endif
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/* Shared memory Layout
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*
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* |-------------------------| CONFIG
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* | CONFIG + Queues |
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* | --------- |
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* | MIB |
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* |-------------------------| TX Pool
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* | TX DAT |
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* | --------- |
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* | TX CTL |
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* |-------------------------| RX Pool
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* | RX |
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* |-------------------------|
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*/
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/**** OFFSET SHOULD BE 4096 BYTES ALIGNED ***/
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/*** CONFIG POOL ***/
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#define HIP4_WLAN_CONFIG_OFFSET 0x00000
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#define HIP4_WLAN_CONFIG_SIZE 0x02000 /* 8 kB */
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/*** MIB POOL ***/
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#define HIP4_WLAN_MIB_OFFSET (HIP4_WLAN_CONFIG_OFFSET + HIP4_WLAN_CONFIG_SIZE)
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#define HIP4_WLAN_MIB_SIZE 0x08000 /* 32 kB */
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/*** TX POOL ***/
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#define HIP4_WLAN_TX_OFFSET (HIP4_WLAN_MIB_OFFSET + HIP4_WLAN_MIB_SIZE)
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/*** TX POOL - DAT POOL ***/
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#define HIP4_WLAN_TX_DAT_OFFSET HIP4_WLAN_TX_OFFSET
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#define HIP4_WLAN_TX_DAT_SIZE 0x100000 /* 1 MB */
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/*** TX POOL - CTL POOL ***/
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#define HIP4_WLAN_TX_CTL_OFFSET (HIP4_WLAN_TX_DAT_OFFSET + HIP4_WLAN_TX_DAT_SIZE)
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#define HIP4_WLAN_TX_CTL_SIZE 0x10000 /* 64 kB */
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#define HIP4_WLAN_TX_SIZE (HIP4_WLAN_TX_DAT_SIZE + HIP4_WLAN_TX_CTL_SIZE)
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/*** RX POOL ***/
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#define HIP4_WLAN_RX_OFFSET (HIP4_WLAN_TX_CTL_OFFSET + HIP4_WLAN_TX_CTL_SIZE)
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#ifdef CONFIG_SCSC_PCIE
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#define HIP4_WLAN_RX_SIZE 0x80000 /* 512 kB */
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#else
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#define HIP4_WLAN_RX_SIZE 0x100000 /* 1 MB */
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#endif
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/*** TOTAL : CONFIG POOL + TX POOL + RX POOL ***/
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#define HIP4_WLAN_TOTAL_MEM (HIP4_WLAN_CONFIG_SIZE + HIP4_WLAN_MIB_SIZE + \
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HIP4_WLAN_TX_SIZE + HIP4_WLAN_RX_SIZE) /* 2 MB + 104 KB*/
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#define HIP4_POLLING_MAX_PACKETS 512
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#define HIP4_DAT_MBULK_SIZE (2 * 1024)
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#define HIP4_DAT_SLOTS (HIP4_WLAN_TX_DAT_SIZE / HIP4_DAT_MBULK_SIZE)
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#define HIP4_CTL_MBULK_SIZE (2 * 1024)
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#define HIP4_CTL_SLOTS (HIP4_WLAN_TX_CTL_SIZE / HIP4_CTL_MBULK_SIZE)
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#define MIF_HIP_CFG_Q_NUM 6
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#define MIF_NO_IRQ 0xff
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/* Current versions supported by this HIP */
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#define HIP4_SUPPORTED_V1 3
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#define HIP4_SUPPORTED_V2 4
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enum hip4_hip_q_conf {
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HIP4_MIF_Q_FH_CTRL,
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HIP4_MIF_Q_FH_DAT,
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HIP4_MIF_Q_FH_RFB,
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HIP4_MIF_Q_TH_CTRL,
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HIP4_MIF_Q_TH_DAT,
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HIP4_MIF_Q_TH_RFB
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};
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struct hip4_hip_config_version_4 {
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/* Host owned */
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u32 magic_number; /* 0xcaba0401 */
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u16 hip_config_ver; /* Version of this configuration structure = 2*/
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u16 config_len; /* Size of this configuration structure */
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/* FW owned */
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u32 compat_flag; /* flag of the expected driver's behaviours */
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u16 sap_mlme_ver; /* Fapi SAP_MLME version*/
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u16 sap_ma_ver; /* Fapi SAP_MA version */
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u16 sap_debug_ver; /* Fapi SAP_DEBUG version */
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u16 sap_test_ver; /* Fapi SAP_TEST version */
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u32 fw_build_id; /* Firmware Build Id */
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u32 fw_patch_id; /* Firmware Patch Id */
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u8 unidat_req_headroom; /* Headroom the host shall reserve in mbulk for MA-UNITDATA.REQ signal */
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u8 unidat_req_tailroom; /* Tailroom the host shall reserve in mbulk for MA-UNITDATA.REQ signal */
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u8 bulk_buffer_align; /* 4 */
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/* Host owned */
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u8 host_cache_line; /* 64 */
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u32 host_buf_loc; /* location of the host buffer in MIF_ADDR */
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u32 host_buf_sz; /* in byte, size of the host buffer */
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u32 fw_buf_loc; /* location of the firmware buffer in MIF_ADDR */
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u32 fw_buf_sz; /* in byte, size of the firmware buffer */
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u32 mib_loc; /* MIB location in MIF_ADDR */
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u32 mib_sz; /* MIB size */
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u32 log_config_loc; /* Logging Configuration Location in MIF_ADDR */
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u32 log_config_sz; /* Logging Configuration Size in MIF_ADDR */
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u8 mif_fh_int_n; /* MIF from-host interrupt bit position for all HIP queue */
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u8 reserved1[3];
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u8 mif_th_int_n[6]; /* MIF to-host interrupt bit positions for each HIP queue */
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u8 reserved2[2];
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u32 scbrd_loc; /* Scoreboard locatin in MIF_ADDR */
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u16 q_num; /* 6 */
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u16 q_len; /* 256 */
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u16 q_idx_sz; /* 1 */
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u8 reserved3[2];
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u32 q_loc[MIF_HIP_CFG_Q_NUM];
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#ifdef CONFIG_SCSC_SMAPPER
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u8 smapper_th_req; /* TH smapper request interrupt bit position */
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u8 smapper_fh_ind; /* FH smapper ind interrupt bit position */
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u8 smapper_mbox_scb; /* SMAPPER MBOX scoreboard location */
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u8 smapper_entries_banks[16]; /* num entries banks */
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u8 smapper_pow_sz[16]; /* Power of size of entry i.e. 12 = 4096B */
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u32 smapper_bank_addr[16]; /* Bank start addr */
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#else
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u8 reserved_nosmapper[99];
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#endif
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u8 reserved4[16];
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} __packed;
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struct hip4_hip_config_version_5 {
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/* Host owned */
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u32 magic_number; /* 0xcaba0401 */
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u16 hip_config_ver; /* Version of this configuration structure = 2*/
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u16 config_len; /* Size of this configuration structure */
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/* FW owned */
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u32 compat_flag; /* flag of the expected driver's behaviours */
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u16 sap_mlme_ver; /* Fapi SAP_MLME version*/
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u16 sap_ma_ver; /* Fapi SAP_MA version */
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u16 sap_debug_ver; /* Fapi SAP_DEBUG version */
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u16 sap_test_ver; /* Fapi SAP_TEST version */
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u32 fw_build_id; /* Firmware Build Id */
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u32 fw_patch_id; /* Firmware Patch Id */
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u8 unidat_req_headroom; /* Headroom the host shall reserve in mbulk for MA-UNITDATA.REQ signal */
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u8 unidat_req_tailroom; /* Tailroom the host shall reserve in mbulk for MA-UNITDATA.REQ signal */
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u8 bulk_buffer_align; /* 4 */
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/* Host owned */
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u8 host_cache_line; /* 64 */
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u32 host_buf_loc; /* location of the host buffer in MIF_ADDR */
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u32 host_buf_sz; /* in byte, size of the host buffer */
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u32 fw_buf_loc; /* location of the firmware buffer in MIF_ADDR */
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u32 fw_buf_sz; /* in byte, size of the firmware buffer */
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u32 mib_loc; /* MIB location in MIF_ADDR */
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u32 mib_sz; /* MIB size */
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u32 log_config_loc; /* Logging Configuration Location in MIF_ADDR */
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u32 log_config_sz; /* Logging Configuration Size in MIF_ADDR */
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u8 mif_fh_int_n; /* MIF from-host interrupt bit position */
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u8 mif_th_int_n; /* MIF to-host interrpt bit position */
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u8 reserved[2];
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u32 scbrd_loc; /* Scoreboard locatin in MIF_ADDR */
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u16 q_num; /* 6 */
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u16 q_len; /* 256 */
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u16 q_idx_sz; /* 1 */
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u8 reserved2[2];
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u32 q_loc[MIF_HIP_CFG_Q_NUM];
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u8 reserved3[16];
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} __packed;
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struct hip4_hip_init {
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/* Host owned */
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u32 magic_number; /* 0xcaaa0400 */
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/* FW owned */
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u32 conf_hip4_ver;
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/* Host owned */
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u32 version_a_ref; /* Location of Config structure A (old) */
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u32 version_b_ref; /* Location of Config structure B (new) */
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} __packed;
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#define MAX_NUM 256
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struct hip4_hip_q {
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u32 array[MAX_NUM];
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u8 idx_read; /* To keep track */
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u8 idx_write; /* To keep track */
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u8 total;
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} __aligned(64);
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struct hip4_hip_control {
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struct hip4_hip_init init;
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struct hip4_hip_config_version_5 config_v5 __aligned(32);
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struct hip4_hip_config_version_4 config_v4 __aligned(32);
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u32 scoreboard[256] __aligned(64);
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struct hip4_hip_q q[MIF_HIP_CFG_Q_NUM] __aligned(64);
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} __aligned(4096);
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struct slsi_hip4;
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/* This struct is private to the HIP implementation */
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struct hip4_priv {
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#ifdef CONFIG_SCSC_WLAN_RX_NAPI
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/* NAPI CPU switch lock */
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spinlock_t napi_cpu_lock;
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struct work_struct intr_wq_napi_cpu_switch;
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struct work_struct intr_wq_ctrl;
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struct tasklet_struct intr_tl_fb;
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struct napi_struct napi;
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unsigned long napi_state;
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#else
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struct work_struct intr_wq;
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#endif
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/* Interrupts cache < v4 */
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/* TOHOST */
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u32 intr_tohost;
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/* Interrupts cache v4 */
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u32 intr_tohost_mul[MIF_HIP_CFG_Q_NUM];
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/* FROMHOST */
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u32 intr_fromhost;
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/* For workqueue */
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struct slsi_hip4 *hip;
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/* Pool for data frames*/
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u8 host_pool_id_dat;
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/* Pool for ctl frames*/
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u8 host_pool_id_ctl;
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/* rx cycle lock */
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spinlock_t rx_lock;
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/* tx cycle lock */
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spinlock_t tx_lock;
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/* Scoreboard update spinlock */
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rwlock_t rw_scoreboard;
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/* Watchdog timer */
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struct timer_list watchdog;
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/* wd spinlock */
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spinlock_t watchdog_lock;
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/* wd timer control */
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atomic_t watchdog_timer_active;
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#ifdef CONFIG_SCSC_WLAN_RX_NAPI
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DECLARE_BITMAP(irq_bitmap, MIF_HIP_CFG_Q_NUM);
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#endif
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#ifdef CONFIG_SCSC_WLAN_ANDROID
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#ifdef CONFIG_SCSC_WLAN_RX_NAPI
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#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0))
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struct scsc_wake_lock hip4_wake_lock_tx;
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struct scsc_wake_lock hip4_wake_lock_ctrl;
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struct scsc_wake_lock hip4_wake_lock_data;
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#else
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struct wake_lock hip4_wake_lock_tx;
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struct wake_lock hip4_wake_lock_ctrl;
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struct wake_lock hip4_wake_lock_data;
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#endif
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#endif
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/* Wakelock for modem_ctl */
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#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0))
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struct scsc_wake_lock hip4_wake_lock;
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#else
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struct wake_lock hip4_wake_lock;
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#endif
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#endif
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/* Control the hip4 deinit */
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atomic_t closing;
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atomic_t in_tx;
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atomic_t in_rx;
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atomic_t in_suspend;
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u32 storm_count;
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struct {
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atomic_t irqs;
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atomic_t spurious_irqs;
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u32 q_num_frames[MIF_HIP_CFG_Q_NUM];
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ktime_t start;
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struct proc_dir_entry *procfs_dir;
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} stats;
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#ifdef CONFIG_SCSC_WLAN_HIP4_PROFILING
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/*minor*/
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u32 minor;
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#endif
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u8 unidat_req_headroom; /* Headroom the host shall reserve in mbulk for MA-UNITDATA.REQ signal */
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u8 unidat_req_tailroom; /* Tailroom the host shall reserve in mbulk for MA-UNITDATA.REQ signal */
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u32 version; /* Version of the running FW */
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void *scbrd_base; /* Scbrd_base pointer */
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/* Global domain Q control*/
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atomic_t gactive;
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atomic_t gmod;
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atomic_t gcod;
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int saturated;
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int guard;
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/* Global domain Q spinlock */
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spinlock_t gbot_lock;
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#ifdef CONFIG_SCSC_SMAPPER
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/* SMAPPER */
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/* Leman has 4 Banks of 160 entries each and 4 Banks of 64 entries each. Each Tx stream is
|
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* expected to use 2 Bank . In RSDB, 5GHz streams require higher throughput
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* so the bigger banks are allocated for 5GHz streams and the
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* smaller banks are for 2.4GHz streams
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*/
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struct hip4_smapper_bank smapper_banks[HIP4_SMAPPER_TOTAL_BANKS];
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struct hip4_smapper_control smapper_control;
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#endif
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#ifdef CONFIG_SCSC_QOS
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/* PM QoS control */
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struct work_struct pm_qos_work;
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/* PM QoS control spinlock */
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||
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spinlock_t pm_qos_lock;
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||
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u8 pm_qos_state;
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||
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#endif
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/* Collection artificats */
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||
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void *mib_collect;
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||
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u16 mib_sz;
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||
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/* Mutex to protect hcf file collection if a tear down is triggered */
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||
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struct mutex in_collection;
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struct workqueue_struct *hip4_workq;
|
||
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};
|
||
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|
||
|
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struct scsc_service;
|
||
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|
||
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struct slsi_hip4 {
|
||
|
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struct hip4_priv *hip_priv;
|
||
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struct hip4_hip_control *hip_control;
|
||
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scsc_mifram_ref hip_ref;
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||
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};
|
||
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|
||
|
|
/* Public functions */
|
||
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int hip4_init(struct slsi_hip4 *hip);
|
||
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int hip4_setup(struct slsi_hip4 *hip);
|
||
|
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void hip4_suspend(struct slsi_hip4 *hip);
|
||
|
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void hip4_resume(struct slsi_hip4 *hip);
|
||
|
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void hip4_freeze(struct slsi_hip4 *hip);
|
||
|
|
void hip4_deinit(struct slsi_hip4 *hip);
|
||
|
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int hip4_free_ctrl_slots_count(struct slsi_hip4 *hip);
|
||
|
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void hip4_set_napi_cpu(struct slsi_hip4 *hip, u8 napi_cpu);
|
||
|
|
int scsc_wifi_transmit_frame(struct slsi_hip4 *hip, struct sk_buff *skb, bool ctrl_packet, u8 vif_index, u8 peer_index, u8 priority);
|
||
|
|
#ifndef CONFIG_SCSC_WLAN_RX_NAPI
|
||
|
|
void hip4_sched_wq(struct slsi_hip4 *hip);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Macros for accessing information stored in the hip_config struct */
|
||
|
|
#define scsc_wifi_get_hip_config_version_4_u8(buff_ptr, member) le16_to_cpu((((struct hip4_hip_config_version_4 *)(buff_ptr))->member))
|
||
|
|
#define scsc_wifi_get_hip_config_version_4_u16(buff_ptr, member) le16_to_cpu((((struct hip4_hip_config_version_4 *)(buff_ptr))->member))
|
||
|
|
#define scsc_wifi_get_hip_config_version_4_u32(buff_ptr, member) le32_to_cpu((((struct hip4_hip_config_version_4 *)(buff_ptr))->member))
|
||
|
|
#define scsc_wifi_get_hip_config_version_5_u8(buff_ptr, member) le16_to_cpu((((struct hip4_hip_config_version_5 *)(buff_ptr))->member))
|
||
|
|
#define scsc_wifi_get_hip_config_version_5_u16(buff_ptr, member) le16_to_cpu((((struct hip4_hip_config_version_5 *)(buff_ptr))->member))
|
||
|
|
#define scsc_wifi_get_hip_config_version_5_u32(buff_ptr, member) le32_to_cpu((((struct hip4_hip_config_version_5 *)(buff_ptr))->member))
|
||
|
|
#define scsc_wifi_get_hip_config_u8(buff_ptr, member, ver) le16_to_cpu((((struct hip4_hip_config_version_##ver *)(buff_ptr->config_v##ver))->member))
|
||
|
|
#define scsc_wifi_get_hip_config_u16(buff_ptr, member, ver) le16_to_cpu((((struct hip4_hip_config_version_##ver *)(buff_ptr->config_v##ver))->member))
|
||
|
|
#define scsc_wifi_get_hip_config_u32(buff_ptr, member, ver) le32_to_cpu((((struct hip4_hip_config_version_##ver *)(buff_ptr->config_v##ver))->member))
|
||
|
|
#define scsc_wifi_get_hip_config_version(buff_ptr) le32_to_cpu((((struct hip4_hip_init *)(buff_ptr))->conf_hip4_ver))
|
||
|
|
|
||
|
|
#endif
|