223 lines
6.0 KiB
C
223 lines
6.0 KiB
C
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/******************************************************************************
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*
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* Copyright(c) 2009-2012 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*****************************************************************************/
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#ifndef __RTL_DEBUG_H__
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#define __RTL_DEBUG_H__
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/*--------------------------------------------------------------
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Debug level
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--------------------------------------------------------------*/
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/*
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*Fatal bug.
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*For example, Tx/Rx/IO locked up,
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*memory access violation,
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*resource allocation failed,
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*unexpected HW behavior, HW BUG
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*and so on.
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*/
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/*#define DBG_EMERG 0 */
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/*
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*Abnormal, rare, or unexpeted cases.
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*For example, Packet/IO Ctl canceled,
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*device suprisely unremoved and so on.
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*/
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#define DBG_WARNING 2
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/*
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*Normal case driver developer should
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*open, we can see link status like
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*assoc/AddBA/DHCP/adapter start and
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*so on basic and useful infromations.
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*/
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#define DBG_DMESG 3
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/*
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*Normal case with useful information
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*about current SW or HW state.
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*For example, Tx/Rx descriptor to fill,
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*Tx/Rx descriptor completed status,
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*SW protocol state change, dynamic
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*mechanism state change and so on.
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*/
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#define DBG_LOUD 4
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/*
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*Normal case with detail execution
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*flow or information.
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*/
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#define DBG_TRACE 5
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/*--------------------------------------------------------------
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Define the rt_trace components
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--------------------------------------------------------------*/
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#define COMP_ERR BIT(0)
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#define COMP_FW BIT(1)
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#define COMP_INIT BIT(2) /*For init/deinit */
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#define COMP_RECV BIT(3) /*For Rx. */
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#define COMP_SEND BIT(4) /*For Tx. */
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#define COMP_MLME BIT(5) /*For MLME. */
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#define COMP_SCAN BIT(6) /*For Scan. */
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#define COMP_INTR BIT(7) /*For interrupt Related. */
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#define COMP_LED BIT(8) /*For LED. */
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#define COMP_SEC BIT(9) /*For sec. */
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#define COMP_BEACON BIT(10) /*For beacon. */
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#define COMP_RATE BIT(11) /*For rate. */
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#define COMP_RXDESC BIT(12) /*For rx desc. */
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#define COMP_DIG BIT(13) /*For DIG */
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#define COMP_TXAGC BIT(14) /*For Tx power */
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#define COMP_HIPWR BIT(15) /*For High Power Mechanism */
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#define COMP_POWER BIT(16) /*For lps/ips/aspm. */
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#define COMP_POWER_TRACKING BIT(17) /*For TX POWER TRACKING */
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#define COMP_BB_POWERSAVING BIT(18)
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#define COMP_SWAS BIT(19) /*For SW Antenna Switch */
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#define COMP_RF BIT(20) /*For RF. */
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#define COMP_TURBO BIT(21) /*For EDCA TURBO. */
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#define COMP_RATR BIT(22)
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#define COMP_CMD BIT(23)
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#define COMP_EFUSE BIT(24)
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#define COMP_QOS BIT(25)
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#define COMP_MAC80211 BIT(26)
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#define COMP_REGD BIT(27)
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#define COMP_CHAN BIT(28)
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#define COMP_USB BIT(29)
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#define COMP_EASY_CONCURRENT COMP_USB /* reuse of this bit is OK */
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#define COMP_BT_COEXIST BIT(30)
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#define COMP_IQK BIT(31)
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#define COMP_TX_REPORT BIT_ULL(32)
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/*--------------------------------------------------------------
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Define the rt_print components
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--------------------------------------------------------------*/
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/* Define EEPROM and EFUSE check module bit*/
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#define EEPROM_W BIT(0)
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#define EFUSE_PG BIT(1)
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#define EFUSE_READ_ALL BIT(2)
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/* Define init check for module bit*/
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#define INIT_EEPROM BIT(0)
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#define INIT_TXPOWER BIT(1)
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#define INIT_IQK BIT(2)
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#define INIT_RF BIT(3)
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/* Define PHY-BB/RF/MAC check module bit */
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#define PHY_BBR BIT(0)
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#define PHY_BBW BIT(1)
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#define PHY_RFR BIT(2)
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#define PHY_RFW BIT(3)
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#define PHY_MACR BIT(4)
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#define PHY_MACW BIT(5)
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#define PHY_ALLR BIT(6)
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#define PHY_ALLW BIT(7)
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#define PHY_TXPWR BIT(8)
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#define PHY_PWRDIFF BIT(9)
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/* Define Dynamic Mechanism check module bit --> FDM */
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#define WA_IOT BIT(0)
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#define DM_PWDB BIT(1)
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#define DM_MONITOR BIT(2)
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#define DM_DIG BIT(3)
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#define DM_EDCA_TURBO BIT(4)
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#define DM_PWDB BIT(1)
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enum dbgp_flag_e {
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FQOS = 0,
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FTX = 1,
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FRX = 2,
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FSEC = 3,
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FMGNT = 4,
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FMLME = 5,
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FRESOURCE = 6,
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FBEACON = 7,
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FISR = 8,
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FPHY = 9,
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FMP = 10,
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FEEPROM = 11,
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FPWR = 12,
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FDM = 13,
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FDBGCtrl = 14,
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FC2H = 15,
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FBT = 16,
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FINIT = 17,
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FIOCTL = 18,
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DBGP_TYPE_MAX
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};
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#ifdef CONFIG_RTLWIFI_DEBUG
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struct rtl_priv;
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__printf(4, 5)
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void _rtl_dbg_trace(struct rtl_priv *rtlpriv, u64 comp, int level,
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const char *fmt, ...);
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__printf(4, 5)
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void _rtl_dbg_print(struct rtl_priv *rtlpriv, u64 comp, int level,
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const char *fmt, ...);
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void _rtl_dbg_print_data(struct rtl_priv *rtlpriv, u64 comp, int level,
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const char *titlestring,
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const void *hexdata, int hexdatalen);
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#define RT_TRACE(rtlpriv, comp, level, fmt, ...) \
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_rtl_dbg_trace(rtlpriv, comp, level, \
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fmt, ##__VA_ARGS__)
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#define RTPRINT(rtlpriv, dbgtype, dbgflag, fmt, ...) \
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_rtl_dbg_print(rtlpriv, dbgtype, dbgflag, fmt, ##__VA_ARGS__)
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#define RT_PRINT_DATA(rtlpriv, _comp, _level, _titlestring, _hexdata, \
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_hexdatalen) \
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_rtl_dbg_print_data(rtlpriv, _comp, _level, \
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_titlestring, _hexdata, _hexdatalen)
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#else
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struct rtl_priv;
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__printf(4, 5)
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static inline void RT_TRACE(struct rtl_priv *rtlpriv,
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u64 comp, int level,
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const char *fmt, ...)
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{
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}
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__printf(4, 5)
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static inline void RTPRINT(struct rtl_priv *rtlpriv,
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int dbgtype, int dbgflag,
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const char *fmt, ...)
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{
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}
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static inline void RT_PRINT_DATA(struct rtl_priv *rtlpriv,
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u64 comp, int level,
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const char *titlestring,
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const void *hexdata, size_t hexdatalen)
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{
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}
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#endif
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#endif
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