354 lines
10 KiB
C
354 lines
10 KiB
C
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/*
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* Samsung Exynos5 SoC series FIMC-IS driver
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*
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef FIMC_IS_FRAME_MGR_H
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#define FIMC_IS_FRAME_MGR_H
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#include <linux/kthread.h>
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#include <linux/videodev2.h>
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#include "fimc-is-time.h"
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#include "fimc-is-config.h"
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#define FIMC_IS_MAX_BUFS VIDEO_MAX_FRAME
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#define FIMC_IS_MAX_PLANES 17
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#define FRAMEMGR_ID_INVALID 0x00000000
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#define FRAMEMGR_ID_SSX 0x00000100
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#define FRAMEMGR_ID_SSXVC0 0x00000011
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#define FRAMEMGR_ID_SSXVC1 0x00000012
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#define FRAMEMGR_ID_SSXVC2 0x00000013
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#define FRAMEMGR_ID_SSXVC3 0x00000014
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#define FRAMEMGR_ID_3XS 0x00000200
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#define FRAMEMGR_ID_3XC 0x00000400
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#define FRAMEMGR_ID_3XP 0x00000800
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#define FRAMEMGR_ID_3XF 0x00000801
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#define FRAMEMGR_ID_3XG 0x00000802
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#define FRAMEMGR_ID_IXS 0x00001000
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#define FRAMEMGR_ID_IXC 0x00002000
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#define FRAMEMGR_ID_IXP 0x00004000
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#define FRAMEMGR_ID_DXS 0x00008000
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#define FRAMEMGR_ID_DXC 0x00010000
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#define FRAMEMGR_ID_MXS 0x00020000
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#define FRAMEMGR_ID_M0P 0x00040000
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#define FRAMEMGR_ID_M1P 0x00080000
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#define FRAMEMGR_ID_M2P 0x00100000
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#define FRAMEMGR_ID_M3P 0x00200000
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#define FRAMEMGR_ID_M4P 0x00400000
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#define FRAMEMGR_ID_M5P 0x00800000
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#define FRAMEMGR_ID_VRA 0x01000000
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#if defined(SOC_DCP)
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#define FRAMEMGR_ID_DCP0S 0x02000000
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#define FRAMEMGR_ID_DCP1S 0x04000000
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#define FRAMEMGR_ID_DCP0C 0x08000000
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#define FRAMEMGR_ID_DCP1C 0x10000000
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#define FRAMEMGR_ID_DCP2C 0x20000000
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#define FRAMEMGR_ID_MEXC 0x40000000 /* for ME */
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#define FRAMEMGR_ID_HW 0x80000000
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#define FRAMEMGR_ID_SHOT (FRAMEMGR_ID_SSX | FRAMEMGR_ID_3XS | \
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FRAMEMGR_ID_IXS | FRAMEMGR_ID_DXS | \
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FRAMEMGR_ID_MXS | FRAMEMGR_ID_VRA | \
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FRAMEMGR_ID_DCP0S)
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#define FRAMEMGR_ID_STREAM (FRAMEMGR_ID_3XC | FRAMEMGR_ID_3XP | \
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FRAMEMGR_ID_DXS | FRAMEMGR_ID_DXC | \
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FRAMEMGR_ID_M0P | FRAMEMGR_ID_M1P | \
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FRAMEMGR_ID_M2P | FRAMEMGR_ID_M3P | \
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FRAMEMGR_ID_M4P | FRAMEMGR_ID_M5P | \
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FRAMEMGR_ID_DCP1S | FRAMEMGR_ID_DCP0C | \
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FRAMEMGR_ID_DCP1C | FRAMEMGR_ID_DCP2C | \
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FRAMEMGR_ID_SSXVC0 | FRAMEMGR_ID_SSXVC1 | \
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FRAMEMGR_ID_SSXVC2 | FRAMEMGR_ID_SSXVC3)
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#else
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#define FRAMEMGR_ID_MEXC 0x02000000 /* for ME */
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#define FRAMEMGR_ID_PAFXS 0x04000000 /* for PAF_RDMA */
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#define FRAMEMGR_ID_HW 0x08000000
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#define FRAMEMGR_ID_SHOT (FRAMEMGR_ID_SSX | FRAMEMGR_ID_3XS | \
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FRAMEMGR_ID_IXS | FRAMEMGR_ID_DXS | \
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FRAMEMGR_ID_MXS | FRAMEMGR_ID_VRA | \
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FRAMEMGR_ID_PAFXS)
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#define FRAMEMGR_ID_STREAM (FRAMEMGR_ID_3XC | FRAMEMGR_ID_3XP | \
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FRAMEMGR_ID_DXS | FRAMEMGR_ID_DXC | \
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FRAMEMGR_ID_M0P | FRAMEMGR_ID_M1P | \
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FRAMEMGR_ID_M2P | FRAMEMGR_ID_M3P | \
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FRAMEMGR_ID_M4P | FRAMEMGR_ID_M5P | \
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FRAMEMGR_ID_SSXVC0 | FRAMEMGR_ID_SSXVC1 | \
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FRAMEMGR_ID_SSXVC2 | FRAMEMGR_ID_SSXVC3)
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#endif
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/* #define TRACE_FRAME */
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#define TRACE_ID (FRAMEMGR_ID_SHOT | FRAMEMGR_ID_STREAM | FRAMEMGR_ID_HW)
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#define FMGR_IDX_0 (1 << 0 )
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#define FMGR_IDX_1 (1 << 1 )
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#define FMGR_IDX_2 (1 << 2 )
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#define FMGR_IDX_3 (1 << 3 )
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#define FMGR_IDX_4 (1 << 4 )
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#define FMGR_IDX_5 (1 << 5 )
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#define FMGR_IDX_6 (1 << 6 )
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#define FMGR_IDX_7 (1 << 7 )
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#define FMGR_IDX_8 (1 << 8 )
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#define FMGR_IDX_9 (1 << 9 )
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#define FMGR_IDX_10 (1 << 10)
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#define FMGR_IDX_11 (1 << 11)
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#define FMGR_IDX_12 (1 << 12)
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#define FMGR_IDX_13 (1 << 13)
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#define FMGR_IDX_14 (1 << 14)
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#define FMGR_IDX_15 (1 << 15)
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#define FMGR_IDX_16 (1 << 16)
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#define FMGR_IDX_17 (1 << 17)
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#define FMGR_IDX_18 (1 << 18)
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#define FMGR_IDX_19 (1 << 19)
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#define FMGR_IDX_20 (1 << 20)
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#define FMGR_IDX_21 (1 << 21)
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#define FMGR_IDX_22 (1 << 22)
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#define FMGR_IDX_23 (1 << 23)
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#define FMGR_IDX_24 (1 << 24)
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#define FMGR_IDX_25 (1 << 25)
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#define FMGR_IDX_26 (1 << 26)
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#define FMGR_IDX_27 (1 << 27)
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#define FMGR_IDX_28 (1 << 28)
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#define FMGR_IDX_29 (1 << 29)
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#define FMGR_IDX_30 (1 << 30)
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#define FMGR_IDX_31 (1 << 31)
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#define framemgr_e_barrier_irqs(this, index, flag) \
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do { \
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this->sindex |= index; \
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spin_lock_irqsave(&this->slock, flag); \
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} while (0)
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#define framemgr_x_barrier_irqr(this, index, flag) \
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do { \
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spin_unlock_irqrestore(&this->slock, flag); \
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this->sindex &= ~index; \
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} while (0)
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#define framemgr_e_barrier_irq(this, index) \
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do { \
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this->sindex |= index; \
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spin_lock_irq(&this->slock); \
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} while (0)
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#define framemgr_x_barrier_irq(this, index) \
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do { \
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spin_unlock_irq(&this->slock); \
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this->sindex &= ~index; \
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} while (0)
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#define framemgr_e_barrier(this, index) \
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do { \
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this->sindex |= index; \
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spin_lock(&this->slock); \
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} while (0)
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#define framemgr_x_barrier(this, index) \
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do { \
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spin_unlock(&this->slock); \
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this->sindex &= ~index; \
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} while (0)
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enum fimc_is_frame_state {
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FS_FREE,
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FS_REQUEST,
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FS_PROCESS,
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FS_COMPLETE,
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FS_STRIPE_PROCESS,
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FS_INVALID
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};
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#define FS_HW_FREE FS_FREE
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#define FS_HW_REQUEST FS_REQUEST
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#define FS_HW_CONFIGURE FS_PROCESS
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#define FS_HW_WAIT_DONE FS_COMPLETE
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#define FS_HW_INVALID FS_INVALID
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#define NR_FRAME_STATE FS_INVALID
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enum fimc_is_frame_mem_state {
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/* initialized memory */
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FRAME_MEM_INIT,
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/* mapped memory */
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FRAME_MEM_MAPPED
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};
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#ifndef ENABLE_IS_CORE
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#define MAX_FRAME_INFO (4)
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enum fimc_is_frame_info_index {
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INFO_FRAME_START,
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INFO_CONFIG_LOCK,
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INFO_FRAME_END_PROC
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};
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struct fimc_is_frame_info {
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int cpu;
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int pid;
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unsigned long long when;
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};
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#endif
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struct fimc_is_stripe_size {
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/* Horizontal pixel ratio how much stripe processing is done. */
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u32 h_pix_ratio;
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/* Horizontal pixel count which stripe processing is done for. */
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u32 h_pix_num;
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};
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struct fimc_is_stripe_info {
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/* Region index. */
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u32 region_id;
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/* Total region num. */
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u32 region_num;
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/* Stripe size for incrop/otcrop */
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struct fimc_is_stripe_size in;
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struct fimc_is_stripe_size out;
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};
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struct fimc_is_frame {
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struct list_head list;
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struct kthread_work work;
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void *groupmgr;
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void *group;
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void *subdev; /* fimc_is_subdev */
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/* group leader use */
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struct camera2_shot_ext *shot_ext;
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struct camera2_shot *shot;
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size_t shot_size;
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/* stream use */
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struct camera2_stream *stream;
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/* common use */
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u32 planes; /* total planes include multi-buffers */
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dma_addr_t dvaddr_buffer[FIMC_IS_MAX_PLANES];
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ulong kvaddr_buffer[FIMC_IS_MAX_PLANES];
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/*
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* target address for capture node
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* [0] invalid address, stop
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* [others] valid address
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*/
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u32 sourceAddress[FIMC_IS_MAX_PLANES]; /* DC1S: DCP slave input DMA */
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u32 txcTargetAddress[FIMC_IS_MAX_PLANES]; /* 3AA capture DMA */
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u32 txpTargetAddress[FIMC_IS_MAX_PLANES]; /* 3AA preview DMA */
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u32 mrgTargetAddress[FIMC_IS_MAX_PLANES];
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u32 efdTargetAddress[FIMC_IS_MAX_PLANES];
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u32 ixcTargetAddress[FIMC_IS_MAX_PLANES];
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u32 ixpTargetAddress[FIMC_IS_MAX_PLANES];
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u64 mexcTargetAddress[FIMC_IS_MAX_PLANES]; /* ME out DMA */
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u32 sccTargetAddress[FIMC_IS_MAX_PLANES]; /* DC0S: DCP master capture DMA */
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u32 scpTargetAddress[FIMC_IS_MAX_PLANES]; /* DC1S: DCP slave capture DMA */
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u32 sc0TargetAddress[FIMC_IS_MAX_PLANES];
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u32 sc1TargetAddress[FIMC_IS_MAX_PLANES];
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u32 sc2TargetAddress[FIMC_IS_MAX_PLANES];
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u32 sc3TargetAddress[FIMC_IS_MAX_PLANES];
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u32 sc4TargetAddress[FIMC_IS_MAX_PLANES];
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u32 sc5TargetAddress[FIMC_IS_MAX_PLANES];
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u32 dxcTargetAddress[FIMC_IS_MAX_PLANES]; /* DC2S: DCP disparity capture DMA */
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/* multi-buffer use */
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u32 num_buffers; /* total number of buffers per frame */
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u32 cur_buf_index; /* current processed buffer index */
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/* internal use */
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unsigned long mem_state;
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u32 state;
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u32 fcount;
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u32 rcount;
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u32 index;
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u32 lindex;
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u32 hindex;
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u32 result;
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unsigned long out_flag;
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unsigned long bak_flag;
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#ifndef ENABLE_IS_CORE
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struct fimc_is_frame_info frame_info[MAX_FRAME_INFO];
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u32 instance; /* device instance */
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u32 type;
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unsigned long core_flag;
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atomic_t shot_done_flag;
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#else
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/* group leader use */
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dma_addr_t dvaddr_shot;
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#endif
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#ifdef ENABLE_SYNC_REPROCESSING
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struct list_head sync_list;
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#endif
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struct list_head votf_list;
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/* for NI(noise index from DDK) use */
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u32 noise_idx; /* Noise index */
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#ifdef MEASURE_TIME
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/* time measure externally */
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struct timeval *tzone;
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/* time measure internally */
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struct fimc_is_monitor mpoint[TMS_END];
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#endif
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#ifdef DBG_DRAW_DIGIT
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u32 width;
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u32 height;
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#endif
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struct fimc_is_stripe_info stripe_info;
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};
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struct fimc_is_framemgr {
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u32 id;
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char name[FIMC_IS_STR_LEN];
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spinlock_t slock;
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ulong sindex;
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u32 num_frames;
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struct fimc_is_frame *frames;
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u32 queued_count[NR_FRAME_STATE];
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struct list_head queued_list[NR_FRAME_STATE];
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};
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static const char * const hw_frame_state_name[NR_FRAME_STATE] = {
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"Free",
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"Request",
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"Configure",
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"Wait_Done"
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};
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static const char * const frame_state_name[NR_FRAME_STATE] = {
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"Free",
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"Request",
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"Process",
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"Complete"
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};
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ulong frame_fcount(struct fimc_is_frame *frame, void *data);
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int put_frame(struct fimc_is_framemgr *this, struct fimc_is_frame *frame,
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enum fimc_is_frame_state state);
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struct fimc_is_frame *get_frame(struct fimc_is_framemgr *this,
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enum fimc_is_frame_state state);
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int trans_frame(struct fimc_is_framemgr *this, struct fimc_is_frame *frame,
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enum fimc_is_frame_state state);
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||
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struct fimc_is_frame *peek_frame(struct fimc_is_framemgr *this,
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enum fimc_is_frame_state state);
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struct fimc_is_frame *peek_frame_tail(struct fimc_is_framemgr *this,
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enum fimc_is_frame_state state);
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||
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struct fimc_is_frame *find_frame(struct fimc_is_framemgr *this,
|
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enum fimc_is_frame_state state,
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ulong (*fn)(struct fimc_is_frame *, void *), void *data);
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struct fimc_is_frame *find_stripe_process_frame(struct fimc_is_framemgr *this,
|
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u32 fcount);
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||
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void print_frame_queue(struct fimc_is_framemgr *this,
|
||
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enum fimc_is_frame_state state);
|
||
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||
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int frame_manager_probe(struct fimc_is_framemgr *this, u32 id, const char *name);
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int frame_manager_open(struct fimc_is_framemgr *this, u32 buffers);
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int frame_manager_close(struct fimc_is_framemgr *this);
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||
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int frame_manager_flush(struct fimc_is_framemgr *this);
|
||
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void frame_manager_print_queues(struct fimc_is_framemgr *this);
|
||
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void frame_manager_print_info_queues(struct fimc_is_framemgr *this);
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||
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#endif
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