222 lines
7.0 KiB
C
222 lines
7.0 KiB
C
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/*
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* cpu-sa1100.c: clock scaling for the SA1100
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*
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* Copyright (C) 2000 2001, The Delft University of Technology
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*
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* Authors:
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* - Johan Pouwelse (J.A.Pouwelse@its.tudelft.nl): initial version
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* - Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
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* - major rewrite for linux-2.3.99
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* - rewritten for the more generic power management scheme in
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* linux-2.4.5-rmk1
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*
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* This software has been developed while working on the LART
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* computing board (http://www.lartmaker.nl/), which is
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* sponsored by the Mobile Multi-media Communications
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* (http://www.mobimedia.org/) and Ubiquitous Communications
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* (http://www.ubicom.tudelft.nl/) projects.
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*
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* The authors can be reached at:
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*
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* Erik Mouw
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* Information and Communication Theory Group
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* Faculty of Information Technology and Systems
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* Delft University of Technology
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* P.O. Box 5031
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* 2600 GA Delft
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* The Netherlands
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*
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* Theory of operations
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* ====================
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*
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* Clock scaling can be used to lower the power consumption of the CPU
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* core. This will give you a somewhat longer running time.
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*
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* The SA-1100 has a single register to change the core clock speed:
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*
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* PPCR 0x90020014 PLL config
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*
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* However, the DRAM timings are closely related to the core clock
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* speed, so we need to change these, too. The used registers are:
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*
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* MDCNFG 0xA0000000 DRAM config
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* MDCAS0 0xA0000004 Access waveform
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* MDCAS1 0xA0000008 Access waveform
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* MDCAS2 0xA000000C Access waveform
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*
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* Care must be taken to change the DRAM parameters the correct way,
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* because otherwise the DRAM becomes unusable and the kernel will
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* crash.
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*
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* The simple solution to avoid a kernel crash is to put the actual
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* clock change in ROM and jump to that code from the kernel. The main
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* disadvantage is that the ROM has to be modified, which is not
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* possible on all SA-1100 platforms. Another disadvantage is that
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* jumping to ROM makes clock switching unnecessary complicated.
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*
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* The idea behind this driver is that the memory configuration can be
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* changed while running from DRAM (even with interrupts turned on!)
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* as long as all re-configuration steps yield a valid DRAM
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* configuration. The advantages are clear: it will run on all SA-1100
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* platforms, and the code is very simple.
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*
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* If you really want to understand what is going on in
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* sa1100_update_dram_timings(), you'll have to read sections 8.2,
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* 9.5.7.3, and 10.2 from the "Intel StrongARM SA-1100 Microprocessor
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* Developers Manual" (available for free from Intel).
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*
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/cpufreq.h>
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#include <linux/io.h>
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#include <asm/cputype.h>
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#include <mach/generic.h>
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#include <mach/hardware.h>
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struct sa1100_dram_regs {
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int speed;
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u32 mdcnfg;
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u32 mdcas0;
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u32 mdcas1;
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u32 mdcas2;
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};
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static struct cpufreq_driver sa1100_driver;
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static struct sa1100_dram_regs sa1100_dram_settings[] = {
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/*speed, mdcnfg, mdcas0, mdcas1, mdcas2, clock freq */
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{ 59000, 0x00dc88a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 59.0 MHz */
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{ 73700, 0x011490a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 73.7 MHz */
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{ 88500, 0x014e90a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 88.5 MHz */
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{103200, 0x01889923, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 103.2 MHz */
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{118000, 0x01c29923, 0x9999998f, 0xfffffff9, 0xffffffff},/* 118.0 MHz */
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{132700, 0x01fb2123, 0x9999998f, 0xfffffff9, 0xffffffff},/* 132.7 MHz */
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{147500, 0x02352123, 0x3333330f, 0xfffffff3, 0xffffffff},/* 147.5 MHz */
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{162200, 0x026b29a3, 0x38e38e1f, 0xfff8e38e, 0xffffffff},/* 162.2 MHz */
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{176900, 0x02a329a3, 0x71c71c1f, 0xfff1c71c, 0xffffffff},/* 176.9 MHz */
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{191700, 0x02dd31a3, 0xe38e383f, 0xffe38e38, 0xffffffff},/* 191.7 MHz */
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{206400, 0x03153223, 0xc71c703f, 0xffc71c71, 0xffffffff},/* 206.4 MHz */
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{221200, 0x034fba23, 0xc71c703f, 0xffc71c71, 0xffffffff},/* 221.2 MHz */
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{235900, 0x03853a23, 0xe1e1e07f, 0xe1e1e1e1, 0xffffffe1},/* 235.9 MHz */
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{250700, 0x03bf3aa3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3},/* 250.7 MHz */
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{265400, 0x03f7c2a3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3},/* 265.4 MHz */
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{280200, 0x0431c2a3, 0x878780ff, 0x87878787, 0xffffff87},/* 280.2 MHz */
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{ 0, 0, 0, 0, 0 } /* last entry */
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};
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static void sa1100_update_dram_timings(int current_speed, int new_speed)
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{
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struct sa1100_dram_regs *settings = sa1100_dram_settings;
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/* find speed */
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while (settings->speed != 0) {
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if (new_speed == settings->speed)
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break;
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settings++;
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}
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if (settings->speed == 0) {
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panic("%s: couldn't find dram setting for speed %d\n",
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__func__, new_speed);
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}
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/* No risk, no fun: run with interrupts on! */
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if (new_speed > current_speed) {
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/* We're going FASTER, so first relax the memory
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* timings before changing the core frequency
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*/
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/* Half the memory access clock */
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MDCNFG |= MDCNFG_CDB2;
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/* The order of these statements IS important, keep 8
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* pulses!!
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*/
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MDCAS2 = settings->mdcas2;
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MDCAS1 = settings->mdcas1;
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MDCAS0 = settings->mdcas0;
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MDCNFG = settings->mdcnfg;
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} else {
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/* We're going SLOWER: first decrease the core
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* frequency and then tighten the memory settings.
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*/
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/* Half the memory access clock */
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MDCNFG |= MDCNFG_CDB2;
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/* The order of these statements IS important, keep 8
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* pulses!!
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*/
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MDCAS0 = settings->mdcas0;
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MDCAS1 = settings->mdcas1;
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MDCAS2 = settings->mdcas2;
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MDCNFG = settings->mdcnfg;
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}
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}
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static int sa1100_target(struct cpufreq_policy *policy, unsigned int ppcr)
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{
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unsigned int cur = sa11x0_getspeed(0);
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unsigned int new_freq;
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new_freq = sa11x0_freq_table[ppcr].frequency;
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if (new_freq > cur)
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sa1100_update_dram_timings(cur, new_freq);
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PPCR = ppcr;
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if (new_freq < cur)
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sa1100_update_dram_timings(cur, new_freq);
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return 0;
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}
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static int __init sa1100_cpu_init(struct cpufreq_policy *policy)
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{
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return cpufreq_generic_init(policy, sa11x0_freq_table, 0);
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}
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static struct cpufreq_driver sa1100_driver __refdata = {
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.flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK |
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CPUFREQ_NO_AUTO_DYNAMIC_SWITCHING,
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.verify = cpufreq_generic_frequency_table_verify,
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.target_index = sa1100_target,
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.get = sa11x0_getspeed,
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.init = sa1100_cpu_init,
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.name = "sa1100",
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};
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static int __init sa1100_dram_init(void)
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{
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if (cpu_is_sa1100())
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return cpufreq_register_driver(&sa1100_driver);
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else
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return -ENODEV;
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}
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arch_initcall(sa1100_dram_init);
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