374 lines
10 KiB
C
374 lines
10 KiB
C
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/*
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* OMAP2/3/4 DPLL clock functions
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*
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* Copyright (C) 2005-2008 Texas Instruments, Inc.
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* Copyright (C) 2004-2010 Nokia Corporation
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*
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* Contacts:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/clk/ti.h>
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#include <asm/div64.h>
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#include "clock.h"
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/* DPLL rate rounding: minimum DPLL multiplier, divider values */
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#define DPLL_MIN_MULTIPLIER 2
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#define DPLL_MIN_DIVIDER 1
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/* Possible error results from _dpll_test_mult */
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#define DPLL_MULT_UNDERFLOW -1
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/*
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* Scale factor to mitigate roundoff errors in DPLL rate rounding.
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* The higher the scale factor, the greater the risk of arithmetic overflow,
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* but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
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* must be a power of DPLL_SCALE_BASE.
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*/
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#define DPLL_SCALE_FACTOR 64
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#define DPLL_SCALE_BASE 2
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#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
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(DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
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/*
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* DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
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* From device data manual section 4.3 "DPLL and DLL Specifications".
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*/
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#define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000
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#define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000
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/* _dpll_test_fint() return codes */
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#define DPLL_FINT_UNDERFLOW -1
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#define DPLL_FINT_INVALID -2
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/* Private functions */
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/*
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* _dpll_test_fint - test whether an Fint value is valid for the DPLL
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* @clk: DPLL struct clk to test
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* @n: divider value (N) to test
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*
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* Tests whether a particular divider @n will result in a valid DPLL
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* internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
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* Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
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* (assuming that it is counting N upwards), or -2 if the enclosing loop
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* should skip to the next iteration (again assuming N is increasing).
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*/
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static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n)
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{
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struct dpll_data *dd;
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long fint, fint_min, fint_max;
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int ret = 0;
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dd = clk->dpll_data;
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/* DPLL divider must result in a valid jitter correction val */
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fint = clk_hw_get_rate(clk_hw_get_parent(&clk->hw)) / n;
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if (dd->flags & DPLL_J_TYPE) {
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fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
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fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
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} else {
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fint_min = ti_clk_get_features()->fint_min;
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fint_max = ti_clk_get_features()->fint_max;
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}
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if (!fint_min || !fint_max) {
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WARN(1, "No fint limits available!\n");
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return DPLL_FINT_INVALID;
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}
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if (fint < ti_clk_get_features()->fint_min) {
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pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
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n);
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dd->max_divider = n;
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ret = DPLL_FINT_UNDERFLOW;
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} else if (fint > ti_clk_get_features()->fint_max) {
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pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
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n);
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dd->min_divider = n;
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ret = DPLL_FINT_INVALID;
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} else if (fint > ti_clk_get_features()->fint_band1_max &&
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fint < ti_clk_get_features()->fint_band2_min) {
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pr_debug("rejecting n=%d due to Fint failure\n", n);
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ret = DPLL_FINT_INVALID;
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}
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return ret;
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}
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static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
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unsigned int m, unsigned int n)
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{
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unsigned long long num;
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num = (unsigned long long)parent_rate * m;
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do_div(num, n);
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return num;
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}
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/*
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* _dpll_test_mult - test a DPLL multiplier value
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* @m: pointer to the DPLL m (multiplier) value under test
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* @n: current DPLL n (divider) value under test
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* @new_rate: pointer to storage for the resulting rounded rate
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* @target_rate: the desired DPLL rate
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* @parent_rate: the DPLL's parent clock rate
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*
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* This code tests a DPLL multiplier value, ensuring that the
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* resulting rate will not be higher than the target_rate, and that
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* the multiplier value itself is valid for the DPLL. Initially, the
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* integer pointed to by the m argument should be prescaled by
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* multiplying by DPLL_SCALE_FACTOR. The code will replace this with
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* a non-scaled m upon return. This non-scaled m will result in a
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* new_rate as close as possible to target_rate (but not greater than
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* target_rate) given the current (parent_rate, n, prescaled m)
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* triple. Returns DPLL_MULT_UNDERFLOW in the event that the
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* non-scaled m attempted to underflow, which can allow the calling
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* function to bail out early; or 0 upon success.
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*/
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static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
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unsigned long target_rate,
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unsigned long parent_rate)
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{
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int r = 0, carry = 0;
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/* Unscale m and round if necessary */
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if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
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carry = 1;
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*m = (*m / DPLL_SCALE_FACTOR) + carry;
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/*
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* The new rate must be <= the target rate to avoid programming
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* a rate that is impossible for the hardware to handle
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*/
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*new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
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if (*new_rate > target_rate) {
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(*m)--;
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*new_rate = 0;
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}
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/* Guard against m underflow */
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if (*m < DPLL_MIN_MULTIPLIER) {
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*m = DPLL_MIN_MULTIPLIER;
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*new_rate = 0;
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r = DPLL_MULT_UNDERFLOW;
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}
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if (*new_rate == 0)
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*new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
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return r;
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}
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/**
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* _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not
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* @v: bitfield value of the DPLL enable
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*
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* Checks given DPLL enable bitfield to see whether the DPLL is in bypass
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* mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise.
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*/
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static int _omap2_dpll_is_in_bypass(u32 v)
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{
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u8 mask, val;
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mask = ti_clk_get_features()->dpll_bypass_vals;
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/*
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* Each set bit in the mask corresponds to a bypass value equal
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* to the bitshift. Go through each set-bit in the mask and
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* compare against the given register value.
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*/
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while (mask) {
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val = __ffs(mask);
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mask ^= (1 << val);
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if (v == val)
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return 1;
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}
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return 0;
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}
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/* Public functions */
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u8 omap2_init_dpll_parent(struct clk_hw *hw)
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{
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struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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u32 v;
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struct dpll_data *dd;
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dd = clk->dpll_data;
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if (!dd)
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return -EINVAL;
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v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
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v &= dd->enable_mask;
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v >>= __ffs(dd->enable_mask);
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/* Reparent the struct clk in case the dpll is in bypass */
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if (_omap2_dpll_is_in_bypass(v))
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return 1;
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return 0;
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}
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/**
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* omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
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* @clk: struct clk * of a DPLL
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*
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* DPLLs can be locked or bypassed - basically, enabled or disabled.
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* When locked, the DPLL output depends on the M and N values. When
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* bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
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* or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
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* 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
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* (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
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* Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
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* locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
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* if the clock @clk is not a DPLL.
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*/
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unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
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{
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u64 dpll_clk;
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u32 dpll_mult, dpll_div, v;
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struct dpll_data *dd;
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dd = clk->dpll_data;
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if (!dd)
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return 0;
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/* Return bypass rate if DPLL is bypassed */
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v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
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v &= dd->enable_mask;
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v >>= __ffs(dd->enable_mask);
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if (_omap2_dpll_is_in_bypass(v))
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return clk_hw_get_rate(dd->clk_bypass);
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v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
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dpll_mult = v & dd->mult_mask;
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dpll_mult >>= __ffs(dd->mult_mask);
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dpll_div = v & dd->div1_mask;
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dpll_div >>= __ffs(dd->div1_mask);
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dpll_clk = (u64)clk_hw_get_rate(dd->clk_ref) * dpll_mult;
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do_div(dpll_clk, dpll_div + 1);
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return dpll_clk;
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}
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/* DPLL rate rounding code */
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/**
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* omap2_dpll_round_rate - round a target rate for an OMAP DPLL
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* @clk: struct clk * for a DPLL
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* @target_rate: desired DPLL clock rate
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*
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* Given a DPLL and a desired target rate, round the target rate to a
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* possible, programmable rate for this DPLL. Attempts to select the
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* minimum possible n. Stores the computed (m, n) in the DPLL's
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* dpll_data structure so set_rate() will not need to call this
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* (expensive) function again. Returns ~0 if the target rate cannot
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* be rounded, or the rounded rate upon success.
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*/
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long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
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unsigned long *parent_rate)
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{
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struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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int m, n, r, scaled_max_m;
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int min_delta_m = INT_MAX, min_delta_n = INT_MAX;
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unsigned long scaled_rt_rp;
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unsigned long new_rate = 0;
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struct dpll_data *dd;
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unsigned long ref_rate;
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long delta;
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long prev_min_delta = LONG_MAX;
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const char *clk_name;
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if (!clk || !clk->dpll_data)
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return ~0;
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dd = clk->dpll_data;
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if (dd->max_rate && target_rate > dd->max_rate)
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target_rate = dd->max_rate;
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ref_rate = clk_hw_get_rate(dd->clk_ref);
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clk_name = clk_hw_get_name(hw);
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pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",
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clk_name, target_rate);
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scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
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scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
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dd->last_rounded_rate = 0;
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for (n = dd->min_divider; n <= dd->max_divider; n++) {
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/* Is the (input clk, divider) pair valid for the DPLL? */
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r = _dpll_test_fint(clk, n);
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if (r == DPLL_FINT_UNDERFLOW)
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break;
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else if (r == DPLL_FINT_INVALID)
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continue;
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/* Compute the scaled DPLL multiplier, based on the divider */
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m = scaled_rt_rp * n;
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/*
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* Since we're counting n up, a m overflow means we
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* can bail out completely (since as n increases in
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* the next iteration, there's no way that m can
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* increase beyond the current m)
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*/
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if (m > scaled_max_m)
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break;
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r = _dpll_test_mult(&m, n, &new_rate, target_rate,
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ref_rate);
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/* m can't be set low enough for this n - try with a larger n */
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if (r == DPLL_MULT_UNDERFLOW)
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continue;
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/* skip rates above our target rate */
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delta = target_rate - new_rate;
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if (delta < 0)
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continue;
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if (delta < prev_min_delta) {
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prev_min_delta = delta;
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min_delta_m = m;
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min_delta_n = n;
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}
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pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n",
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clk_name, m, n, new_rate);
|
||
|
|
|
||
|
|
if (delta == 0)
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (prev_min_delta == LONG_MAX) {
|
||
|
|
pr_debug("clock: %s: cannot round to rate %lu\n",
|
||
|
|
clk_name, target_rate);
|
||
|
|
return ~0;
|
||
|
|
}
|
||
|
|
|
||
|
|
dd->last_rounded_m = min_delta_m;
|
||
|
|
dd->last_rounded_n = min_delta_n;
|
||
|
|
dd->last_rounded_rate = target_rate - prev_min_delta;
|
||
|
|
|
||
|
|
return dd->last_rounded_rate;
|
||
|
|
}
|