61 lines
1.7 KiB
Plaintext
61 lines
1.7 KiB
Plaintext
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Qualcomm Technologies Inc. adreno/snapdragon eDP output
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Required properties:
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- compatible:
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* "qcom,mdss-edp"
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- reg: Physical base address and length of the registers of controller and PLL
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- reg-names: The names of register regions. The following regions are required:
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* "edp"
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* "pll_base"
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- interrupts: The interrupt signal from the eDP block.
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- power-domains: Should be <&mmcc MDSS_GDSC>.
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- clocks: device clocks
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See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
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- clock-names: the following clocks are required:
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* "core_clk"
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* "iface_clk"
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* "mdp_core_clk"
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* "pixel_clk"
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* "link_clk"
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- #clock-cells: The value should be 1.
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- vdda-supply: phandle to vdda regulator device node
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- lvl-vdd-supply: phandle to regulator device node which is used to supply power
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to HPD receiving chip
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- panel-en-gpios: GPIO pin to supply power to panel.
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- panel-hpd-gpios: GPIO pin used for eDP hpd.
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Optional properties:
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- interrupt-parent: phandle to the MDP block if the interrupt signal is routed
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through MDP block
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Example:
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mdss_edp: qcom,mdss_edp@fd923400 {
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compatible = "qcom,mdss-edp";
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reg-names =
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"edp",
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"pll_base";
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reg = <0xfd923400 0x700>,
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<0xfd923a00 0xd4>;
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interrupt-parent = <&mdss_mdp>;
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interrupts = <12 0>;
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power-domains = <&mmcc MDSS_GDSC>;
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clock-names =
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"core_clk",
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"pixel_clk",
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"iface_clk",
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"link_clk",
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"mdp_core_clk";
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clocks =
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<&mmcc MDSS_EDPAUX_CLK>,
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<&mmcc MDSS_EDPPIXEL_CLK>,
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<&mmcc MDSS_AHB_CLK>,
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<&mmcc MDSS_EDPLINK_CLK>,
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<&mmcc MDSS_MDP_CLK>;
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#clock-cells = <1>;
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vdda-supply = <&pma8084_l12>;
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lvl-vdd-supply = <&lvl_vreg>;
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panel-en-gpios = <&tlmm 137 0>;
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panel-hpd-gpios = <&tlmm 103 0>;
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};
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