370 lines
10 KiB
C
370 lines
10 KiB
C
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/*
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* s2mpu09-regulator.h - Voltage regulator driver for the s2mpu09
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*
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* Copyright (C) 2016 Samsung Electrnoics
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __LINUX_MFD_S2MPU09_PRIV_H
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#define __LINUX_MFD_S2MPU09_PRIV_H
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#include <linux/i2c.h>
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#define S2MPU09_REG_INVALID (0xff)
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#define S2MPU09_IRQSRC_PMIC (1 << 0)
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/* PMIC Top-Level Registers */
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#define S2MPU09_PMIC_REG_PMICID 0x00
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#define S2MPU09_PMIC_REG_INTSRC 0x01
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#define S2MPU09_PMIC_REG_INTSRC_MASK 0x02
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/* Slave addr = 0xCC */
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/* PMIC Registers */
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#define S2MPU09_PMIC_REG_INT1 0x00
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#define S2MPU09_PMIC_REG_INT2 0x01
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#define S2MPU09_PMIC_REG_INT3 0x02
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#define S2MPU09_PMIC_REG_INT4 0x03
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#define S2MPU09_PMIC_REG_INT5 0x04
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#define S2MPU09_PMIC_REG_INT1M 0x05
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#define S2MPU09_PMIC_REG_INT2M 0x06
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#define S2MPU09_PMIC_REG_INT3M 0x07
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#define S2MPU09_PMIC_REG_INT4M 0x08
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#define S2MPU09_PMIC_REG_INT5M 0x09
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#define S2MPU09_PMIC_REG_STATUS1 0x0A
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#define S2MPU09_PMIC_REG_STATUS2 0x0B
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#define S2MPU09_PMIC_REG_PWRONSRC 0x0C
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#define S2MPU09_PMIC_REG_OFFSRC 0x0D
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#define S2MPU09_PMIC_REG_BUCHG 0x0E
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#define S2MPU09_PMIC_REG_RTCBUF 0x0F
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#define S2MPU09_PMIC_REG_CTRL1 0x10
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#define S2MPU09_PMIC_REG_CTRL2 0x11
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#define S2MPU09_PMIC_REG_CTRL3 0x12
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#define S2MPU09_PMIC_REG_ETCOTP 0x13
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#define S2MPU09_PMIC_REG_UVLOOTP 0x14
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#define S2MPU09_PMIC_REG_UVLOTRIM 0x15
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#define S2MPU09_PMIC_REG_CFG1 0x16
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#define S2MPU09_PMIC_REG_CFG2 0x17
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#define S2MPU09_PMIC_REG_B1CTRL 0x18
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#define S2MPU09_PMIC_REG_B1OUT 0x19
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#define S2MPU09_PMIC_REG_B2CTRL 0x1A
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#define S2MPU09_PMIC_REG_B2OUT 0x1B
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#define S2MPU09_PMIC_REG_B3CTRL 0x1C
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#define S2MPU09_PMIC_REG_B3OUT 0x1D
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#define S2MPU09_PMIC_REG_B4CTRL 0x1E
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#define S2MPU09_PMIC_REG_B4OUT 0x1F
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#define S2MPU09_PMIC_REG_B5CTRL 0x20
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#define S2MPU09_PMIC_REG_B5OUT 0x21
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#define S2MPU09_PMIC_REG_B6CTRL 0x22
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#define S2MPU09_PMIC_REG_B6OUT 0x23
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#define S2MPU09_PMIC_REG_B7CTRL 0x24
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#define S2MPU09_PMIC_REG_B7OUT 0x25
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#define S2MPU09_PMIC_REG_B8CTRL 0x26
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#define S2MPU09_PMIC_REG_B8OUT1 0x27
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#define S2MPU09_PMIC_REG_B8OUT2 0x28
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#define S2MPU09_PMIC_REG_B9CTRL 0x29
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#define S2MPU09_PMIC_REG_B9OUT1 0x2A
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#define S2MPU09_PMIC_REG_B9OUT2 0x2B
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#define S2MPU09_PMIC_REG_B10CTRL 0x2C
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#define S2MPU09_PMIC_REG_B10OUT 0x2D
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#define S2MPU09_PMIC_REG_BUCKRAMP1 0x2E
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#define S2MPU09_PMIC_REG_BUCKRAMP2 0x2F
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#define S2MPU09_PMIC_REG_LDORAMP1 0x30
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#define S2MPU09_PMIC_REG_OCPWARN1 0x31
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#define S2MPU09_PMIC_REG_BUCK2_PH_DVS 0x32
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#define S2MPU09_PMIC_REG_LDO8_DVS 0x33
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#define S2MPU09_PMIC_REG_LDO9_DVS 0x34
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#define S2MPU09_PMIC_REG_LDO10_DVS 0x35
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#define S2MPU09_PMIC_REG_LDO11_DVS 0x36
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#define S2MPU09_PMIC_REG_LDO36_DVS 0x37
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#define S2MPU09_PMIC_REG_LDO43_DVS 0x38
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#define S2MPU09_PMIC_REG_L1CTRL 0x39
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#define S2MPU09_PMIC_REG_L2CTRL1 0x3A
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#define S2MPU09_PMIC_REG_L2CTRL2 0x3B
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#define S2MPU09_PMIC_REG_L3CTRL 0x3C
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#define S2MPU09_PMIC_REG_L4CTRL 0x3D
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#define S2MPU09_PMIC_REG_L5CTRL 0x3E
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#define S2MPU09_PMIC_REG_L6CTRL 0x3F
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#define S2MPU09_PMIC_REG_L7CTRL 0x40
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#define S2MPU09_PMIC_REG_L8CTRL 0x41
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#define S2MPU09_PMIC_REG_L9CTRL 0x42
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#define S2MPU09_PMIC_REG_L10CTRL 0x43
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#define S2MPU09_PMIC_REG_L11CTRL 0x44
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#define S2MPU09_PMIC_REG_L12CTRL 0x45
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#define S2MPU09_PMIC_REG_L13CTRL 0x46
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#define S2MPU09_PMIC_REG_L14CTRL 0x47
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#define S2MPU09_PMIC_REG_L15CTRL 0x48
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#define S2MPU09_PMIC_REG_L16CTRL 0x49
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#define S2MPU09_PMIC_REG_L17CTRL 0x4A
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#define S2MPU09_PMIC_REG_L18CTRL 0x4B
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#define S2MPU09_PMIC_REG_L19CTRL 0x4C
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#define S2MPU09_PMIC_REG_L20CTRL 0x4D
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#define S2MPU09_PMIC_REG_L21CTRL 0x4E
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#define S2MPU09_PMIC_REG_L22CTRL 0x4F
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#define S2MPU09_PMIC_REG_L23CTRL 0x50
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#define S2MPU09_PMIC_REG_L24CTRL 0x51
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#define S2MPU09_PMIC_REG_L25CTRL 0x52
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#define S2MPU09_PMIC_REG_L26CTRL 0x53
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#define S2MPU09_PMIC_REG_L27CTRL 0x54
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#define S2MPU09_PMIC_REG_L28CTRL 0x55
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#define S2MPU09_PMIC_REG_L29CTRL 0x56
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#define S2MPU09_PMIC_REG_L30CTRL 0x57
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#define S2MPU09_PMIC_REG_L31CTRL 0x58
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#define S2MPU09_PMIC_REG_L32CTRL 0x59
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#define S2MPU09_PMIC_REG_L33CTRL 0x5A
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#define S2MPU09_PMIC_REG_L34CTRL 0x5B
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#define S2MPU09_PMIC_REG_L35CTRL 0x5C
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#define S2MPU09_PMIC_REG_L36CTRL 0x5D
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#define S2MPU09_PMIC_REG_L37CTRL 0x5E
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#define S2MPU09_PMIC_REG_L38CTRL 0x5F
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#define S2MPU09_PMIC_REG_L39CTRL 0x60
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#define S2MPU09_PMIC_REG_L40CTRL 0x61
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#define S2MPU09_PMIC_REG_L41CTRL 0x62
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#define S2MPU09_PMIC_REG_L42CTRL 0x63
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#define S2MPU09_PMIC_REG_L43CTRL 0x64
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#define S2MPU09_PMIC_REG_L44CTRL 0x65
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#define S2MPU09_PMIC_REG_LDO_DSCH1 0x66
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#define S2MPU09_PMIC_REG_LDO_DSCH2 0x67
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#define S2MPU09_PMIC_REG_LDO_DSCH3 0x68
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#define S2MPU09_PMIC_REG_LDO_DSCH4 0x69
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#define S2MPU09_PMIC_REG_LDO_DSCH5 0x6A
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#define S2MPU09_PMIC_REG_LDO_DSCH6 0x6B
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#define S2MPU09_PMIC_REG_LDO_SIM_RF 0x6C
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#define S2MPU09_PMIC_REG_LDO_DRAM1 0x6D
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#define S2MPU09_PMIC_REG_LDO_DRAM2 0x6E
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#define S2MPU09_PMIC_REG_LDO_CTRL1 0x6F
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#define S2MPU09_PMIC_REG_LDO_CTRL2 0x70
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#define S2MPU09_PMIC_REG_OFF_SEQ 0x75
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#define S2MPU09_PMIC_REG_TCXO_CTRL 0x76
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#define S2MPU09_PMIC_REG_SELMIF0 0xA7
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#define S2MPU09_PMIC_REG_SELMIF1 0xA8
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#define S2MPU09_PMIC_REG_EXT_EN 0xAD
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#define S2MPU09_PMIC_REG_EXT_CTRL 0xFF
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/* S2MPU09 regulator ids */
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enum S2MPU09_regulators {
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S2MPU09_LDO1,
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S2MPU09_LDO2,
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S2MPU09_LDO3,
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S2MPU09_LDO4,
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S2MPU09_LDO5,
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S2MPU09_LDO6,
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S2MPU09_LDO7,
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S2MPU09_LDO8,
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S2MPU09_LDO9,
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S2MPU09_LDO10,
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S2MPU09_LDO11,
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S2MPU09_LDO12,
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S2MPU09_LDO13,
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S2MPU09_LDO14,
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/* S2MPU09_LDO15,
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S2MPU09_LDO16,
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S2MPU09_LDO17,
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S2MPU09_LDO18,
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S2MPU09_LDO19,
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S2MPU09_LDO20,
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S2MPU09_LDO21,
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S2MPU09_LDO22,
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S2MPU09_LDO23,
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S2MPU09_LDO24,
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S2MPU09_LDO25,
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S2MPU09_LDO24,
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S2MPU09_LDO25,
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S2MPU09_LDO26,
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S2MPU09_LDO27,
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S2MPU09_LDO28,
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S2MPU09_LDO29,
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S2MPU09_LDO30,
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S2MPU09_LDO31,
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S2MPU09_LDO32,
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*/ S2MPU09_LDO33,
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S2MPU09_LDO34,
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S2MPU09_LDO35,
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S2MPU09_LDO36,
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S2MPU09_LDO37,
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S2MPU09_LDO38,
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S2MPU09_LDO39,
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S2MPU09_LDO40,
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S2MPU09_LDO41,
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S2MPU09_LDO42,
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S2MPU09_LDO43,
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S2MPU09_LDO44,
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S2MPU09_BUCK1,
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S2MPU09_BUCK2,
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S2MPU09_BUCK3,
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S2MPU09_BUCK4,
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S2MPU09_BUCK5,
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S2MPU09_BUCK6,
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S2MPU09_BUCK7,
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S2MPU09_BUCK8,
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S2MPU09_BUCK9,
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// S2MPU09_BUCK10,
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S2MPU09_REG_MAX,
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};
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#define S2MPU09_BUCK_MIN1 300000
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#define S2MPU09_BUCK_MIN2 600000
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#define S2MPU09_LDO_MIN1 300000
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#define S2MPU09_LDO_MIN2 400000
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#define S2MPU09_LDO_MIN3 700000
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#define S2MPU09_LDO_MIN4 1800000
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#define S2MPU09_BUCK_STEP1 6250
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#define S2MPU09_BUCK_STEP2 12500
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#define S2MPU09_LDO_STEP1 12500
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#define S2MPU09_LDO_STEP2 25000
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#define S2MPU09_LDO_VSEL_MASK 0x3F
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#define S2MPU09_BUCK_VSEL_MASK 0xFF
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#define S2MPU09_ENABLE_MASK (0x03 << S2MPU09_ENABLE_SHIFT)
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#define S2MPU09_SW_ENABLE_MASK 0x03
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#define S2MPU09_RAMP_DELAY 12000
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#define S2MPU09_ENABLE_TIME_LDO 128
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#define S2MPU09_ENABLE_TIME_BUCK1 110
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#define S2MPU09_ENABLE_TIME_BUCK2 110
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#define S2MPU09_ENABLE_TIME_BUCK3 110
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#define S2MPU09_ENABLE_TIME_BUCK4 150
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#define S2MPU09_ENABLE_TIME_BUCK5 150
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#define S2MPU09_ENABLE_TIME_BUCK6 150
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#define S2MPU09_ENABLE_TIME_BUCK7 150
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#define S2MPU09_ENABLE_TIME_BUCK8 150
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#define S2MPU09_ENABLE_TIME_BUCK9 150
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#define S2MPU09_ENABLE_TIME_BUCK10 150
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#define S2MPU09_ENABLE_SHIFT 0x06
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#define S2MPU09_LDO_N_VOLTAGES (S2MPU09_LDO_VSEL_MASK + 1)
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#define S2MPU09_BUCK_N_VOLTAGES (S2MPU09_BUCK_VSEL_MASK + 1)
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#define S2MPU09_PMIC_EN_SHIFT 6
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#define S2MPU09_REGULATOR_MAX (S2MPU09_REG_MAX)
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#define SEC_PMIC_REV(iodev) (iodev)->pmic_rev
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/*
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* sec_opmode_data - regulator operation mode data
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* @id: regulator id
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* @mode: regulator operation mode
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*/
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enum s2mpu09_irq_source {
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PMIC_INT1 = 0,
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PMIC_INT2,
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PMIC_INT3,
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PMIC_INT4,
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PMIC_INT5,
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S2MPU09_IRQ_GROUP_NR,
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};
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#define S2MPU09_NUM_IRQ_PMIC_REGS 5
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enum s2mpu09_irq {
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/* PMIC */
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S2MPU09_PMIC_IRQ_PWRONF_INT1,
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S2MPU09_PMIC_IRQ_PWRONR_INT1,
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S2MPU09_PMIC_IRQ_JIGONBF_INT1,
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S2MPU09_PMIC_IRQ_JIGONBR_INT1,
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S2MPU09_PMIC_IRQ_ACOKF_INT1,
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S2MPU09_PMIC_IRQ_ACOKR_INT1,
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S2MPU09_PMIC_IRQ_PWRON1S_INT1,
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S2MPU09_PMIC_IRQ_MRB_INT1,
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S2MPU09_PMIC_IRQ_RTC60S_INT2,
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S2MPU09_PMIC_IRQ_RTCA1_INT2,
|
||
|
|
S2MPU09_PMIC_IRQ_RTCA0_INT2,
|
||
|
|
S2MPU09_PMIC_IRQ_SMPL_INT2,
|
||
|
|
S2MPU09_PMIC_IRQ_RTC1S_INT2,
|
||
|
|
S2MPU09_PMIC_IRQ_WTSR_INT2,
|
||
|
|
S2MPU09_PMIC_IRQ_WTSRB_INT2,
|
||
|
|
|
||
|
|
S2MPU09_PMIC_IRQ_120C_INT3,
|
||
|
|
S2MPU09_PMIC_IRQ_140C_INT3,
|
||
|
|
S2MPU09_PMIC_IRQ_TSD_INT3,
|
||
|
|
S2MPU09_PMIC_IRQ_OCPB1_INT3,
|
||
|
|
S2MPU09_PMIC_IRQ_OCPB2_INT3,
|
||
|
|
|
||
|
|
S2MPU09_PMIC_IRQ_OCPB3_INT4,
|
||
|
|
S2MPU09_PMIC_IRQ_OCPB4_INT4,
|
||
|
|
S2MPU09_PMIC_IRQ_OCPB5_INT4,
|
||
|
|
S2MPU09_PMIC_IRQ_OCPB6_INT4,
|
||
|
|
S2MPU09_PMIC_IRQ_OCPB7_INT4,
|
||
|
|
S2MPU09_PMIC_IRQ_OCPB8_INT4,
|
||
|
|
S2MPU09_PMIC_IRQ_OCPB9_INT4,
|
||
|
|
S2MPU09_PMIC_IRQ_OCPB10_INT4,
|
||
|
|
|
||
|
|
S2MPU09_PMIC_IRQ_SCLDO2_INT5,
|
||
|
|
S2MPU09_PMIC_IRQ_SCLDO18_INT5,
|
||
|
|
S2MPU09_PMIC_IRQ_SCLDO19_INT5,
|
||
|
|
S2MPU09_PMIC_IRQ_SCLDO33_INT5,
|
||
|
|
S2MPU09_PMIC_IRQ_SCLDO34_INT5,
|
||
|
|
S2MPU09_PMIC_IRQ_SCLDO35_INT5,
|
||
|
|
|
||
|
|
S2MPU09_IRQ_NR,
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
enum sec_device_type {
|
||
|
|
S2MPU09X,
|
||
|
|
};
|
||
|
|
|
||
|
|
struct s2mpu09_dev {
|
||
|
|
struct device *dev;
|
||
|
|
struct i2c_client *i2c;
|
||
|
|
struct i2c_client *pmic;
|
||
|
|
struct i2c_client *rtc;
|
||
|
|
struct mutex i2c_lock;
|
||
|
|
struct apm_ops *ops;
|
||
|
|
|
||
|
|
int type;
|
||
|
|
int device_type;
|
||
|
|
int irq;
|
||
|
|
int irq_base;
|
||
|
|
int irq_gpio;
|
||
|
|
bool wakeup;
|
||
|
|
struct mutex irqlock;
|
||
|
|
int irq_masks_cur[S2MPU09_IRQ_GROUP_NR];
|
||
|
|
int irq_masks_cache[S2MPU09_IRQ_GROUP_NR];
|
||
|
|
|
||
|
|
/* pmic REV register */
|
||
|
|
u8 pmic_rev; /* pmic Rev */
|
||
|
|
|
||
|
|
struct s2mpu09_platform_data *pdata;
|
||
|
|
};
|
||
|
|
|
||
|
|
enum s2mpu09_types {
|
||
|
|
TYPE_S2MPU09,
|
||
|
|
};
|
||
|
|
|
||
|
|
extern int s2mpu09_irq_init(struct s2mpu09_dev *s2mpu09);
|
||
|
|
extern void s2mpu09_irq_exit(struct s2mpu09_dev *s2mpu09);
|
||
|
|
|
||
|
|
/* S2MPU09 shared i2c API function */
|
||
|
|
extern int s2mpu09_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest);
|
||
|
|
extern int s2mpu09_bulk_read(struct i2c_client *i2c, u8 reg, int count,
|
||
|
|
u8 *buf);
|
||
|
|
extern int s2mpu09_write_reg(struct i2c_client *i2c, u8 reg, u8 value);
|
||
|
|
extern int s2mpu09_bulk_write(struct i2c_client *i2c, u8 reg, int count,
|
||
|
|
u8 *buf);
|
||
|
|
extern int s2mpu09_write_word(struct i2c_client *i2c, u8 reg, u16 value);
|
||
|
|
extern int s2mpu09_read_word(struct i2c_client *i2c, u8 reg);
|
||
|
|
|
||
|
|
extern int s2mpu09_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask);
|
||
|
|
|
||
|
|
#endif /* __LINUX_MFD_S2MPU09_PRIV_H */
|