251 lines
8.0 KiB
C
251 lines
8.0 KiB
C
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/*
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* Copyright (c) 2017 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Sung-Hyun Na <sunghyun.na@samsung.com>
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*
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* Chip Abstraction Layer for USB PHY
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include "phy-samsung-usb-cal.h"
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#include "phy-exynos-usbdp-reg.h"
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void phy_exynos_usbdp_tune_each(struct exynos_usbphy_info *info, char *name,
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int val)
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{
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void __iomem *regs_base = info->regs_base;
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u32 reg;
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if (!name)
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return;
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if (!strcmp(name, "sstx_deemph")) {
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reg = readl(regs_base + EXYNOS_USBDP_COM_TRSV_R0C);
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reg &= ~USBDP_TRSV0C_MAN_TX_DE_EMP_LVL_MASK;
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reg |= USBDP_TRSV0C_MAN_TX_DE_EMP_LVL_SET(val);
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writel(reg, regs_base + EXYNOS_USBDP_COM_TRSV_R0C);
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} else if (!strcmp(name, "sstx_amp")) {
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reg = readl(regs_base + EXYNOS_USBDP_COM_TRSV_R0C);
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reg &= ~USBDP_TRSV0C_MAN_TX_DRVR_LVL_MASK;
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reg |= USBDP_TRSV0C_MAN_TX_DRVR_LVL_SET(val);
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writel(reg, regs_base + EXYNOS_USBDP_COM_TRSV_R0C);
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} else if (!strcmp(name, "ssrx_los")) {
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reg = readl(regs_base + EXYNOS_USBDP_COM_TRSV_R0A);
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reg &= ~USBDP_TRSV0A_APB_CAL_OFFSET_DIFP_MASK;
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reg |= USBDP_TRSV0A_APB_CAL_OFFSET_DIFP_SET(val);
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writel(reg, regs_base + EXYNOS_USBDP_COM_TRSV_R0A);
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reg = readl(regs_base + EXYNOS_USBDP_COM_TRSV_R0B);
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reg &= ~USBDP_TRSV0B_APB_CAL_OFFSET_DIFN_MASK;
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reg |= USBDP_TRSV0B_APB_CAL_OFFSET_DIFN_SET(val);
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writel(reg, regs_base + EXYNOS_USBDP_COM_TRSV_R0B);
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} else if (!strcmp(name, "ssrx_ctle")) {
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reg = USBDP_TRSV02_RXAFE_LEQ_CSEL_GEN2_SET(0x2);
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reg |= USBDP_TRSV02_RXAFE_LEQ_CSEL_GEN1_SET(0x7);
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writel(reg, regs_base + EXYNOS_USBDP_COM_TRSV_R02);
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reg = USBDP_TRSV03_RXAFE_TERM_MODE;
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reg &= ~USBDP_TRSV03_RXAFE_LEQ_RSEL_GEN2_MASK;
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reg |= USBDP_TRSV03_RXAFE_LEQ_RSEL_GEN2_SET(0x7);
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reg &= ~USBDP_TRSV03_RXAFE_LEQ_RSEL_GEN1_MASK;
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writel(reg, regs_base + EXYNOS_USBDP_COM_TRSV_R03);
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reg = USBDP_TRSV04_RXAFE_TUNE_SET(val);
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reg |= USBDP_TRSV04_RXAFE_SQ_VFFSET_CTRL_SET(val);
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writel(reg, regs_base + EXYNOS_USBDP_COM_TRSV_R04);
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}
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}
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void phy_exynos_usbdp_tune(struct exynos_usbphy_info *info)
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{
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u32 cnt = 0;
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for (; info->tune_param[cnt].value != EXYNOS_USB_TUNE_LAST; cnt++) {
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char *para_name;
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int val;
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val = info->tune_param[cnt].value;
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if (val == -1)
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continue;
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para_name = info->tune_param[cnt].name;
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if (!para_name)
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break;
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phy_exynos_usbdp_tune_each(info, para_name, val);
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}
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}
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void phy_exynos_usbdp_ilbk(struct exynos_usbphy_info *info)
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{
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}
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void phy_exynos_usbdp_enable(struct exynos_usbphy_info *info)
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{
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void __iomem *regs_base = info->regs_base;
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u32 reg, reg_2c, reg_2d, reg_dp_b3;
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/* Recevier Detection Off */
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reg = readl(regs_base + EXYNOS_USBDP_COM_TRSV_R24);
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reg |= USBDP_TRSV24_MAN_TX_RCV_DET_EN;
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writel(reg, regs_base + EXYNOS_USBDP_COM_TRSV_R24);
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/* Set Proper Value for PCS to avoid abnormal RX Detect */
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reg = readl(info->regs_base_2nd + USBDP_PCSREG_FRONT_END_MODE_VEC);
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reg |= USBDP_PCSREG_EN_REALIGN;
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writel(reg, info->regs_base_2nd + USBDP_PCSREG_FRONT_END_MODE_VEC);
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reg = USBDP_PCSREG_COMP_EN_ASSERT_SET(0x3f);
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writel(reg, info->regs_base_2nd + USBDP_PCSREG_DET_COMP_EN_SET);
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reg = 0;
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reg |= USBDP_CMN0E_PLL_AFC_VCO_CNT_RUN_NO_SET(0x4);
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reg |= USBDP_CMN0E_PLL_AFC_ANA_CPI_CTRL_SET(0x2);
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writel(reg, regs_base + EXYNOS_USBDP_COM_CMN_R0E);
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reg = 0;
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reg |= USBDP_CMN0F_PLL_ANA_EN_PI;
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reg |= USBDP_CMN0F_PLL_ANA_DCC_EN_SET(0xf);
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reg |= USBDP_CMN0F_PLL_ANA_CPP_CTRL_SET(0x7);
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writel(reg, regs_base + EXYNOS_USBDP_COM_CMN_R0F);
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reg = 0;
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reg |= USBDP_CMN10_PLL_ANA_VCI_SEL_SET(0x6);
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reg |= USBDP_CMN10_PLL_ANA_LPF_RSEL_SET(0x8);
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writel(reg, regs_base + EXYNOS_USBDP_COM_CMN_R10);
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reg = 0;
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reg |= USBDP_CMN25_PLL_AGMC_TG_CODE_SET(0x30);
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writel(reg, regs_base + EXYNOS_USBDP_COM_CMN_R25);
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reg = 0;
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reg |= USBDP_CMN26_PLL_AGMC_COMP_EN;
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reg |= USBDP_CMN26_PLL_AGMC_FROM_MAX_GM;
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reg |= USBDP_CMN26_PLL_AFC_FROM_PRE_CODE;
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reg |= USBDP_CMN26_PLL_AFC_MAN_BSEL_L_SET(0x3);
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writel(reg, regs_base + EXYNOS_USBDP_COM_CMN_R26);
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reg = 0;
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reg |= USBDP_CMN27_PLL_ANA_LC_VREF_BYPASS_EN;
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reg |= USBDP_CMN27_PLL_ANA_LC_VCDO_CAP_OFFSET_SEL_SET(0x5);
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reg |= USBDP_CMN27_PLL_ANA_LC_VCO_BUFF_EN;
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reg |= USBDP_CMN27_PLL_ANA_LC_GM_COMP_VCI_SEL_SET(0x4);
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writel(reg, regs_base + EXYNOS_USBDP_COM_CMN_R27);
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reg = 0;
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reg |= USBDP_TRSV23_DATA_CLEAR_BY_SIGVAL;
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reg |= USBDP_TRSV23_FBB_H_BW_DIFF_SET(0x5);
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writel(reg, regs_base + EXYNOS_USBDP_COM_TRSV_R23);
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/* SSC Setting */
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reg = readl(regs_base + EXYNOS_USBDP_COM_CMN_R24);
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reg |= USBDP_CMN24_SSC_EN;
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writel(reg, regs_base + EXYNOS_USBDP_COM_CMN_R24);
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reg_2c = readl(regs_base + EXYNOS_USBDP_COM_CMN_R2C);
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reg_2d = readl(regs_base + EXYNOS_USBDP_COM_CMN_R2D);
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reg_dp_b3 = readl(regs_base + EXYNOS_USBDP_COM_DP_RB3);
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if (info->used_phy_port == 0) {
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reg_2c |= USBDP_CMN2C_MAN_USBDP_MODE_SET(0x3);
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reg_2d |= USBDP_CMN2D_USB_TX1_SEL;
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reg_2d &= ~USBDP_CMN2D_USB_TX3_SEL;
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reg_dp_b3 &= ~USBDP_DPB3_CMN_DUMMY_CTRL_7;
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reg_dp_b3 |= USBDP_DPB3_CMN_DUMMY_CTRL_6;
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reg_dp_b3 |= USBDP_DPB3_CMN_DUMMY_CTRL_1;
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reg_dp_b3 |= USBDP_DPB3_CMN_DUMMY_CTRL_0;
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} else {
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reg_2c &= ~USBDP_CMN2C_MAN_USBDP_MODE_MASK;
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reg_2d &= ~USBDP_CMN2D_USB_TX1_SEL;
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reg_2d |= USBDP_CMN2D_USB_TX3_SEL;
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reg_dp_b3 |= USBDP_DPB3_CMN_DUMMY_CTRL_7;
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reg_dp_b3 &= ~USBDP_DPB3_CMN_DUMMY_CTRL_6;
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reg_dp_b3 &= ~USBDP_DPB3_CMN_DUMMY_CTRL_1;
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reg_dp_b3 &= ~USBDP_DPB3_CMN_DUMMY_CTRL_0;
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}
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reg_2c |= USBDP_CMN2C_MAN_USBDP_MODE_EN;
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reg_2d &= ~USBDP_CMN2D_LCPLL_SSCDIV_MASK;
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reg_2d |= USBDP_CMN2D_LCPLL_SSCDIV_SET(0x1);
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writel(reg_2c, regs_base + EXYNOS_USBDP_COM_CMN_R2C);
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writel(reg_2d, regs_base + EXYNOS_USBDP_COM_CMN_R2D);
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writel(reg_dp_b3, regs_base + EXYNOS_USBDP_COM_DP_RB3);
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reg = 0;
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reg |= USBDP_TRSV38_SFR_RX_LFPS_LPF_CTRL_SET(0x2);
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reg |= USBDP_TRSV38_SFR_RX_LFPS_TH_CTRL_SET(0x2);
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reg |= USBDP_TRSV38_RX_LFPS_DET_EN;
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writel(reg, regs_base + EXYNOS_USBDP_COM_TRSV_R38);
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/* RX EQ tuning */
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reg = readl(regs_base + EXYNOS_USBDP_COM_TRSV_R01);
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reg &= ~USBDP_TRSV01_RXAFE_CTLE_SEL_MASK;
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reg |= USBDP_TRSV01_RXAFE_CTLE_SEL_SET(0x3);
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writel(reg, regs_base + EXYNOS_USBDP_COM_TRSV_R01);
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reg = readl(regs_base + EXYNOS_USBDP_COM_TRSV_R03);
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reg &= ~USBDP_TRSV03_RXAFE_LEQ_RSEL_GEN1_MASK;
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reg &= ~USBDP_TRSV03_RXAFE_LEQ_RSEL_GEN2_MASK;
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reg |= USBDP_TRSV03_RXAFE_LEQ_RSEL_GEN1_SET(0x0);
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reg |= USBDP_TRSV03_RXAFE_LEQ_RSEL_GEN2_SET(0x5);
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writel(reg, regs_base + EXYNOS_USBDP_COM_TRSV_R03);
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reg = readl(regs_base + EXYNOS_USBDP_COM_TRSV_R0D);
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reg |= USBDP_TRSV0D_MAN_DRVR_DE_EMP_LVL_MAN_EN;
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writel(reg, regs_base + EXYNOS_USBDP_COM_TRSV_R0D);
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/* Sys Valid Debouncd Digital Filter */
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reg = 0;
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reg |= USBDP_TRSV34_INT_SIGVAL_FILT_SEL;
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reg |= USBDP_TRSV34_OUT_SIGVAL_FILT_SEL;
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reg |= USBDP_TRSV34_SIGVAL_FILT_DLY_CODE_SET(0x3);
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writel(reg, regs_base + EXYNOS_USBDP_COM_TRSV_R34);
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reg = readl(regs_base + EXYNOS_USBDP_COM_TRSV_R27);
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reg |= USBDP_TRSV27_MAN_RSTN_EN;
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writel(reg, regs_base + EXYNOS_USBDP_COM_TRSV_R27);
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/* Recevier Detection On */
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reg = readl(regs_base + EXYNOS_USBDP_COM_TRSV_R24);
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reg &= ~USBDP_TRSV24_MAN_TX_RCV_DET_EN;
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writel(reg, regs_base + EXYNOS_USBDP_COM_TRSV_R24);
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/* Set Tune Value */
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phy_exynos_usbdp_tune(info);
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}
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int phy_exynos_usbdp_check_pll_lock(struct exynos_usbphy_info *info)
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{
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void __iomem *regs_base = info->regs_base;
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u32 reg;
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reg = readl(regs_base + EXYNOS_USBDP_COM_CMN_R2F);
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printk("CMN_2F(0x%p) : 0x%x\n",
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regs_base + EXYNOS_USBDP_COM_CMN_R2F,
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reg);
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if (!(reg & USBDP_CMN2F_PLL_LOCK_DONE))
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return -1;
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reg = readl(regs_base + EXYNOS_USBDP_COM_TRSV_R4B);
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printk("TRSV_4B(0x%p) : 0x%x\n",
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regs_base + EXYNOS_USBDP_COM_TRSV_R4B,
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reg);
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if (!(reg & USBDP_TRSV4B_CDR_FLD_PLL_MODE_DONE))
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return -1;
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return 0;
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}
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void phy_exynos_usbdp_disable(struct exynos_usbphy_info *info)
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{
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}
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